nl-linux 0.2.0

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data/linux/dpll.yaml ADDED
@@ -0,0 +1,681 @@
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+ # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
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+ ---
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+ name: dpll
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+
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+ doc: DPLL subsystem.
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+
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+ definitions:
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+ -
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+ type: enum
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+ name: mode
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+ doc: |
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+ working modes a dpll can support, differentiates if and how dpll selects
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+ one of its inputs to syntonize with it, valid values for DPLL_A_MODE
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+ attribute
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+ entries:
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+ -
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+ name: manual
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+ doc: input can be only selected by sending a request to dpll
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+ value: 1
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+ -
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+ name: automatic
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+ doc: highest prio input pin auto selected by dpll
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+ render-max: true
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+ -
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+ type: enum
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+ name: lock-status
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+ doc: |
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+ provides information of dpll device lock status, valid values for
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+ DPLL_A_LOCK_STATUS attribute
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+ entries:
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+ -
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+ name: unlocked
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+ doc: |
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+ dpll was not yet locked to any valid input (or forced by setting
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+ DPLL_A_MODE to DPLL_MODE_DETACHED)
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+ value: 1
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+ -
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+ name: locked
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+ doc: |
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+ dpll is locked to a valid signal, but no holdover available
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+ -
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+ name: locked-ho-acq
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+ doc: |
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+ dpll is locked and holdover acquired
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+ -
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+ name: holdover
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+ doc: |
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+ dpll is in holdover state - lost a valid lock or was forced
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+ by disconnecting all the pins (latter possible only
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+ when dpll lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ,
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+ if dpll lock-state was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the
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+ dpll's lock-state shall remain DPLL_LOCK_STATUS_UNLOCKED)
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+ render-max: true
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+ -
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+ type: enum
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+ name: lock-status-error
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+ doc: |
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+ if previous status change was done due to a failure, this provides
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+ information of dpll device lock status error.
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+ Valid values for DPLL_A_LOCK_STATUS_ERROR attribute
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+ entries:
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+ -
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+ name: none
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+ doc: |
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+ dpll device lock status was changed without any error
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+ value: 1
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+ -
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+ name: undefined
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+ doc: |
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+ dpll device lock status was changed due to undefined error.
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+ Driver fills this value up in case it is not able
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+ to obtain suitable exact error type.
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+ -
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+ name: media-down
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+ doc: |
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+ dpll device lock status was changed because of associated
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+ media got down.
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+ This may happen for example if dpll device was previously
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+ locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
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+ -
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+ name: fractional-frequency-offset-too-high
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+ doc: |
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+ the FFO (Fractional Frequency Offset) between the RX and TX
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+ symbol rate on the media got too high.
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+ This may happen for example if dpll device was previously
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+ locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
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+ render-max: true
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+ -
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+ type: enum
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+ name: clock-quality-level
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+ doc: |
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+ level of quality of a clock device. This mainly applies when
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+ the dpll lock-status is DPLL_LOCK_STATUS_HOLDOVER.
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+ The current list is defined according to the table 11-7 contained
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+ in ITU-T G.8264/Y.1364 document. One may extend this list freely
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+ by other ITU-T defined clock qualities, or different ones defined
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+ by another standardization body (for those, please use
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+ different prefix).
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+ entries:
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+ -
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+ name: itu-opt1-prc
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+ value: 1
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+ -
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+ name: itu-opt1-ssu-a
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+ -
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+ name: itu-opt1-ssu-b
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+ -
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+ name: itu-opt1-eec1
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+ -
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+ name: itu-opt1-prtc
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+ -
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+ name: itu-opt1-eprtc
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+ -
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+ name: itu-opt1-eeec
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+ -
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+ name: itu-opt1-eprc
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+ render-max: true
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+ -
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+ type: const
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+ name: temp-divider
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+ value: 1000
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+ doc: |
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+ temperature divider allowing userspace to calculate the
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+ temperature as float with three digit decimal precision.
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+ Value of (DPLL_A_TEMP / DPLL_TEMP_DIVIDER) is integer part of
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+ temperature value.
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+ Value of (DPLL_A_TEMP % DPLL_TEMP_DIVIDER) is fractional part of
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+ temperature value.
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+ -
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+ type: enum
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+ name: type
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+ doc: type of dpll, valid values for DPLL_A_TYPE attribute
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+ entries:
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+ -
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+ name: pps
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+ doc: dpll produces Pulse-Per-Second signal
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+ value: 1
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+ -
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+ name: eec
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+ doc: dpll drives the Ethernet Equipment Clock
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+ render-max: true
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+ -
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+ type: enum
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+ name: pin-type
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+ doc: |
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+ defines possible types of a pin, valid values for DPLL_A_PIN_TYPE
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+ attribute
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+ entries:
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+ -
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+ name: mux
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+ doc: aggregates another layer of selectable pins
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+ value: 1
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+ -
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+ name: ext
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+ doc: external input
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+ -
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+ name: synce-eth-port
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+ doc: ethernet port PHY's recovered clock
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+ -
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+ name: int-oscillator
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+ doc: device internal oscillator
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+ -
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+ name: gnss
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+ doc: GNSS recovered clock
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+ render-max: true
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+ -
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+ type: enum
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+ name: pin-direction
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+ doc: |
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+ defines possible direction of a pin, valid values for
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+ DPLL_A_PIN_DIRECTION attribute
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+ entries:
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+ -
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+ name: input
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+ doc: pin used as a input of a signal
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+ value: 1
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+ -
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+ name: output
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+ doc: pin used to output the signal
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+ render-max: true
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+ -
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+ type: const
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+ name: pin-frequency-1-hz
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+ value: 1
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+ -
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+ type: const
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+ name: pin-frequency-10-khz
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+ value: 10000
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+ -
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+ type: const
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+ name: pin-frequency-77-5-khz
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+ value: 77500
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+ -
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+ type: const
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+ name: pin-frequency-10-mhz
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+ value: 10000000
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+ -
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+ type: enum
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+ name: pin-state
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+ doc: |
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+ defines possible states of a pin, valid values for
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+ DPLL_A_PIN_STATE attribute
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+ entries:
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+ -
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+ name: connected
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+ doc: pin connected, active input of phase locked loop
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+ value: 1
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+ -
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+ name: disconnected
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+ doc: pin disconnected, not considered as a valid input
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+ -
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+ name: selectable
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+ doc: pin enabled for automatic input selection
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+ render-max: true
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+ -
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+ type: flags
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+ name: pin-capabilities
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+ doc: |
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+ defines possible capabilities of a pin, valid flags on
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+ DPLL_A_PIN_CAPABILITIES attribute
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+ entries:
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+ -
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+ name: direction-can-change
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+ doc: pin direction can be changed
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+ -
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+ name: priority-can-change
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+ doc: pin priority can be changed
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+ -
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+ name: state-can-change
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+ doc: pin state can be changed
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+ -
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+ type: const
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+ name: phase-offset-divider
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+ value: 1000
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+ doc: |
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+ phase offset divider allows userspace to calculate a value of
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+ measured signal phase difference between a pin and dpll device
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+ as a fractional value with three digit decimal precision.
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+ Value of (DPLL_A_PHASE_OFFSET / DPLL_PHASE_OFFSET_DIVIDER) is an
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+ integer part of a measured phase offset value.
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+ Value of (DPLL_A_PHASE_OFFSET % DPLL_PHASE_OFFSET_DIVIDER) is a
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+ fractional part of a measured phase offset value.
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+ -
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+ type: enum
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+ name: feature-state
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+ doc: |
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+ Allow control (enable/disable) and status checking over features.
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+ entries:
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+ -
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+ name: disable
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+ doc: |
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+ feature shall be disabled
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+ -
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+ name: enable
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+ doc: |
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+ feature shall be enabled
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+
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+ attribute-sets:
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+ -
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+ name: dpll
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+ enum-name: dpll_a
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+ attributes:
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+ -
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+ name: id
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+ type: u32
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+ -
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+ name: module-name
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+ type: string
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+ -
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+ name: pad
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+ type: pad
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+ -
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+ name: clock-id
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+ type: u64
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+ -
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+ name: mode
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+ type: u32
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+ enum: mode
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+ -
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+ name: mode-supported
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+ type: u32
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+ enum: mode
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+ multi-attr: true
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+ -
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+ name: lock-status
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+ type: u32
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+ enum: lock-status
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+ -
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+ name: temp
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+ type: s32
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+ -
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+ name: type
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+ type: u32
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+ enum: type
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+ -
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+ name: lock-status-error
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+ type: u32
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+ enum: lock-status-error
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+ -
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+ name: clock-quality-level
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+ type: u32
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+ enum: clock-quality-level
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+ multi-attr: true
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+ doc: |
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+ Level of quality of a clock device. This mainly applies when
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+ the dpll lock-status is DPLL_LOCK_STATUS_HOLDOVER. This could
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+ be put to message multiple times to indicate possible parallel
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+ quality levels (e.g. one specified by ITU option 1 and another
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+ one specified by option 2).
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+ -
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+ name: phase-offset-monitor
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+ type: u32
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+ enum: feature-state
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+ doc: Receive or request state of phase offset monitor feature.
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+ If enabled, dpll device shall monitor and notify all currently
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+ available inputs for changes of their phase offset against the
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+ dpll device.
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+ -
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+ name: phase-offset-avg-factor
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+ type: u32
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+ doc: Averaging factor applied to calculation of reported phase offset.
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+ -
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+ name: pin
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+ enum-name: dpll_a_pin
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+ attributes:
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+ -
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+ name: id
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+ type: u32
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+ -
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+ name: parent-id
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+ type: u32
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+ -
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+ name: module-name
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+ type: string
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+ -
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+ name: pad
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+ type: pad
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+ -
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+ name: clock-id
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+ type: u64
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+ -
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+ name: board-label
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+ type: string
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+ -
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+ name: panel-label
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+ type: string
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+ -
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+ name: package-label
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+ type: string
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+ -
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+ name: type
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+ type: u32
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+ enum: pin-type
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+ -
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+ name: direction
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+ type: u32
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+ enum: pin-direction
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+ -
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+ name: frequency
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+ type: u64
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+ -
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+ name: frequency-supported
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+ type: nest
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+ multi-attr: true
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+ nested-attributes: frequency-range
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+ -
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+ name: frequency-min
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+ type: u64
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+ -
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+ name: frequency-max
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+ type: u64
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+ -
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+ name: prio
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+ type: u32
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+ -
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+ name: state
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+ type: u32
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+ enum: pin-state
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+ -
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+ name: capabilities
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+ type: u32
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+ enum: pin-capabilities
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+ -
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+ name: parent-device
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+ type: nest
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+ multi-attr: true
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+ nested-attributes: pin-parent-device
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+ -
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+ name: parent-pin
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+ type: nest
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+ multi-attr: true
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+ nested-attributes: pin-parent-pin
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+ -
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+ name: phase-adjust-min
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+ type: s32
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+ -
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+ name: phase-adjust-max
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+ type: s32
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+ -
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+ name: phase-adjust
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+ type: s32
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+ -
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+ name: phase-offset
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+ type: s64
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+ -
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+ name: fractional-frequency-offset
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+ type: sint
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+ doc: |
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+ The FFO (Fractional Frequency Offset) between the RX and TX
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+ symbol rate on the media associated with the pin:
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+ (rx_frequency-tx_frequency)/rx_frequency
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+ Value is in PPM (parts per million).
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+ This may be implemented for example for pin of type
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+ PIN_TYPE_SYNCE_ETH_PORT.
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+ -
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+ name: esync-frequency
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+ type: u64
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+ doc: |
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+ Frequency of Embedded SYNC signal. If provided, the pin is configured
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+ with a SYNC signal embedded into its base clock frequency.
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+ -
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+ name: esync-frequency-supported
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+ type: nest
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+ multi-attr: true
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+ nested-attributes: frequency-range
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+ doc: |
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+ If provided a pin is capable of embedding a SYNC signal (within given
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+ range) into its base frequency signal.
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+ -
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+ name: esync-pulse
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+ type: u32
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+ doc: |
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+ A ratio of high to low state of a SYNC signal pulse embedded
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+ into base clock frequency. Value is in percents.
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+ -
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+ name: reference-sync
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+ type: nest
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+ multi-attr: true
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+ nested-attributes: reference-sync
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+ doc: |
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+ Capable pin provides list of pins that can be bound to create a
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+ reference-sync pin pair.
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+ -
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+ name: phase-adjust-gran
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+ type: u32
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+ doc: |
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+ Granularity of phase adjustment, in picoseconds. The value of
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+ phase adjustment must be a multiple of this granularity.
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+
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+ -
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+ name: pin-parent-device
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+ subset-of: pin
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+ attributes:
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+ -
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+ name: parent-id
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+ -
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+ name: direction
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+ -
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+ name: prio
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+ -
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+ name: state
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+ -
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+ name: phase-offset
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+ -
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+ name: pin-parent-pin
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+ subset-of: pin
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+ attributes:
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+ -
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+ name: parent-id
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+ -
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+ name: state
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+ -
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+ name: frequency-range
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+ subset-of: pin
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+ attributes:
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+ -
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+ name: frequency-min
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+ -
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+ name: frequency-max
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+ -
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+ name: reference-sync
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+ subset-of: pin
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+ attributes:
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+ -
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+ name: id
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+ -
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+ name: state
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+
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+ operations:
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+ enum-name: dpll_cmd
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+ list:
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+ -
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+ name: device-id-get
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+ doc: |
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+ Get id of dpll device that matches given attributes
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+ attribute-set: dpll
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+ flags: [admin-perm]
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+
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+ do:
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+ pre: dpll-lock-doit
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+ post: dpll-unlock-doit
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+ request:
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+ attributes:
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+ - module-name
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+ - clock-id
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+ - type
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+ reply:
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+ attributes:
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+ - id
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+
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+ -
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+ name: device-get
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+ doc: |
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+ Get list of DPLL devices (dump) or attributes of a single dpll device
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+ attribute-set: dpll
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+ flags: [admin-perm]
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+
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+ do:
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+ pre: dpll-pre-doit
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+ post: dpll-post-doit
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+ request:
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+ attributes:
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+ - id
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+ reply: &dev-attrs
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+ attributes:
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+ - id
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+ - module-name
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+ - mode
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+ - mode-supported
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+ - lock-status
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+ - lock-status-error
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+ - temp
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+ - clock-id
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+ - type
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+ - phase-offset-monitor
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+ - phase-offset-avg-factor
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+
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+ dump:
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+ reply: *dev-attrs
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+
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+ -
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+ name: device-set
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+ doc: Set attributes for a DPLL device
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+ attribute-set: dpll
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+ flags: [admin-perm]
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+
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+ do:
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+ pre: dpll-pre-doit
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+ post: dpll-post-doit
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+ request:
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+ attributes:
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+ - id
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+ - phase-offset-monitor
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+ - phase-offset-avg-factor
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+ -
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+ name: device-create-ntf
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+ doc: Notification about device appearing
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+ notify: device-get
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+ mcgrp: monitor
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+ -
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+ name: device-delete-ntf
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+ doc: Notification about device disappearing
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+ notify: device-get
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+ mcgrp: monitor
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+ -
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+ name: device-change-ntf
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+ doc: Notification about device configuration being changed
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+ notify: device-get
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+ mcgrp: monitor
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+ -
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+ name: pin-id-get
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+ doc: |
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+ Get id of a pin that matches given attributes
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+ attribute-set: pin
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+ flags: [admin-perm]
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+
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+ do:
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+ pre: dpll-lock-doit
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+ post: dpll-unlock-doit
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+ request:
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+ attributes:
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+ - module-name
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+ - clock-id
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+ - board-label
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+ - panel-label
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+ - package-label
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+ - type
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+ reply:
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+ attributes:
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+ - id
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+
592
+ -
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+ name: pin-get
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+ doc: |
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+ Get list of pins and its attributes.
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+
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+ - dump request without any attributes given - list all the pins in the
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+ system
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+ - dump request with target dpll - list all the pins registered with
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+ a given dpll device
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+ - do request with target dpll and target pin - single pin attributes
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+ attribute-set: pin
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+ flags: [admin-perm]
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+
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+ do:
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+ pre: dpll-pin-pre-doit
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+ post: dpll-pin-post-doit
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+ request:
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+ attributes:
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+ - id
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+ reply: &pin-attrs
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+ attributes:
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+ - id
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+ - module-name
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+ - clock-id
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+ - board-label
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+ - panel-label
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+ - package-label
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+ - type
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+ - frequency
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+ - frequency-supported
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+ - capabilities
623
+ - parent-device
624
+ - parent-pin
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+ - phase-adjust-gran
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+ - phase-adjust-min
627
+ - phase-adjust-max
628
+ - phase-adjust
629
+ - fractional-frequency-offset
630
+ - esync-frequency
631
+ - esync-frequency-supported
632
+ - esync-pulse
633
+ - reference-sync
634
+
635
+ dump:
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+ request:
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+ attributes:
638
+ - id
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+ reply: *pin-attrs
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+
641
+ -
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+ name: pin-set
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+ doc: Set attributes of a target pin
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+ attribute-set: pin
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+ flags: [admin-perm]
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+
647
+ do:
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+ pre: dpll-pin-pre-doit
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+ post: dpll-pin-post-doit
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+ request:
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+ attributes:
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+ - id
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+ - frequency
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+ - direction
655
+ - prio
656
+ - state
657
+ - parent-device
658
+ - parent-pin
659
+ - phase-adjust
660
+ - esync-frequency
661
+ - reference-sync
662
+ -
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+ name: pin-create-ntf
664
+ doc: Notification about pin appearing
665
+ notify: pin-get
666
+ mcgrp: monitor
667
+ -
668
+ name: pin-delete-ntf
669
+ doc: Notification about pin disappearing
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+ notify: pin-get
671
+ mcgrp: monitor
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+ -
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+ name: pin-change-ntf
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+ doc: Notification about pin configuration being changed
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+ notify: pin-get
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+ mcgrp: monitor
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+
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+ mcast-groups:
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+ list:
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+ -
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+ name: monitor