mustang 0.0.1 → 0.1.0
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- data/.rspec +1 -0
- data/Isolate +9 -0
- data/README.md +6 -12
- data/Rakefile +30 -4
- data/TODO.md +9 -0
- data/ext/v8/extconf.rb +56 -0
- data/ext/v8/v8.cpp +37 -0
- data/ext/v8/v8_array.cpp +161 -0
- data/ext/v8/v8_array.h +17 -0
- data/ext/v8/v8_base.cpp +147 -0
- data/ext/v8/v8_base.h +23 -0
- data/ext/v8/v8_cast.cpp +151 -0
- data/ext/v8/v8_cast.h +64 -0
- data/ext/v8/v8_context.cpp +174 -0
- data/ext/v8/v8_context.h +12 -0
- data/ext/v8/v8_date.cpp +61 -0
- data/ext/v8/v8_date.h +16 -0
- data/ext/v8/v8_errors.cpp +147 -0
- data/ext/v8/v8_errors.h +19 -0
- data/ext/v8/v8_external.cpp +66 -0
- data/ext/v8/v8_external.h +16 -0
- data/ext/v8/v8_function.cpp +182 -0
- data/ext/v8/v8_function.h +14 -0
- data/ext/v8/v8_integer.cpp +70 -0
- data/ext/v8/v8_integer.h +16 -0
- data/ext/v8/v8_macros.h +30 -0
- data/ext/v8/v8_main.cpp +53 -0
- data/ext/v8/v8_main.h +13 -0
- data/ext/v8/v8_number.cpp +62 -0
- data/ext/v8/v8_number.h +16 -0
- data/ext/v8/v8_object.cpp +172 -0
- data/ext/v8/v8_object.h +17 -0
- data/ext/v8/v8_ref.cpp +72 -0
- data/ext/v8/v8_ref.h +43 -0
- data/ext/v8/v8_regexp.cpp +148 -0
- data/ext/v8/v8_regexp.h +16 -0
- data/ext/v8/v8_string.cpp +78 -0
- data/ext/v8/v8_string.h +16 -0
- data/ext/v8/v8_value.cpp +370 -0
- data/ext/v8/v8_value.h +19 -0
- data/gemspec.yml +2 -1
- data/lib/core_ext/class.rb +14 -0
- data/lib/core_ext/object.rb +12 -0
- data/lib/core_ext/symbol.rb +23 -0
- data/lib/mustang.rb +44 -0
- data/lib/mustang/context.rb +69 -0
- data/lib/mustang/errors.rb +36 -0
- data/lib/support/delegated.rb +25 -0
- data/lib/v8/array.rb +21 -0
- data/lib/v8/context.rb +13 -0
- data/lib/v8/date.rb +20 -0
- data/lib/v8/error.rb +15 -0
- data/lib/v8/external.rb +16 -0
- data/lib/v8/function.rb +11 -0
- data/lib/v8/integer.rb +16 -0
- data/lib/v8/number.rb +16 -0
- data/lib/v8/object.rb +66 -0
- data/lib/v8/regexp.rb +23 -0
- data/lib/v8/string.rb +27 -0
- data/mustang.gemspec +3 -0
- data/spec/core_ext/class_spec.rb +19 -0
- data/spec/core_ext/object_spec.rb +19 -0
- data/spec/core_ext/symbol_spec.rb +27 -0
- data/spec/fixtures/test1.js +2 -0
- data/spec/fixtures/test2.js +2 -0
- data/spec/spec_helper.rb +20 -0
- data/spec/v8/array_spec.rb +88 -0
- data/spec/v8/cast_spec.rb +151 -0
- data/spec/v8/context_spec.rb +78 -0
- data/spec/v8/data_spec.rb +39 -0
- data/spec/v8/date_spec.rb +45 -0
- data/spec/v8/empty_spec.rb +27 -0
- data/spec/v8/errors_spec.rb +142 -0
- data/spec/v8/external_spec.rb +44 -0
- data/spec/v8/function_spec.rb +170 -0
- data/spec/v8/integer_spec.rb +41 -0
- data/spec/v8/main_spec.rb +18 -0
- data/spec/v8/null_spec.rb +27 -0
- data/spec/v8/number_spec.rb +40 -0
- data/spec/v8/object_spec.rb +79 -0
- data/spec/v8/primitive_spec.rb +9 -0
- data/spec/v8/regexp_spec.rb +65 -0
- data/spec/v8/string_spec.rb +48 -0
- data/spec/v8/undefined_spec.rb +27 -0
- data/spec/v8/value_spec.rb +215 -0
- data/vendor/v8/.gitignore +2 -0
- data/vendor/v8/AUTHORS +3 -1
- data/vendor/v8/ChangeLog +117 -0
- data/vendor/v8/SConstruct +334 -53
- data/vendor/v8/include/v8-debug.h +21 -11
- data/vendor/v8/include/v8-preparser.h +1 -1
- data/vendor/v8/include/v8-profiler.h +122 -43
- data/vendor/v8/include/v8-testing.h +5 -0
- data/vendor/v8/include/v8.h +171 -17
- data/vendor/v8/preparser/SConscript +38 -0
- data/vendor/v8/preparser/preparser-process.cc +77 -114
- data/vendor/v8/samples/shell.cc +232 -46
- data/vendor/v8/src/SConscript +29 -5
- data/vendor/v8/src/accessors.cc +70 -211
- data/vendor/v8/{test/cctest/test-mips.cc → src/allocation-inl.h} +15 -18
- data/vendor/v8/src/allocation.cc +0 -82
- data/vendor/v8/src/allocation.h +9 -42
- data/vendor/v8/src/api.cc +1645 -1156
- data/vendor/v8/src/api.h +76 -12
- data/vendor/v8/src/apiutils.h +0 -7
- data/vendor/v8/src/arguments.h +15 -4
- data/vendor/v8/src/arm/assembler-arm-inl.h +10 -9
- data/vendor/v8/src/arm/assembler-arm.cc +62 -23
- data/vendor/v8/src/arm/assembler-arm.h +76 -11
- data/vendor/v8/src/arm/builtins-arm.cc +39 -33
- data/vendor/v8/src/arm/code-stubs-arm.cc +1182 -402
- data/vendor/v8/src/arm/code-stubs-arm.h +20 -54
- data/vendor/v8/src/arm/codegen-arm.cc +159 -106
- data/vendor/v8/src/arm/codegen-arm.h +6 -6
- data/vendor/v8/src/arm/constants-arm.h +16 -1
- data/vendor/v8/src/arm/cpu-arm.cc +7 -5
- data/vendor/v8/src/arm/debug-arm.cc +6 -4
- data/vendor/v8/src/arm/deoptimizer-arm.cc +51 -14
- data/vendor/v8/src/arm/disasm-arm.cc +47 -15
- data/vendor/v8/src/arm/frames-arm.h +1 -1
- data/vendor/v8/src/arm/full-codegen-arm.cc +724 -408
- data/vendor/v8/src/arm/ic-arm.cc +90 -85
- data/vendor/v8/src/arm/lithium-arm.cc +140 -69
- data/vendor/v8/src/arm/lithium-arm.h +161 -46
- data/vendor/v8/src/arm/lithium-codegen-arm.cc +567 -297
- data/vendor/v8/src/arm/lithium-codegen-arm.h +21 -9
- data/vendor/v8/src/arm/lithium-gap-resolver-arm.cc +2 -0
- data/vendor/v8/src/arm/macro-assembler-arm.cc +457 -96
- data/vendor/v8/src/arm/macro-assembler-arm.h +115 -18
- data/vendor/v8/src/arm/regexp-macro-assembler-arm.cc +20 -13
- data/vendor/v8/src/arm/regexp-macro-assembler-arm.h +1 -0
- data/vendor/v8/src/arm/simulator-arm.cc +184 -101
- data/vendor/v8/src/arm/simulator-arm.h +26 -21
- data/vendor/v8/src/arm/stub-cache-arm.cc +450 -467
- data/vendor/v8/src/arm/virtual-frame-arm.cc +14 -12
- data/vendor/v8/src/arm/virtual-frame-arm.h +11 -8
- data/vendor/v8/src/array.js +35 -18
- data/vendor/v8/src/assembler.cc +186 -92
- data/vendor/v8/src/assembler.h +106 -69
- data/vendor/v8/src/ast-inl.h +5 -0
- data/vendor/v8/src/ast.cc +46 -35
- data/vendor/v8/src/ast.h +107 -50
- data/vendor/v8/src/atomicops.h +2 -0
- data/vendor/v8/src/atomicops_internals_mips_gcc.h +169 -0
- data/vendor/v8/src/bootstrapper.cc +649 -399
- data/vendor/v8/src/bootstrapper.h +94 -27
- data/vendor/v8/src/builtins.cc +359 -227
- data/vendor/v8/src/builtins.h +157 -123
- data/vendor/v8/src/checks.cc +2 -2
- data/vendor/v8/src/checks.h +4 -0
- data/vendor/v8/src/code-stubs.cc +27 -17
- data/vendor/v8/src/code-stubs.h +38 -17
- data/vendor/v8/src/codegen-inl.h +5 -1
- data/vendor/v8/src/codegen.cc +27 -17
- data/vendor/v8/src/codegen.h +9 -9
- data/vendor/v8/src/compilation-cache.cc +92 -206
- data/vendor/v8/src/compilation-cache.h +205 -30
- data/vendor/v8/src/compiler.cc +107 -120
- data/vendor/v8/src/compiler.h +17 -2
- data/vendor/v8/src/contexts.cc +22 -15
- data/vendor/v8/src/contexts.h +14 -8
- data/vendor/v8/src/conversions.cc +86 -30
- data/vendor/v8/src/counters.cc +19 -4
- data/vendor/v8/src/counters.h +28 -16
- data/vendor/v8/src/cpu-profiler-inl.h +4 -3
- data/vendor/v8/src/cpu-profiler.cc +123 -72
- data/vendor/v8/src/cpu-profiler.h +33 -19
- data/vendor/v8/src/cpu.h +2 -0
- data/vendor/v8/src/d8-debug.cc +3 -3
- data/vendor/v8/src/d8-debug.h +7 -6
- data/vendor/v8/src/d8-posix.cc +2 -0
- data/vendor/v8/src/d8.cc +22 -12
- data/vendor/v8/src/d8.gyp +3 -0
- data/vendor/v8/src/d8.js +618 -0
- data/vendor/v8/src/data-flow.h +3 -3
- data/vendor/v8/src/dateparser.h +4 -2
- data/vendor/v8/src/debug-agent.cc +10 -9
- data/vendor/v8/src/debug-agent.h +9 -11
- data/vendor/v8/src/debug-debugger.js +121 -0
- data/vendor/v8/src/debug.cc +331 -227
- data/vendor/v8/src/debug.h +248 -219
- data/vendor/v8/src/deoptimizer.cc +173 -62
- data/vendor/v8/src/deoptimizer.h +119 -19
- data/vendor/v8/src/disasm.h +3 -0
- data/vendor/v8/src/disassembler.cc +10 -9
- data/vendor/v8/src/execution.cc +185 -129
- data/vendor/v8/src/execution.h +47 -78
- data/vendor/v8/src/extensions/experimental/break-iterator.cc +250 -0
- data/vendor/v8/src/extensions/experimental/break-iterator.h +89 -0
- data/vendor/v8/src/extensions/experimental/experimental.gyp +2 -0
- data/vendor/v8/src/extensions/experimental/i18n-extension.cc +22 -2
- data/vendor/v8/src/extensions/externalize-string-extension.cc +2 -2
- data/vendor/v8/src/extensions/gc-extension.cc +1 -1
- data/vendor/v8/src/factory.cc +261 -154
- data/vendor/v8/src/factory.h +162 -158
- data/vendor/v8/src/flag-definitions.h +17 -11
- data/vendor/v8/src/frame-element.cc +0 -5
- data/vendor/v8/src/frame-element.h +9 -13
- data/vendor/v8/src/frames-inl.h +7 -0
- data/vendor/v8/src/frames.cc +56 -46
- data/vendor/v8/src/frames.h +36 -25
- data/vendor/v8/src/full-codegen.cc +15 -24
- data/vendor/v8/src/full-codegen.h +13 -41
- data/vendor/v8/src/func-name-inferrer.cc +7 -6
- data/vendor/v8/src/func-name-inferrer.h +1 -1
- data/vendor/v8/src/gdb-jit.cc +1 -0
- data/vendor/v8/src/global-handles.cc +118 -56
- data/vendor/v8/src/global-handles.h +98 -40
- data/vendor/v8/src/globals.h +2 -2
- data/vendor/v8/src/handles-inl.h +106 -9
- data/vendor/v8/src/handles.cc +220 -157
- data/vendor/v8/src/handles.h +38 -59
- data/vendor/v8/src/hashmap.h +3 -3
- data/vendor/v8/src/heap-inl.h +141 -25
- data/vendor/v8/src/heap-profiler.cc +117 -63
- data/vendor/v8/src/heap-profiler.h +38 -21
- data/vendor/v8/src/heap.cc +805 -564
- data/vendor/v8/src/heap.h +640 -594
- data/vendor/v8/src/hydrogen-instructions.cc +216 -73
- data/vendor/v8/src/hydrogen-instructions.h +259 -124
- data/vendor/v8/src/hydrogen.cc +996 -1171
- data/vendor/v8/src/hydrogen.h +163 -144
- data/vendor/v8/src/ia32/assembler-ia32-inl.h +12 -11
- data/vendor/v8/src/ia32/assembler-ia32.cc +85 -39
- data/vendor/v8/src/ia32/assembler-ia32.h +82 -16
- data/vendor/v8/src/ia32/builtins-ia32.cc +64 -58
- data/vendor/v8/src/ia32/code-stubs-ia32.cc +248 -324
- data/vendor/v8/src/ia32/code-stubs-ia32.h +3 -44
- data/vendor/v8/src/ia32/codegen-ia32.cc +217 -165
- data/vendor/v8/src/ia32/codegen-ia32.h +3 -0
- data/vendor/v8/src/ia32/cpu-ia32.cc +6 -5
- data/vendor/v8/src/ia32/debug-ia32.cc +8 -5
- data/vendor/v8/src/ia32/deoptimizer-ia32.cc +124 -14
- data/vendor/v8/src/ia32/disasm-ia32.cc +85 -62
- data/vendor/v8/src/ia32/frames-ia32.h +1 -1
- data/vendor/v8/src/ia32/full-codegen-ia32.cc +348 -435
- data/vendor/v8/src/ia32/ic-ia32.cc +91 -91
- data/vendor/v8/src/ia32/lithium-codegen-ia32.cc +500 -255
- data/vendor/v8/src/ia32/lithium-codegen-ia32.h +13 -4
- data/vendor/v8/src/ia32/lithium-gap-resolver-ia32.cc +6 -0
- data/vendor/v8/src/ia32/lithium-ia32.cc +122 -45
- data/vendor/v8/src/ia32/lithium-ia32.h +128 -41
- data/vendor/v8/src/ia32/macro-assembler-ia32.cc +109 -84
- data/vendor/v8/src/ia32/macro-assembler-ia32.h +18 -9
- data/vendor/v8/src/ia32/regexp-macro-assembler-ia32.cc +26 -15
- data/vendor/v8/src/ia32/regexp-macro-assembler-ia32.h +1 -0
- data/vendor/v8/src/ia32/register-allocator-ia32.cc +30 -30
- data/vendor/v8/src/ia32/simulator-ia32.h +4 -4
- data/vendor/v8/src/ia32/stub-cache-ia32.cc +383 -400
- data/vendor/v8/src/ia32/virtual-frame-ia32.cc +36 -13
- data/vendor/v8/src/ia32/virtual-frame-ia32.h +11 -5
- data/vendor/v8/src/ic-inl.h +12 -2
- data/vendor/v8/src/ic.cc +304 -221
- data/vendor/v8/src/ic.h +115 -58
- data/vendor/v8/src/interpreter-irregexp.cc +25 -21
- data/vendor/v8/src/interpreter-irregexp.h +2 -1
- data/vendor/v8/src/isolate.cc +883 -0
- data/vendor/v8/src/isolate.h +1304 -0
- data/vendor/v8/src/json.js +10 -10
- data/vendor/v8/src/jsregexp.cc +111 -80
- data/vendor/v8/src/jsregexp.h +6 -7
- data/vendor/v8/src/jump-target-heavy.cc +5 -8
- data/vendor/v8/src/jump-target-heavy.h +0 -6
- data/vendor/v8/src/jump-target-inl.h +1 -1
- data/vendor/v8/src/jump-target-light.cc +3 -3
- data/vendor/v8/src/lithium-allocator-inl.h +2 -0
- data/vendor/v8/src/lithium-allocator.cc +42 -30
- data/vendor/v8/src/lithium-allocator.h +8 -22
- data/vendor/v8/src/lithium.cc +1 -0
- data/vendor/v8/src/liveedit.cc +141 -99
- data/vendor/v8/src/liveedit.h +7 -2
- data/vendor/v8/src/liveobjectlist-inl.h +90 -0
- data/vendor/v8/src/liveobjectlist.cc +2537 -1
- data/vendor/v8/src/liveobjectlist.h +245 -35
- data/vendor/v8/src/log-utils.cc +122 -35
- data/vendor/v8/src/log-utils.h +33 -36
- data/vendor/v8/src/log.cc +299 -241
- data/vendor/v8/src/log.h +177 -110
- data/vendor/v8/src/mark-compact.cc +612 -470
- data/vendor/v8/src/mark-compact.h +153 -80
- data/vendor/v8/src/messages.cc +16 -14
- data/vendor/v8/src/messages.js +30 -7
- data/vendor/v8/src/mips/assembler-mips-inl.h +155 -35
- data/vendor/v8/src/mips/assembler-mips.cc +1093 -219
- data/vendor/v8/src/mips/assembler-mips.h +552 -153
- data/vendor/v8/src/mips/builtins-mips.cc +43 -100
- data/vendor/v8/src/mips/code-stubs-mips.cc +752 -0
- data/vendor/v8/src/mips/code-stubs-mips.h +511 -0
- data/vendor/v8/src/mips/codegen-mips-inl.h +8 -14
- data/vendor/v8/src/mips/codegen-mips.cc +672 -896
- data/vendor/v8/src/mips/codegen-mips.h +271 -69
- data/vendor/v8/src/mips/constants-mips.cc +44 -20
- data/vendor/v8/src/mips/constants-mips.h +238 -40
- data/vendor/v8/src/mips/cpu-mips.cc +20 -3
- data/vendor/v8/src/mips/debug-mips.cc +35 -7
- data/vendor/v8/src/mips/deoptimizer-mips.cc +91 -0
- data/vendor/v8/src/mips/disasm-mips.cc +329 -93
- data/vendor/v8/src/mips/frames-mips.cc +2 -50
- data/vendor/v8/src/mips/frames-mips.h +24 -9
- data/vendor/v8/src/mips/full-codegen-mips.cc +473 -23
- data/vendor/v8/src/mips/ic-mips.cc +81 -45
- data/vendor/v8/src/mips/jump-target-mips.cc +11 -106
- data/vendor/v8/src/mips/lithium-codegen-mips.h +65 -0
- data/vendor/v8/src/mips/lithium-mips.h +304 -0
- data/vendor/v8/src/mips/macro-assembler-mips.cc +2391 -390
- data/vendor/v8/src/mips/macro-assembler-mips.h +718 -121
- data/vendor/v8/src/mips/regexp-macro-assembler-mips.cc +478 -0
- data/vendor/v8/src/mips/regexp-macro-assembler-mips.h +250 -0
- data/vendor/v8/src/mips/register-allocator-mips-inl.h +0 -3
- data/vendor/v8/src/mips/register-allocator-mips.h +3 -2
- data/vendor/v8/src/mips/simulator-mips.cc +1009 -221
- data/vendor/v8/src/mips/simulator-mips.h +119 -36
- data/vendor/v8/src/mips/stub-cache-mips.cc +331 -148
- data/vendor/v8/src/mips/{fast-codegen-mips.cc → virtual-frame-mips-inl.h} +11 -30
- data/vendor/v8/src/mips/virtual-frame-mips.cc +137 -149
- data/vendor/v8/src/mips/virtual-frame-mips.h +294 -312
- data/vendor/v8/src/mirror-debugger.js +9 -8
- data/vendor/v8/src/mksnapshot.cc +2 -2
- data/vendor/v8/src/objects-debug.cc +16 -16
- data/vendor/v8/src/objects-inl.h +421 -195
- data/vendor/v8/src/objects-printer.cc +7 -7
- data/vendor/v8/src/objects-visiting.cc +1 -1
- data/vendor/v8/src/objects-visiting.h +33 -12
- data/vendor/v8/src/objects.cc +935 -658
- data/vendor/v8/src/objects.h +234 -139
- data/vendor/v8/src/parser.cc +484 -439
- data/vendor/v8/src/parser.h +35 -14
- data/vendor/v8/src/platform-cygwin.cc +173 -107
- data/vendor/v8/src/platform-freebsd.cc +224 -72
- data/vendor/v8/src/platform-linux.cc +234 -95
- data/vendor/v8/src/platform-macos.cc +215 -82
- data/vendor/v8/src/platform-nullos.cc +9 -3
- data/vendor/v8/src/platform-openbsd.cc +22 -7
- data/vendor/v8/src/platform-posix.cc +30 -5
- data/vendor/v8/src/platform-solaris.cc +120 -38
- data/vendor/v8/src/platform-tls-mac.h +62 -0
- data/vendor/v8/src/platform-tls-win32.h +62 -0
- data/vendor/v8/src/platform-tls.h +50 -0
- data/vendor/v8/src/platform-win32.cc +195 -97
- data/vendor/v8/src/platform.h +72 -15
- data/vendor/v8/src/preparse-data.cc +2 -0
- data/vendor/v8/src/preparser-api.cc +8 -2
- data/vendor/v8/src/preparser.cc +1 -1
- data/vendor/v8/src/prettyprinter.cc +43 -52
- data/vendor/v8/src/prettyprinter.h +1 -1
- data/vendor/v8/src/profile-generator-inl.h +0 -28
- data/vendor/v8/src/profile-generator.cc +942 -685
- data/vendor/v8/src/profile-generator.h +210 -176
- data/vendor/v8/src/property.cc +6 -0
- data/vendor/v8/src/property.h +14 -3
- data/vendor/v8/src/regexp-macro-assembler-irregexp.cc +1 -1
- data/vendor/v8/src/regexp-macro-assembler.cc +28 -19
- data/vendor/v8/src/regexp-macro-assembler.h +11 -6
- data/vendor/v8/src/regexp-stack.cc +18 -10
- data/vendor/v8/src/regexp-stack.h +45 -21
- data/vendor/v8/src/regexp.js +3 -3
- data/vendor/v8/src/register-allocator-inl.h +3 -3
- data/vendor/v8/src/register-allocator.cc +1 -7
- data/vendor/v8/src/register-allocator.h +5 -15
- data/vendor/v8/src/rewriter.cc +2 -1
- data/vendor/v8/src/runtime-profiler.cc +158 -128
- data/vendor/v8/src/runtime-profiler.h +131 -15
- data/vendor/v8/src/runtime.cc +2409 -1692
- data/vendor/v8/src/runtime.h +93 -17
- data/vendor/v8/src/safepoint-table.cc +3 -0
- data/vendor/v8/src/safepoint-table.h +9 -3
- data/vendor/v8/src/scanner-base.cc +21 -28
- data/vendor/v8/src/scanner-base.h +22 -11
- data/vendor/v8/src/scanner.cc +3 -5
- data/vendor/v8/src/scanner.h +4 -2
- data/vendor/v8/src/scopeinfo.cc +11 -16
- data/vendor/v8/src/scopeinfo.h +26 -15
- data/vendor/v8/src/scopes.cc +67 -37
- data/vendor/v8/src/scopes.h +26 -12
- data/vendor/v8/src/serialize.cc +193 -154
- data/vendor/v8/src/serialize.h +41 -36
- data/vendor/v8/src/small-pointer-list.h +163 -0
- data/vendor/v8/src/snapshot-common.cc +1 -1
- data/vendor/v8/src/snapshot.h +3 -1
- data/vendor/v8/src/spaces-inl.h +30 -25
- data/vendor/v8/src/spaces.cc +263 -370
- data/vendor/v8/src/spaces.h +178 -166
- data/vendor/v8/src/string-search.cc +4 -3
- data/vendor/v8/src/string-search.h +21 -20
- data/vendor/v8/src/string-stream.cc +32 -24
- data/vendor/v8/src/string.js +7 -7
- data/vendor/v8/src/stub-cache.cc +324 -248
- data/vendor/v8/src/stub-cache.h +181 -155
- data/vendor/v8/src/token.cc +3 -3
- data/vendor/v8/src/token.h +3 -3
- data/vendor/v8/src/top.cc +218 -390
- data/vendor/v8/src/type-info.cc +98 -32
- data/vendor/v8/src/type-info.h +10 -3
- data/vendor/v8/src/unicode.cc +1 -1
- data/vendor/v8/src/unicode.h +1 -1
- data/vendor/v8/src/utils.h +3 -0
- data/vendor/v8/src/v8-counters.cc +18 -11
- data/vendor/v8/src/v8-counters.h +34 -13
- data/vendor/v8/src/v8.cc +66 -121
- data/vendor/v8/src/v8.h +7 -4
- data/vendor/v8/src/v8globals.h +18 -12
- data/vendor/v8/src/{memory.h → v8memory.h} +0 -0
- data/vendor/v8/src/v8natives.js +59 -18
- data/vendor/v8/src/v8threads.cc +127 -114
- data/vendor/v8/src/v8threads.h +42 -35
- data/vendor/v8/src/v8utils.h +2 -39
- data/vendor/v8/src/variables.h +1 -1
- data/vendor/v8/src/version.cc +26 -5
- data/vendor/v8/src/version.h +4 -0
- data/vendor/v8/src/virtual-frame-heavy-inl.h +2 -4
- data/vendor/v8/src/virtual-frame-light-inl.h +5 -4
- data/vendor/v8/src/vm-state-inl.h +21 -17
- data/vendor/v8/src/vm-state.h +7 -5
- data/vendor/v8/src/win32-headers.h +1 -0
- data/vendor/v8/src/x64/assembler-x64-inl.h +12 -11
- data/vendor/v8/src/x64/assembler-x64.cc +80 -40
- data/vendor/v8/src/x64/assembler-x64.h +67 -17
- data/vendor/v8/src/x64/builtins-x64.cc +34 -33
- data/vendor/v8/src/x64/code-stubs-x64.cc +636 -377
- data/vendor/v8/src/x64/code-stubs-x64.h +14 -48
- data/vendor/v8/src/x64/codegen-x64-inl.h +1 -1
- data/vendor/v8/src/x64/codegen-x64.cc +158 -136
- data/vendor/v8/src/x64/codegen-x64.h +4 -1
- data/vendor/v8/src/x64/cpu-x64.cc +7 -5
- data/vendor/v8/src/x64/debug-x64.cc +8 -6
- data/vendor/v8/src/x64/deoptimizer-x64.cc +195 -20
- data/vendor/v8/src/x64/disasm-x64.cc +42 -23
- data/vendor/v8/src/x64/frames-x64.cc +1 -1
- data/vendor/v8/src/x64/frames-x64.h +2 -2
- data/vendor/v8/src/x64/full-codegen-x64.cc +780 -218
- data/vendor/v8/src/x64/ic-x64.cc +77 -79
- data/vendor/v8/src/x64/jump-target-x64.cc +1 -1
- data/vendor/v8/src/x64/lithium-codegen-x64.cc +698 -181
- data/vendor/v8/src/x64/lithium-codegen-x64.h +31 -6
- data/vendor/v8/src/x64/lithium-x64.cc +136 -54
- data/vendor/v8/src/x64/lithium-x64.h +142 -51
- data/vendor/v8/src/x64/macro-assembler-x64.cc +456 -187
- data/vendor/v8/src/x64/macro-assembler-x64.h +166 -34
- data/vendor/v8/src/x64/regexp-macro-assembler-x64.cc +44 -28
- data/vendor/v8/src/x64/regexp-macro-assembler-x64.h +8 -4
- data/vendor/v8/src/x64/register-allocator-x64-inl.h +3 -3
- data/vendor/v8/src/x64/register-allocator-x64.cc +12 -8
- data/vendor/v8/src/x64/simulator-x64.h +5 -5
- data/vendor/v8/src/x64/stub-cache-x64.cc +299 -344
- data/vendor/v8/src/x64/virtual-frame-x64.cc +37 -13
- data/vendor/v8/src/x64/virtual-frame-x64.h +13 -7
- data/vendor/v8/src/zone-inl.h +49 -3
- data/vendor/v8/src/zone.cc +42 -41
- data/vendor/v8/src/zone.h +37 -34
- data/vendor/v8/test/benchmarks/testcfg.py +100 -0
- data/vendor/v8/test/cctest/SConscript +5 -4
- data/vendor/v8/test/cctest/cctest.h +3 -2
- data/vendor/v8/test/cctest/cctest.status +6 -11
- data/vendor/v8/test/cctest/test-accessors.cc +3 -3
- data/vendor/v8/test/cctest/test-alloc.cc +39 -33
- data/vendor/v8/test/cctest/test-api.cc +1092 -205
- data/vendor/v8/test/cctest/test-assembler-arm.cc +39 -25
- data/vendor/v8/test/cctest/test-assembler-ia32.cc +36 -37
- data/vendor/v8/test/cctest/test-assembler-mips.cc +1098 -40
- data/vendor/v8/test/cctest/test-assembler-x64.cc +32 -25
- data/vendor/v8/test/cctest/test-ast.cc +1 -0
- data/vendor/v8/test/cctest/test-circular-queue.cc +8 -5
- data/vendor/v8/test/cctest/test-compiler.cc +24 -24
- data/vendor/v8/test/cctest/test-cpu-profiler.cc +140 -5
- data/vendor/v8/test/cctest/test-dataflow.cc +1 -0
- data/vendor/v8/test/cctest/test-debug.cc +136 -77
- data/vendor/v8/test/cctest/test-decls.cc +1 -1
- data/vendor/v8/test/cctest/test-deoptimization.cc +25 -24
- data/vendor/v8/test/cctest/test-disasm-arm.cc +9 -4
- data/vendor/v8/test/cctest/test-disasm-ia32.cc +10 -8
- data/vendor/v8/test/cctest/test-func-name-inference.cc +10 -4
- data/vendor/v8/test/cctest/test-heap-profiler.cc +226 -164
- data/vendor/v8/test/cctest/test-heap.cc +240 -217
- data/vendor/v8/test/cctest/test-liveedit.cc +1 -0
- data/vendor/v8/test/cctest/test-log-stack-tracer.cc +18 -20
- data/vendor/v8/test/cctest/test-log.cc +114 -108
- data/vendor/v8/test/cctest/test-macro-assembler-x64.cc +247 -177
- data/vendor/v8/test/cctest/test-mark-compact.cc +129 -90
- data/vendor/v8/test/cctest/test-parsing.cc +15 -14
- data/vendor/v8/test/cctest/test-platform-linux.cc +1 -0
- data/vendor/v8/test/cctest/test-platform-tls.cc +66 -0
- data/vendor/v8/test/cctest/test-platform-win32.cc +1 -0
- data/vendor/v8/test/cctest/test-profile-generator.cc +1 -1
- data/vendor/v8/test/cctest/test-regexp.cc +53 -41
- data/vendor/v8/test/cctest/test-reloc-info.cc +18 -11
- data/vendor/v8/test/cctest/test-serialize.cc +44 -43
- data/vendor/v8/test/cctest/test-sockets.cc +8 -3
- data/vendor/v8/test/cctest/test-spaces.cc +47 -29
- data/vendor/v8/test/cctest/test-strings.cc +20 -20
- data/vendor/v8/test/cctest/test-thread-termination.cc +8 -3
- data/vendor/v8/test/cctest/test-threads.cc +5 -3
- data/vendor/v8/test/cctest/test-utils.cc +5 -4
- data/vendor/v8/test/cctest/testcfg.py +7 -3
- data/vendor/v8/test/es5conform/es5conform.status +2 -77
- data/vendor/v8/test/es5conform/testcfg.py +1 -1
- data/vendor/v8/test/message/testcfg.py +1 -1
- data/vendor/v8/test/mjsunit/accessors-on-global-object.js +3 -3
- data/vendor/v8/test/mjsunit/array-concat.js +43 -1
- data/vendor/v8/test/mjsunit/array-join.js +25 -0
- data/vendor/v8/test/mjsunit/bitops-info.js +7 -1
- data/vendor/v8/test/mjsunit/compiler/array-length.js +2 -2
- data/vendor/v8/test/mjsunit/compiler/global-accessors.js +47 -0
- data/vendor/v8/test/mjsunit/compiler/pic.js +1 -1
- data/vendor/v8/test/mjsunit/compiler/regress-loadfield.js +65 -0
- data/vendor/v8/test/mjsunit/math-sqrt.js +5 -1
- data/vendor/v8/test/mjsunit/mjsunit.js +59 -8
- data/vendor/v8/test/mjsunit/mjsunit.status +0 -12
- data/vendor/v8/test/mjsunit/mul-exhaustive.js +129 -11
- data/vendor/v8/test/mjsunit/negate-zero.js +1 -1
- data/vendor/v8/test/mjsunit/object-freeze.js +5 -13
- data/vendor/v8/test/mjsunit/object-prevent-extensions.js +9 -50
- data/vendor/v8/test/mjsunit/object-seal.js +4 -13
- data/vendor/v8/test/mjsunit/override-eval-with-non-function.js +36 -0
- data/vendor/v8/test/mjsunit/regress/regress-1145.js +54 -0
- data/vendor/v8/test/mjsunit/regress/regress-1172-bis.js +37 -0
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- data/vendor/v8/test/mjsunit/regress/regress-1218.js +29 -0
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- data/vendor/v8/test/mjsunit/regress/regress-1278.js +69 -0
- data/vendor/v8/test/mjsunit/regress/regress-create-exception.js +1 -0
- data/vendor/v8/test/mjsunit/regress/regress-lazy-deopt-reloc.js +52 -0
- data/vendor/v8/test/mjsunit/sin-cos.js +15 -10
- data/vendor/v8/test/mjsunit/smi-negative-zero.js +2 -2
- data/vendor/v8/test/mjsunit/str-to-num.js +1 -1
- data/vendor/v8/test/mjsunit/strict-mode.js +435 -0
- data/vendor/v8/test/mjsunit/testcfg.py +23 -6
- data/vendor/v8/test/mozilla/mozilla.status +0 -2
- data/vendor/v8/test/mozilla/testcfg.py +1 -1
- data/vendor/v8/test/preparser/empty.js +28 -0
- data/vendor/v8/test/preparser/functions-only.js +38 -0
- data/vendor/v8/test/preparser/non-alphanum.js +34 -0
- data/vendor/v8/test/preparser/symbols-only.js +49 -0
- data/vendor/v8/test/preparser/testcfg.py +90 -0
- data/vendor/v8/test/sputnik/testcfg.py +1 -1
- data/vendor/v8/test/test262/README +16 -0
- data/vendor/v8/test/test262/harness-adapt.js +80 -0
- data/vendor/v8/test/test262/test262.status +1506 -0
- data/vendor/v8/test/test262/testcfg.py +123 -0
- data/vendor/v8/tools/freebsd-tick-processor +10 -0
- data/vendor/v8/tools/gyp/v8.gyp +8 -33
- data/vendor/v8/tools/linux-tick-processor +5 -3
- data/vendor/v8/tools/test.py +37 -14
- data/vendor/v8/tools/tickprocessor.js +22 -8
- data/vendor/v8/tools/visual_studio/v8_base.vcproj +13 -1
- data/vendor/v8/tools/visual_studio/v8_base_arm.vcproj +5 -1
- data/vendor/v8/tools/visual_studio/v8_base_x64.vcproj +5 -1
- data/vendor/v8/tools/visual_studio/x64.vsprops +1 -0
- metadata +1495 -1341
- data/ext/extconf.rb +0 -22
- data/ext/mustang.cpp +0 -58
- data/vendor/v8/src/top.h +0 -608
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// Copyright 2006-2010 the V8 project authors. All rights reserved.
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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class RegExpMacroAssemblerMIPS: public RegExpMacroAssembler {
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RegExpMacroAssemblerMIPS();
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};
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class RegExpMacroAssemblerMIPS: public NativeRegExpMacroAssembler {
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RegExpMacroAssemblerMIPS(Mode mode, int registers_to_save);
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virtual ~RegExpMacroAssemblerMIPS();
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uint32_t mask,
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Label* on_equal);
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virtual void GoTo(Label* label);
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Label* on_end_of_input,
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int characters = 1);
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StackCheckFlag check_stack_limit);
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virtual void ReadCurrentPositionFromRegister(int reg);
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virtual void Succeed();
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static const int kInputEnd = kFramePointer - kPointerSize;
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static const int kInputStart = kInputEnd - kPointerSize;
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static const int kStartIndex = kInputStart - kPointerSize;
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static const int kInputString = kStartIndex - kPointerSize;
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|
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// the frame in GetCode.
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static const int kInputStartMinusOne = kInputString - kPointerSize;
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static const int kAtStart = kInputStartMinusOne - kPointerSize;
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// First register address. Following registers are below it on the stack.
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static const size_t kRegExpCodeSize = 1024;
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void LoadCurrentCharacterUnchecked(int cp_offset, int character_count);
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void CheckPreemption();
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void CheckStackLimit();
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void CallCheckStackGuardState(Register scratch);
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MemOperand register_location(int register_index);
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|
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// the end of the string.
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inline Register current_input_offset() { return t2; }
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inline Register current_character() { return t3; }
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// Register holding address of the end of the input string.
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inline Register end_of_input_address() { return t6; }
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// Register holding the frame address. Local variables, parameters and
|
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inline Register frame_pointer() { return fp; }
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// name to the register.
|
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inline Register backtrack_stackpointer() { return t4; }
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// Register holding pointer to the current code object.
|
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inline Register code_pointer() { return t1; }
|
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// Byte size of chars in the string to match (decided by the Mode argument)
|
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inline int char_size() { return static_cast<int>(mode_); }
|
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|
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// Equivalent to a conditional branch to the label, unless the label
|
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// is NULL, in which case it is a conditional Backtrack.
|
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void BranchOrBacktrack(Label* to,
|
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Condition condition,
|
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Register rs,
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const Operand& rt);
|
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|
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// Call and return internally in the generated code in a way that
|
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// is GC-safe (i.e., doesn't leave absolute code addresses on the stack)
|
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inline void SafeCall(Label* to,
|
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Condition cond,
|
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Register rs,
|
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const Operand& rt);
|
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inline void SafeReturn();
|
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inline void SafeCallTarget(Label* name);
|
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|
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// Pushes the value of a register on the backtrack stack. Decrements the
|
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// stack pointer by a word size and stores the register's value there.
|
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|
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inline void Push(Register source);
|
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+
|
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|
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// Pops a value from the backtrack stack. Reads the word at the stack pointer
|
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// and increments it by a word size.
|
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inline void Pop(Register target);
|
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|
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|
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// Calls a C function and cleans up the frame alignment done by
|
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|
+
// by FrameAlign. The called function *is* allowed to trigger a garbage
|
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|
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// collection, but may not take more than four arguments (no arguments
|
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// passed on the stack), and the first argument will be a pointer to the
|
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// return address.
|
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|
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inline void CallCFunctionUsingStub(ExternalReference function,
|
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+
int num_arguments);
|
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+
|
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+
|
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|
+
MacroAssembler* masm_;
|
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|
+
|
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|
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// Which mode to generate code for (ASCII or UC16).
|
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Mode mode_;
|
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|
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|
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// One greater than maximal register index actually used.
|
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+
int num_registers_;
|
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|
+
|
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|
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// Number of registers to output at the end (the saved registers
|
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|
+
// are always 0..num_saved_registers_-1)
|
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|
+
int num_saved_registers_;
|
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|
+
|
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|
+
// Labels used internally.
|
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|
+
Label entry_label_;
|
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|
+
Label start_label_;
|
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|
+
Label success_label_;
|
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Label backtrack_label_;
|
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|
+
Label exit_label_;
|
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|
+
Label check_preempt_label_;
|
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|
+
Label stack_overflow_label_;
|
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|
+
};
|
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|
+
|
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|
+
#endif // V8_INTERPRETED_REGEXP
|
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|
+
|
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|
+
|
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|
+
}} // namespace v8::internal
|
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|
+
|
249
|
+
#endif // V8_MIPS_REGEXP_MACRO_ASSEMBLER_MIPS_H_
|
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|
+
|
@@ -125,9 +125,6 @@ Register RegisterAllocator::ToRegister(int num) {
|
|
125
125
|
|
126
126
|
void RegisterAllocator::Initialize() {
|
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127
|
Reset();
|
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|
-
// The non-reserved a1 and ra registers are live on JS function entry.
|
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|
-
Use(a1); // JS function.
|
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|
-
Use(ra); // Return address.
|
131
128
|
}
|
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129
|
|
133
130
|
|
@@ -35,8 +35,9 @@ namespace internal {
|
|
35
35
|
|
36
36
|
class RegisterAllocatorConstants : public AllStatic {
|
37
37
|
public:
|
38
|
-
|
39
|
-
static const int
|
38
|
+
// No registers are currently managed by the register allocator on MIPS.
|
39
|
+
static const int kNumRegisters = 0;
|
40
|
+
static const int kInvalidRegister = -1;
|
40
41
|
};
|
41
42
|
|
42
43
|
|
@@ -26,6 +26,8 @@
|
|
26
26
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
27
27
|
|
28
28
|
#include <stdlib.h>
|
29
|
+
#include <math.h>
|
30
|
+
#include <limits.h>
|
29
31
|
#include <cstdarg>
|
30
32
|
#include "v8.h"
|
31
33
|
|
@@ -37,23 +39,25 @@
|
|
37
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|
#include "mips/constants-mips.h"
|
38
40
|
#include "mips/simulator-mips.h"
|
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41
|
|
40
|
-
namespace v8i = v8::internal;
|
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|
-
|
42
|
-
#if !defined(__mips) || defined(USE_SIMULATOR)
|
43
42
|
|
44
43
|
// Only build the simulator if not compiling for real MIPS hardware.
|
45
|
-
|
46
|
-
namespace mips {
|
44
|
+
#if defined(USE_SIMULATOR)
|
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45
|
|
48
|
-
|
49
|
-
|
50
|
-
using ::v8::internal::OS;
|
51
|
-
using ::v8::internal::ReadLine;
|
52
|
-
using ::v8::internal::DeleteArray;
|
46
|
+
namespace v8 {
|
47
|
+
namespace internal {
|
53
48
|
|
54
49
|
// Utils functions
|
55
50
|
bool HaveSameSign(int32_t a, int32_t b) {
|
56
|
-
return ((a ^ b)
|
51
|
+
return ((a ^ b) >= 0);
|
52
|
+
}
|
53
|
+
|
54
|
+
|
55
|
+
uint32_t get_fcsr_condition_bit(uint32_t cc) {
|
56
|
+
if (cc == 0) {
|
57
|
+
return 23;
|
58
|
+
} else {
|
59
|
+
return 24 + cc;
|
60
|
+
}
|
57
61
|
}
|
58
62
|
|
59
63
|
|
@@ -63,15 +67,18 @@ bool HaveSameSign(int32_t a, int32_t b) {
|
|
63
67
|
// Library does not provide vsscanf.
|
64
68
|
#define SScanF sscanf // NOLINT
|
65
69
|
|
66
|
-
// The
|
70
|
+
// The MipsDebugger class is used by the simulator while debugging simulated
|
67
71
|
// code.
|
68
|
-
class
|
72
|
+
class MipsDebugger {
|
69
73
|
public:
|
70
|
-
explicit
|
71
|
-
~
|
74
|
+
explicit MipsDebugger(Simulator* sim);
|
75
|
+
~MipsDebugger();
|
72
76
|
|
73
77
|
void Stop(Instruction* instr);
|
74
78
|
void Debug();
|
79
|
+
// Print all registers with a nice formatting.
|
80
|
+
void PrintAllRegs();
|
81
|
+
void PrintAllRegsIncludingFPU();
|
75
82
|
|
76
83
|
private:
|
77
84
|
// We set the breakpoint code to 0xfffff to easily recognize it.
|
@@ -81,6 +88,10 @@ class Debugger {
|
|
81
88
|
Simulator* sim_;
|
82
89
|
|
83
90
|
int32_t GetRegisterValue(int regnum);
|
91
|
+
int32_t GetFPURegisterValueInt(int regnum);
|
92
|
+
int64_t GetFPURegisterValueLong(int regnum);
|
93
|
+
float GetFPURegisterValueFloat(int regnum);
|
94
|
+
double GetFPURegisterValueDouble(int regnum);
|
84
95
|
bool GetValue(const char* desc, int32_t* value);
|
85
96
|
|
86
97
|
// Set or delete a breakpoint. Returns true if successful.
|
@@ -91,18 +102,17 @@ class Debugger {
|
|
91
102
|
// execution to skip past breakpoints when run from the debugger.
|
92
103
|
void UndoBreakpoints();
|
93
104
|
void RedoBreakpoints();
|
94
|
-
|
95
|
-
// Print all registers with a nice formatting.
|
96
|
-
void PrintAllRegs();
|
97
105
|
};
|
98
106
|
|
99
|
-
|
107
|
+
MipsDebugger::MipsDebugger(Simulator* sim) {
|
100
108
|
sim_ = sim;
|
101
109
|
}
|
102
110
|
|
103
|
-
|
111
|
+
|
112
|
+
MipsDebugger::~MipsDebugger() {
|
104
113
|
}
|
105
114
|
|
115
|
+
|
106
116
|
#ifdef GENERATED_CODE_COVERAGE
|
107
117
|
static FILE* coverage_log = NULL;
|
108
118
|
|
@@ -115,7 +125,7 @@ static void InitializeCoverage() {
|
|
115
125
|
}
|
116
126
|
|
117
127
|
|
118
|
-
void
|
128
|
+
void MipsDebugger::Stop(Instruction* instr) {
|
119
129
|
UNIMPLEMENTED_MIPS();
|
120
130
|
char* str = reinterpret_cast<char*>(instr->InstructionBits());
|
121
131
|
if (strlen(str) > 0) {
|
@@ -125,9 +135,10 @@ void Debugger::Stop(Instruction* instr) {
|
|
125
135
|
}
|
126
136
|
instr->SetInstructionBits(0x0); // Overwrite with nop.
|
127
137
|
}
|
128
|
-
sim_->set_pc(sim_->get_pc() + Instruction::
|
138
|
+
sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize);
|
129
139
|
}
|
130
140
|
|
141
|
+
|
131
142
|
#else // ndef GENERATED_CODE_COVERAGE
|
132
143
|
|
133
144
|
#define UNSUPPORTED() printf("Unsupported instruction.\n");
|
@@ -135,16 +146,16 @@ void Debugger::Stop(Instruction* instr) {
|
|
135
146
|
static void InitializeCoverage() {}
|
136
147
|
|
137
148
|
|
138
|
-
void
|
149
|
+
void MipsDebugger::Stop(Instruction* instr) {
|
139
150
|
const char* str = reinterpret_cast<char*>(instr->InstructionBits());
|
140
151
|
PrintF("Simulator hit %s\n", str);
|
141
|
-
sim_->set_pc(sim_->get_pc() + Instruction::
|
152
|
+
sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize);
|
142
153
|
Debug();
|
143
154
|
}
|
144
155
|
#endif // GENERATED_CODE_COVERAGE
|
145
156
|
|
146
157
|
|
147
|
-
int32_t
|
158
|
+
int32_t MipsDebugger::GetRegisterValue(int regnum) {
|
148
159
|
if (regnum == kNumSimuRegisters) {
|
149
160
|
return sim_->get_pc();
|
150
161
|
} else {
|
@@ -153,11 +164,54 @@ int32_t Debugger::GetRegisterValue(int regnum) {
|
|
153
164
|
}
|
154
165
|
|
155
166
|
|
156
|
-
|
167
|
+
int32_t MipsDebugger::GetFPURegisterValueInt(int regnum) {
|
168
|
+
if (regnum == kNumFPURegisters) {
|
169
|
+
return sim_->get_pc();
|
170
|
+
} else {
|
171
|
+
return sim_->get_fpu_register(regnum);
|
172
|
+
}
|
173
|
+
}
|
174
|
+
|
175
|
+
|
176
|
+
int64_t MipsDebugger::GetFPURegisterValueLong(int regnum) {
|
177
|
+
if (regnum == kNumFPURegisters) {
|
178
|
+
return sim_->get_pc();
|
179
|
+
} else {
|
180
|
+
return sim_->get_fpu_register_long(regnum);
|
181
|
+
}
|
182
|
+
}
|
183
|
+
|
184
|
+
|
185
|
+
float MipsDebugger::GetFPURegisterValueFloat(int regnum) {
|
186
|
+
if (regnum == kNumFPURegisters) {
|
187
|
+
return sim_->get_pc();
|
188
|
+
} else {
|
189
|
+
return sim_->get_fpu_register_float(regnum);
|
190
|
+
}
|
191
|
+
}
|
192
|
+
|
193
|
+
|
194
|
+
double MipsDebugger::GetFPURegisterValueDouble(int regnum) {
|
195
|
+
if (regnum == kNumFPURegisters) {
|
196
|
+
return sim_->get_pc();
|
197
|
+
} else {
|
198
|
+
return sim_->get_fpu_register_double(regnum);
|
199
|
+
}
|
200
|
+
}
|
201
|
+
|
202
|
+
|
203
|
+
bool MipsDebugger::GetValue(const char* desc, int32_t* value) {
|
157
204
|
int regnum = Registers::Number(desc);
|
205
|
+
int fpuregnum = FPURegisters::Number(desc);
|
206
|
+
|
158
207
|
if (regnum != kInvalidRegister) {
|
159
208
|
*value = GetRegisterValue(regnum);
|
160
209
|
return true;
|
210
|
+
} else if (fpuregnum != kInvalidFPURegister) {
|
211
|
+
*value = GetFPURegisterValueInt(fpuregnum);
|
212
|
+
return true;
|
213
|
+
} else if (strncmp(desc, "0x", 2) == 0) {
|
214
|
+
return SScanF(desc, "%x", reinterpret_cast<uint32_t*>(value)) == 1;
|
161
215
|
} else {
|
162
216
|
return SScanF(desc, "%i", value) == 1;
|
163
217
|
}
|
@@ -165,7 +219,7 @@ bool Debugger::GetValue(const char* desc, int32_t* value) {
|
|
165
219
|
}
|
166
220
|
|
167
221
|
|
168
|
-
bool
|
222
|
+
bool MipsDebugger::SetBreakpoint(Instruction* breakpc) {
|
169
223
|
// Check if a breakpoint can be set. If not return without any side-effects.
|
170
224
|
if (sim_->break_pc_ != NULL) {
|
171
225
|
return false;
|
@@ -180,7 +234,7 @@ bool Debugger::SetBreakpoint(Instruction* breakpc) {
|
|
180
234
|
}
|
181
235
|
|
182
236
|
|
183
|
-
bool
|
237
|
+
bool MipsDebugger::DeleteBreakpoint(Instruction* breakpc) {
|
184
238
|
if (sim_->break_pc_ != NULL) {
|
185
239
|
sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
|
186
240
|
}
|
@@ -191,20 +245,21 @@ bool Debugger::DeleteBreakpoint(Instruction* breakpc) {
|
|
191
245
|
}
|
192
246
|
|
193
247
|
|
194
|
-
void
|
248
|
+
void MipsDebugger::UndoBreakpoints() {
|
195
249
|
if (sim_->break_pc_ != NULL) {
|
196
250
|
sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
|
197
251
|
}
|
198
252
|
}
|
199
253
|
|
200
254
|
|
201
|
-
void
|
255
|
+
void MipsDebugger::RedoBreakpoints() {
|
202
256
|
if (sim_->break_pc_ != NULL) {
|
203
257
|
sim_->break_pc_->SetInstructionBits(kBreakpointInstr);
|
204
258
|
}
|
205
259
|
}
|
206
260
|
|
207
|
-
|
261
|
+
|
262
|
+
void MipsDebugger::PrintAllRegs() {
|
208
263
|
#define REG_INFO(n) Registers::Name(n), GetRegisterValue(n), GetRegisterValue(n)
|
209
264
|
|
210
265
|
PrintF("\n");
|
@@ -237,10 +292,45 @@ void Debugger::PrintAllRegs() {
|
|
237
292
|
// pc
|
238
293
|
PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n",
|
239
294
|
REG_INFO(31), REG_INFO(34));
|
295
|
+
|
296
|
+
#undef REG_INFO
|
297
|
+
#undef FPU_REG_INFO
|
298
|
+
}
|
299
|
+
|
300
|
+
|
301
|
+
void MipsDebugger::PrintAllRegsIncludingFPU() {
|
302
|
+
#define FPU_REG_INFO(n) FPURegisters::Name(n), FPURegisters::Name(n+1), \
|
303
|
+
GetFPURegisterValueInt(n+1), \
|
304
|
+
GetFPURegisterValueInt(n), \
|
305
|
+
GetFPURegisterValueDouble(n)
|
306
|
+
|
307
|
+
PrintAllRegs();
|
308
|
+
|
309
|
+
PrintF("\n\n");
|
310
|
+
// f0, f1, f2, ... f31
|
311
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(0) );
|
312
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(2) );
|
313
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(4) );
|
314
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(6) );
|
315
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(8) );
|
316
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(10));
|
317
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(12));
|
318
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(14));
|
319
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(16));
|
320
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(18));
|
321
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(20));
|
322
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(22));
|
323
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(24));
|
324
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(26));
|
325
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(28));
|
326
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(30));
|
327
|
+
|
240
328
|
#undef REG_INFO
|
329
|
+
#undef FPU_REG_INFO
|
241
330
|
}
|
242
331
|
|
243
|
-
|
332
|
+
|
333
|
+
void MipsDebugger::Debug() {
|
244
334
|
intptr_t last_pc = -1;
|
245
335
|
bool done = false;
|
246
336
|
|
@@ -253,6 +343,7 @@ void Debugger::Debug() {
|
|
253
343
|
char cmd[COMMAND_SIZE + 1];
|
254
344
|
char arg1[ARG_SIZE + 1];
|
255
345
|
char arg2[ARG_SIZE + 1];
|
346
|
+
char* argv[3] = { cmd, arg1, arg2 };
|
256
347
|
|
257
348
|
// make sure to have a proper terminating character if reaching the limit
|
258
349
|
cmd[COMMAND_SIZE] = 0;
|
@@ -280,19 +371,21 @@ void Debugger::Debug() {
|
|
280
371
|
} else {
|
281
372
|
// Use sscanf to parse the individual parts of the command line. At the
|
282
373
|
// moment no command expects more than two parameters.
|
283
|
-
int
|
374
|
+
int argc = SScanF(line,
|
284
375
|
"%" XSTR(COMMAND_SIZE) "s "
|
285
376
|
"%" XSTR(ARG_SIZE) "s "
|
286
377
|
"%" XSTR(ARG_SIZE) "s",
|
287
378
|
cmd, arg1, arg2);
|
288
379
|
if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) {
|
289
|
-
|
380
|
+
Instruction* instr = reinterpret_cast<Instruction*>(sim_->get_pc());
|
381
|
+
if (!(instr->IsTrap()) ||
|
382
|
+
instr->InstructionBits() == rtCallRedirInstr) {
|
290
383
|
sim_->InstructionDecode(
|
291
|
-
|
384
|
+
reinterpret_cast<Instruction*>(sim_->get_pc()));
|
292
385
|
} else {
|
293
386
|
// Allow si to jump over generated breakpoints.
|
294
387
|
PrintF("/!\\ Jumping over generated breakpoint.\n");
|
295
|
-
sim_->set_pc(sim_->get_pc() + Instruction::
|
388
|
+
sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize);
|
296
389
|
}
|
297
390
|
} else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) {
|
298
391
|
// Execute the one instruction we broke at with breakpoints disabled.
|
@@ -300,23 +393,65 @@ void Debugger::Debug() {
|
|
300
393
|
// Leave the debugger shell.
|
301
394
|
done = true;
|
302
395
|
} else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) {
|
303
|
-
if (
|
396
|
+
if (argc == 2) {
|
304
397
|
int32_t value;
|
398
|
+
float fvalue;
|
305
399
|
if (strcmp(arg1, "all") == 0) {
|
306
400
|
PrintAllRegs();
|
401
|
+
} else if (strcmp(arg1, "allf") == 0) {
|
402
|
+
PrintAllRegsIncludingFPU();
|
307
403
|
} else {
|
308
|
-
|
404
|
+
int regnum = Registers::Number(arg1);
|
405
|
+
int fpuregnum = FPURegisters::Number(arg1);
|
406
|
+
|
407
|
+
if (regnum != kInvalidRegister) {
|
408
|
+
value = GetRegisterValue(regnum);
|
309
409
|
PrintF("%s: 0x%08x %d \n", arg1, value, value);
|
410
|
+
} else if (fpuregnum != kInvalidFPURegister) {
|
411
|
+
if (fpuregnum % 2 == 1) {
|
412
|
+
value = GetFPURegisterValueInt(fpuregnum);
|
413
|
+
fvalue = GetFPURegisterValueFloat(fpuregnum);
|
414
|
+
PrintF("%s: 0x%08x %11.4e\n", arg1, value, fvalue);
|
415
|
+
} else {
|
416
|
+
double dfvalue;
|
417
|
+
int32_t lvalue1 = GetFPURegisterValueInt(fpuregnum);
|
418
|
+
int32_t lvalue2 = GetFPURegisterValueInt(fpuregnum + 1);
|
419
|
+
dfvalue = GetFPURegisterValueDouble(fpuregnum);
|
420
|
+
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n",
|
421
|
+
FPURegisters::Name(fpuregnum+1),
|
422
|
+
FPURegisters::Name(fpuregnum),
|
423
|
+
lvalue1,
|
424
|
+
lvalue2,
|
425
|
+
dfvalue);
|
426
|
+
}
|
310
427
|
} else {
|
311
428
|
PrintF("%s unrecognized\n", arg1);
|
312
429
|
}
|
313
430
|
}
|
314
431
|
} else {
|
315
|
-
|
432
|
+
if (argc == 3) {
|
433
|
+
if (strcmp(arg2, "single") == 0) {
|
434
|
+
int32_t value;
|
435
|
+
float fvalue;
|
436
|
+
int fpuregnum = FPURegisters::Number(arg1);
|
437
|
+
|
438
|
+
if (fpuregnum != kInvalidFPURegister) {
|
439
|
+
value = GetFPURegisterValueInt(fpuregnum);
|
440
|
+
fvalue = GetFPURegisterValueFloat(fpuregnum);
|
441
|
+
PrintF("%s: 0x%08x %11.4e\n", arg1, value, fvalue);
|
442
|
+
} else {
|
443
|
+
PrintF("%s unrecognized\n", arg1);
|
444
|
+
}
|
445
|
+
} else {
|
446
|
+
PrintF("print <fpu register> single\n");
|
447
|
+
}
|
448
|
+
} else {
|
449
|
+
PrintF("print <register> or print <fpu register> single\n");
|
450
|
+
}
|
316
451
|
}
|
317
452
|
} else if ((strcmp(cmd, "po") == 0)
|
318
453
|
|| (strcmp(cmd, "printobject") == 0)) {
|
319
|
-
if (
|
454
|
+
if (argc == 2) {
|
320
455
|
int32_t value;
|
321
456
|
if (GetValue(arg1, &value)) {
|
322
457
|
Object* obj = reinterpret_cast<Object*>(value);
|
@@ -333,6 +468,39 @@ void Debugger::Debug() {
|
|
333
468
|
} else {
|
334
469
|
PrintF("printobject <value>\n");
|
335
470
|
}
|
471
|
+
} else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) {
|
472
|
+
int32_t* cur = NULL;
|
473
|
+
int32_t* end = NULL;
|
474
|
+
int next_arg = 1;
|
475
|
+
|
476
|
+
if (strcmp(cmd, "stack") == 0) {
|
477
|
+
cur = reinterpret_cast<int32_t*>(sim_->get_register(Simulator::sp));
|
478
|
+
} else { // "mem"
|
479
|
+
int32_t value;
|
480
|
+
if (!GetValue(arg1, &value)) {
|
481
|
+
PrintF("%s unrecognized\n", arg1);
|
482
|
+
continue;
|
483
|
+
}
|
484
|
+
cur = reinterpret_cast<int32_t*>(value);
|
485
|
+
next_arg++;
|
486
|
+
}
|
487
|
+
|
488
|
+
int32_t words;
|
489
|
+
if (argc == next_arg) {
|
490
|
+
words = 10;
|
491
|
+
} else if (argc == next_arg + 1) {
|
492
|
+
if (!GetValue(argv[next_arg], &words)) {
|
493
|
+
words = 10;
|
494
|
+
}
|
495
|
+
}
|
496
|
+
end = cur + words;
|
497
|
+
|
498
|
+
while (cur < end) {
|
499
|
+
PrintF(" 0x%08x: 0x%08x %10d\n",
|
500
|
+
reinterpret_cast<intptr_t>(cur), *cur, *cur);
|
501
|
+
cur++;
|
502
|
+
}
|
503
|
+
|
336
504
|
} else if ((strcmp(cmd, "disasm") == 0) || (strcmp(cmd, "dpc") == 0)) {
|
337
505
|
disasm::NameConverter converter;
|
338
506
|
disasm::Disassembler dasm(converter);
|
@@ -342,36 +510,37 @@ void Debugger::Debug() {
|
|
342
510
|
byte_* cur = NULL;
|
343
511
|
byte_* end = NULL;
|
344
512
|
|
345
|
-
if (
|
513
|
+
if (argc == 1) {
|
346
514
|
cur = reinterpret_cast<byte_*>(sim_->get_pc());
|
347
|
-
end = cur + (10 * Instruction::
|
348
|
-
} else if (
|
515
|
+
end = cur + (10 * Instruction::kInstrSize);
|
516
|
+
} else if (argc == 2) {
|
349
517
|
int32_t value;
|
350
518
|
if (GetValue(arg1, &value)) {
|
351
519
|
cur = reinterpret_cast<byte_*>(value);
|
352
520
|
// no length parameter passed, assume 10 instructions
|
353
|
-
end = cur + (10 * Instruction::
|
521
|
+
end = cur + (10 * Instruction::kInstrSize);
|
354
522
|
}
|
355
523
|
} else {
|
356
524
|
int32_t value1;
|
357
525
|
int32_t value2;
|
358
526
|
if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) {
|
359
527
|
cur = reinterpret_cast<byte_*>(value1);
|
360
|
-
end = cur + (value2 * Instruction::
|
528
|
+
end = cur + (value2 * Instruction::kInstrSize);
|
361
529
|
}
|
362
530
|
}
|
363
531
|
|
364
532
|
while (cur < end) {
|
365
533
|
dasm.InstructionDecode(buffer, cur);
|
366
|
-
PrintF(" 0x%08x %s\n",
|
367
|
-
|
534
|
+
PrintF(" 0x%08x %s\n",
|
535
|
+
reinterpret_cast<intptr_t>(cur), buffer.start());
|
536
|
+
cur += Instruction::kInstrSize;
|
368
537
|
}
|
369
538
|
} else if (strcmp(cmd, "gdb") == 0) {
|
370
539
|
PrintF("relinquishing control to gdb\n");
|
371
540
|
v8::internal::OS::DebugBreak();
|
372
541
|
PrintF("regaining control from gdb\n");
|
373
542
|
} else if (strcmp(cmd, "break") == 0) {
|
374
|
-
if (
|
543
|
+
if (argc == 2) {
|
375
544
|
int32_t value;
|
376
545
|
if (GetValue(arg1, &value)) {
|
377
546
|
if (!SetBreakpoint(reinterpret_cast<Instruction*>(value))) {
|
@@ -404,29 +573,30 @@ void Debugger::Debug() {
|
|
404
573
|
byte_* cur = NULL;
|
405
574
|
byte_* end = NULL;
|
406
575
|
|
407
|
-
if (
|
576
|
+
if (argc == 1) {
|
408
577
|
cur = reinterpret_cast<byte_*>(sim_->get_pc());
|
409
|
-
end = cur + (10 * Instruction::
|
410
|
-
} else if (
|
578
|
+
end = cur + (10 * Instruction::kInstrSize);
|
579
|
+
} else if (argc == 2) {
|
411
580
|
int32_t value;
|
412
581
|
if (GetValue(arg1, &value)) {
|
413
582
|
cur = reinterpret_cast<byte_*>(value);
|
414
583
|
// no length parameter passed, assume 10 instructions
|
415
|
-
end = cur + (10 * Instruction::
|
584
|
+
end = cur + (10 * Instruction::kInstrSize);
|
416
585
|
}
|
417
586
|
} else {
|
418
587
|
int32_t value1;
|
419
588
|
int32_t value2;
|
420
589
|
if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) {
|
421
590
|
cur = reinterpret_cast<byte_*>(value1);
|
422
|
-
end = cur + (value2 * Instruction::
|
591
|
+
end = cur + (value2 * Instruction::kInstrSize);
|
423
592
|
}
|
424
593
|
}
|
425
594
|
|
426
595
|
while (cur < end) {
|
427
596
|
dasm.InstructionDecode(buffer, cur);
|
428
|
-
PrintF(" 0x%08x %s\n",
|
429
|
-
|
597
|
+
PrintF(" 0x%08x %s\n",
|
598
|
+
reinterpret_cast<intptr_t>(cur), buffer.start());
|
599
|
+
cur += Instruction::kInstrSize;
|
430
600
|
}
|
431
601
|
} else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) {
|
432
602
|
PrintF("cont\n");
|
@@ -438,6 +608,10 @@ void Debugger::Debug() {
|
|
438
608
|
PrintF(" use register name 'all' to print all registers\n");
|
439
609
|
PrintF("printobject <register>\n");
|
440
610
|
PrintF(" print an object from a register (alias 'po')\n");
|
611
|
+
PrintF("stack [<words>]\n");
|
612
|
+
PrintF(" dump stack content, default dump 10 words)\n");
|
613
|
+
PrintF("mem <address> [<words>]\n");
|
614
|
+
PrintF(" dump memory content, default dump 10 words)\n");
|
441
615
|
PrintF("flags\n");
|
442
616
|
PrintF(" print flags\n");
|
443
617
|
PrintF("disasm [<instructions>]\n");
|
@@ -471,29 +645,120 @@ void Debugger::Debug() {
|
|
471
645
|
}
|
472
646
|
|
473
647
|
|
474
|
-
|
475
|
-
|
648
|
+
static bool ICacheMatch(void* one, void* two) {
|
649
|
+
ASSERT((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0);
|
650
|
+
ASSERT((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0);
|
651
|
+
return one == two;
|
652
|
+
}
|
653
|
+
|
476
654
|
|
655
|
+
static uint32_t ICacheHash(void* key) {
|
656
|
+
return static_cast<uint32_t>(reinterpret_cast<uintptr_t>(key)) >> 2;
|
657
|
+
}
|
477
658
|
|
478
|
-
|
659
|
+
|
660
|
+
static bool AllOnOnePage(uintptr_t start, int size) {
|
661
|
+
intptr_t start_page = (start & ~CachePage::kPageMask);
|
662
|
+
intptr_t end_page = ((start + size) & ~CachePage::kPageMask);
|
663
|
+
return start_page == end_page;
|
664
|
+
}
|
665
|
+
|
666
|
+
|
667
|
+
void Simulator::FlushICache(v8::internal::HashMap* i_cache,
|
668
|
+
void* start_addr,
|
669
|
+
size_t size) {
|
670
|
+
intptr_t start = reinterpret_cast<intptr_t>(start_addr);
|
671
|
+
int intra_line = (start & CachePage::kLineMask);
|
672
|
+
start -= intra_line;
|
673
|
+
size += intra_line;
|
674
|
+
size = ((size - 1) | CachePage::kLineMask) + 1;
|
675
|
+
int offset = (start & CachePage::kPageMask);
|
676
|
+
while (!AllOnOnePage(start, size - 1)) {
|
677
|
+
int bytes_to_flush = CachePage::kPageSize - offset;
|
678
|
+
FlushOnePage(i_cache, start, bytes_to_flush);
|
679
|
+
start += bytes_to_flush;
|
680
|
+
size -= bytes_to_flush;
|
681
|
+
ASSERT_EQ(0, start & CachePage::kPageMask);
|
682
|
+
offset = 0;
|
683
|
+
}
|
684
|
+
if (size != 0) {
|
685
|
+
FlushOnePage(i_cache, start, size);
|
686
|
+
}
|
687
|
+
}
|
688
|
+
|
689
|
+
|
690
|
+
CachePage* Simulator::GetCachePage(v8::internal::HashMap* i_cache, void* page) {
|
691
|
+
v8::internal::HashMap::Entry* entry = i_cache->Lookup(page,
|
692
|
+
ICacheHash(page),
|
693
|
+
true);
|
694
|
+
if (entry->value == NULL) {
|
695
|
+
CachePage* new_page = new CachePage();
|
696
|
+
entry->value = new_page;
|
697
|
+
}
|
698
|
+
return reinterpret_cast<CachePage*>(entry->value);
|
699
|
+
}
|
700
|
+
|
701
|
+
|
702
|
+
// Flush from start up to and not including start + size.
|
703
|
+
void Simulator::FlushOnePage(v8::internal::HashMap* i_cache,
|
704
|
+
intptr_t start,
|
705
|
+
int size) {
|
706
|
+
ASSERT(size <= CachePage::kPageSize);
|
707
|
+
ASSERT(AllOnOnePage(start, size - 1));
|
708
|
+
ASSERT((start & CachePage::kLineMask) == 0);
|
709
|
+
ASSERT((size & CachePage::kLineMask) == 0);
|
710
|
+
void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask));
|
711
|
+
int offset = (start & CachePage::kPageMask);
|
712
|
+
CachePage* cache_page = GetCachePage(i_cache, page);
|
713
|
+
char* valid_bytemap = cache_page->ValidityByte(offset);
|
714
|
+
memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift);
|
715
|
+
}
|
716
|
+
|
717
|
+
|
718
|
+
void Simulator::CheckICache(v8::internal::HashMap* i_cache,
|
719
|
+
Instruction* instr) {
|
720
|
+
intptr_t address = reinterpret_cast<intptr_t>(instr);
|
721
|
+
void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask));
|
722
|
+
void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask));
|
723
|
+
int offset = (address & CachePage::kPageMask);
|
724
|
+
CachePage* cache_page = GetCachePage(i_cache, page);
|
725
|
+
char* cache_valid_byte = cache_page->ValidityByte(offset);
|
726
|
+
bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID);
|
727
|
+
char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask);
|
728
|
+
if (cache_hit) {
|
729
|
+
// Check that the data in memory matches the contents of the I-cache.
|
730
|
+
CHECK(memcmp(reinterpret_cast<void*>(instr),
|
731
|
+
cache_page->CachedData(offset),
|
732
|
+
Instruction::kInstrSize) == 0);
|
733
|
+
} else {
|
734
|
+
// Cache miss. Load memory into the cache.
|
735
|
+
memcpy(cached_line, line, CachePage::kLineLength);
|
736
|
+
*cache_valid_byte = CachePage::LINE_VALID;
|
737
|
+
}
|
738
|
+
}
|
479
739
|
|
480
740
|
|
481
741
|
void Simulator::Initialize() {
|
482
|
-
if (
|
483
|
-
|
484
|
-
initialized_ = true;
|
742
|
+
if (Isolate::Current()->simulator_initialized()) return;
|
743
|
+
Isolate::Current()->set_simulator_initialized(true);
|
485
744
|
::v8::internal::ExternalReference::set_redirector(&RedirectExternalReference);
|
486
745
|
}
|
487
746
|
|
488
747
|
|
489
|
-
Simulator::Simulator() {
|
748
|
+
Simulator::Simulator() : isolate_(Isolate::Current()) {
|
749
|
+
i_cache_ = isolate_->simulator_i_cache();
|
750
|
+
if (i_cache_ == NULL) {
|
751
|
+
i_cache_ = new v8::internal::HashMap(&ICacheMatch);
|
752
|
+
isolate_->set_simulator_i_cache(i_cache_);
|
753
|
+
}
|
490
754
|
Initialize();
|
491
755
|
// Setup simulator support first. Some of this information is needed to
|
492
756
|
// setup the architecture state.
|
493
|
-
|
494
|
-
stack_ = reinterpret_cast<char*>(malloc(
|
757
|
+
stack_size_ = 1 * 1024*1024; // allocate 1MB for stack
|
758
|
+
stack_ = reinterpret_cast<char*>(malloc(stack_size_));
|
495
759
|
pc_modified_ = false;
|
496
760
|
icount_ = 0;
|
761
|
+
break_count_ = 0;
|
497
762
|
break_pc_ = NULL;
|
498
763
|
break_instr_ = 0;
|
499
764
|
|
@@ -502,16 +767,23 @@ Simulator::Simulator() {
|
|
502
767
|
for (int i = 0; i < kNumSimuRegisters; i++) {
|
503
768
|
registers_[i] = 0;
|
504
769
|
}
|
770
|
+
for (int i = 0; i < kNumFPURegisters; i++) {
|
771
|
+
FPUregisters_[i] = 0;
|
772
|
+
}
|
773
|
+
FCSR_ = 0;
|
505
774
|
|
506
775
|
// The sp is initialized to point to the bottom (high address) of the
|
507
776
|
// allocated stack area. To be safe in potential stack underflows we leave
|
508
777
|
// some buffer below.
|
509
|
-
registers_[sp] = reinterpret_cast<int32_t>(stack_) +
|
778
|
+
registers_[sp] = reinterpret_cast<int32_t>(stack_) + stack_size_ - 64;
|
510
779
|
// The ra and pc are initialized to a known bad value that will cause an
|
511
780
|
// access violation if the simulator ever tries to execute it.
|
512
781
|
registers_[pc] = bad_ra;
|
513
782
|
registers_[ra] = bad_ra;
|
514
783
|
InitializeCoverage();
|
784
|
+
for (int i = 0; i < kNumExceptions; i++) {
|
785
|
+
exceptions[i] = 0;
|
786
|
+
}
|
515
787
|
}
|
516
788
|
|
517
789
|
|
@@ -524,12 +796,18 @@ Simulator::Simulator() {
|
|
524
796
|
// offset from the swi instruction so the simulator knows what to call.
|
525
797
|
class Redirection {
|
526
798
|
public:
|
527
|
-
Redirection(void* external_function,
|
799
|
+
Redirection(void* external_function, ExternalReference::Type type)
|
528
800
|
: external_function_(external_function),
|
529
801
|
swi_instruction_(rtCallRedirInstr),
|
530
|
-
|
531
|
-
next_(
|
532
|
-
|
802
|
+
type_(type),
|
803
|
+
next_(NULL) {
|
804
|
+
Isolate* isolate = Isolate::Current();
|
805
|
+
next_ = isolate->simulator_redirection();
|
806
|
+
Simulator::current(isolate)->
|
807
|
+
FlushICache(isolate->simulator_i_cache(),
|
808
|
+
reinterpret_cast<void*>(&swi_instruction_),
|
809
|
+
Instruction::kInstrSize);
|
810
|
+
isolate->set_simulator_redirection(this);
|
533
811
|
}
|
534
812
|
|
535
813
|
void* address_of_swi_instruction() {
|
@@ -537,14 +815,16 @@ class Redirection {
|
|
537
815
|
}
|
538
816
|
|
539
817
|
void* external_function() { return external_function_; }
|
540
|
-
|
818
|
+
ExternalReference::Type type() { return type_; }
|
541
819
|
|
542
|
-
static Redirection* Get(void* external_function,
|
543
|
-
|
544
|
-
|
820
|
+
static Redirection* Get(void* external_function,
|
821
|
+
ExternalReference::Type type) {
|
822
|
+
Isolate* isolate = Isolate::Current();
|
823
|
+
Redirection* current = isolate->simulator_redirection();
|
824
|
+
for (; current != NULL; current = current->next_) {
|
545
825
|
if (current->external_function_ == external_function) return current;
|
546
826
|
}
|
547
|
-
return new Redirection(external_function,
|
827
|
+
return new Redirection(external_function, type);
|
548
828
|
}
|
549
829
|
|
550
830
|
static Redirection* FromSwiInstruction(Instruction* swi_instruction) {
|
@@ -557,31 +837,33 @@ class Redirection {
|
|
557
837
|
private:
|
558
838
|
void* external_function_;
|
559
839
|
uint32_t swi_instruction_;
|
560
|
-
|
840
|
+
ExternalReference::Type type_;
|
561
841
|
Redirection* next_;
|
562
|
-
static Redirection* list_;
|
563
842
|
};
|
564
843
|
|
565
844
|
|
566
|
-
Redirection* Redirection::list_ = NULL;
|
567
|
-
|
568
|
-
|
569
845
|
void* Simulator::RedirectExternalReference(void* external_function,
|
570
|
-
|
571
|
-
Redirection* redirection = Redirection::Get(external_function,
|
846
|
+
ExternalReference::Type type) {
|
847
|
+
Redirection* redirection = Redirection::Get(external_function, type);
|
572
848
|
return redirection->address_of_swi_instruction();
|
573
849
|
}
|
574
850
|
|
575
851
|
|
576
852
|
// Get the active Simulator for the current thread.
|
577
|
-
Simulator* Simulator::current() {
|
578
|
-
|
579
|
-
|
580
|
-
|
853
|
+
Simulator* Simulator::current(Isolate* isolate) {
|
854
|
+
v8::internal::Isolate::PerIsolateThreadData* isolate_data =
|
855
|
+
Isolate::CurrentPerIsolateThreadData();
|
856
|
+
if (isolate_data == NULL) {
|
857
|
+
Isolate::EnterDefaultIsolate();
|
858
|
+
isolate_data = Isolate::CurrentPerIsolateThreadData();
|
859
|
+
}
|
860
|
+
ASSERT(isolate_data != NULL);
|
861
|
+
|
862
|
+
Simulator* sim = isolate_data->simulator();
|
581
863
|
if (sim == NULL) {
|
582
|
-
// TODO(146): delete the simulator object when a thread goes away.
|
864
|
+
// TODO(146): delete the simulator object when a thread/isolate goes away.
|
583
865
|
sim = new Simulator();
|
584
|
-
|
866
|
+
isolate_data->set_simulator(sim);
|
585
867
|
}
|
586
868
|
return sim;
|
587
869
|
}
|
@@ -599,14 +881,22 @@ void Simulator::set_register(int reg, int32_t value) {
|
|
599
881
|
registers_[reg] = (reg == 0) ? 0 : value;
|
600
882
|
}
|
601
883
|
|
884
|
+
|
602
885
|
void Simulator::set_fpu_register(int fpureg, int32_t value) {
|
603
886
|
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
|
604
887
|
FPUregisters_[fpureg] = value;
|
605
888
|
}
|
606
889
|
|
890
|
+
|
891
|
+
void Simulator::set_fpu_register_float(int fpureg, float value) {
|
892
|
+
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
|
893
|
+
*BitCast<float*>(&FPUregisters_[fpureg]) = value;
|
894
|
+
}
|
895
|
+
|
896
|
+
|
607
897
|
void Simulator::set_fpu_register_double(int fpureg, double value) {
|
608
898
|
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0));
|
609
|
-
*
|
899
|
+
*BitCast<double*>(&FPUregisters_[fpureg]) = value;
|
610
900
|
}
|
611
901
|
|
612
902
|
|
@@ -620,22 +910,75 @@ int32_t Simulator::get_register(int reg) const {
|
|
620
910
|
return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0);
|
621
911
|
}
|
622
912
|
|
913
|
+
|
623
914
|
int32_t Simulator::get_fpu_register(int fpureg) const {
|
624
915
|
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
|
625
916
|
return FPUregisters_[fpureg];
|
626
917
|
}
|
627
918
|
|
919
|
+
|
920
|
+
int64_t Simulator::get_fpu_register_long(int fpureg) const {
|
921
|
+
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0));
|
922
|
+
return *BitCast<int64_t*>(
|
923
|
+
const_cast<int32_t*>(&FPUregisters_[fpureg]));
|
924
|
+
}
|
925
|
+
|
926
|
+
|
927
|
+
float Simulator::get_fpu_register_float(int fpureg) const {
|
928
|
+
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
|
929
|
+
return *BitCast<float*>(
|
930
|
+
const_cast<int32_t*>(&FPUregisters_[fpureg]));
|
931
|
+
}
|
932
|
+
|
933
|
+
|
628
934
|
double Simulator::get_fpu_register_double(int fpureg) const {
|
629
935
|
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0));
|
630
|
-
return *
|
936
|
+
return *BitCast<double*>(const_cast<int32_t*>(&FPUregisters_[fpureg]));
|
937
|
+
}
|
938
|
+
|
939
|
+
|
940
|
+
// Helper functions for setting and testing the FCSR register's bits.
|
941
|
+
void Simulator::set_fcsr_bit(uint32_t cc, bool value) {
|
942
|
+
if (value) {
|
943
|
+
FCSR_ |= (1 << cc);
|
944
|
+
} else {
|
945
|
+
FCSR_ &= ~(1 << cc);
|
946
|
+
}
|
947
|
+
}
|
948
|
+
|
949
|
+
|
950
|
+
bool Simulator::test_fcsr_bit(uint32_t cc) {
|
951
|
+
return FCSR_ & (1 << cc);
|
631
952
|
}
|
632
953
|
|
954
|
+
|
955
|
+
// Sets the rounding error codes in FCSR based on the result of the rounding.
|
956
|
+
// Returns true if the operation was invalid.
|
957
|
+
bool Simulator::set_fcsr_round_error(double original, double rounded) {
|
958
|
+
if (!isfinite(original) ||
|
959
|
+
rounded > LONG_MAX ||
|
960
|
+
rounded < LONG_MIN) {
|
961
|
+
set_fcsr_bit(6, true); // Invalid operation.
|
962
|
+
return true;
|
963
|
+
} else if (original != static_cast<double>(rounded)) {
|
964
|
+
set_fcsr_bit(2, true); // Inexact.
|
965
|
+
}
|
966
|
+
return false;
|
967
|
+
}
|
968
|
+
|
969
|
+
|
633
970
|
// Raw access to the PC register.
|
634
971
|
void Simulator::set_pc(int32_t value) {
|
635
972
|
pc_modified_ = true;
|
636
973
|
registers_[pc] = value;
|
637
974
|
}
|
638
975
|
|
976
|
+
|
977
|
+
bool Simulator::has_bad_pc() const {
|
978
|
+
return ((registers_[pc] == bad_ra) || (registers_[pc] == end_sim_pc));
|
979
|
+
}
|
980
|
+
|
981
|
+
|
639
982
|
// Raw access to the PC register without the special adjustment when reading.
|
640
983
|
int32_t Simulator::get_pc() const {
|
641
984
|
return registers_[pc];
|
@@ -651,24 +994,38 @@ int32_t Simulator::get_pc() const {
|
|
651
994
|
// get the correct MIPS-like behaviour on unaligned accesses.
|
652
995
|
|
653
996
|
int Simulator::ReadW(int32_t addr, Instruction* instr) {
|
654
|
-
if (
|
997
|
+
if (addr >=0 && addr < 0x400) {
|
998
|
+
// this has to be a NULL-dereference
|
999
|
+
MipsDebugger dbg(this);
|
1000
|
+
dbg.Debug();
|
1001
|
+
}
|
1002
|
+
if ((addr & kPointerAlignmentMask) == 0) {
|
655
1003
|
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
|
656
1004
|
return *ptr;
|
657
1005
|
}
|
658
|
-
PrintF("Unaligned read at 0x%08x, pc=%p\n", addr,
|
659
|
-
|
1006
|
+
PrintF("Unaligned read at 0x%08x, pc=%p\n", addr,
|
1007
|
+
reinterpret_cast<void*>(instr));
|
1008
|
+
MipsDebugger dbg(this);
|
1009
|
+
dbg.Debug();
|
660
1010
|
return 0;
|
661
1011
|
}
|
662
1012
|
|
663
1013
|
|
664
1014
|
void Simulator::WriteW(int32_t addr, int value, Instruction* instr) {
|
665
|
-
if (
|
1015
|
+
if (addr >= 0 && addr < 0x400) {
|
1016
|
+
// this has to be a NULL-dereference
|
1017
|
+
MipsDebugger dbg(this);
|
1018
|
+
dbg.Debug();
|
1019
|
+
}
|
1020
|
+
if ((addr & kPointerAlignmentMask) == 0) {
|
666
1021
|
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
|
667
1022
|
*ptr = value;
|
668
1023
|
return;
|
669
1024
|
}
|
670
|
-
PrintF("Unaligned write at 0x%08x, pc=%p\n", addr,
|
671
|
-
|
1025
|
+
PrintF("Unaligned write at 0x%08x, pc=%p\n", addr,
|
1026
|
+
reinterpret_cast<void*>(instr));
|
1027
|
+
MipsDebugger dbg(this);
|
1028
|
+
dbg.Debug();
|
672
1029
|
}
|
673
1030
|
|
674
1031
|
|
@@ -677,7 +1034,8 @@ double Simulator::ReadD(int32_t addr, Instruction* instr) {
|
|
677
1034
|
double* ptr = reinterpret_cast<double*>(addr);
|
678
1035
|
return *ptr;
|
679
1036
|
}
|
680
|
-
PrintF("Unaligned read at 0x%08x, pc=%p\n", addr,
|
1037
|
+
PrintF("Unaligned (double) read at 0x%08x, pc=%p\n", addr,
|
1038
|
+
reinterpret_cast<void*>(instr));
|
681
1039
|
OS::Abort();
|
682
1040
|
return 0;
|
683
1041
|
}
|
@@ -689,7 +1047,8 @@ void Simulator::WriteD(int32_t addr, double value, Instruction* instr) {
|
|
689
1047
|
*ptr = value;
|
690
1048
|
return;
|
691
1049
|
}
|
692
|
-
PrintF("Unaligned write at 0x%08x, pc=%p\n", addr,
|
1050
|
+
PrintF("Unaligned (double) write at 0x%08x, pc=%p\n", addr,
|
1051
|
+
reinterpret_cast<void*>(instr));
|
693
1052
|
OS::Abort();
|
694
1053
|
}
|
695
1054
|
|
@@ -699,7 +1058,8 @@ uint16_t Simulator::ReadHU(int32_t addr, Instruction* instr) {
|
|
699
1058
|
uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
|
700
1059
|
return *ptr;
|
701
1060
|
}
|
702
|
-
PrintF("Unaligned unsigned halfword read at 0x%08x, pc=%p\n", addr,
|
1061
|
+
PrintF("Unaligned unsigned halfword read at 0x%08x, pc=%p\n", addr,
|
1062
|
+
reinterpret_cast<void*>(instr));
|
703
1063
|
OS::Abort();
|
704
1064
|
return 0;
|
705
1065
|
}
|
@@ -710,7 +1070,8 @@ int16_t Simulator::ReadH(int32_t addr, Instruction* instr) {
|
|
710
1070
|
int16_t* ptr = reinterpret_cast<int16_t*>(addr);
|
711
1071
|
return *ptr;
|
712
1072
|
}
|
713
|
-
PrintF("Unaligned signed halfword read at 0x%08x, pc=%p\n", addr,
|
1073
|
+
PrintF("Unaligned signed halfword read at 0x%08x, pc=%p\n", addr,
|
1074
|
+
reinterpret_cast<void*>(instr));
|
714
1075
|
OS::Abort();
|
715
1076
|
return 0;
|
716
1077
|
}
|
@@ -722,7 +1083,8 @@ void Simulator::WriteH(int32_t addr, uint16_t value, Instruction* instr) {
|
|
722
1083
|
*ptr = value;
|
723
1084
|
return;
|
724
1085
|
}
|
725
|
-
PrintF("Unaligned unsigned halfword write at 0x%08x, pc=%p\n", addr,
|
1086
|
+
PrintF("Unaligned unsigned halfword write at 0x%08x, pc=%p\n", addr,
|
1087
|
+
reinterpret_cast<void*>(instr));
|
726
1088
|
OS::Abort();
|
727
1089
|
}
|
728
1090
|
|
@@ -733,7 +1095,8 @@ void Simulator::WriteH(int32_t addr, int16_t value, Instruction* instr) {
|
|
733
1095
|
*ptr = value;
|
734
1096
|
return;
|
735
1097
|
}
|
736
|
-
PrintF("Unaligned halfword write at 0x%08x, pc=%p\n", addr,
|
1098
|
+
PrintF("Unaligned halfword write at 0x%08x, pc=%p\n", addr,
|
1099
|
+
reinterpret_cast<void*>(instr));
|
737
1100
|
OS::Abort();
|
738
1101
|
}
|
739
1102
|
|
@@ -746,7 +1109,7 @@ uint32_t Simulator::ReadBU(int32_t addr) {
|
|
746
1109
|
|
747
1110
|
int32_t Simulator::ReadB(int32_t addr) {
|
748
1111
|
int8_t* ptr = reinterpret_cast<int8_t*>(addr);
|
749
|
-
return
|
1112
|
+
return *ptr;
|
750
1113
|
}
|
751
1114
|
|
752
1115
|
|
@@ -773,7 +1136,7 @@ uintptr_t Simulator::StackLimit() const {
|
|
773
1136
|
// Unsupported instructions use Format to print an error and stop execution.
|
774
1137
|
void Simulator::Format(Instruction* instr, const char* format) {
|
775
1138
|
PrintF("Simulator found unsupported instruction:\n 0x%08x: %s\n",
|
776
|
-
instr, format);
|
1139
|
+
reinterpret_cast<intptr_t>(instr), format);
|
777
1140
|
UNIMPLEMENTED_MIPS();
|
778
1141
|
}
|
779
1142
|
|
@@ -782,75 +1145,140 @@ void Simulator::Format(Instruction* instr, const char* format) {
|
|
782
1145
|
// Note: To be able to return two values from some calls the code in runtime.cc
|
783
1146
|
// uses the ObjectPair which is essentially two 32-bit values stuffed into a
|
784
1147
|
// 64-bit value. With the code below we assume that all runtime calls return
|
785
|
-
// 64 bits of result. If they don't, the
|
1148
|
+
// 64 bits of result. If they don't, the v1 result register contains a bogus
|
786
1149
|
// value, which is fine because it is caller-saved.
|
787
1150
|
typedef int64_t (*SimulatorRuntimeCall)(int32_t arg0,
|
788
1151
|
int32_t arg1,
|
789
1152
|
int32_t arg2,
|
790
|
-
int32_t arg3
|
791
|
-
|
792
|
-
|
793
|
-
|
1153
|
+
int32_t arg3,
|
1154
|
+
int32_t arg4,
|
1155
|
+
int32_t arg5);
|
1156
|
+
typedef double (*SimulatorRuntimeFPCall)(int32_t arg0,
|
1157
|
+
int32_t arg1,
|
1158
|
+
int32_t arg2,
|
1159
|
+
int32_t arg3);
|
794
1160
|
|
795
1161
|
// Software interrupt instructions are used by the simulator to call into the
|
796
|
-
// C-based V8 runtime.
|
1162
|
+
// C-based V8 runtime. They are also used for debugging with simulator.
|
797
1163
|
void Simulator::SoftwareInterrupt(Instruction* instr) {
|
1164
|
+
// There are several instructions that could get us here,
|
1165
|
+
// the break_ instruction, or several variants of traps. All
|
1166
|
+
// Are "SPECIAL" class opcode, and are distinuished by function.
|
1167
|
+
int32_t func = instr->FunctionFieldRaw();
|
1168
|
+
int32_t code = (func == BREAK) ? instr->Bits(25, 6) : -1;
|
1169
|
+
|
798
1170
|
// We first check if we met a call_rt_redirected.
|
799
1171
|
if (instr->InstructionBits() == rtCallRedirInstr) {
|
1172
|
+
// Check if stack is aligned. Error if not aligned is reported below to
|
1173
|
+
// include information on the function called.
|
1174
|
+
bool stack_aligned =
|
1175
|
+
(get_register(sp)
|
1176
|
+
& (::v8::internal::FLAG_sim_stack_alignment - 1)) == 0;
|
800
1177
|
Redirection* redirection = Redirection::FromSwiInstruction(instr);
|
801
1178
|
int32_t arg0 = get_register(a0);
|
802
1179
|
int32_t arg1 = get_register(a1);
|
803
1180
|
int32_t arg2 = get_register(a2);
|
804
1181
|
int32_t arg3 = get_register(a3);
|
805
|
-
|
806
|
-
|
807
|
-
|
808
|
-
|
1182
|
+
int32_t arg4 = 0;
|
1183
|
+
int32_t arg5 = 0;
|
1184
|
+
|
1185
|
+
// Need to check if sp is valid before assigning arg4, arg5.
|
1186
|
+
// This is a fix for cctest test-api/CatchStackOverflow which causes
|
1187
|
+
// the stack to overflow. For some reason arm doesn't need this
|
1188
|
+
// stack check here.
|
1189
|
+
int32_t* stack_pointer = reinterpret_cast<int32_t*>(get_register(sp));
|
1190
|
+
int32_t* stack = reinterpret_cast<int32_t*>(stack_);
|
1191
|
+
if (stack_pointer >= stack && stack_pointer < stack + stack_size_) {
|
1192
|
+
arg4 = stack_pointer[0];
|
1193
|
+
arg5 = stack_pointer[1];
|
1194
|
+
}
|
809
1195
|
// This is dodgy but it works because the C entry stubs are never moved.
|
810
1196
|
// See comment in codegen-arm.cc and bug 1242173.
|
811
1197
|
int32_t saved_ra = get_register(ra);
|
812
|
-
|
813
|
-
|
814
|
-
|
1198
|
+
|
1199
|
+
intptr_t external =
|
1200
|
+
reinterpret_cast<int32_t>(redirection->external_function());
|
1201
|
+
|
1202
|
+
// Based on CpuFeatures::IsSupported(FPU), Mips will use either hardware
|
1203
|
+
// FPU, or gcc soft-float routines. Hardware FPU is simulated in this
|
1204
|
+
// simulator. Soft-float has additional abstraction of ExternalReference,
|
1205
|
+
// to support serialization. Finally, when simulated on x86 host, the
|
1206
|
+
// x86 softfloat routines are used, and this Redirection infrastructure
|
1207
|
+
// lets simulated-mips make calls into x86 C code.
|
1208
|
+
// When doing that, the 'double' return type must be handled differently
|
1209
|
+
// than the usual int64_t return. The data is returned in different
|
1210
|
+
// registers and cannot be cast from one type to the other. However, the
|
1211
|
+
// calling arguments are passed the same way in both cases.
|
1212
|
+
if (redirection->type() == ExternalReference::FP_RETURN_CALL) {
|
815
1213
|
SimulatorRuntimeFPCall target =
|
816
1214
|
reinterpret_cast<SimulatorRuntimeFPCall>(external);
|
817
|
-
if (::v8::internal::FLAG_trace_sim) {
|
818
|
-
PrintF("Call to host function at %p with args %
|
819
|
-
FUNCTION_ADDR(target),
|
1215
|
+
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
|
1216
|
+
PrintF("Call to host function at %p with args %08x:%08x %08x:%08x",
|
1217
|
+
FUNCTION_ADDR(target), arg0, arg1, arg2, arg3);
|
1218
|
+
if (!stack_aligned) {
|
1219
|
+
PrintF(" with unaligned stack %08x\n", get_register(sp));
|
1220
|
+
}
|
1221
|
+
PrintF("\n");
|
820
1222
|
}
|
821
|
-
double result = target(
|
822
|
-
|
1223
|
+
double result = target(arg0, arg1, arg2, arg3);
|
1224
|
+
// fp result -> registers v0 and v1.
|
1225
|
+
int32_t gpreg_pair[2];
|
1226
|
+
memcpy(&gpreg_pair[0], &result, 2 * sizeof(int32_t));
|
1227
|
+
set_register(v0, gpreg_pair[0]);
|
1228
|
+
set_register(v1, gpreg_pair[1]);
|
1229
|
+
} else if (redirection->type() == ExternalReference::DIRECT_API_CALL) {
|
1230
|
+
PrintF("Mips does not yet support ExternalReference::DIRECT_API_CALL\n");
|
1231
|
+
ASSERT(redirection->type() != ExternalReference::DIRECT_API_CALL);
|
1232
|
+
} else if (redirection->type() == ExternalReference::DIRECT_GETTER_CALL) {
|
1233
|
+
PrintF("Mips does not support ExternalReference::DIRECT_GETTER_CALL\n");
|
1234
|
+
ASSERT(redirection->type() != ExternalReference::DIRECT_GETTER_CALL);
|
823
1235
|
} else {
|
824
|
-
|
825
|
-
|
1236
|
+
// Builtin call.
|
1237
|
+
ASSERT(redirection->type() == ExternalReference::BUILTIN_CALL);
|
826
1238
|
SimulatorRuntimeCall target =
|
827
1239
|
reinterpret_cast<SimulatorRuntimeCall>(external);
|
828
|
-
if (::v8::internal::FLAG_trace_sim) {
|
1240
|
+
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
|
829
1241
|
PrintF(
|
830
|
-
"Call to host function at %p
|
1242
|
+
"Call to host function at %p: %08x, %08x, %08x, %08x, %08x, %08x",
|
831
1243
|
FUNCTION_ADDR(target),
|
832
1244
|
arg0,
|
833
1245
|
arg1,
|
834
1246
|
arg2,
|
835
|
-
arg3
|
836
|
-
|
837
|
-
|
838
|
-
|
839
|
-
|
840
|
-
|
841
|
-
PrintF("
|
1247
|
+
arg3,
|
1248
|
+
arg4,
|
1249
|
+
arg5);
|
1250
|
+
if (!stack_aligned) {
|
1251
|
+
PrintF(" with unaligned stack %08x\n", get_register(sp));
|
1252
|
+
}
|
1253
|
+
PrintF("\n");
|
842
1254
|
}
|
843
|
-
|
844
|
-
|
1255
|
+
|
1256
|
+
int64_t result = target(arg0, arg1, arg2, arg3, arg4, arg5);
|
1257
|
+
set_register(v0, static_cast<int32_t>(result));
|
1258
|
+
set_register(v1, static_cast<int32_t>(result >> 32));
|
1259
|
+
}
|
1260
|
+
if (::v8::internal::FLAG_trace_sim) {
|
1261
|
+
PrintF("Returned %08x : %08x\n", get_register(v1), get_register(v0));
|
845
1262
|
}
|
846
1263
|
set_register(ra, saved_ra);
|
847
1264
|
set_pc(get_register(ra));
|
1265
|
+
|
1266
|
+
} else if (func == BREAK && code >= 0 && code < 16) {
|
1267
|
+
// First 16 break_ codes interpreted as debug markers.
|
1268
|
+
MipsDebugger dbg(this);
|
1269
|
+
++break_count_;
|
1270
|
+
PrintF("\n---- break %d marker: %3d (instr count: %8d) ----------"
|
1271
|
+
"----------------------------------",
|
1272
|
+
code, break_count_, icount_);
|
1273
|
+
dbg.PrintAllRegs(); // Print registers and continue running.
|
848
1274
|
} else {
|
849
|
-
|
1275
|
+
// All remaining break_ codes, and all traps are handled here.
|
1276
|
+
MipsDebugger dbg(this);
|
850
1277
|
dbg.Debug();
|
851
1278
|
}
|
852
1279
|
}
|
853
1280
|
|
1281
|
+
|
854
1282
|
void Simulator::SignalExceptions() {
|
855
1283
|
for (int i = 1; i < kNumExceptions; i++) {
|
856
1284
|
if (exceptions[i] != 0) {
|
@@ -859,51 +1287,52 @@ void Simulator::SignalExceptions() {
|
|
859
1287
|
}
|
860
1288
|
}
|
861
1289
|
|
862
|
-
// Handle execution based on instruction types.
|
863
|
-
void Simulator::DecodeTypeRegister(Instruction* instr) {
|
864
|
-
// Instruction fields
|
865
|
-
Opcode op = instr->OpcodeFieldRaw();
|
866
|
-
int32_t rs_reg = instr->RsField();
|
867
|
-
int32_t rs = get_register(rs_reg);
|
868
|
-
uint32_t rs_u = static_cast<uint32_t>(rs);
|
869
|
-
int32_t rt_reg = instr->RtField();
|
870
|
-
int32_t rt = get_register(rt_reg);
|
871
|
-
uint32_t rt_u = static_cast<uint32_t>(rt);
|
872
|
-
int32_t rd_reg = instr->RdField();
|
873
|
-
uint32_t sa = instr->SaField();
|
874
|
-
|
875
|
-
int32_t fs_reg= instr->FsField();
|
876
1290
|
|
877
|
-
|
878
|
-
// It should not be used as is. Instructions using it should always initialize
|
879
|
-
// it first.
|
880
|
-
int32_t alu_out = 0x12345678;
|
881
|
-
// Output or temporary for floating point.
|
882
|
-
double fp_out = 0.0;
|
1291
|
+
// Handle execution based on instruction types.
|
883
1292
|
|
884
|
-
|
885
|
-
|
1293
|
+
void Simulator::ConfigureTypeRegister(Instruction* instr,
|
1294
|
+
int32_t& alu_out,
|
1295
|
+
int64_t& i64hilo,
|
1296
|
+
uint64_t& u64hilo,
|
1297
|
+
int32_t& next_pc,
|
1298
|
+
bool& do_interrupt) {
|
1299
|
+
// Every local variable declared here needs to be const.
|
1300
|
+
// This is to make sure that changed values are sent back to
|
1301
|
+
// DecodeTypeRegister correctly.
|
1302
|
+
|
1303
|
+
// Instruction fields.
|
1304
|
+
const Opcode op = instr->OpcodeFieldRaw();
|
1305
|
+
const int32_t rs_reg = instr->RsValue();
|
1306
|
+
const int32_t rs = get_register(rs_reg);
|
1307
|
+
const uint32_t rs_u = static_cast<uint32_t>(rs);
|
1308
|
+
const int32_t rt_reg = instr->RtValue();
|
1309
|
+
const int32_t rt = get_register(rt_reg);
|
1310
|
+
const uint32_t rt_u = static_cast<uint32_t>(rt);
|
1311
|
+
const int32_t rd_reg = instr->RdValue();
|
1312
|
+
const uint32_t sa = instr->SaValue();
|
1313
|
+
|
1314
|
+
const int32_t fs_reg = instr->FsValue();
|
886
1315
|
|
887
|
-
// For jr and jalr
|
888
|
-
// Get current pc.
|
889
|
-
int32_t current_pc = get_pc();
|
890
|
-
// Next pc
|
891
|
-
int32_t next_pc = 0;
|
892
1316
|
|
893
1317
|
// ---------- Configuration
|
894
1318
|
switch (op) {
|
895
1319
|
case COP1: // Coprocessor instructions
|
896
1320
|
switch (instr->RsFieldRaw()) {
|
897
|
-
case BC1: //
|
1321
|
+
case BC1: // Handled in DecodeTypeImmed, should never come here.
|
898
1322
|
UNREACHABLE();
|
899
1323
|
break;
|
1324
|
+
case CFC1:
|
1325
|
+
// At the moment only FCSR is supported.
|
1326
|
+
ASSERT(fs_reg == kFCSRRegister);
|
1327
|
+
alu_out = FCSR_;
|
1328
|
+
break;
|
900
1329
|
case MFC1:
|
901
1330
|
alu_out = get_fpu_register(fs_reg);
|
902
1331
|
break;
|
903
1332
|
case MFHC1:
|
904
|
-
|
905
|
-
alu_out = *v8i::BitCast<int32_t*>(&fp_out);
|
1333
|
+
UNIMPLEMENTED_MIPS();
|
906
1334
|
break;
|
1335
|
+
case CTC1:
|
907
1336
|
case MTC1:
|
908
1337
|
case MTHC1:
|
909
1338
|
// Do the store in the execution step.
|
@@ -923,13 +1352,22 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
923
1352
|
switch (instr->FunctionFieldRaw()) {
|
924
1353
|
case JR:
|
925
1354
|
case JALR:
|
926
|
-
next_pc = get_register(instr->
|
1355
|
+
next_pc = get_register(instr->RsValue());
|
927
1356
|
break;
|
928
1357
|
case SLL:
|
929
1358
|
alu_out = rt << sa;
|
930
1359
|
break;
|
931
1360
|
case SRL:
|
932
|
-
|
1361
|
+
if (rs_reg == 0) {
|
1362
|
+
// Regular logical right shift of a word by a fixed number of
|
1363
|
+
// bits instruction. RS field is always equal to 0.
|
1364
|
+
alu_out = rt_u >> sa;
|
1365
|
+
} else {
|
1366
|
+
// Logical right-rotate of a word by a fixed number of bits. This
|
1367
|
+
// is special case of SRL instruction, added in MIPS32 Release 2.
|
1368
|
+
// RS field is equal to 00001
|
1369
|
+
alu_out = (rt_u >> sa) | (rt_u << (32 - sa));
|
1370
|
+
}
|
933
1371
|
break;
|
934
1372
|
case SRA:
|
935
1373
|
alu_out = rt >> sa;
|
@@ -938,7 +1376,16 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
938
1376
|
alu_out = rt << rs;
|
939
1377
|
break;
|
940
1378
|
case SRLV:
|
941
|
-
|
1379
|
+
if (sa == 0) {
|
1380
|
+
// Regular logical right-shift of a word by a variable number of
|
1381
|
+
// bits instruction. SA field is always equal to 0.
|
1382
|
+
alu_out = rt_u >> rs;
|
1383
|
+
} else {
|
1384
|
+
// Logical right-rotate of a word by a variable number of bits.
|
1385
|
+
// This is special case od SRLV instruction, added in MIPS32
|
1386
|
+
// Release 2. SA field is equal to 00001
|
1387
|
+
alu_out = (rt_u >> rs_u) | (rt_u << (32 - rs_u));
|
1388
|
+
}
|
942
1389
|
break;
|
943
1390
|
case SRAV:
|
944
1391
|
alu_out = rt >> rs;
|
@@ -950,10 +1397,10 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
950
1397
|
alu_out = get_register(LO);
|
951
1398
|
break;
|
952
1399
|
case MULT:
|
953
|
-
|
1400
|
+
i64hilo = static_cast<int64_t>(rs) * static_cast<int64_t>(rt);
|
954
1401
|
break;
|
955
1402
|
case MULTU:
|
956
|
-
|
1403
|
+
u64hilo = static_cast<uint64_t>(rs_u) * static_cast<uint64_t>(rt_u);
|
957
1404
|
break;
|
958
1405
|
case DIV:
|
959
1406
|
case DIVU:
|
@@ -1005,6 +1452,7 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1005
1452
|
break;
|
1006
1453
|
// Break and trap instructions
|
1007
1454
|
case BREAK:
|
1455
|
+
|
1008
1456
|
do_interrupt = true;
|
1009
1457
|
break;
|
1010
1458
|
case TGE:
|
@@ -1025,6 +1473,11 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1025
1473
|
case TNE:
|
1026
1474
|
do_interrupt = rs != rt;
|
1027
1475
|
break;
|
1476
|
+
case MOVN:
|
1477
|
+
case MOVZ:
|
1478
|
+
case MOVCI:
|
1479
|
+
// No action taken on decode.
|
1480
|
+
break;
|
1028
1481
|
default:
|
1029
1482
|
UNREACHABLE();
|
1030
1483
|
};
|
@@ -1034,13 +1487,83 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1034
1487
|
case MUL:
|
1035
1488
|
alu_out = rs_u * rt_u; // Only the lower 32 bits are kept.
|
1036
1489
|
break;
|
1490
|
+
case CLZ:
|
1491
|
+
alu_out = __builtin_clz(rs_u);
|
1492
|
+
break;
|
1037
1493
|
default:
|
1038
1494
|
UNREACHABLE();
|
1039
|
-
}
|
1495
|
+
};
|
1496
|
+
break;
|
1497
|
+
case SPECIAL3:
|
1498
|
+
switch (instr->FunctionFieldRaw()) {
|
1499
|
+
case INS: { // Mips32r2 instruction.
|
1500
|
+
// Interpret Rd field as 5-bit msb of insert.
|
1501
|
+
uint16_t msb = rd_reg;
|
1502
|
+
// Interpret sa field as 5-bit lsb of insert.
|
1503
|
+
uint16_t lsb = sa;
|
1504
|
+
uint16_t size = msb - lsb + 1;
|
1505
|
+
uint32_t mask = (1 << size) - 1;
|
1506
|
+
alu_out = (rt_u & ~(mask << lsb)) | ((rs_u & mask) << lsb);
|
1507
|
+
break;
|
1508
|
+
}
|
1509
|
+
case EXT: { // Mips32r2 instruction.
|
1510
|
+
// Interpret Rd field as 5-bit msb of extract.
|
1511
|
+
uint16_t msb = rd_reg;
|
1512
|
+
// Interpret sa field as 5-bit lsb of extract.
|
1513
|
+
uint16_t lsb = sa;
|
1514
|
+
uint16_t size = msb + 1;
|
1515
|
+
uint32_t mask = (1 << size) - 1;
|
1516
|
+
alu_out = (rs_u & (mask << lsb)) >> lsb;
|
1517
|
+
break;
|
1518
|
+
}
|
1519
|
+
default:
|
1520
|
+
UNREACHABLE();
|
1521
|
+
};
|
1040
1522
|
break;
|
1041
1523
|
default:
|
1042
1524
|
UNREACHABLE();
|
1043
1525
|
};
|
1526
|
+
}
|
1527
|
+
|
1528
|
+
|
1529
|
+
void Simulator::DecodeTypeRegister(Instruction* instr) {
|
1530
|
+
// Instruction fields.
|
1531
|
+
const Opcode op = instr->OpcodeFieldRaw();
|
1532
|
+
const int32_t rs_reg = instr->RsValue();
|
1533
|
+
const int32_t rs = get_register(rs_reg);
|
1534
|
+
const uint32_t rs_u = static_cast<uint32_t>(rs);
|
1535
|
+
const int32_t rt_reg = instr->RtValue();
|
1536
|
+
const int32_t rt = get_register(rt_reg);
|
1537
|
+
const uint32_t rt_u = static_cast<uint32_t>(rt);
|
1538
|
+
const int32_t rd_reg = instr->RdValue();
|
1539
|
+
|
1540
|
+
const int32_t fs_reg = instr->FsValue();
|
1541
|
+
const int32_t ft_reg = instr->FtValue();
|
1542
|
+
const int32_t fd_reg = instr->FdValue();
|
1543
|
+
int64_t i64hilo = 0;
|
1544
|
+
uint64_t u64hilo = 0;
|
1545
|
+
|
1546
|
+
// ALU output
|
1547
|
+
// It should not be used as is. Instructions using it should always
|
1548
|
+
// initialize it first.
|
1549
|
+
int32_t alu_out = 0x12345678;
|
1550
|
+
|
1551
|
+
// For break and trap instructions.
|
1552
|
+
bool do_interrupt = false;
|
1553
|
+
|
1554
|
+
// For jr and jalr
|
1555
|
+
// Get current pc.
|
1556
|
+
int32_t current_pc = get_pc();
|
1557
|
+
// Next pc
|
1558
|
+
int32_t next_pc = 0;
|
1559
|
+
|
1560
|
+
// Setup the variables if needed before executing the instruction.
|
1561
|
+
ConfigureTypeRegister(instr,
|
1562
|
+
alu_out,
|
1563
|
+
i64hilo,
|
1564
|
+
u64hilo,
|
1565
|
+
next_pc,
|
1566
|
+
do_interrupt);
|
1044
1567
|
|
1045
1568
|
// ---------- Raise exceptions triggered.
|
1046
1569
|
SignalExceptions();
|
@@ -1052,25 +1575,42 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1052
1575
|
case BC1: // branch on coprocessor condition
|
1053
1576
|
UNREACHABLE();
|
1054
1577
|
break;
|
1578
|
+
case CFC1:
|
1579
|
+
set_register(rt_reg, alu_out);
|
1055
1580
|
case MFC1:
|
1056
|
-
case MFHC1:
|
1057
1581
|
set_register(rt_reg, alu_out);
|
1058
1582
|
break;
|
1583
|
+
case MFHC1:
|
1584
|
+
UNIMPLEMENTED_MIPS();
|
1585
|
+
break;
|
1586
|
+
case CTC1:
|
1587
|
+
// At the moment only FCSR is supported.
|
1588
|
+
ASSERT(fs_reg == kFCSRRegister);
|
1589
|
+
FCSR_ = registers_[rt_reg];
|
1590
|
+
break;
|
1059
1591
|
case MTC1:
|
1060
|
-
// We don't need to set the higher bits to 0, because MIPS ISA says
|
1061
|
-
// they are in an unpredictable state after executing MTC1.
|
1062
1592
|
FPUregisters_[fs_reg] = registers_[rt_reg];
|
1063
|
-
FPUregisters_[fs_reg+1] = Unpredictable;
|
1064
1593
|
break;
|
1065
1594
|
case MTHC1:
|
1066
|
-
|
1067
|
-
FPUregisters_[fs_reg+1] = registers_[rt_reg];
|
1595
|
+
UNIMPLEMENTED_MIPS();
|
1068
1596
|
break;
|
1069
1597
|
case S:
|
1598
|
+
float f;
|
1070
1599
|
switch (instr->FunctionFieldRaw()) {
|
1071
1600
|
case CVT_D_S:
|
1601
|
+
f = get_fpu_register_float(fs_reg);
|
1602
|
+
set_fpu_register_double(fd_reg, static_cast<double>(f));
|
1603
|
+
break;
|
1072
1604
|
case CVT_W_S:
|
1073
1605
|
case CVT_L_S:
|
1606
|
+
case TRUNC_W_S:
|
1607
|
+
case TRUNC_L_S:
|
1608
|
+
case ROUND_W_S:
|
1609
|
+
case ROUND_L_S:
|
1610
|
+
case FLOOR_W_S:
|
1611
|
+
case FLOOR_L_S:
|
1612
|
+
case CEIL_W_S:
|
1613
|
+
case CEIL_L_S:
|
1074
1614
|
case CVT_PS_S:
|
1075
1615
|
UNIMPLEMENTED_MIPS();
|
1076
1616
|
break;
|
@@ -1079,10 +1619,133 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1079
1619
|
}
|
1080
1620
|
break;
|
1081
1621
|
case D:
|
1622
|
+
double ft, fs;
|
1623
|
+
uint32_t cc, fcsr_cc;
|
1624
|
+
int64_t i64;
|
1625
|
+
fs = get_fpu_register_double(fs_reg);
|
1626
|
+
ft = get_fpu_register_double(ft_reg);
|
1627
|
+
cc = instr->FCccValue();
|
1628
|
+
fcsr_cc = get_fcsr_condition_bit(cc);
|
1082
1629
|
switch (instr->FunctionFieldRaw()) {
|
1083
|
-
case
|
1084
|
-
|
1085
|
-
|
1630
|
+
case ADD_D:
|
1631
|
+
set_fpu_register_double(fd_reg, fs + ft);
|
1632
|
+
break;
|
1633
|
+
case SUB_D:
|
1634
|
+
set_fpu_register_double(fd_reg, fs - ft);
|
1635
|
+
break;
|
1636
|
+
case MUL_D:
|
1637
|
+
set_fpu_register_double(fd_reg, fs * ft);
|
1638
|
+
break;
|
1639
|
+
case DIV_D:
|
1640
|
+
set_fpu_register_double(fd_reg, fs / ft);
|
1641
|
+
break;
|
1642
|
+
case ABS_D:
|
1643
|
+
set_fpu_register_double(fd_reg, fs < 0 ? -fs : fs);
|
1644
|
+
break;
|
1645
|
+
case MOV_D:
|
1646
|
+
set_fpu_register_double(fd_reg, fs);
|
1647
|
+
break;
|
1648
|
+
case NEG_D:
|
1649
|
+
set_fpu_register_double(fd_reg, -fs);
|
1650
|
+
break;
|
1651
|
+
case SQRT_D:
|
1652
|
+
set_fpu_register_double(fd_reg, sqrt(fs));
|
1653
|
+
break;
|
1654
|
+
case C_UN_D:
|
1655
|
+
set_fcsr_bit(fcsr_cc, isnan(fs) || isnan(ft));
|
1656
|
+
break;
|
1657
|
+
case C_EQ_D:
|
1658
|
+
set_fcsr_bit(fcsr_cc, (fs == ft));
|
1659
|
+
break;
|
1660
|
+
case C_UEQ_D:
|
1661
|
+
set_fcsr_bit(fcsr_cc, (fs == ft) || (isnan(fs) || isnan(ft)));
|
1662
|
+
break;
|
1663
|
+
case C_OLT_D:
|
1664
|
+
set_fcsr_bit(fcsr_cc, (fs < ft));
|
1665
|
+
break;
|
1666
|
+
case C_ULT_D:
|
1667
|
+
set_fcsr_bit(fcsr_cc, (fs < ft) || (isnan(fs) || isnan(ft)));
|
1668
|
+
break;
|
1669
|
+
case C_OLE_D:
|
1670
|
+
set_fcsr_bit(fcsr_cc, (fs <= ft));
|
1671
|
+
break;
|
1672
|
+
case C_ULE_D:
|
1673
|
+
set_fcsr_bit(fcsr_cc, (fs <= ft) || (isnan(fs) || isnan(ft)));
|
1674
|
+
break;
|
1675
|
+
case CVT_W_D: // Convert double to word.
|
1676
|
+
// Rounding modes are not yet supported.
|
1677
|
+
ASSERT((FCSR_ & 3) == 0);
|
1678
|
+
// In rounding mode 0 it should behave like ROUND.
|
1679
|
+
case ROUND_W_D: // Round double to word.
|
1680
|
+
{
|
1681
|
+
double rounded = fs > 0 ? floor(fs + 0.5) : ceil(fs - 0.5);
|
1682
|
+
int32_t result = static_cast<int32_t>(rounded);
|
1683
|
+
set_fpu_register(fd_reg, result);
|
1684
|
+
if (set_fcsr_round_error(fs, rounded)) {
|
1685
|
+
set_fpu_register(fd_reg, kFPUInvalidResult);
|
1686
|
+
}
|
1687
|
+
}
|
1688
|
+
break;
|
1689
|
+
case TRUNC_W_D: // Truncate double to word (round towards 0).
|
1690
|
+
{
|
1691
|
+
int32_t result = static_cast<int32_t>(fs);
|
1692
|
+
set_fpu_register(fd_reg, result);
|
1693
|
+
if (set_fcsr_round_error(fs, static_cast<double>(result))) {
|
1694
|
+
set_fpu_register(fd_reg, kFPUInvalidResult);
|
1695
|
+
}
|
1696
|
+
}
|
1697
|
+
break;
|
1698
|
+
case FLOOR_W_D: // Round double to word towards negative infinity.
|
1699
|
+
{
|
1700
|
+
double rounded = floor(fs);
|
1701
|
+
int32_t result = static_cast<int32_t>(rounded);
|
1702
|
+
set_fpu_register(fd_reg, result);
|
1703
|
+
if (set_fcsr_round_error(fs, rounded)) {
|
1704
|
+
set_fpu_register(fd_reg, kFPUInvalidResult);
|
1705
|
+
}
|
1706
|
+
}
|
1707
|
+
break;
|
1708
|
+
case CEIL_W_D: // Round double to word towards positive infinity.
|
1709
|
+
{
|
1710
|
+
double rounded = ceil(fs);
|
1711
|
+
int32_t result = static_cast<int32_t>(rounded);
|
1712
|
+
set_fpu_register(fd_reg, result);
|
1713
|
+
if (set_fcsr_round_error(fs, rounded)) {
|
1714
|
+
set_fpu_register(fd_reg, kFPUInvalidResult);
|
1715
|
+
}
|
1716
|
+
}
|
1717
|
+
break;
|
1718
|
+
case CVT_S_D: // Convert double to float (single).
|
1719
|
+
set_fpu_register_float(fd_reg, static_cast<float>(fs));
|
1720
|
+
break;
|
1721
|
+
case CVT_L_D: // Mips32r2: Truncate double to 64-bit long-word.
|
1722
|
+
i64 = static_cast<int64_t>(fs);
|
1723
|
+
set_fpu_register(fd_reg, i64 & 0xffffffff);
|
1724
|
+
set_fpu_register(fd_reg + 1, i64 >> 32);
|
1725
|
+
break;
|
1726
|
+
case TRUNC_L_D: // Mips32r2 instruction.
|
1727
|
+
i64 = static_cast<int64_t>(fs);
|
1728
|
+
set_fpu_register(fd_reg, i64 & 0xffffffff);
|
1729
|
+
set_fpu_register(fd_reg + 1, i64 >> 32);
|
1730
|
+
break;
|
1731
|
+
case ROUND_L_D: { // Mips32r2 instruction.
|
1732
|
+
double rounded = fs > 0 ? floor(fs + 0.5) : ceil(fs - 0.5);
|
1733
|
+
i64 = static_cast<int64_t>(rounded);
|
1734
|
+
set_fpu_register(fd_reg, i64 & 0xffffffff);
|
1735
|
+
set_fpu_register(fd_reg + 1, i64 >> 32);
|
1736
|
+
break;
|
1737
|
+
}
|
1738
|
+
case FLOOR_L_D: // Mips32r2 instruction.
|
1739
|
+
i64 = static_cast<int64_t>(floor(fs));
|
1740
|
+
set_fpu_register(fd_reg, i64 & 0xffffffff);
|
1741
|
+
set_fpu_register(fd_reg + 1, i64 >> 32);
|
1742
|
+
break;
|
1743
|
+
case CEIL_L_D: // Mips32r2 instruction.
|
1744
|
+
i64 = static_cast<int64_t>(ceil(fs));
|
1745
|
+
set_fpu_register(fd_reg, i64 & 0xffffffff);
|
1746
|
+
set_fpu_register(fd_reg + 1, i64 >> 32);
|
1747
|
+
break;
|
1748
|
+
case C_F_D:
|
1086
1749
|
UNIMPLEMENTED_MIPS();
|
1087
1750
|
break;
|
1088
1751
|
default:
|
@@ -1091,11 +1754,13 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1091
1754
|
break;
|
1092
1755
|
case W:
|
1093
1756
|
switch (instr->FunctionFieldRaw()) {
|
1094
|
-
case CVT_S_W:
|
1095
|
-
|
1757
|
+
case CVT_S_W: // Convert word to float (single).
|
1758
|
+
alu_out = get_fpu_register(fs_reg);
|
1759
|
+
set_fpu_register_float(fd_reg, static_cast<float>(alu_out));
|
1096
1760
|
break;
|
1097
1761
|
case CVT_D_W: // Convert word to double.
|
1098
|
-
|
1762
|
+
alu_out = get_fpu_register(fs_reg);
|
1763
|
+
set_fpu_register_double(fd_reg, static_cast<double>(alu_out));
|
1099
1764
|
break;
|
1100
1765
|
default:
|
1101
1766
|
UNREACHABLE();
|
@@ -1103,8 +1768,14 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1103
1768
|
break;
|
1104
1769
|
case L:
|
1105
1770
|
switch (instr->FunctionFieldRaw()) {
|
1771
|
+
case CVT_D_L: // Mips32r2 instruction.
|
1772
|
+
// Watch the signs here, we want 2 32-bit vals
|
1773
|
+
// to make a sign-64.
|
1774
|
+
i64 = (uint32_t) get_fpu_register(fs_reg);
|
1775
|
+
i64 |= ((int64_t) get_fpu_register(fs_reg + 1) << 32);
|
1776
|
+
set_fpu_register_double(fd_reg, static_cast<double>(i64));
|
1777
|
+
break;
|
1106
1778
|
case CVT_S_L:
|
1107
|
-
case CVT_D_L:
|
1108
1779
|
UNIMPLEMENTED_MIPS();
|
1109
1780
|
break;
|
1110
1781
|
default:
|
@@ -1121,7 +1792,7 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1121
1792
|
switch (instr->FunctionFieldRaw()) {
|
1122
1793
|
case JR: {
|
1123
1794
|
Instruction* branch_delay_instr = reinterpret_cast<Instruction*>(
|
1124
|
-
current_pc+Instruction::
|
1795
|
+
current_pc+Instruction::kInstrSize);
|
1125
1796
|
BranchDelayInstructionDecode(branch_delay_instr);
|
1126
1797
|
set_pc(next_pc);
|
1127
1798
|
pc_modified_ = true;
|
@@ -1129,16 +1800,21 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1129
1800
|
}
|
1130
1801
|
case JALR: {
|
1131
1802
|
Instruction* branch_delay_instr = reinterpret_cast<Instruction*>(
|
1132
|
-
current_pc+Instruction::
|
1803
|
+
current_pc+Instruction::kInstrSize);
|
1133
1804
|
BranchDelayInstructionDecode(branch_delay_instr);
|
1134
|
-
set_register(31, current_pc + 2* Instruction::
|
1805
|
+
set_register(31, current_pc + 2* Instruction::kInstrSize);
|
1135
1806
|
set_pc(next_pc);
|
1136
1807
|
pc_modified_ = true;
|
1137
1808
|
break;
|
1138
1809
|
}
|
1139
1810
|
// Instructions using HI and LO registers.
|
1140
1811
|
case MULT:
|
1812
|
+
set_register(LO, static_cast<int32_t>(i64hilo & 0xffffffff));
|
1813
|
+
set_register(HI, static_cast<int32_t>(i64hilo >> 32));
|
1814
|
+
break;
|
1141
1815
|
case MULTU:
|
1816
|
+
set_register(LO, static_cast<int32_t>(u64hilo & 0xffffffff));
|
1817
|
+
set_register(HI, static_cast<int32_t>(u64hilo >> 32));
|
1142
1818
|
break;
|
1143
1819
|
case DIV:
|
1144
1820
|
// Divide by zero was checked in the configuration step.
|
@@ -1149,7 +1825,7 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1149
1825
|
set_register(LO, rs_u / rt_u);
|
1150
1826
|
set_register(HI, rs_u % rt_u);
|
1151
1827
|
break;
|
1152
|
-
// Break and trap instructions
|
1828
|
+
// Break and trap instructions.
|
1153
1829
|
case BREAK:
|
1154
1830
|
case TGE:
|
1155
1831
|
case TGEU:
|
@@ -1161,6 +1837,23 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1161
1837
|
SoftwareInterrupt(instr);
|
1162
1838
|
}
|
1163
1839
|
break;
|
1840
|
+
// Conditional moves.
|
1841
|
+
case MOVN:
|
1842
|
+
if (rt) set_register(rd_reg, rs);
|
1843
|
+
break;
|
1844
|
+
case MOVCI: {
|
1845
|
+
uint32_t cc = instr->FCccValue();
|
1846
|
+
uint32_t fcsr_cc = get_fcsr_condition_bit(cc);
|
1847
|
+
if (instr->Bit(16)) { // Read Tf bit
|
1848
|
+
if (test_fcsr_bit(fcsr_cc)) set_register(rd_reg, rs);
|
1849
|
+
} else {
|
1850
|
+
if (!test_fcsr_bit(fcsr_cc)) set_register(rd_reg, rs);
|
1851
|
+
}
|
1852
|
+
break;
|
1853
|
+
}
|
1854
|
+
case MOVZ:
|
1855
|
+
if (!rt) set_register(rd_reg, rs);
|
1856
|
+
break;
|
1164
1857
|
default: // For other special opcodes we do the default operation.
|
1165
1858
|
set_register(rd_reg, alu_out);
|
1166
1859
|
};
|
@@ -1173,9 +1866,23 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1173
1866
|
set_register(LO, Unpredictable);
|
1174
1867
|
set_register(HI, Unpredictable);
|
1175
1868
|
break;
|
1869
|
+
default: // For other special2 opcodes we do the default operation.
|
1870
|
+
set_register(rd_reg, alu_out);
|
1871
|
+
}
|
1872
|
+
break;
|
1873
|
+
case SPECIAL3:
|
1874
|
+
switch (instr->FunctionFieldRaw()) {
|
1875
|
+
case INS:
|
1876
|
+
// Ins instr leaves result in Rt, rather than Rd.
|
1877
|
+
set_register(rt_reg, alu_out);
|
1878
|
+
break;
|
1879
|
+
case EXT:
|
1880
|
+
// Ext instr leaves result in Rt, rather than Rd.
|
1881
|
+
set_register(rt_reg, alu_out);
|
1882
|
+
break;
|
1176
1883
|
default:
|
1177
1884
|
UNREACHABLE();
|
1178
|
-
}
|
1885
|
+
};
|
1179
1886
|
break;
|
1180
1887
|
// Unimplemented opcodes raised an error in the configuration step before,
|
1181
1888
|
// so we can use the default here to set the destination register in common
|
@@ -1185,22 +1892,22 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
1185
1892
|
};
|
1186
1893
|
}
|
1187
1894
|
|
1895
|
+
|
1188
1896
|
// Type 2: instructions using a 16 bytes immediate. (eg: addi, beq)
|
1189
1897
|
void Simulator::DecodeTypeImmediate(Instruction* instr) {
|
1190
|
-
// Instruction fields
|
1898
|
+
// Instruction fields.
|
1191
1899
|
Opcode op = instr->OpcodeFieldRaw();
|
1192
|
-
int32_t rs = get_register(instr->
|
1900
|
+
int32_t rs = get_register(instr->RsValue());
|
1193
1901
|
uint32_t rs_u = static_cast<uint32_t>(rs);
|
1194
|
-
int32_t rt_reg = instr->
|
1902
|
+
int32_t rt_reg = instr->RtValue(); // destination register
|
1195
1903
|
int32_t rt = get_register(rt_reg);
|
1196
|
-
int16_t imm16 = instr->
|
1904
|
+
int16_t imm16 = instr->Imm16Value();
|
1197
1905
|
|
1198
|
-
int32_t ft_reg = instr->
|
1199
|
-
int32_t ft = get_register(ft_reg);
|
1906
|
+
int32_t ft_reg = instr->FtValue(); // destination register
|
1200
1907
|
|
1201
|
-
//
|
1908
|
+
// Zero extended immediate.
|
1202
1909
|
uint32_t oe_imm16 = 0xffff & imm16;
|
1203
|
-
//
|
1910
|
+
// Sign extended immediate.
|
1204
1911
|
int32_t se_imm16 = imm16;
|
1205
1912
|
|
1206
1913
|
// Get current pc.
|
@@ -1208,25 +1915,38 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
|
|
1208
1915
|
// Next pc.
|
1209
1916
|
int32_t next_pc = bad_ra;
|
1210
1917
|
|
1211
|
-
// Used for conditional branch instructions
|
1918
|
+
// Used for conditional branch instructions.
|
1212
1919
|
bool do_branch = false;
|
1213
1920
|
bool execute_branch_delay_instruction = false;
|
1214
1921
|
|
1215
|
-
// Used for arithmetic instructions
|
1922
|
+
// Used for arithmetic instructions.
|
1216
1923
|
int32_t alu_out = 0;
|
1217
|
-
// Floating point
|
1924
|
+
// Floating point.
|
1218
1925
|
double fp_out = 0.0;
|
1926
|
+
uint32_t cc, cc_value, fcsr_cc;
|
1219
1927
|
|
1220
|
-
// Used for memory instructions
|
1928
|
+
// Used for memory instructions.
|
1221
1929
|
int32_t addr = 0x0;
|
1930
|
+
// Value to be written in memory
|
1931
|
+
uint32_t mem_value = 0x0;
|
1222
1932
|
|
1223
1933
|
// ---------- Configuration (and execution for REGIMM)
|
1224
1934
|
switch (op) {
|
1225
|
-
// ------------- COP1. Coprocessor instructions
|
1935
|
+
// ------------- COP1. Coprocessor instructions.
|
1226
1936
|
case COP1:
|
1227
1937
|
switch (instr->RsFieldRaw()) {
|
1228
|
-
case BC1: //
|
1229
|
-
|
1938
|
+
case BC1: // Branch on coprocessor condition.
|
1939
|
+
cc = instr->FBccValue();
|
1940
|
+
fcsr_cc = get_fcsr_condition_bit(cc);
|
1941
|
+
cc_value = test_fcsr_bit(fcsr_cc);
|
1942
|
+
do_branch = (instr->FBtrueValue()) ? cc_value : !cc_value;
|
1943
|
+
execute_branch_delay_instruction = true;
|
1944
|
+
// Set next_pc
|
1945
|
+
if (do_branch) {
|
1946
|
+
next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize;
|
1947
|
+
} else {
|
1948
|
+
next_pc = current_pc + kBranchReturnOffset;
|
1949
|
+
}
|
1230
1950
|
break;
|
1231
1951
|
default:
|
1232
1952
|
UNREACHABLE();
|
@@ -1259,7 +1979,7 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
|
|
1259
1979
|
execute_branch_delay_instruction = true;
|
1260
1980
|
// Set next_pc
|
1261
1981
|
if (do_branch) {
|
1262
|
-
next_pc = current_pc + (imm16 << 2) + Instruction::
|
1982
|
+
next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize;
|
1263
1983
|
if (instr->IsLinkingInstruction()) {
|
1264
1984
|
set_register(31, current_pc + kBranchReturnOffset);
|
1265
1985
|
}
|
@@ -1323,6 +2043,21 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
|
|
1323
2043
|
addr = rs + se_imm16;
|
1324
2044
|
alu_out = ReadB(addr);
|
1325
2045
|
break;
|
2046
|
+
case LH:
|
2047
|
+
addr = rs + se_imm16;
|
2048
|
+
alu_out = ReadH(addr, instr);
|
2049
|
+
break;
|
2050
|
+
case LWL: {
|
2051
|
+
// al_offset is an offset of the effective address within an aligned word
|
2052
|
+
uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask;
|
2053
|
+
uint8_t byte_shift = kPointerAlignmentMask - al_offset;
|
2054
|
+
uint32_t mask = (1 << byte_shift * 8) - 1;
|
2055
|
+
addr = rs + se_imm16 - al_offset;
|
2056
|
+
alu_out = ReadW(addr, instr);
|
2057
|
+
alu_out <<= byte_shift * 8;
|
2058
|
+
alu_out |= rt & mask;
|
2059
|
+
break;
|
2060
|
+
}
|
1326
2061
|
case LW:
|
1327
2062
|
addr = rs + se_imm16;
|
1328
2063
|
alu_out = ReadW(addr, instr);
|
@@ -1331,12 +2066,47 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
|
|
1331
2066
|
addr = rs + se_imm16;
|
1332
2067
|
alu_out = ReadBU(addr);
|
1333
2068
|
break;
|
2069
|
+
case LHU:
|
2070
|
+
addr = rs + se_imm16;
|
2071
|
+
alu_out = ReadHU(addr, instr);
|
2072
|
+
break;
|
2073
|
+
case LWR: {
|
2074
|
+
// al_offset is an offset of the effective address within an aligned word
|
2075
|
+
uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask;
|
2076
|
+
uint8_t byte_shift = kPointerAlignmentMask - al_offset;
|
2077
|
+
uint32_t mask = al_offset ? (~0 << (byte_shift + 1) * 8) : 0;
|
2078
|
+
addr = rs + se_imm16 - al_offset;
|
2079
|
+
alu_out = ReadW(addr, instr);
|
2080
|
+
alu_out = static_cast<uint32_t> (alu_out) >> al_offset * 8;
|
2081
|
+
alu_out |= rt & mask;
|
2082
|
+
break;
|
2083
|
+
}
|
1334
2084
|
case SB:
|
1335
2085
|
addr = rs + se_imm16;
|
1336
2086
|
break;
|
2087
|
+
case SH:
|
2088
|
+
addr = rs + se_imm16;
|
2089
|
+
break;
|
2090
|
+
case SWL: {
|
2091
|
+
uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask;
|
2092
|
+
uint8_t byte_shift = kPointerAlignmentMask - al_offset;
|
2093
|
+
uint32_t mask = byte_shift ? (~0 << (al_offset + 1) * 8) : 0;
|
2094
|
+
addr = rs + se_imm16 - al_offset;
|
2095
|
+
mem_value = ReadW(addr, instr) & mask;
|
2096
|
+
mem_value |= static_cast<uint32_t>(rt) >> byte_shift * 8;
|
2097
|
+
break;
|
2098
|
+
}
|
1337
2099
|
case SW:
|
1338
2100
|
addr = rs + se_imm16;
|
1339
2101
|
break;
|
2102
|
+
case SWR: {
|
2103
|
+
uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask;
|
2104
|
+
uint32_t mask = (1 << al_offset * 8) - 1;
|
2105
|
+
addr = rs + se_imm16 - al_offset;
|
2106
|
+
mem_value = ReadW(addr, instr);
|
2107
|
+
mem_value = (rt << al_offset * 8) | (mem_value & mask);
|
2108
|
+
break;
|
2109
|
+
}
|
1340
2110
|
case LWC1:
|
1341
2111
|
addr = rs + se_imm16;
|
1342
2112
|
alu_out = ReadW(addr, instr);
|
@@ -1367,12 +2137,12 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
|
|
1367
2137
|
execute_branch_delay_instruction = true;
|
1368
2138
|
// Set next_pc
|
1369
2139
|
if (do_branch) {
|
1370
|
-
next_pc = current_pc + (imm16 << 2) + Instruction::
|
2140
|
+
next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize;
|
1371
2141
|
if (instr->IsLinkingInstruction()) {
|
1372
|
-
set_register(31, current_pc + 2* Instruction::
|
2142
|
+
set_register(31, current_pc + 2* Instruction::kInstrSize);
|
1373
2143
|
}
|
1374
2144
|
} else {
|
1375
|
-
next_pc = current_pc + 2 * Instruction::
|
2145
|
+
next_pc = current_pc + 2 * Instruction::kInstrSize;
|
1376
2146
|
}
|
1377
2147
|
break;
|
1378
2148
|
// ------------- Arithmetic instructions
|
@@ -1388,16 +2158,29 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
|
|
1388
2158
|
break;
|
1389
2159
|
// ------------- Memory instructions
|
1390
2160
|
case LB:
|
2161
|
+
case LH:
|
2162
|
+
case LWL:
|
1391
2163
|
case LW:
|
1392
2164
|
case LBU:
|
2165
|
+
case LHU:
|
2166
|
+
case LWR:
|
1393
2167
|
set_register(rt_reg, alu_out);
|
1394
2168
|
break;
|
1395
2169
|
case SB:
|
1396
2170
|
WriteB(addr, static_cast<int8_t>(rt));
|
1397
2171
|
break;
|
2172
|
+
case SH:
|
2173
|
+
WriteH(addr, static_cast<uint16_t>(rt), instr);
|
2174
|
+
break;
|
2175
|
+
case SWL:
|
2176
|
+
WriteW(addr, mem_value, instr);
|
2177
|
+
break;
|
1398
2178
|
case SW:
|
1399
2179
|
WriteW(addr, rt, instr);
|
1400
2180
|
break;
|
2181
|
+
case SWR:
|
2182
|
+
WriteW(addr, mem_value, instr);
|
2183
|
+
break;
|
1401
2184
|
case LWC1:
|
1402
2185
|
set_fpu_register(ft_reg, alu_out);
|
1403
2186
|
break;
|
@@ -1410,7 +2193,7 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
|
|
1410
2193
|
break;
|
1411
2194
|
case SDC1:
|
1412
2195
|
addr = rs + se_imm16;
|
1413
|
-
WriteD(addr,
|
2196
|
+
WriteD(addr, get_fpu_register_double(ft_reg), instr);
|
1414
2197
|
break;
|
1415
2198
|
default:
|
1416
2199
|
break;
|
@@ -1422,7 +2205,7 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
|
|
1422
2205
|
// We don't check for end_sim_pc. First it should not be met as the current
|
1423
2206
|
// pc is valid. Secondly a jump should always execute its branch delay slot.
|
1424
2207
|
Instruction* branch_delay_instr =
|
1425
|
-
reinterpret_cast<Instruction*>(current_pc+Instruction::
|
2208
|
+
reinterpret_cast<Instruction*>(current_pc+Instruction::kInstrSize);
|
1426
2209
|
BranchDelayInstructionDecode(branch_delay_instr);
|
1427
2210
|
}
|
1428
2211
|
|
@@ -1432,6 +2215,7 @@ void Simulator::DecodeTypeImmediate(Instruction* instr) {
|
|
1432
2215
|
}
|
1433
2216
|
}
|
1434
2217
|
|
2218
|
+
|
1435
2219
|
// Type 3: instructions using a 26 bytes immediate. (eg: j, jal)
|
1436
2220
|
void Simulator::DecodeTypeJump(Instruction* instr) {
|
1437
2221
|
// Get current pc.
|
@@ -1439,35 +2223,39 @@ void Simulator::DecodeTypeJump(Instruction* instr) {
|
|
1439
2223
|
// Get unchanged bits of pc.
|
1440
2224
|
int32_t pc_high_bits = current_pc & 0xf0000000;
|
1441
2225
|
// Next pc
|
1442
|
-
int32_t next_pc = pc_high_bits | (instr->
|
2226
|
+
int32_t next_pc = pc_high_bits | (instr->Imm26Value() << 2);
|
1443
2227
|
|
1444
2228
|
// Execute branch delay slot
|
1445
2229
|
// We don't check for end_sim_pc. First it should not be met as the current pc
|
1446
2230
|
// is valid. Secondly a jump should always execute its branch delay slot.
|
1447
2231
|
Instruction* branch_delay_instr =
|
1448
|
-
reinterpret_cast<Instruction*>(current_pc+Instruction::
|
2232
|
+
reinterpret_cast<Instruction*>(current_pc+Instruction::kInstrSize);
|
1449
2233
|
BranchDelayInstructionDecode(branch_delay_instr);
|
1450
2234
|
|
1451
2235
|
// Update pc and ra if necessary.
|
1452
2236
|
// Do this after the branch delay execution.
|
1453
2237
|
if (instr->IsLinkingInstruction()) {
|
1454
|
-
set_register(31, current_pc + 2* Instruction::
|
2238
|
+
set_register(31, current_pc + 2* Instruction::kInstrSize);
|
1455
2239
|
}
|
1456
2240
|
set_pc(next_pc);
|
1457
2241
|
pc_modified_ = true;
|
1458
2242
|
}
|
1459
2243
|
|
2244
|
+
|
1460
2245
|
// Executes the current instruction.
|
1461
2246
|
void Simulator::InstructionDecode(Instruction* instr) {
|
2247
|
+
if (v8::internal::FLAG_check_icache) {
|
2248
|
+
CheckICache(isolate_->simulator_i_cache(), instr);
|
2249
|
+
}
|
1462
2250
|
pc_modified_ = false;
|
1463
2251
|
if (::v8::internal::FLAG_trace_sim) {
|
1464
2252
|
disasm::NameConverter converter;
|
1465
2253
|
disasm::Disassembler dasm(converter);
|
1466
2254
|
// use a reasonably large buffer
|
1467
2255
|
v8::internal::EmbeddedVector<char, 256> buffer;
|
1468
|
-
dasm.InstructionDecode(buffer,
|
1469
|
-
|
1470
|
-
|
2256
|
+
dasm.InstructionDecode(buffer, reinterpret_cast<byte_*>(instr));
|
2257
|
+
PrintF(" 0x%08x %s\n", reinterpret_cast<intptr_t>(instr),
|
2258
|
+
buffer.start());
|
1471
2259
|
}
|
1472
2260
|
|
1473
2261
|
switch (instr->InstructionType()) {
|
@@ -1485,7 +2273,7 @@ void Simulator::InstructionDecode(Instruction* instr) {
|
|
1485
2273
|
}
|
1486
2274
|
if (!pc_modified_) {
|
1487
2275
|
set_register(pc, reinterpret_cast<int32_t>(instr) +
|
1488
|
-
Instruction::
|
2276
|
+
Instruction::kInstrSize);
|
1489
2277
|
}
|
1490
2278
|
}
|
1491
2279
|
|
@@ -1511,7 +2299,7 @@ void Simulator::Execute() {
|
|
1511
2299
|
Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
|
1512
2300
|
icount_++;
|
1513
2301
|
if (icount_ == ::v8::internal::FLAG_stop_sim_at) {
|
1514
|
-
|
2302
|
+
MipsDebugger dbg(this);
|
1515
2303
|
dbg.Debug();
|
1516
2304
|
} else {
|
1517
2305
|
InstructionDecode(instr);
|
@@ -1538,7 +2326,7 @@ int32_t Simulator::Call(byte_* entry, int argument_count, ...) {
|
|
1538
2326
|
int original_stack = get_register(sp);
|
1539
2327
|
// Compute position of stack on entry to generated code.
|
1540
2328
|
int entry_stack = (original_stack - (argument_count - 4) * sizeof(int32_t)
|
1541
|
-
-
|
2329
|
+
- kCArgsSlotsSize);
|
1542
2330
|
if (OS::ActivationFrameAlignment() != 0) {
|
1543
2331
|
entry_stack &= -OS::ActivationFrameAlignment();
|
1544
2332
|
}
|
@@ -1643,8 +2431,8 @@ uintptr_t Simulator::PopAddress() {
|
|
1643
2431
|
|
1644
2432
|
#undef UNSUPPORTED
|
1645
2433
|
|
1646
|
-
} } // namespace
|
2434
|
+
} } // namespace v8::internal
|
1647
2435
|
|
1648
|
-
#endif //
|
2436
|
+
#endif // USE_SIMULATOR
|
1649
2437
|
|
1650
2438
|
#endif // V8_TARGET_ARCH_MIPS
|