mfrc522 0.2.0 → 1.0.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
-  metadata.gz: 3ae695036f039f29942ea9a3e46cb365fb1e4fe7
-  data.tar.gz: c144d7dcf96074d047a3eba55523a27f2b3a74fb
+  metadata.gz: ec95f072c266803e40c9178fba2435c8f113d5ab
+  data.tar.gz: 98eb6c503409371dcb7e25f7e61f02494c5c13b4
 SHA512:
-  metadata.gz: ae5877e53851c774fdf68ac3ccb65fe3623d6a446e42e39f1ac843b0ecc8bcb7aaac68bf657ce632154d0e6876ee5786e884acebb9d9c53156818f6c9f1a8ecf
-  data.tar.gz: b8e8e5df57870a7da924c7a8dd207d2fa6ba89be281116c1b7ba5da5327bd3eb35b1e402bc80d61e06bce57293c8325f46dad25aca5409da129668c6f52e4ee7
+  metadata.gz: 23304b26becaed10dc250a013bc5a098894e9ce03f688986ca9fd403897bdf4472603aba2f7bc216bb26732a70c515c5f302c656e559a4fc2e6e51f5a8ec68a3
+  data.tar.gz: b8afd661c9ed6e8e898716e5c91bbfee19d373bb1287822f12fa8f42890d42e1cce1fc844312e312a52724a1f97ca58c5a53ad85215e12ac7931e12cd797cf88

data/lib/core_ext.rb

@@ -0,0 +1,35 @@
+class Array
+  def append_uint(number, byte)
+    raise 'Only support unsigned integer' if number < 0
+    raise 'Insufficient bytes' if number.abs >= (1 << (byte * 8))
+
+    until byte == 0
+      self << (number & 0xFF)
+      number >>= 8
+      byte -= 1
+    end
+    self
+  end
+
+  def to_uint
+    int = 0
+    self.each_with_index do |byte, index|
+      int |= (byte << (index * 8))
+    end
+    int
+  end
+
+  def append_sint(number, byte)
+    raise 'Insufficient bytes' if number.abs >= (1 << (byte * 8))
+
+    sign = (number < 0) ? 1 : 0
+    number &= (1 << ((byte * 8) - 1)) - 1
+    self.append_uint(number, byte)
+    self << (self.pop | (sign << 7))
+  end
+
+  def to_sint
+    sign = (self.last & 0x80 != 0) ? (-1 ^ ((1 << ((self.size * 8) - 1)) - 1)) : 0
+    sign | self.to_uint
+  end
+end

data/lib/exceptions.rb

@@ -0,0 +1,14 @@
+class CommunicationError < StandardError; end
+class PICCTimeoutError < CommunicationError; end
+class PCDTimeoutError < CommunicationError; end
+class IncorrectCRCError < CommunicationError; end
+class CollisionError < CommunicationError; end
+
+class UnexpectedDataError < StandardError; end
+
+class MifareNakError < StandardError; end
+
+class DESFireError < StandardError; end
+class UnauthenticatedError < DESFireError; end
+class ReceiptStatusError < DESFireError; end
+class ReceiptIntegrityError < DESFireError; end

data/lib/iso144434.rb

@@ -0,0 +1,245 @@
+class ISO144434 < PICC
+  FSCI_to_FSC = [16, 24, 32, 40, 48, 64, 96, 128, 256]
+
+  CMD_RATS              = 0xE0
+  CMD_PPS               = 0xD0
+  CMD_DESELECT          = 0xC2
+  CMD_SUCCESS           = 0x00
+  CMD_ADDITIONAL_FRAME  = 0xAF
+
+  def initialize(pcd, uid, sak)
+    super
+
+    @cid = 0x00 # We don't support CID
+    @fsc = 16 # Assume PICC only supports 16 bytes frame
+    @fwt = 256 # 77.33ms(256 ticks) default frame waiting time
+
+    @support_cid = false
+    @support_nad = false
+    @block_number = 0
+    @selected = false
+  end
+
+  # ISO/IEC 14443-4 select
+  def select
+    # Send RATS (Request for Answer To Select)
+    buffer = [CMD_RATS, 0x50 | @cid]
+    received_data = @pcd.picc_transceive(buffer)
+
+    dr, ds = process_ats(received_data)
+
+    # Send PPS (Protocol and Parameter Selection Request)
+    buffer = [CMD_PPS | @cid, 0x11, (ds << 2) | dr]
+    received_data = @pcd.picc_transceive(buffer)
+    raise UnexpectedDataError, 'Incorrect response' if received_data[0] != (0xD0 | @cid)
+
+    # Set PCD baud rate
+    @pcd.transceiver_baud_rate(:tx, dr)
+    @pcd.transceiver_baud_rate(:rx, ds)
+
+    @block_number = 0
+    @max_frame_size = [64, @fsc].min
+    @max_inf_size = @max_frame_size - 3 # PCB + CRC16
+    @max_inf_size -= 1 if @support_cid
+    @max_inf_size -= 1 if @support_nad
+    @selected = true
+  end
+
+  # Send S(DESELECT)
+  def deselect
+    buffer = [CMD_DESELECT]
+    received_data = @pcd.picc_transceive(buffer)
+
+    if received_data[0] & 0xF7 == CMD_DESELECT
+      @selected = false
+      true
+    else
+      false
+    end
+  end
+
+  # Wrapper for handling ISO protocol
+  def transceive(send_data)
+    # Split data according to max buffer size
+    send_data = [send_data] unless send_data.is_a? Array
+    chained_data = send_data.each_slice(@max_inf_size).to_a
+
+    # Initialize I-block
+    pcb = 0x02
+
+    # Send chained data
+    until chained_data.empty?
+      pcb &= 0xEF # Reset chaining indicator
+      pcb |= 0x10 if chained_data.size > 1 # Set chaining
+      pcb |= @block_number # Set block number
+      data = chained_data.shift
+
+      buffer = [pcb] + data
+
+      finished = false
+      until finished
+        received_data = handle_wtx(buffer)
+
+        # Retreive response pcb from data
+        r_pcb = received_data[0]
+
+        # Received ACK
+        if r_pcb & 0xF6 == 0xA2
+          # If ACK matches current block number means success
+          # Otherwise transmit it again
+          if (pcb & 0x01) == (r_pcb & 0x01)
+            finished = true
+          end
+        else
+          finished = true
+        end
+      end
+
+      @block_number ^= 1 # toggle block number for next frame
+    end
+
+    received_chained_data = [received_data]
+
+    # Receive chained data
+    while r_pcb & 0x10 != 0
+      ack = 0xA2 | @block_number # Set block number
+      received_data = handle_wtx([ack]) # Send ACK to receive next frame
+
+      r_pcb = received_data[0]
+
+      received_chained_data << received_data
+
+      @block_number ^= 1 # toggle block number for next frame
+    end
+
+    # Collect INF from chain
+    inf = []
+    received_chained_data.each do |data|
+      inf_position = 1
+      inf_position += 1 if data[0] & 0x08 != 0 # CID present
+      inf_position += 1 if data[0] & 0x04 != 0 # NAD present
+
+      inf.concat(data[inf_position..-1])
+    end
+
+    inf
+  end
+
+  def resume_communication
+    deselect rescue nil
+    super
+  end
+
+  def halt
+    deselect rescue nil
+    super
+  end
+
+  private
+
+  def convert_iso_baud_rate_to_pcd_setting(value)
+    # ISO
+    # 0b000: 106kBd, 0b001: 212kBd, 0b010: 424kBd, 0b100: 848kBd
+    # MFRC522 register
+    # 0b000: 106kBd, 0b001: 212kBd, 0b010: 424kBd, 0b011: 848kBd
+    x = (value >> 2) & 0x01
+    y = (value >> 1) & 0x01
+    z = value & 0x01
+
+    ((x | y) << 1) + (x | (~y & z))
+  end
+
+  # Gether information from ATS (Answer to Select)
+  def process_ats(ats)
+    position = 1
+    t0 = ats[position] # Format byte
+
+    fsci = t0 & 0x0F # PICC buffer size integer
+    y1 = (t0 >> 4) & 0x07 # Optional frame(TA, TB, TC) indicator
+    @fsc = FSCI_to_FSC[fsci] # Convert buffer size integer to bytes
+    dr = 0 # default baud rate 106kBd
+    ds = 0
+
+    # Frame: TA
+    if y1 & 0x01 != 0
+      position += 1
+      ta = ats[position]
+
+      dr = ta & 0x07 # PCD to PICC baud rate
+      ds = (ta >> 4) & 0x07 # PICC to PCD baud rate
+
+      # Convert fastest baud rate to PCD setting
+      dr = convert_iso_baud_rate_to_pcd_setting(dr)
+      ds = convert_iso_baud_rate_to_pcd_setting(ds)
+
+      dr = 0
+      ds = 0
+    end
+
+    # Frame: TB
+    if y1 & 0x02 != 0
+      position += 1
+      tb = ats[position]
+
+      fwi = (tb >> 4) & 0x0F # Frame wating integer
+      sgfi = tb & 0x0F # Start-up frame guard integer
+
+      # Convert integers to real time
+      @fwt = (1 << fwi)
+      sgft = (1 << sgfi)
+
+      # Set frame waiting time
+      @pcd.internal_timer(@fwt)
+    end
+
+    # Get info about CID or NAD
+    if y1 & 0x04 != 0
+      position += 1
+      tc = ats[position]
+
+      @support_cid = true if tc & 0x02 != 0
+      @support_nad = true if tc & 0x01 != 0
+    end
+
+    # Start-up guard time
+    sleep 0.000302 * sgft
+
+    return dr, ds
+  end
+
+  def handle_wtx(data)
+    24.times do
+      begin
+        received_data = @pcd.picc_transceive(data)
+      rescue CommunicationError => e
+        raise e unless e.is_a? PICCTimeoutError
+
+        # Try sending NAK when timeout
+        nak = 0xB2 | @block_number
+        data = [nak]
+        next
+      end
+      
+      pcb = received_data[0]
+
+      # WTX detected
+      if pcb & 0xF7 == 0xF2
+        inf_position = (pcb & 0x08 != 0) ? 2 : 1
+        wtxm = received_data[inf_position] & 0x3F
+
+        # Set temporary timer
+        @pcd.internal_timer(@fwt * wtxm)
+
+        # Set WTX response
+        data = [0xF2, wtxm]
+      else
+        # Set timer back to FWT
+        @pcd.internal_timer(@fwt)
+
+        return received_data
+      end
+    end
+
+    raise PICCTimeoutError
+  end
+end

data/lib/mfrc522.rb

@@ -1,14 +1,18 @@
 require 'pi_piper'
 
-# For 3DES auth
 require 'openssl'
 require 'securerandom'
 
-require 'mifare/base'
+require 'core_ext'
+require 'exceptions'
+
+require 'picc'
+require 'iso144434'
+
+require 'mifare/key'
 require 'mifare/classic'
 require 'mifare/ultralight'
 require 'mifare/ultralight_c'
-require 'mifare/plus'
 require 'mifare/des_fire'
 
 include PiPiper
@@ -16,31 +20,15 @@ include PiPiper
 class MFRC522
 
   # PICC commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
-  PICC_REQA           = 0x26  # REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
-  PICC_WUPA           = 0x52  # Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
-  PICC_CT             = 0x88  # Cascade Tag. Not really a command, but used during anti collision.
-  PICC_SEL_CL1        = 0x93  # Anti collision/Select, Cascade Level 1
-  PICC_SEL_CL2        = 0x95  # Anti collision/Select, Cascade Level 2
-  PICC_SEL_CL3        = 0x97  # Anti collision/Select, Cascade Level 3
-  PICC_HLTA           = 0x50  # HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
-  # The commands used for MIFARE Classic (from http://www.mouser.com/ds/2/302/MF1S503x-89574.pdf, Section 9)
-  # Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
-  # The read/write commands can also be used for MIFARE Ultralight.
-  PICC_MF_AUTH_KEY_A  = 0x60  # Perform authentication with Key A
-  PICC_MF_AUTH_KEY_B  = 0x61  # Perform authentication with Key B
-  PICC_MF_READ        = 0x30  # Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
-  PICC_MF_WRITE       = 0xA0  # Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
-  PICC_MF_DECREMENT   = 0xC0  # Decrements the contents of a block and stores the result in the internal data register.
-  PICC_MF_INCREMENT   = 0xC1  # Increments the contents of a block and stores the result in the internal data register.
-  PICC_MF_RESTORE     = 0xC2  # Reads the contents of a block into the internal data register.
-  PICC_MF_TRANSFER    = 0xB0  # Writes the contents of the internal data register to a block.
-  # The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
-  # The PICC_MF_READ and PICC_MF_WRITE can also be used for MIFARE Ultralight.
-  PICC_UL_WRITE       = 0xA2  # Writes one 4 byte page to the PICC.
-  # The commands here is for Ultralight 3DES Authentication
-  PICC_UL_3DES_AUTH   = 0x1A
-  #
-  PICC_MF_ACK         = 0x0A   # Mifare Acknowledge
+  PICC_REQA         = 0x26  # REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
+  PICC_WUPA         = 0x52  # Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
+  PICC_CT           = 0x88  # Cascade Tag. Not really a command, but used during anti collision.
+  PICC_SEL_CL1      = 0x93  # Anti collision/Select, Cascade Level 1
+  PICC_SEL_CL2      = 0x95  # Anti collision/Select, Cascade Level 2
+  PICC_SEL_CL3      = 0x97  # Anti collision/Select, Cascade Level 3
+  PICC_HLTA         = 0x50  # HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
+  # Mifare Acknowledge
+  PICC_MF_ACK       = 0x0A
 
   # PCD commands
   PCD_Idle          = 0x00  # no action, cancels current command execution
@@ -112,14 +100,14 @@ class MFRC522
   TestDAC2Reg       = 0x3A  # defines the test value for TestDAC2
   TestADCReg        = 0x3B  # shows the value of ADC I and Q channels
 
-  # Constructor
-  def initialize(nrstpd = 24, chip = 0, spd = 8000000, timer = 50)
+  def initialize(nrstpd = 24, chip = 0, spd = 8000000, timer = 256)
     chip_option = { 0 => PiPiper::Spi::CHIP_SELECT_0,
                     1 => PiPiper::Spi::CHIP_SELECT_1,
                     2 => PiPiper::Spi::CHIP_SELECT_BOTH,
                     3 => PiPiper::Spi::CHIP_SELECT_NONE }
     @spi_chip = chip_option[chip]
     @spi_spd = spd
+    @timer = timer
 
     # Power it up
     nrstpd_pin = PiPiper::Pin.new(pin: nrstpd, direction: :out)
@@ -128,13 +116,7 @@ class MFRC522
 
     soft_reset # Perform software reset
 
-    write_spi(TModeReg, 0x8D) # Start timer by setting TAuto=1, and higher part of TPrescalerReg
-    write_spi(TPrescalerReg, 0x3E) # Set lower part of TPrescalerReg, and results in 2khz timer (f_timer = 13.56 MHz / (2*TPreScaler+1))
-    write_spi(TReloadRegH, (timer >> 8))
-    write_spi(TReloadRegL, (timer & 0xFF)) # 50 ticks @2khz defines 25ms per timer cycle
-    
-    write_spi(TxASKReg, 0x40) # Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
-    write_spi(ModeReg, 0x3D) # Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
+    pcd_config_reset # Set default setting
 
     antenna_on # Turn antenna on. They were disabled by the reset.
   end
@@ -143,47 +125,48 @@ class MFRC522
   def soft_reset
     write_spi(CommandReg, PCD_SoftReset)
     sleep 1.0 / 20.0 # wait 50ms
+
+    write_spi(TModeReg, 0x87) # Start timer by setting TAuto=1, and higher part of TPrescalerReg
+    write_spi(TPrescalerReg, 0xFF) # Set lower part of TPrescalerReg, and results in 302us timer (f_timer = 13.56 MHz / (2*TPreScaler+1))
+    
+    write_spi(TxASKReg, 0x40) # Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
+    write_spi(ModeReg, 0x3D) # Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
   end
 
-  # Read from SPI communication
-  def read_spi(reg)
-    output = 0
-    PiPiper::Spi.begin do |spi|
-      spi.chip_select_active_low(true)
-      spi.bit_order Spi::MSBFIRST
-      spi.clock @spi_spd
+  # Reset PCD config to default
+  def pcd_config_reset
+    # Clear ValuesAfterColl bit
+    write_spi_clear_bitmask(CollReg, 0x80)
 
-      spi.chip_select(@spi_chip) do
-        spi.write((reg << 1) & 0x7E | 0x80)
-        output = spi.read
-      end
-    end
-    output
-  end
+    # Reset transceiver baud rate to 106 kBd
+    transceiver_baud_rate(:tx, 0)
+    transceiver_baud_rate(:rx, 0)
 
-  # Write to SPI communication
-  def write_spi(reg, values)
-    PiPiper::Spi.begin do |spi|
-      spi.chip_select_active_low(true)
-      spi.bit_order Spi::MSBFIRST
-      spi.clock @spi_spd
+    # Set PCD timer value for 302us default timer
+    internal_timer(@timer)
+  end
 
-      spi.chip_select(@spi_chip) do
-        spi.write((reg << 1) & 0x7E, *values)
-      end
+  # Control transceive timeout value
+  def internal_timer(timer = nil)
+    if timer
+      write_spi(TReloadRegH, (timer >> 8) & 0xFF)
+      write_spi(TReloadRegL, (timer & 0xFF))
     end
+    (read_spi(TReloadRegH) << 8) | read_spi(TReloadRegL)
   end
 
-  # Helper for setting bits by mask
-  def write_spi_set_bitmask(reg, mask)
-    value = read_spi(reg)
-    write_spi(reg, value | mask)
-  end
+  # Control transceiver baud rate
+  # value = 0: 106kBd, 1: 212kBd, 2: 424kBd, 3: 848kBd
+  def transceiver_baud_rate(direction, value = nil)
+    reg = {tx: TxModeReg, rx: RxModeReg}
 
-  # Helper for clearing bits by mask
-  def write_spi_clear_bitmask(reg, mask)
-    value = read_spi(reg)
-    write_spi(reg, value & (~mask))
+    if value
+      value <<= 4
+      value |= 0x80 if value != 0
+      write_spi(reg.fetch(direction), value)
+    end
+
+    (read_spi(reg.fetch(direction)) >> 4) & 0x07
   end
 
   # Turn antenna on
@@ -206,135 +189,25 @@ class MFRC522
     (read_spi(RFCfgReg) & 0x70) >> 4
   end
 
-  # Calculate CRC using MFRC522's built-in coprocessor
-  def calculate_crc(data)
-    write_spi(CommandReg, PCD_Idle)               # Stop any active command.
-    write_spi(DivIrqReg, 0x04)                    # Clear the CRCIRq interrupt request bit
-    write_spi_set_bitmask(FIFOLevelReg, 0x80)     # FlushBuffer = 1, FIFO initialization
-    write_spi(FIFODataReg, data)                  # Write data to the FIFO
-    write_spi(CommandReg, PCD_CalcCRC)            # Start the calculation
-
-    # Wait for the command to complete
-    i = 5000
-    loop do
-      irq = read_spi(DivIrqReg)
-      break if (irq & 0x04) != 0
-      return :status_pcd_timeout if i == 0
-      i -= 1
-    end
-
-    write_spi(CommandReg, PCD_Idle)               # Stop calculating CRC for new content in the FIFO.
-
-    result = []
-    result << read_spi(CRCResultRegL)
-    result << read_spi(CRCResultRegH)
-    
-    return :status_ok, result
-  end
-
-  # Calculate and append CRC to data
-  def append_crc(data)
-    status, crc = calculate_crc(data)
-    return status if status != :status_ok
-    data << crc[0] << crc[1]
-
-    return :status_ok, data
-  end
-
-  # Check CRC using MFRC522's built-in coprocessor
-  def check_crc(data)
-    status, crc = calculate_crc(data[0..-3])
-    return status if status != :status_ok
-    return :status_crc_error if data[-2] != crc[0] || data[-1] != crc[1]
-
-    return :status_ok
-  end
-
-  # PCD transceive helper
-  def communicate_with_picc(command, send_data, framing_bit = 0, check_crc = false)
-    wait_irq = 0x00
-    wait_irq = 0x10 if command == PCD_MFAuthent
-    wait_irq = 0x30 if command == PCD_Transceive
-
-    write_spi(CommandReg, PCD_Idle)               # Stop any active command.
-    write_spi(ComIrqReg, 0x7F)                    # Clear all seven interrupt request bits
-    write_spi_set_bitmask(FIFOLevelReg, 0x80)     # FlushBuffer = 1, FIFO initialization
-    write_spi(FIFODataReg, send_data)             # Write sendData to the FIFO
-    write_spi(BitFramingReg, framing_bit)         # Bit adjustments
-    write_spi(CommandReg, command)                # Execute the command
-    if command == PCD_Transceive
-      write_spi_set_bitmask(BitFramingReg, 0x80)  # StartSend=1, transmission of data starts
-    end
-
-    # Wait for the command to complete
-    i = 2000
-    loop do
-      irq = read_spi(ComIrqReg)
-      break if (irq & wait_irq) != 0
-      return :status_picc_timeout if (irq & 0x01) != 0
-      return :status_pcd_timeout if i == 0
-      i -= 1
-    end
-
-    # Check for error
-    error = read_spi(ErrorReg)
-    return :status_error if (error & 0x13) != 0 # BufferOvfl ParityErr ProtocolErr
-
-    # Receiving data
-    received_data = []
-    data_length = read_spi(FIFOLevelReg)
-    while data_length > 0 do
-      data = read_spi(FIFODataReg)
-      received_data << data
-      data_length -=1
-    end
-    valid_bits = read_spi(ControlReg) & 0x07
-
-    # Check CRC if requested
-    if !received_data.empty? && check_crc
-      return :status_mifare_nack if received_data.count == 1 && valid_bits == 4
-      return :status_crc_error if received_data.count < 2 || valid_bits != 0
-
-      status = check_crc(received_data)
-      return status if status != :status_ok
-    end
-
-    status = :status_ok
-    status = :status_collision if (error & 0x08) != 0 # CollErr
-
-    return status, received_data, valid_bits
-  end
-
   # Wakes PICC from HALT or IDLE to ACTIVE state
-  #
   # Accept PICC_REQA and PICC_WUPA command
   def picc_request(picc_command)
-    write_spi_clear_bitmask(CollReg, 0x80)  # ValuesAfterColl=1 => Bits received after collision are cleared.
+    pcd_config_reset
 
     status, _received_data, valid_bits = communicate_with_picc(PCD_Transceive, picc_command, 0x07)
 
-    return status if status != :status_ok
-    return :status_unknown_data if valid_bits != 0 # REQA or WUPA command return 16 bits(full byte)
-
-    return :status_ok
+    status == :status_ok && valid_bits == 0 # REQA or WUPA command return 16 bits(full byte)
   end
 
   # Instruct PICC in ACTIVE state go to HALT state
   def picc_halt
-    buffer = [PICC_HLTA, 0]
-
-    # Calculate CRC and append it into buffer
-    status, buffer = append_crc(buffer)
-    return status if status != :status_ok
+    buffer = append_crc([PICC_HLTA, 0])
 
     status, _received_data, _valid_bits = communicate_with_picc(PCD_Transceive, buffer)
 
     # PICC in HALT state will not respond
     # If PICC sent reply, means it didn't acknowledge the command we sent
-    return :status_ok if status == :status_picc_timeout
-    return :status_error if status == :status_ok
-
-    return status
+    status == :status_picc_timeout
   end
 
   # Select PICC for further communication
@@ -364,13 +237,14 @@ class MFRC522
     #  10 bytes        1       CT    uid0  uid1  uid2
     #                  2       CT    uid3  uid4  uid5
     #                  3       uid6  uid7  uid8  uid9
+    pcd_config_reset
 
-    write_spi_clear_bitmask(CollReg, 0x80)    # ValuesAfterColl=1 => Bits received after collision are cleared.
-    select_level = [PICC_SEL_CL1, PICC_SEL_CL2, PICC_SEL_CL3]
+    cascade_levels = [PICC_SEL_CL1, PICC_SEL_CL2, PICC_SEL_CL3]
     uid = []
+    sak = 0
 
-    for current_cascade_level in 0..2
-      buffer = [select_level[current_cascade_level]]
+    cascade_levels.each do |cascade_level|
+      buffer = [cascade_level]
       current_level_known_bits = 0
       received_data = []
       valid_bits = 0
@@ -380,7 +254,7 @@ class MFRC522
           # ensure there's nothing weird in buffer
           if buffer.size != 6 && !buffer.select{|b| !buffer.is_a?(Fixnum)}.empty?
             current_level_known_bits = 0
-            buffer = []
+            buffer = [cascade_level]
             next
           end
 
@@ -389,8 +263,7 @@ class MFRC522
           buffer << (buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5]) # Block Check Character
 
           # Append CRC to buffer
-          status, buffer = append_crc(buffer)
-          return status if status != :status_ok
+          buffer = append_crc(buffer)
         else
           tx_last_bits = current_level_known_bits % 8
           uid_full_byte = current_level_known_bits / 8
@@ -400,9 +273,8 @@ class MFRC522
 
         framing_bit = (tx_last_bits << 4) + tx_last_bits
 
-        # Try to fetch UID
+        # Select it
         status, received_data, valid_bits = communicate_with_picc(PCD_Transceive, buffer, framing_bit)
-        return status if status != :status_ok
 
         # Append received UID into buffer if not doing full select
         buffer = buffer[0...all_full_byte] + received_data[0..3] if current_level_known_bits < 32
@@ -411,12 +283,14 @@ class MFRC522
         if status == :status_collision
           collision = read_spi(CollReg)
 
-          return :status_collision if (collision & 0x20) != 0 # CollPosNotValid - We don't know where collision happened
+          # CollPosNotValid - We don't know where collision happened
+          raise CollisionError if (collision & 0x20) != 0
+          
           collision_position = collision & 0x1F
           collision_position = 32 if collision_position == 0 # Values 0-31, 0 means bit 32
-          return :status_internal_error if collision_position <= current_level_known_bits
+          raise CollisionError if collision_position <= current_level_known_bits
         
-          # Mark the bit
+          # Mark the collision bit
           current_level_known_bits = collision_position
           uid_bit = (current_level_known_bits - 1) % 8
           uid_byte = (current_level_known_bits / 8) + (uid_bit != 0 ? 1 : 0)
@@ -425,88 +299,42 @@ class MFRC522
           break if current_level_known_bits >= 32
           current_level_known_bits = 32 # We've already known all bits, loop again for a complete select
         else
-          return status
+          raise CommunicationError, status
         end 
       end
 
       # We've finished current cascade level
-      # Check and collect all uid in this level
+      # Check and collect all uid stored in buffer
 
       # Append UID
       uid << buffer[2] if buffer[2] != PICC_CT
       uid << buffer[3] << buffer[4] << buffer[5]
 
       # Check the result of full select
-      return :status_sak_error if received_data.count != 3 || valid_bits != 0 # Select Acknowledge is 1 byte + CRC_A
-
-      status = check_crc(received_data)
-      return status if status != :status_ok
+      # Select Acknowledge is 1 byte + CRC16
+      raise UnexpectedDataError, 'Unknown SAK format' if received_data.size != 3 || valid_bits != 0 
+      raise IncorrectCRCError unless check_crc(received_data)
 
       sak = received_data[0]
-
-      break if (received_data[0] & 0x04) == 0 # No more cascade level
+      break if (sak & 0x04) == 0 # No more cascade level
     end
 
-    return :status_ok, uid, sak
+    return uid, sak
   end
 
-  # Trying to wake it up again
+  # Trying to restart picc
   def reestablish_picc_communication(uid)
-    status = picc_halt
-    return status if status != :status_ok
-
-    status = picc_request(PICC_WUPA)
-    return status if status != :status_ok
-
-    status, new_uid, new_sak = picc_select
-    return status if status != :status_ok
-
-    if uid == new_uid
-      return :status_ok
-    else
-      return :status_different_card_detected
+    picc_halt
+    picc_request(PICC_WUPA)
+
+    begin
+      new_uid, _new_sak = picc_select
+      status = true
+    rescue CommunicationError
+      status = false
     end
-  end
 
-  # ISO/IEC 14443-4 select
-  def iso_select
-    
-  end
-
-  # Lookup error message
-  def error_type(error)
-    case error
-    when :status_ok
-      'It worked'
-    when :status_pcd_timeout
-      'Reader did not responding'
-    when :status_picc_timeout
-      'Tag did not responding'
-    when :status_crc_error
-      'CRC check failed'
-    when :status_mifare_nack
-      'Tag sent negative acknowledge'
-    when :status_collision
-      'Multiple tags detected'
-    when :status_unknown_data
-      'Incorrect data received'
-    when :status_internal_error
-      'Something went wrong but it shouldnt happen'
-    when :status_sak_error
-      'Incorrect select acknowledge'
-    when :status_auth_failed
-      'Authentication failed'
-    when :status_data_length_error
-      'Incorrect input data length'
-    when :status_incorrect_input
-      'Incorrect input'
-    when :status_different_card_detected
-      'Different card detected while reselecting'
-    when :status_error
-      'Something went wrong'
-    else
-      'Unknown error type'
-    end
+    status && uid == new_uid
   end
 
   # Lookup PICC name using sak
@@ -557,7 +385,7 @@ class MFRC522
     return :picc_unknown
   end
 
-  # Start encrypted Crypto1 communication between reader and Mifare PICC
+  # Start Crypto1 communication between reader and Mifare PICC
   #
   # PICC must be selected before calling for authentication
   # Remember to deauthenticate after communication, or no new communication can be made
@@ -566,106 +394,170 @@ class MFRC522
   # Checks datasheets for block address numbering of your PICC
   #
   def mifare_crypto1_authenticate(command, block_addr, sector_key, uid)
-    #
     # Buffer[12]: {command, block_addr, sector_key[6], uid[4]}
-    #
     buffer = [command, block_addr]
-    buffer += sector_key[0..5]
-    buffer += uid[0..3]
+    buffer.concat(sector_key[0..5])
+    buffer.concat(uid[0..3])
 
-    status, _received_data, _valid_bits = communicate_with_picc(PCD_MFAuthent, buffer)
+    communicate_with_picc(PCD_MFAuthent, buffer)
 
-    return status if status != :status_ok
-    return :status_auth_failed if (read_spi(Status2Reg) & 0x08) == 0
-
-    return :status_ok
+    # Check MFCrypto1On bit
+    (read_spi(Status2Reg) & 0x08) != 0
   end
 
-  # Stop Mifare encrypted communication
+  # Stop Crypto1 communication
   def mifare_crypto1_deauthenticate
     write_spi_clear_bitmask(Status2Reg, 0x08) # Clear MFCrypto1On bit
   end
 
-  def mifare_ultralight_3des_check
-    # Ask for authentication
-    buffer = [PICC_UL_3DES_AUTH, 0x00]
-    status, received_data = mifare_transceive(buffer)
-    return status if status != :status_ok
-    return :status_unknown_data if received_data[0] != 0xAF
+  # Append CRC to buffer and check CRC or Mifare acknowledge
+  def picc_transceive(send_data, accept_timeout = false)
+    send_data = append_crc(send_data)
+
+    puts "Sending Data: #{send_data.map{|x|x.to_s(16).rjust(2,'0').upcase}}" if ENV['DEBUG']
+
+    # Transfer data
+    status, received_data, valid_bits = communicate_with_picc(PCD_Transceive, send_data)
+    return [] if status == :status_picc_timeout && accept_timeout
+    raise PICCTimeoutError if status == :status_picc_timeout
+    raise CommunicationError, status if status != :status_ok
+
+    puts "Received Data: #{received_data.map{|x|x.to_s(16).rjust(2,'0').upcase}}" if ENV['DEBUG']
 
-    return :status_ok, received_data
+    # Data exists, check CRC and return
+    if received_data.size > 1
+      raise IncorrectCRCError unless check_crc(received_data)
+
+      return received_data[0..-3]
+    end
+
+    raise UnexpectedDataError, 'Incorrect Mifare ACK format' if received_data.size != 1 || valid_bits != 4 # ACK is 4 bits long
+    raise MifareNakError, received_data[0] if received_data[0] != PICC_MF_ACK
+
+    received_data
   end
 
-  def mifare_ultralight_3des_authenticate(des_key)
-    status, received_data = mifare_ultralight_3des_check
-    return status if status != :status_ok
-
-    # Use received data as IV for next transmission
-    next_iv = received_data[1..8]
-
-    # Cipher
-    cipher = OpenSSL::Cipher.new 'des-ede3-cbc'
-    cipher.key = [des_key*2].pack('H*')
-    cipher.padding = 0
-
-    # Decrypt challenge random number and rotate it by 8 bits
-    cipher.decrypt
-    cipher.iv = "\x00"*8
-    challenge = received_data[1..8].pack('C*')
-    challenge = cipher.update(challenge) + cipher.final
-    challenge = challenge.bytes.rotate
-
-    # Generate 8 bytes random number and encrypt the response 
-    random_number = SecureRandom.random_bytes(8)
-    cipher.encrypt
-    cipher.iv = next_iv.pack('C*')
-    response = cipher.update(random_number + challenge.pack('C*')) + cipher.final
-    response = response.bytes
-
-    # Receive verification
-    buffer = [0xAF] + response
-    status, received_data = mifare_transceive(buffer)
-    return status if status != :status_ok
-    return :status_unknown_data if received_data[0] != 0x00
-
-    # Check if verification matches random_number rotated by 8 bits
-    cipher.decrypt
-    cipher.iv = response[-8..-1].pack('C*')
-    verification = received_data[1..8].pack('C*')
-    verification = cipher.update(verification) + cipher.final
-
-    if random_number.bytes.rotate != verification.bytes
-      picc_halt
-      return :status_auth_failed
+  private
+
+  # Read from SPI communication
+  def read_spi(reg)
+    output = 0
+    PiPiper::Spi.begin do |spi|
+      spi.chip_select_active_low(true)
+      spi.bit_order Spi::MSBFIRST
+      spi.clock @spi_spd
+
+      spi.chip_select(@spi_chip) do
+        spi.write((reg << 1) & 0x7E | 0x80)
+        output = spi.read
+      end
     end
+    output
+  end
+
+  # Write to SPI communication
+  def write_spi(reg, values)
+    PiPiper::Spi.begin do |spi|
+      spi.chip_select_active_low(true)
+      spi.bit_order Spi::MSBFIRST
+      spi.clock @spi_spd
 
-    return :status_ok
+      spi.chip_select(@spi_chip) do
+        spi.write((reg << 1) & 0x7E, *values)
+      end
+    end
   end
 
-  # Helper that append CRC to buffer and check CRC or Mifare acknowledge
-  def mifare_transceive(send_data, accept_timeout = false)
-    # Append CRC
-    status, send_data = append_crc(send_data)
-    return status if status != :status_ok
+  # Set bits by mask
+  def write_spi_set_bitmask(reg, mask)
+    value = read_spi(reg)
+    write_spi(reg, value | mask)
+  end
 
-    # Transfer data
-    status, received_data, valid_bits = communicate_with_picc(PCD_Transceive, send_data)
-    return :status_ok if status == :status_picc_timeout && accept_timeout
-    return status if status != :status_ok
+  # Clear bits by mask
+  def write_spi_clear_bitmask(reg, mask)
+    value = read_spi(reg)
+    write_spi(reg, value & (~mask))
+  end
 
-    # Data exists, check CRC and return
-    if received_data.size > 1
-      return :status_crc_error if received_data.size < 3 || valid_bits != 0
+  # PCD transceive helper
+  def communicate_with_picc(command, send_data, framing_bit = 0)
+    wait_irq = 0x00
+    wait_irq = 0x10 if command == PCD_MFAuthent
+    wait_irq = 0x30 if command == PCD_Transceive
+
+    write_spi(CommandReg, PCD_Idle)               # Stop any active command.
+    write_spi(ComIrqReg, 0x7F)                    # Clear all seven interrupt request bits
+    write_spi_set_bitmask(FIFOLevelReg, 0x80)     # FlushBuffer = 1, FIFO initialization
+    write_spi(FIFODataReg, send_data)             # Write sendData to the FIFO
+    write_spi(BitFramingReg, framing_bit)         # Bit adjustments
+    write_spi(CommandReg, command)                # Execute the command
+    if command == PCD_Transceive
+      write_spi_set_bitmask(BitFramingReg, 0x80)  # StartSend=1, transmission of data starts
+    end
+
+    # Wait for the command to complete
+    i = 2000
+    loop do
+      irq = read_spi(ComIrqReg)
+      break if (irq & wait_irq) != 0
+      return :status_picc_timeout if (irq & 0x01) != 0
+      return :status_pcd_timeout if i == 0
+      i -= 1
+    end
+
+    # Check for error
+    error = read_spi(ErrorReg)
+    return :status_error if (error & 0x13) != 0 # BufferOvfl ParityErr ProtocolErr
 
-      status = check_crc(received_data)
-      return status, received_data[0..-3]
+    # Receiving data
+    received_data = []
+    data_length = read_spi(FIFOLevelReg)
+    while data_length > 0 do
+      data = read_spi(FIFODataReg)
+      received_data << data
+      data_length -=1
     end
+    valid_bits = read_spi(ControlReg) & 0x07
+
+    status = :status_ok
+    status = :status_collision if (error & 0x08) != 0 # CollErr
+
+    return status, received_data, valid_bits
+  end
+
+  def calculate_crc(data)
+    write_spi(CommandReg, PCD_Idle)               # Stop any active command.
+    write_spi(DivIrqReg, 0x04)                    # Clear the CRCIRq interrupt request bit
+    write_spi_set_bitmask(FIFOLevelReg, 0x80)     # FlushBuffer = 1, FIFO initialization
+    write_spi(FIFODataReg, data)                  # Write data to the FIFO
+    write_spi(CommandReg, PCD_CalcCRC)            # Start the calculation
+
+    # Wait for the command to complete
+    i = 5000
+    loop do
+      irq = read_spi(DivIrqReg)
+      break if (irq & 0x04) != 0
+      raise PCDTimeoutError, 'Error calculating CRC' if i == 0
+      i -= 1
+    end
+
+    write_spi(CommandReg, PCD_Idle)               # Stop calculating CRC for new content in the FIFO.
+
+    [read_spi(CRCResultRegL), read_spi(CRCResultRegH)]
+  end
+
+  def append_crc(data)
+    data + calculate_crc(data)
+  end
+
+  def check_crc(data)
+    raise UnexpectedDataError, 'Data too short for CRC check' if data.size < 3
 
-    # Data doesn't exist, check mifare acknowledge
-    return :status_error if received_data.size != 1 || valid_bits != 4 # ACK is 4 bits long
-    return :status_mifare_nack if received_data[0] != PICC_MF_ACK
+    data = data.dup
+    crc = data.pop(2)
 
-    return :status_ok
+    crc == calculate_crc(data)
   end
 
 end