metasm 1.0.3 → 1.0.4

data/metasm/cpu/openrisc/render.rb

@@ -0,0 +1,37 @@
+#    This file is part of Metasm, the Ruby assembly manipulation suite
+#    Copyright (C) 2006-2009 Yoann GUILLOT
+#
+#    Licence is LGPL, see LICENCE in the top-level directory
+
+
+require 'metasm/cpu/openrisc/opcodes'
+require 'metasm/render'
+
+module Metasm
+class OpenRisc
+	class Reg
+		include Renderable
+		def render ; ["r#@v"] end
+	end
+
+	class FpReg
+		include Renderable
+		def render ; ["f#@v"] end
+	end
+
+	class Memref
+		include Renderable
+		def render
+			off = @offset
+			off = nil if off == Expression[0]
+			r = []
+			r << { 1 => 'byte ', 2 => 'word ', 4 => 'dword ', 8 => 'qword ' }[@msz]
+			r << '['
+			r << @base if @base
+			r << '+' if @base and off
+			r << off if off
+			r << ']'
+		end
+	end
+end
+end

data/metasm/cpu/ppc/decode.rb

@@ -176,12 +176,6 @@ class PowerPC
 		df
 	end
 
-	# hash opname => lambda { |di, *sym_args| binding }
-	def backtrace_binding
-		@backtrace_binding ||= init_backtrace_binding
-	end
-	def backtrace_binding=(b) @backtrace_binding = b end
-
 	def init_backtrace_binding
 		@backtrace_binding ||= {}
 		opcode_list.map { |ol| ol.name }.uniq.each { |op|
@@ -231,25 +225,6 @@ class PowerPC
 		@backtrace_binding
 	end
 
-	def get_backtrace_binding(di)
-		a = di.instruction.args.map { |arg|
-			case arg
-			when Memref; arg.symbolic(di.address)
-			when Reg; arg.symbolic
-			else arg
-			end
-		}
-
-		binding = if binding = backtrace_binding[di.instruction.opname]
-			binding[di, *a]
-		else
-			puts "unknown instruction to emu #{di}" if $VERBOSE
-			{}
-		end
-
-		binding
-	end
-
 	def get_xrefs_x(dasm, di)
 		return [] if not di.opcode.props[:setip]
 

data/metasm/cpu/ppc/main.rb

@@ -32,7 +32,7 @@ class PowerPC < CPU
 		@s_to_i = (0..31).inject({}) { |h, i| h.update((i == 1 ? 'sp' : "r#{i}") => i) }
 		@i_to_s = @s_to_i.invert
 		Sym = @s_to_i.sort.transpose.last
-		def symbolic ; Sym[@i] end
+		def symbolic(di=nil) ; Sym[@i] end
 	end
 
 	# special purpose reg
@@ -47,7 +47,7 @@ class PowerPC < CPU
 		end
 
 		Sym = @i_to_s.sort.inject({}) { |h, (k, v)| h.update k => v.to_sym }
-		def symbolic ; Sym[@i] end
+		def symbolic(di=nil) ; Sym[@i] end
 		def render ; [self.class.i_to_s[@i] || "spr#@i"] end
 	end
 
@@ -65,7 +65,7 @@ class PowerPC < CPU
 
 	# machine state reg
 	class MSR < Reg
-		def symbolic ; :msr end
+		def symbolic(di=nil) ; :msr end
 		def render ; ['msr'] end
 	end
 
@@ -79,7 +79,7 @@ class PowerPC < CPU
 		@s_to_i = (0..31).inject({}) { |h, i| h.update "cr#{i}" => i }
 		@i_to_s = @s_to_i.invert
 		Sym = @s_to_i.sort.transpose.last
-		def symbolic ; "cr#@i".to_sym end
+		def symbolic(di=nil) ; "cr#@i".to_sym end
 	end
 
 	# indirection : reg+reg or reg+16b_off
@@ -90,12 +90,12 @@ class PowerPC < CPU
 			@base, @offset = base, offset
 		end
 
-		def symbolic(orig)
+		def symbolic(di=nil)
 			b = @base.symbolic
 			b = nil if b == :r0	# XXX is it true ?
 			o = @offset
 			o = o.symbolic if o.kind_of?(Reg)
-			Indirection[Expression[b, :+, o].reduce, 4, orig]
+			Indirection[Expression[b, :+, o].reduce, 4, (di.address if di)]
 		end
 
 		include Renderable

data/metasm/cpu/ppc/opcodes.rb

@@ -39,7 +39,7 @@ class PowerPC
 		addop_branch(nbase+'dz',  bin|(0b10010<<21), :ign_bo_at2, :stopexec, *argprops) if not argprops.include? :ctr
 		addop_branch(nbase+'dnz', bin|(0b10000<<21), :ign_bo_at2, :stopexec, *argprops) if not argprops.include? :ctr
 
-		# conditionnal
+		# conditional
 		%w[lt gt eq so].each_with_index { |cd, i|
 			ncd = {'lt' => 'gte', 'gt' => 'lte', 'eq' => 'ne', 'so' => 'nso'}[cd]
 			addop_branch(nbase+cd, bin|(0b1100<<21)|(i<<16), :ign_bo_at, *argprops)
@@ -116,14 +116,13 @@ class PowerPC
 			:tbr => 0x3FF, :th => 15, :to => 31, :u => 15, :ui => 0xFFFF,
 			:ign_bo_zzz => 0b101111111, :ign_bo_z => 1, :ign_bo_at => 3, :ign_bo_at2 => 0b100111111
 
-		@valid_args = @fields_mask.dup
-		[:ign_bo_zzz, :ign_bo_z, :ign_bo_at, :ign_bo_at2, :aa, :lk, :oe, :rc, :l].each { |k| @valid_args.delete k }
-
 		@fields_shift[:ra_i16]  = @fields_shift[:ra_i16s] = @fields_shift[:ra_i16q] = 0
 		@fields_mask[:ra_i16]  = (@fields_mask[:d]  << @fields_shift[:d]) | (@fields_mask[:ra] << @fields_shift[:ra])
 		@fields_mask[:ra_i16s] = (@fields_mask[:ds] << @fields_shift[:d]) | (@fields_mask[:ra] << @fields_shift[:ra])
 		@fields_mask[:ra_i16q] = (@fields_mask[:dq] << @fields_shift[:d]) | (@fields_mask[:ra] << @fields_shift[:ra])
 
+		@valid_args = @fields_mask.dup
+		[:ign_bo_zzz, :ign_bo_z, :ign_bo_at, :ign_bo_at2, :aa, :lk, :oe, :rc, :l].each { |k| @valid_args.delete k }
 
 		addop_branch 'b', 0x48000000, :li, :stopexec
 		addop_branchcond 'b', 0x40000000, :bd

data/metasm/cpu/python/decode.rb

@@ -66,10 +66,6 @@ class Python
 		di
 	end
 
-	def backtrace_binding
-		@backtrace_binding ||= init_backtrace_binding
-	end
-
 	def init_backtrace_binding
 		@backtrace_binding ||= {}
 
@@ -83,22 +79,6 @@ class Python
 		@backtrace_binding
 	end
 
-	def get_backtrace_binding(di)
-		a = di.instruction.args.map { |arg|
-			case arg
-			when Var; arg.symbolic
-			else arg
-			end
-		}
-
-		if binding = backtrace_binding[di.opcode.basename]
-			binding[di, *a]
-		else
-			puts "unhandled instruction to backtrace: #{di}" if $VERBOSE
-			{ :incomplete_binding => Expression[1] }
-		end
-	end
-
 	def get_xrefs_x(dasm, di)
 		return [] if not di.opcode.props[:setip]
 

data/metasm/cpu/python/main.rb

@@ -25,7 +25,7 @@ class Python < CPU
 			o.class == self.class and o.i == i
 		end
 
-		def symbolic; "var_#{@i}".to_sym end
+		def symbolic(di=nil); "var_#{@i}".to_sym end
 
 		def render
 			["var_#@i"]

data/metasm/cpu/sh4/decode.rb

@@ -197,10 +197,6 @@ class Sh4
 		end
 	end
 
-	def backtrace_binding
-		@backtrace_binding ||= init_backtrace_binding
-	end
-
 	def opsz(di)
 		ret = @size
 		ret = 8 if di and di.opcode.name =~ /\.b/
@@ -298,7 +294,7 @@ class Sh4
 			when GPR, XFR, XDR, FVR, DR, FR, XMTRX; arg.symbolic
 			when MACH, MACL, PR, FPUL, PC, FPSCR; arg.symbolic
 			when SR, SSR, SPC, GBR, VBR, SGR, DBR; arg.symbolic
-			when Memref; arg.symbolic(di.address, di.opcode.props[:memsz]/8)
+			when Memref; arg.symbolic(di)
 			else arg
 			end
 		}
@@ -332,7 +328,7 @@ class Sh4
 
 		val = case val
 		      when Reg; val.symbolic
-		      when Memref; arg.symbolic(di.address, 4)
+		      when Memref; arg.symbolic(di)
 		      else val
 		      end
 

data/metasm/cpu/sh4/main.rb

@@ -48,7 +48,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..15).map { |i| "r#{i}".to_sym }
 
-		def symbolic ; Sym[@i] end
+		def symbolic(di=nil) ; Sym[@i] end
 
 		def render ; ["r#@i"] end
 	end
@@ -59,7 +59,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..7).map { |i| "r#{i}_bank".to_sym }
 
-		def symbolic ; Sym[@i] end
+		def symbolic(di=nil) ; Sym[@i] end
 
 		def render ; ["r#{@i}_bank"] end
 	end
@@ -71,7 +71,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..15).map { |i| "fr#{i}".to_sym }
 
-		def symbolic ; Sym[@i] end
+		def symbolic(di=nil) ; Sym[@i] end
 
 		def render ; ["fr#@i"] end
 	end
@@ -91,7 +91,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..7).map { |i| "dr#{i*2}".to_sym }
 
-		def symbolic ; Sym[@i/2] end
+		def symbolic(di=nil) ; Sym[@i/2] end
 
 		def render ; ["dr#@i"] end
 	end
@@ -107,7 +107,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..3).map { |i| "fv#{i*4}".to_sym }
 
-		def symbolic ; Sym[@i/4] end
+		def symbolic(di=nil) ; Sym[@i/4] end
 
 		def render ; ["fv#@i"] end
 	end
@@ -119,7 +119,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..15).map { |i| "xf#{i}".to_sym }
 
-		def symbolic ; Sym[@i] end
+		def symbolic(di=nil) ; Sym[@i] end
 
 		def render ; ["xf#@i"] end
 	end
@@ -139,14 +139,14 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..7).map { |i| "xd#{i*2}".to_sym }
 
-		def symbolic ; Sym[@i/2] end
+		def symbolic(di=nil) ; Sym[@i/2] end
 
 		def render ; ["xd#@i"] end
 	end
 
 	# Single-precision floating-point extended register matrix
 	class XMTRX < Reg
-		def symbolic ; :xmtrx ; end
+		def symbolic(di=nil) ; :xmtrx ; end
 		def render ; ['xmtrx'] ; end
 	end
 
@@ -154,42 +154,42 @@ class Sh4 < CPU
 	# Multiply-and-accumulate register high
 	class MACH < Reg
 
-		def symbolic ; :mach end
+		def symbolic(di=nil) ; :mach end
 		def render ; ['mach'] end
 	end
 
 	# Multiply-and-accumulate register low
 	class MACL < Reg
 
-		def symbolic ; :macl end
+		def symbolic(di=nil) ; :macl end
 		def render ; ['macl'] end
 	end
 
 	# Procedure register
 	class PR < Reg
 
-		def symbolic ; :pr end
+		def symbolic(di=nil) ; :pr end
 		def render ; ['pr'] end
 	end
 
 	# Floating-point communication register
 	class FPUL < Reg
 
-		def symbolic ; :fpul end
+		def symbolic(di=nil) ; :fpul end
 		def render ; ['fpul'] end
 	end
 
 	# Program counter
 	class PC < Reg
 
-		def symbolic ; :pc end
+		def symbolic(di=nil) ; :pc end
 		def render ; ['pc'] end
 	end
 
 	# Floating-point status/control register
 	class FPSCR < Reg
 
-		def symbolic ; :fpscr end
+		def symbolic(di=nil) ; :fpscr end
 		def render ; ['fpscr'] end
 	end
 
@@ -198,49 +198,49 @@ class Sh4 < CPU
 	# Status register
 	class SR < Reg
 
-		def symbolic ; :sr end
+		def symbolic(di=nil) ; :sr end
 		def render ; ['sr'] end
 	end
 
 	# Saved status register
 	class SSR < Reg
 
-		def symbolic ; :ssr end
+		def symbolic(di=nil) ; :ssr end
 		def render ; ['ssr'] end
 	end
 
 	# Saved program counter
 	class SPC < Reg
 
-		def symbolic ; :spc end
+		def symbolic(di=nil) ; :spc end
 		def render ; ['spc'] end
 	end
 
 	# Global base register
 	class GBR < Reg
 
-		def symbolic ; :spc end
+		def symbolic(di=nil) ; :spc end
 		def render ; ['gbr'] end
 	end
 
 	# Vector base register
 	class VBR < Reg
 
-		def symbolic ; :spc end
+		def symbolic(di=nil) ; :spc end
 		def render ; ['vbr'] end
 	end
 
 	# Saved general register
 	class SGR < Reg
 
-		def symbolic ; :sgr end
+		def symbolic(di=nil) ; :sgr end
 		def render ; ['sgr'] end
 	end
 
 	# Debug base register
 	class DBR < Reg
 
-		def symbolic ; :dbr end
+		def symbolic(di=nil) ; :dbr end
 		def render ; ['dbr'] end
 	end
 
@@ -253,7 +253,9 @@ class Sh4 < CPU
 			@base, @disp, @action = base, offset, action
 		end
 
-		def symbolic(orig=nil, sz=32)
+		def symbolic(di=nil)
+			sz = 32
+			sz = di.opcode.props[:memsz] if di
 			b = @base
 			b = b.symbolic if b.kind_of? Reg
 
@@ -267,7 +269,7 @@ class Sh4 < CPU
 				e = Expression[b].reduce
 			end
 
-			Indirection[e, sz, orig]
+			Indirection[e, sz, (di.address if di)]
 		end
 
 		include Renderable

data/metasm/cpu/st20/decode.rb

@@ -169,12 +169,5 @@ class ST20
 	def backtrace_is_stack_address(expr)
 		Expression[expr].expr_externals.include?(:sp)
 	end
-
-	# updates an instruction's argument replacing an expression with another (eg label renamed)
-	def replace_instr_arg_immediate(i, old, new)
-		i.args.map! { |a|
-			a == old ? new : Expression[a.bind(old => new).reduce]
-		}
-	end
 end
 end

data/metasm/cpu/webasm.rb

@@ -0,0 +1,11 @@
+#    This file is part of Metasm, the Ruby assembly manipulation suite
+#    Copyright (C) 2006-2009 Yoann GUILLOT
+#
+#    Licence is LGPL, see LICENCE in the top-level directory
+
+
+require 'metasm/main'
+require 'metasm/cpu/webasm/decode'
+require 'metasm/cpu/webasm/encode'
+require 'metasm/cpu/webasm/decompile'
+require 'metasm/cpu/webasm/debug'

data/metasm/cpu/webasm/debug.rb

@@ -0,0 +1,31 @@
+#    This file is part of Metasm, the Ruby assembly manipulation suite
+#    Copyright (C) 2006-2009 Yoann GUILLOT
+#
+#    Licence is LGPL, see LICENCE in the top-level directory
+
+
+require 'metasm/cpu/webasm/opcodes'
+
+module Metasm
+class WebAsm
+	def dbg_register_list
+		@dbg_register_list ||= [:pc, :opstack, :mem, :local_base]
+	end
+
+	def dbg_resolve_pc(di, fbd, pc_reg, dbg_ctx)
+		case di.opcode.name
+		when 'br_if', 'if'
+			if dbg_ctx.resolve(Indirection[:opstack, 8]) != 0
+				fbd[pc_reg] = (di.opcode.name == 'if' ? di.next_addr : di.misc[:x])
+			else
+				fbd[pc_reg] = (di.opcode.name == 'if' ? di.misc[:x] : di.next_addr)
+			end
+		else return super(di, fbd, pc_reg, dbg_ctx)
+		end
+	end
+
+	def dbg_end_stepout(dbg, addr, di)
+		di and di.opcode.props[:stopexec] and (di.opcode.name == 'return' or di.opcode.name == 'end')
+	end
+end
+end