logicuit 0.3.1 → 0.3.2

data/lib/logicuit/signals/signal.rb

@@ -41,6 +41,18 @@ module Logicuit
         current ? "1" : "0"
       end
 
+      def &(other)
+        Signal.new(current && other.current)
+      end
+
+      def |(other)
+        Signal.new(current || other.current)
+      end
+
+      def !
+        Signal.new(!current)
+      end
+
       private
 
       def propagate_current

data/lib/logicuit/signals/signal_group.rb

@@ -24,7 +24,7 @@ module Logicuit
 
       def set(vals)
         vals.split("").zip(signals).each do |v, o|
-          v == "1" ? o.on : o.off
+          v == "1" ? o&.on : o&.off
         end
       end
     end

data/lib/logicuit/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module Logicuit
-  VERSION = "0.3.1"
+  VERSION = "0.3.2"
 end

data/sig/generated/logicuit/circuits/combinational/full_adder.rbs

@@ -0,0 +1,20 @@
+# Generated from lib/logicuit/circuits/combinational/full_adder.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # FullAdder class
+      class FullAdder < DSL
+        attr_reader cin: Signals::Signal
+
+        attr_reader a: Signals::Signal
+
+        attr_reader b: Signals::Signal
+
+        attr_reader s: Signals::Signal
+
+        attr_reader c: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/combinational/full_adder_4bit.rbs

@@ -0,0 +1,38 @@
+# Generated from lib/logicuit/circuits/combinational/full_adder_4bit.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # FullAdder class
+      class FullAdder4bit < DSL
+        attr_reader cin: Signals::Signal
+
+        attr_reader a0: Signals::Signal
+
+        attr_reader b0: Signals::Signal
+
+        attr_reader a1: Signals::Signal
+
+        attr_reader b1: Signals::Signal
+
+        attr_reader a2: Signals::Signal
+
+        attr_reader b2: Signals::Signal
+
+        attr_reader a3: Signals::Signal
+
+        attr_reader b3: Signals::Signal
+
+        attr_reader s0: Signals::Signal
+
+        attr_reader s1: Signals::Signal
+
+        attr_reader s2: Signals::Signal
+
+        attr_reader s3: Signals::Signal
+
+        attr_reader c: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/combinational/half_adder.rbs

@@ -0,0 +1,18 @@
+# Generated from lib/logicuit/circuits/combinational/half_adder.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # HalfAdder class
+      class HalfAdder < DSL
+        attr_reader a: Signals::Signal
+
+        attr_reader b: Signals::Signal
+
+        attr_reader c: Signals::Signal
+
+        attr_reader s: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/combinational/multiplexer_2to1.rbs

@@ -0,0 +1,18 @@
+# Generated from lib/logicuit/circuits/combinational/multiplexer_2to1.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # A Multiplexer with 2 inputs and 1 output
+      class Multiplexer2to1 < DSL
+        attr_reader c0: Signals::Signal
+
+        attr_reader c1: Signals::Signal
+
+        attr_reader a: Signals::Signal
+
+        attr_reader y: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/combinational/multiplexer_4to1.rbs

@@ -0,0 +1,24 @@
+# Generated from lib/logicuit/circuits/combinational/multiplexer_4to1.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # A Multiplexer with 4 inputs and 1 output
+      class Multiplexer4to1 < DSL
+        attr_reader c0: Signals::Signal
+
+        attr_reader c1: Signals::Signal
+
+        attr_reader c2: Signals::Signal
+
+        attr_reader c3: Signals::Signal
+
+        attr_reader b: Signals::Signal
+
+        attr_reader a: Signals::Signal
+
+        attr_reader y: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/sequential/d_flip_flop.rbs

@@ -0,0 +1,14 @@
+# Generated from lib/logicuit/circuits/sequential/d_flip_flop.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # D Flip-Flop
+      class DFlipFlop < DSL
+        attr_reader d: Signals::Signal
+
+        attr_reader q: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/sequential/one_bit_cpu.rbs

@@ -0,0 +1,16 @@
+# Generated from lib/logicuit/circuits/sequential/one_bit_cpu.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # 1 bit CPU with a Multiplexer
+      # Input A is H, MOV A,A
+      # Input A is L, NOT A
+      class OneBitCpu < DSL
+        attr_reader a: Signals::Signal
+
+        attr_reader y: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/sequential/program_counter.rbs

@@ -0,0 +1,28 @@
+# Generated from lib/logicuit/circuits/sequential/program_counter.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # Program Counter
+      class ProgramCounter < DSL
+        attr_reader a: Signals::Signal
+
+        attr_reader b: Signals::Signal
+
+        attr_reader c: Signals::Signal
+
+        attr_reader d: Signals::Signal
+
+        attr_reader ld: Signals::Signal
+
+        attr_reader qa: Signals::Signal
+
+        attr_reader qb: Signals::Signal
+
+        attr_reader qc: Signals::Signal
+
+        attr_reader qd: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/sequential/register_4bit.rbs

@@ -0,0 +1,28 @@
+# Generated from lib/logicuit/circuits/sequential/register_4bit.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # 4 bit register
+      class Register4bit < DSL
+        attr_reader a: Signals::Signal
+
+        attr_reader b: Signals::Signal
+
+        attr_reader c: Signals::Signal
+
+        attr_reader d: Signals::Signal
+
+        attr_reader ld: Signals::Signal
+
+        attr_reader qa: Signals::Signal
+
+        attr_reader qb: Signals::Signal
+
+        attr_reader qc: Signals::Signal
+
+        attr_reader qd: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/td4/cpu.rbs

@@ -0,0 +1,28 @@
+# Generated from lib/logicuit/circuits/td4/cpu.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Td4
+      # TD4 CPU
+      class Cpu < DSL
+        attr_reader in0: untyped
+
+        attr_reader in1: untyped
+
+        attr_reader in2: untyped
+
+        attr_reader in3: untyped
+
+        attr_reader led1: untyped
+
+        attr_reader led2: untyped
+
+        attr_reader led3: untyped
+
+        attr_reader led4: untyped
+
+        def to_s: () -> untyped
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/td4/decoder.rbs

@@ -0,0 +1,32 @@
+# Generated from lib/logicuit/circuits/td4/decoder.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Td4
+      # Decoder class
+      class Decoder < DSL
+        attr_reader op3: Signals::Signal
+
+        attr_reader op2: Signals::Signal
+
+        attr_reader op1: Signals::Signal
+
+        attr_reader op0: Signals::Signal
+
+        attr_reader c_flag: Signals::Signal
+
+        attr_reader sel_b: Signals::Signal
+
+        attr_reader sel_a: Signals::Signal
+
+        attr_reader ld0: Signals::Signal
+
+        attr_reader ld1: Signals::Signal
+
+        attr_reader ld2: Signals::Signal
+
+        attr_reader ld3: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/td4/rom.rbs

@@ -0,0 +1,36 @@
+# Generated from lib/logicuit/circuits/td4/rom.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Td4
+      # Timer
+      class Rom < DSL
+        attr_reader a3: Signals::Signal
+
+        attr_reader a2: Signals::Signal
+
+        attr_reader a1: Signals::Signal
+
+        attr_reader a0: Signals::Signal
+
+        attr_reader d7: Signals::Signal
+
+        attr_reader d6: Signals::Signal
+
+        attr_reader d5: Signals::Signal
+
+        attr_reader d4: Signals::Signal
+
+        attr_reader d3: Signals::Signal
+
+        attr_reader d2: Signals::Signal
+
+        attr_reader d1: Signals::Signal
+
+        attr_reader d0: Signals::Signal
+
+        def evaluate: () -> untyped
+      end
+    end
+  end
+end

data/sig/generated/logicuit/gates/and.rbs

@@ -0,0 +1,14 @@
+# Generated from lib/logicuit/gates/and.rb with RBS::Inline
+
+module Logicuit
+  module Gates
+    # AND gate
+    class And < DSL
+      attr_reader a: Signals::Signal
+
+      attr_reader b: Signals::Signal
+
+      attr_reader y: Signals::Signal
+    end
+  end
+end

data/sig/generated/logicuit/gates/nand.rbs

@@ -0,0 +1,14 @@
+# Generated from lib/logicuit/gates/nand.rb with RBS::Inline
+
+module Logicuit
+  module Gates
+    # NAND gate
+    class Nand < DSL
+      attr_reader a: Signals::Signal
+
+      attr_reader b: Signals::Signal
+
+      attr_reader y: Signals::Signal
+    end
+  end
+end

data/sig/generated/logicuit/gates/not.rbs

@@ -0,0 +1,12 @@
+# Generated from lib/logicuit/gates/not.rb with RBS::Inline
+
+module Logicuit
+  module Gates
+    # NOT gate
+    class Not < DSL
+      attr_reader a: Signals::Signal
+
+      attr_reader y: Signals::Signal
+    end
+  end
+end

data/sig/generated/logicuit/gates/or.rbs

@@ -0,0 +1,14 @@
+# Generated from lib/logicuit/gates/or.rb with RBS::Inline
+
+module Logicuit
+  module Gates
+    # OR gate
+    class Or < DSL
+      attr_reader a: Signals::Signal
+
+      attr_reader b: Signals::Signal
+
+      attr_reader y: Signals::Signal
+    end
+  end
+end

data/sig/generated/logicuit/gates/xor.rbs

@@ -0,0 +1,14 @@
+# Generated from lib/logicuit/gates/xor.rb with RBS::Inline
+
+module Logicuit
+  module Gates
+    # XOR gate
+    class Xor < DSL
+      attr_reader a: Signals::Signal
+
+      attr_reader b: Signals::Signal
+
+      attr_reader y: Signals::Signal
+    end
+  end
+end

data/sig/logicuit/array_as_signal_group.rbs

@@ -0,0 +1,11 @@
+# Logicuit module
+module Logicuit
+  # Treats Array#>> as SignalGroup#>> for the purpose of connecting signals
+  module ArrayAsSignalGroup
+    def >>: (untyped other) -> void
+  end
+end
+
+class Array[unchecked out T]
+  def >>: (untyped other) -> void
+end

data/sig/logicuit/dsl.rbs

@@ -0,0 +1,35 @@
+# Logicuit module
+module Logicuit
+  # base class for all gates and circuits
+  class DSL
+    def initialize: (*(0 | 1) args) -> void
+
+    def evaluate: (*Signals::Signal args) -> void
+
+    attr_reader input_targets: Array[Symbol]
+
+    attr_reader output_targets: Array[Symbol]
+
+    attr_reader clock: bool
+
+    attr_reader components: Array[untyped]
+
+    attr_reader initialized: bool 
+
+    def self.inputs: (*Symbol args, ?clock: Symbol) -> void
+
+    def []: (*Symbol keys) -> Signals::SignalGroup
+
+    def self.outputs: (*Symbol args, **^(instance) [self: instance] -> Signals::Signal kwargs) -> void
+
+    def self.assembling: () { () [self: instance] -> void } -> void
+
+    def self.diagram: (String source) -> void
+
+    def self.truth_table: (String source) -> void
+
+    def self.verify_against_truth_table: () -> void
+
+    def self.run: (?hz: ::Integer, ?noclear: bool) -> void
+  end
+end

data/sig/logicuit/runner.rbs

@@ -0,0 +1,4 @@
+# Logicuit module
+module Logicuit
+  def self.run: (DSL circuit, ?hz: ::Integer, ?noclear: bool) -> void
+end

data/sig/logicuit/signals/clock.rbs

@@ -0,0 +1,30 @@
+module Logicuit
+  module Signals
+    # Clock
+    class Clock
+      self.@instance: Clock
+
+      @downstreams: Array[DSL]
+
+      @tick_count: Integer
+
+      def initialize: () -> void
+
+      attr_reader downstreams: Array[DSL]
+
+      attr_reader tick_count: Integer
+
+      def tick: () -> void
+
+      def self.instance: () -> Clock
+
+      def self.connects_to: (DSL component) -> void
+
+      alias self.>> self.connects_to
+
+      def self.tick: () -> void
+
+      def self.tick_count: () -> Integer
+    end
+  end
+end

data/sig/logicuit/signals/signal.rbs

@@ -0,0 +1,32 @@
+module Logicuit
+  module Signals
+    # Signal
+    class Signal
+      @current: bool
+
+      @downstreams: Array[Signal | DSL]
+
+      def initialize: (?bool current) -> void
+
+      attr_reader current: bool
+
+      def on: () -> void
+
+      def off: () -> void
+
+      def connects_to: (Signal | SignalGroup | Array[Signal] | DSL other) -> void
+
+      alias >> connects_to
+
+      def to_s: () -> ("1" | "0")
+
+      def &: (Signal other) -> Signal
+      def |: (Signal other) -> Signal
+      def !: () -> Signal
+
+      private
+
+      def propagate_current: () -> void
+    end
+  end
+end

data/sig/logicuit/signals/signal_group.rbs

@@ -0,0 +1,20 @@
+module Logicuit
+  module Signals
+    # Signal Group
+    class SignalGroup
+      @signals: Array[Signal]
+
+      def initialize: (*Signal signals) -> void
+
+      def signals: () -> Array[Signal]
+
+      def connects_to: (SignalGroup | Array[Signal] others) -> void
+
+      alias >> connects_to
+
+      def to_s: () -> String
+
+      def set: (String vals) -> void
+    end
+  end
+end

data/sig/logicuit/version.rbs

@@ -0,0 +1,3 @@
+module Logicuit
+  VERSION: String
+end

metadata

@@ -1,7 +1,7 @@
 --- !ruby/object:Gem::Specification
 name: logicuit
 version: !ruby/object:Gem::Version
-  version: 0.3.1
+  version: 0.3.2
 platform: ruby
 authors:
 - Koji NAKAMURA
@@ -20,6 +20,7 @@ files:
 - LICENSE.txt
 - README.md
 - Rakefile
+- Steepfile
 - lib/logicuit.rb
 - lib/logicuit/array_as_signal_group.rb
 - lib/logicuit/circuits/combinational/full_adder.rb
@@ -45,7 +46,30 @@ files:
 - lib/logicuit/signals/signal.rb
 - lib/logicuit/signals/signal_group.rb
 - lib/logicuit/version.rb
-- sig/logicuit.rbs
+- sig/generated/logicuit/circuits/combinational/full_adder.rbs
+- sig/generated/logicuit/circuits/combinational/full_adder_4bit.rbs
+- sig/generated/logicuit/circuits/combinational/half_adder.rbs
+- sig/generated/logicuit/circuits/combinational/multiplexer_2to1.rbs
+- sig/generated/logicuit/circuits/combinational/multiplexer_4to1.rbs
+- sig/generated/logicuit/circuits/sequential/d_flip_flop.rbs
+- sig/generated/logicuit/circuits/sequential/one_bit_cpu.rbs
+- sig/generated/logicuit/circuits/sequential/program_counter.rbs
+- sig/generated/logicuit/circuits/sequential/register_4bit.rbs
+- sig/generated/logicuit/circuits/td4/cpu.rbs
+- sig/generated/logicuit/circuits/td4/decoder.rbs
+- sig/generated/logicuit/circuits/td4/rom.rbs
+- sig/generated/logicuit/gates/and.rbs
+- sig/generated/logicuit/gates/nand.rbs
+- sig/generated/logicuit/gates/not.rbs
+- sig/generated/logicuit/gates/or.rbs
+- sig/generated/logicuit/gates/xor.rbs
+- sig/logicuit/array_as_signal_group.rbs
+- sig/logicuit/dsl.rbs
+- sig/logicuit/runner.rbs
+- sig/logicuit/signals/clock.rbs
+- sig/logicuit/signals/signal.rbs
+- sig/logicuit/signals/signal_group.rbs
+- sig/logicuit/version.rbs
 homepage: https://github.com/kozy4324/logicuit
 licenses:
 - MIT

data/sig/logicuit.rbs

@@ -1,4 +0,0 @@
-module Logicuit
-  VERSION: String
-  # See the writing guide of rbs: https://github.com/ruby/rbs#guides
-end