logicuit 0.3.0 → 0.3.2

data/lib/logicuit/dsl.rb

@@ -1,5 +1,7 @@
 # frozen_string_literal: true
 
+# steep:ignore:start
+
 # Logicuit module
 module Logicuit
   # base class for all gates and circuits
@@ -26,7 +28,9 @@ module Logicuit
 
     def self.inputs(*args, **kwargs)
       # define getter methods for inputs
-      attr_reader(*args)
+      args.each do |arg|
+        attr_reader(arg) unless instance_methods.include?(arg)
+      end
 
       # define initializer for inputs
       define_method(:inputs) do |*instance_method_args|
@@ -54,7 +58,9 @@ module Logicuit
 
     def self.outputs(*args, **kwargs)
       # define getter methods for outputs
-      attr_reader(*(args + kwargs.keys))
+      (args + kwargs.keys).each do |arg|
+        attr_reader(arg) unless instance_methods.include?(arg)
+      end
 
       # define initializer for outputs
       define_method(:outputs) do
@@ -71,19 +77,13 @@ module Logicuit
         return unless initialized
 
         kwargs.each do |output, evaluator|
-          signal = instance_variable_get("@#{output}")
-          e_args = if override_args.empty?
-                     @input_targets.map do |input|
-                       instance_variable_get("@#{input}").current
-                     end
-                   else
-                     override_args
-                   end
-          if @inputs_as_bool_struct.new(*e_args).instance_exec(&evaluator)
-            signal.on
-          else
-            signal.off
-          end
+          ret = if override_args.empty?
+                  instance_exec(&evaluator)
+                else
+                  o = @inputs_as_bool_struct.new(*override_args)
+                  o.instance_exec(&evaluator)
+                end
+          send(output).send(ret.current ? :on : :off)
         end
       end
     end
@@ -91,7 +91,7 @@ module Logicuit
     def self.assembling(&block)
       define_method(:assembling) do
         ret = instance_eval(&block)
-        ret.each { @components << it } if ret.is_a?(Array)
+        ret.each { @components << _1 } if ret.is_a?(Array)
       end
     end
 
@@ -132,8 +132,10 @@ module Logicuit
           headers.size == values.size
         end.map do |values|
           array = [values]
-          while array.any? { it.any? { |v| v == :any } }
-            target_index = array.find_index { it.any? { |v| v == :any } }
+          while array.any? { _1.any? { |v| v == :any } }
+            target_index = array.find_index { _1.any? { |v| v == :any } }
+            next if target_index.nil? # avoid rbs error...
+
             target = array[target_index]
             prop_index = target.find_index { |v| v == :any }
             array.delete_at(target_index)
@@ -151,8 +153,35 @@ module Logicuit
       end
     end
 
+    def self.verify_against_truth_table
+      new.truth_table.each do |row|
+        args = row.values_at(*new.input_targets).map { _1 ? 1 : 0 }
+        subject = new(*args)
+
+        previous_values = row.reject do |_k, v|
+          v == :clock
+        end.keys.reduce({}) { |acc, key| acc.merge(key => subject.send(key).current) }
+
+        Signals::Clock.tick if row.values.find :clock
+
+        row.each do |key, value|
+          next if value == :clock
+
+          if value.is_a?(Array) && value.first == :ref
+            expected = previous_values[value.last]
+
+            raise "#{self}.new(#{args.join(", ")}).#{key} should be #{expected ? 1 : 0}" unless expected == subject.send(key).current
+          else
+            raise "#{self}.new(#{args.join(", ")}).#{key} should be #{value ? 1 : 0}" unless value == subject.send(key).current
+          end
+        end
+      end
+    end
+
     def self.run(opts = {})
       ::Logicuit.run(new, **opts)
     end
   end
 end
+
+# steep:ignore:end

data/lib/logicuit/gates/and.rb

@@ -1,5 +1,7 @@
 # frozen_string_literal: true
 
+# rbs_inline: enabled
+
 module Logicuit
   module Gates
     # AND gate
@@ -10,9 +12,11 @@ module Logicuit
         (B)-|   |
       DIAGRAM
 
+      attr_reader :a, :b, :y #: Signals::Signal
+
       inputs :a, :b
 
-      outputs y: -> { a && b }
+      outputs y: -> { a & b }
 
       truth_table <<~TRUTH_TABLE
         | A | B | Y |

data/lib/logicuit/gates/nand.rb

@@ -1,5 +1,7 @@
 # frozen_string_literal: true
 
+# rbs_inline: enabled
+
 module Logicuit
   module Gates
     # NAND gate
@@ -10,9 +12,11 @@ module Logicuit
         (B)-|    |
       DIAGRAM
 
+      attr_reader :a, :b, :y #: Signals::Signal
+
       inputs :a, :b
 
-      outputs y: -> { !(a && b) }
+      outputs y: -> { !(a & b) }
 
       truth_table <<~TRUTH_TABLE
         | A | B | Y |

data/lib/logicuit/gates/not.rb

@@ -1,5 +1,7 @@
 # frozen_string_literal: true
 
+# rbs_inline: enabled
+
 module Logicuit
   module Gates
     # NOT gate
@@ -8,6 +10,8 @@ module Logicuit
         (A)-|NOT|-(Y)
       DIAGRAM
 
+      attr_reader :a, :y #: Signals::Signal
+
       inputs :a
 
       outputs y: -> { !a }

data/lib/logicuit/gates/or.rb

@@ -1,5 +1,7 @@
 # frozen_string_literal: true
 
+# rbs_inline: enabled
+
 module Logicuit
   module Gates
     # OR gate
@@ -10,9 +12,11 @@ module Logicuit
         (B)-|  |
       DIAGRAM
 
+      attr_reader :a, :b, :y #: Signals::Signal
+
       inputs :a, :b
 
-      outputs y: -> { a || b }
+      outputs y: -> { a | b }
 
       truth_table <<~TRUTH_TABLE
         | A | B | Y |

data/lib/logicuit/gates/xor.rb

@@ -1,5 +1,7 @@
 # frozen_string_literal: true
 
+# rbs_inline: enabled
+
 module Logicuit
   module Gates
     # XOR gate
@@ -10,9 +12,11 @@ module Logicuit
         (B)-|   |
       DIAGRAM
 
+      attr_reader :a, :b, :y #: Signals::Signal
+
       inputs :a, :b
 
-      outputs y: -> { (a && !b) || (!a && b) }
+      outputs y: -> { (a & !b) | (!a & b) }
 
       truth_table <<~TRUTH_TABLE
         | A | B | Y |

data/lib/logicuit/runner.rb

@@ -23,7 +23,7 @@ module Logicuit
       render.call
     end
 
-    while (input = gets.chomp)
+    while (input = gets&.chomp)
       key = input.to_sym
       unless circuit.respond_to? key
         if circuit.clock && hz.zero?

data/lib/logicuit/signals/clock.rb

@@ -16,7 +16,7 @@ module Logicuit
         # Call the `evaluate` method for all components.
         # However, the input argument values should be bound to the values at the time `tick` is called.
         @downstreams.map do |component|
-          args = component.input_targets.map { |input| component.instance_variable_get("@#{input}").current }
+          args = component.input_targets.map { |input| Signal.new(component.send(input).current) }
           -> { component.evaluate(*args) }
         end.each(&:call)
       end

data/lib/logicuit/signals/signal.rb

@@ -41,6 +41,18 @@ module Logicuit
         current ? "1" : "0"
       end
 
+      def &(other)
+        Signal.new(current && other.current)
+      end
+
+      def |(other)
+        Signal.new(current || other.current)
+      end
+
+      def !
+        Signal.new(!current)
+      end
+
       private
 
       def propagate_current

data/lib/logicuit/signals/signal_group.rb

@@ -19,7 +19,13 @@ module Logicuit
       alias >> connects_to
 
       def to_s
-        signals.map { it.current ? "1" : "0" }.join
+        signals.map { _1.current ? "1" : "0" }.join
+      end
+
+      def set(vals)
+        vals.split("").zip(signals).each do |v, o|
+          v == "1" ? o&.on : o&.off
+        end
       end
     end
   end

data/lib/logicuit/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module Logicuit
-  VERSION = "0.3.0"
+  VERSION = "0.3.2"
 end

data/sig/generated/logicuit/circuits/combinational/full_adder.rbs

@@ -0,0 +1,20 @@
+# Generated from lib/logicuit/circuits/combinational/full_adder.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # FullAdder class
+      class FullAdder < DSL
+        attr_reader cin: Signals::Signal
+
+        attr_reader a: Signals::Signal
+
+        attr_reader b: Signals::Signal
+
+        attr_reader s: Signals::Signal
+
+        attr_reader c: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/combinational/full_adder_4bit.rbs

@@ -0,0 +1,38 @@
+# Generated from lib/logicuit/circuits/combinational/full_adder_4bit.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # FullAdder class
+      class FullAdder4bit < DSL
+        attr_reader cin: Signals::Signal
+
+        attr_reader a0: Signals::Signal
+
+        attr_reader b0: Signals::Signal
+
+        attr_reader a1: Signals::Signal
+
+        attr_reader b1: Signals::Signal
+
+        attr_reader a2: Signals::Signal
+
+        attr_reader b2: Signals::Signal
+
+        attr_reader a3: Signals::Signal
+
+        attr_reader b3: Signals::Signal
+
+        attr_reader s0: Signals::Signal
+
+        attr_reader s1: Signals::Signal
+
+        attr_reader s2: Signals::Signal
+
+        attr_reader s3: Signals::Signal
+
+        attr_reader c: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/combinational/half_adder.rbs

@@ -0,0 +1,18 @@
+# Generated from lib/logicuit/circuits/combinational/half_adder.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # HalfAdder class
+      class HalfAdder < DSL
+        attr_reader a: Signals::Signal
+
+        attr_reader b: Signals::Signal
+
+        attr_reader c: Signals::Signal
+
+        attr_reader s: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/combinational/multiplexer_2to1.rbs

@@ -0,0 +1,18 @@
+# Generated from lib/logicuit/circuits/combinational/multiplexer_2to1.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # A Multiplexer with 2 inputs and 1 output
+      class Multiplexer2to1 < DSL
+        attr_reader c0: Signals::Signal
+
+        attr_reader c1: Signals::Signal
+
+        attr_reader a: Signals::Signal
+
+        attr_reader y: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/combinational/multiplexer_4to1.rbs

@@ -0,0 +1,24 @@
+# Generated from lib/logicuit/circuits/combinational/multiplexer_4to1.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # A Multiplexer with 4 inputs and 1 output
+      class Multiplexer4to1 < DSL
+        attr_reader c0: Signals::Signal
+
+        attr_reader c1: Signals::Signal
+
+        attr_reader c2: Signals::Signal
+
+        attr_reader c3: Signals::Signal
+
+        attr_reader b: Signals::Signal
+
+        attr_reader a: Signals::Signal
+
+        attr_reader y: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/sequential/d_flip_flop.rbs

@@ -0,0 +1,14 @@
+# Generated from lib/logicuit/circuits/sequential/d_flip_flop.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # D Flip-Flop
+      class DFlipFlop < DSL
+        attr_reader d: Signals::Signal
+
+        attr_reader q: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/sequential/one_bit_cpu.rbs

@@ -0,0 +1,16 @@
+# Generated from lib/logicuit/circuits/sequential/one_bit_cpu.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # 1 bit CPU with a Multiplexer
+      # Input A is H, MOV A,A
+      # Input A is L, NOT A
+      class OneBitCpu < DSL
+        attr_reader a: Signals::Signal
+
+        attr_reader y: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/sequential/program_counter.rbs

@@ -0,0 +1,28 @@
+# Generated from lib/logicuit/circuits/sequential/program_counter.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # Program Counter
+      class ProgramCounter < DSL
+        attr_reader a: Signals::Signal
+
+        attr_reader b: Signals::Signal
+
+        attr_reader c: Signals::Signal
+
+        attr_reader d: Signals::Signal
+
+        attr_reader ld: Signals::Signal
+
+        attr_reader qa: Signals::Signal
+
+        attr_reader qb: Signals::Signal
+
+        attr_reader qc: Signals::Signal
+
+        attr_reader qd: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/sequential/register_4bit.rbs

@@ -0,0 +1,28 @@
+# Generated from lib/logicuit/circuits/sequential/register_4bit.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # 4 bit register
+      class Register4bit < DSL
+        attr_reader a: Signals::Signal
+
+        attr_reader b: Signals::Signal
+
+        attr_reader c: Signals::Signal
+
+        attr_reader d: Signals::Signal
+
+        attr_reader ld: Signals::Signal
+
+        attr_reader qa: Signals::Signal
+
+        attr_reader qb: Signals::Signal
+
+        attr_reader qc: Signals::Signal
+
+        attr_reader qd: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/td4/cpu.rbs

@@ -0,0 +1,28 @@
+# Generated from lib/logicuit/circuits/td4/cpu.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Td4
+      # TD4 CPU
+      class Cpu < DSL
+        attr_reader in0: untyped
+
+        attr_reader in1: untyped
+
+        attr_reader in2: untyped
+
+        attr_reader in3: untyped
+
+        attr_reader led1: untyped
+
+        attr_reader led2: untyped
+
+        attr_reader led3: untyped
+
+        attr_reader led4: untyped
+
+        def to_s: () -> untyped
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/td4/decoder.rbs

@@ -0,0 +1,32 @@
+# Generated from lib/logicuit/circuits/td4/decoder.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Td4
+      # Decoder class
+      class Decoder < DSL
+        attr_reader op3: Signals::Signal
+
+        attr_reader op2: Signals::Signal
+
+        attr_reader op1: Signals::Signal
+
+        attr_reader op0: Signals::Signal
+
+        attr_reader c_flag: Signals::Signal
+
+        attr_reader sel_b: Signals::Signal
+
+        attr_reader sel_a: Signals::Signal
+
+        attr_reader ld0: Signals::Signal
+
+        attr_reader ld1: Signals::Signal
+
+        attr_reader ld2: Signals::Signal
+
+        attr_reader ld3: Signals::Signal
+      end
+    end
+  end
+end

data/sig/generated/logicuit/circuits/td4/rom.rbs

@@ -0,0 +1,36 @@
+# Generated from lib/logicuit/circuits/td4/rom.rb with RBS::Inline
+
+module Logicuit
+  module Circuits
+    module Td4
+      # Timer
+      class Rom < DSL
+        attr_reader a3: Signals::Signal
+
+        attr_reader a2: Signals::Signal
+
+        attr_reader a1: Signals::Signal
+
+        attr_reader a0: Signals::Signal
+
+        attr_reader d7: Signals::Signal
+
+        attr_reader d6: Signals::Signal
+
+        attr_reader d5: Signals::Signal
+
+        attr_reader d4: Signals::Signal
+
+        attr_reader d3: Signals::Signal
+
+        attr_reader d2: Signals::Signal
+
+        attr_reader d1: Signals::Signal
+
+        attr_reader d0: Signals::Signal
+
+        def evaluate: () -> untyped
+      end
+    end
+  end
+end

data/sig/generated/logicuit/gates/and.rbs

@@ -0,0 +1,14 @@
+# Generated from lib/logicuit/gates/and.rb with RBS::Inline
+
+module Logicuit
+  module Gates
+    # AND gate
+    class And < DSL
+      attr_reader a: Signals::Signal
+
+      attr_reader b: Signals::Signal
+
+      attr_reader y: Signals::Signal
+    end
+  end
+end

data/sig/generated/logicuit/gates/nand.rbs

@@ -0,0 +1,14 @@
+# Generated from lib/logicuit/gates/nand.rb with RBS::Inline
+
+module Logicuit
+  module Gates
+    # NAND gate
+    class Nand < DSL
+      attr_reader a: Signals::Signal
+
+      attr_reader b: Signals::Signal
+
+      attr_reader y: Signals::Signal
+    end
+  end
+end

data/sig/generated/logicuit/gates/not.rbs

@@ -0,0 +1,12 @@
+# Generated from lib/logicuit/gates/not.rb with RBS::Inline
+
+module Logicuit
+  module Gates
+    # NOT gate
+    class Not < DSL
+      attr_reader a: Signals::Signal
+
+      attr_reader y: Signals::Signal
+    end
+  end
+end

data/sig/generated/logicuit/gates/or.rbs

@@ -0,0 +1,14 @@
+# Generated from lib/logicuit/gates/or.rb with RBS::Inline
+
+module Logicuit
+  module Gates
+    # OR gate
+    class Or < DSL
+      attr_reader a: Signals::Signal
+
+      attr_reader b: Signals::Signal
+
+      attr_reader y: Signals::Signal
+    end
+  end
+end

data/sig/generated/logicuit/gates/xor.rbs

@@ -0,0 +1,14 @@
+# Generated from lib/logicuit/gates/xor.rb with RBS::Inline
+
+module Logicuit
+  module Gates
+    # XOR gate
+    class Xor < DSL
+      attr_reader a: Signals::Signal
+
+      attr_reader b: Signals::Signal
+
+      attr_reader y: Signals::Signal
+    end
+  end
+end

data/sig/logicuit/array_as_signal_group.rbs

@@ -0,0 +1,11 @@
+# Logicuit module
+module Logicuit
+  # Treats Array#>> as SignalGroup#>> for the purpose of connecting signals
+  module ArrayAsSignalGroup
+    def >>: (untyped other) -> void
+  end
+end
+
+class Array[unchecked out T]
+  def >>: (untyped other) -> void
+end