logicuit 0.2.0 → 0.3.1

data/lib/logicuit/circuits/combinational/multiplexer_4to1.rb

@@ -4,36 +4,32 @@ module Logicuit
   module Circuits
     module Combinational
       # A Multiplexer with 4 inputs and 1 output
-      class Multiplexer4to1 < Base
-        tag :MUX4, :MUX4TO1
-
+      class Multiplexer4to1 < DSL
         diagram <<~DIAGRAM
-          (C0)---------------|
+          (C0)---------------|   |
                          +---|AND|---+
-                         | +-|       |
+                         | +-|   |   |
                          | |         |
-          (C1)---------------|       +-|
+          (C1)---------------|   |   +-|
                          +---|AND|-+   |
-                 +-----------|     +---|
+                 +-----------|   | +---|
                  |       | |           |OR|--(Y)
-          (C2)---------------|     +---|
+          (C2)---------------|   | +---|
                +-------------|AND|-+   |
-               | |       | +-|       +-|
+               | |       | +-|   |   +-|
                | |       | |         |
-          (C3)---------------|       |
+          (C3)---------------|   |   |
                +-------------|AND|---+
-               | +-----------|
+               | +-----------|   |
                | |       | |
           (B)--+---|NOT|-+ |
                  |         |
           (A)----+-|NOT|---+
         DIAGRAM
 
-        define_inputs :c0, :c1, :c2, :c3, :b, :a
+        inputs :c0, :c1, :c2, :c3, :b, :a
 
-        define_outputs y: lambda { |c0, c1, c2, c3, b, a|
-          (c0 && !b && !a) || (c1 && !b && a) || (c2 && b && !a) || (c3 && b && a)
-        }
+        outputs y: -> { (c0 && !b && !a) || (c1 && !b && a) || (c2 && b && !a) || (c3 && b && a) }
 
         truth_table <<~TRUTH_TABLE
           | B | A | C0 | C1 | C2 | C3 | Y |

data/lib/logicuit/circuits/sequential/d_flip_flop.rb

@@ -4,18 +4,16 @@ module Logicuit
   module Circuits
     module Sequential
       # D Flip-Flop
-      class DFlipFlop < Base
-        tag :DFF
-
+      class DFlipFlop < DSL
         diagram <<~DIAGRAM
           (D)--|   |--(Q)
                |DFF|
           (CK)-|>  |
         DIAGRAM
 
-        define_inputs :d, clock: :ck
+        inputs :d, clock: :ck
 
-        define_outputs q: ->(d) { d }
+        outputs q: -> { d }
 
         truth_table <<~TRUTH_TABLE
           | CK | D | Q |

data/lib/logicuit/circuits/{system_level/one_bit_cpu2.rb → sequential/one_bit_cpu.rb}

@@ -2,38 +2,36 @@
 
 module Logicuit
   module Circuits
-    module SystemLevel
+    module Sequential
       # 1 bit CPU with a Multiplexer
       # Input A is H, MOV A,A
       # Input A is L, NOT A
-      class OneBitCpu2 < Base
-        tag :ONE_BIT_CPU2
-
+      class OneBitCpu < DSL
         diagram <<~DIAGRAM
-          +------------------------+
-          |              +-------------(Y)
-          +----|   |-+---+---|     |
-               |DFF| |       |     |
-          (CK)-|>  | +-|NOT|-|MUX|-+
-                             |
-                       (A)---|
+          +-----------------------------+
+          |                             |
+          +----|   |---+---------|   |  |
+               |DFF|   |         |   |  |
+          (CK)-|>  |   +--|NOT|--|MUX|--+--(Y)
+                                 |   |
+                            (A)--|   |
         DIAGRAM
 
-        define_inputs :a, clock: :ck
+        inputs :a, clock: :ck
 
-        define_outputs :y
+        outputs :y
 
-        assembling do |a, y|
+        assembling do
           dff = Sequential::DFlipFlop.new
           not_gate = Gates::Not.new
           mux = Combinational::Multiplexer2to1.new
 
-          dff.q >> y
           dff.q >> mux.c0
           dff.q >> not_gate.a
           not_gate.y >> mux.c1
           a >> mux.a
           mux.y >> dff.d
+          mux.y >> y
         end
       end
     end

data/lib/logicuit/circuits/sequential/program_counter.rb

@@ -4,23 +4,21 @@ module Logicuit
   module Circuits
     module Sequential
       # Program Counter
-      class ProgramCounter < Base
-        tag :PC
-
+      class ProgramCounter < DSL
         diagram <<~DIAGRAM
           (A)---|  |---(QA)
           (B)---|  |---(QB)
           (C)---|PC|---(QC)
           (D)---|  |---(QD)
-          (LD)--|
+          (LD)--|  |
         DIAGRAM
 
-        define_inputs :a, :b, :c, :d, :ld, clock: :ck
+        inputs :a, :b, :c, :d, :ld, clock: :ck
 
-        define_outputs :qa, :qb, :qc, :qd
+        outputs :qa, :qb, :qc, :qd
 
-        assembling do |a, b, c, d, ld, qa, qb, qc, qd|
-          # define_inputs :cin, :a0, :b0, :a1, :b1, :a2, :b2, :a3, :b3
+        assembling do
+          # inputs :cin, :a0, :b0, :a1, :b1, :a2, :b2, :a3, :b3
           fadd = Combinational::FullAdder4bit.new(0, 0, 1, 0, 0, 0, 0, 0, 0)
 
           [[a, qa, :a0, :s0], [b, qb, :a1, :s1], [c, qc, :a2, :s2],

data/lib/logicuit/circuits/sequential/register_4bit.rb

@@ -4,37 +4,35 @@ module Logicuit
   module Circuits
     module Sequential
       # 4 bit register
-      class Register4bit < Base
-        tag :REG4
-
+      class Register4bit < DSL
         diagram <<~DIAGRAM
                   +---------------------+
-                  +-|                   |
+                  +-|   |               |
           (A)-------|MUX|-------|DFF|---+---(QA)
-                +---|       +---|
+                +---|   |   +---|   |
                 |           |
                 | +---------------------+
-                | +-|       |           |
+                | +-|   |   |           |
           (B)-------|MUX|-------|DFF|---+---(QB)
-                +---|       +---|
+                +---|   |   +---|   |
                 |           |
                 | +---------------------+
-                | +-|       |           |
+                | +-|   |   |           |
           (C)-------|MUX|-------|DFF|---+---(QC)
-                +---|       +---|
+                +---|   |   +---|   |
                 |           |
                 | +---------------------+
-                | +-|       |           |
+                | +-|   |   |           |
           (D)-------|MUX|-------|DFF|---+---(QD)
-                +---|       +---|
+                +---|   |   +---|   |
           (LD)--+     (CK)--+
         DIAGRAM
 
-        define_inputs :a, :b, :c, :d, :ld, clock: :ck
+        inputs :a, :b, :c, :d, :ld, clock: :ck
 
-        define_outputs :qa, :qb, :qc, :qd
+        outputs :qa, :qb, :qc, :qd
 
-        assembling do |a, b, c, d, ld, qa, qb, qc, qd|
+        assembling do
           [[a, qa], [b, qb], [c, qc], [d, qd]].each do |input, output|
             dff = Sequential::DFlipFlop.new
             mux = Combinational::Multiplexer2to1.new

data/lib/logicuit/circuits/{system_level/cpu_td4.rb → td4/cpu.rb}

@@ -2,68 +2,43 @@
 
 module Logicuit
   module Circuits
-    module SystemLevel
-      # TD4
-      class CpuTd4 < Base
-        tag :TD4
+    module Td4
+      # TD4 CPU
+      class Cpu < DSL
+        using Logicuit::ArrayAsSignalGroup
 
-        define_inputs :in0, :in1, :in2, :in3, clock: :ck
+        inputs :in0, :in1, :in2, :in3, clock: :ck
 
-        define_outputs :led1, :led2, :led3, :led4
+        outputs :led1, :led2, :led3, :led4
 
-        assembling do |in0, in1, in2, in3, led1, led2, led3, led4|
-          register_a = Sequential::Register4bit.new
-          register_b = Sequential::Register4bit.new
-          register_c = Sequential::Register4bit.new
+        assembling do
+          register_a, register_b, register_c = (:a..:c).map { Sequential::Register4bit.new }
           pc = Sequential::ProgramCounter.new
-          rom = Rom::Timer.new
-          dec = Combinational::Decoder.new
-          mux0 = Combinational::Multiplexer4to1.new
-          mux1 = Combinational::Multiplexer4to1.new
-          mux2 = Combinational::Multiplexer4to1.new
-          mux3 = Combinational::Multiplexer4to1.new
+          rom = Rom.new
+          dec = Decoder.new
+          mux0, mux1, mux2, mux3 = (0..3).map { Combinational::Multiplexer4to1.new }
           alu = Combinational::FullAdder4bit.new
           dff = Sequential::DFlipFlop.new
 
-          [%i[s0 a], %i[s1 b], %i[s2 c], %i[s3 d]].each do |sel, reg|
-            alu.send(sel) >> register_a.send(reg)
-            alu.send(sel) >> register_b.send(reg)
-            alu.send(sel) >> register_c.send(reg)
-            alu.send(sel) >> pc.send(reg)
-          end
+          alu.s0 >> [register_a.a, register_b.a, register_c.a, pc.a]
+          alu.s1 >> [register_a.b, register_b.b, register_c.b, pc.b]
+          alu.s2 >> [register_a.c, register_b.c, register_c.c, pc.c]
+          alu.s3 >> [register_a.d, register_b.d, register_c.d, pc.d]
           alu.c >> dff.d
 
-          [[:qa, in0, mux0, :a0], [:qb, in1, mux1, :a1], [:qc, in2, mux2, :a2], [:qd, in3, mux3, :a3]].each do |reg_out, in_port, mux, alu_in|
-            register_a.send(reg_out) >> mux.c0
-            register_b.send(reg_out) >> mux.c1
-            in_port >> mux.c2
-            Signals::Signal.new.off >> mux.c3
-            dec.sel_a >> mux.a
-            dec.sel_b >> mux.b
-            mux.y >> alu.send(alu_in)
-          end
+          [register_a.qa, register_b.qa, in0] >> mux0[:c0, :c1, :c2]
+          [register_a.qb, register_b.qb, in1] >> mux1[:c0, :c1, :c2]
+          [register_a.qc, register_b.qc, in2] >> mux2[:c0, :c1, :c2]
+          [register_a.qd, register_b.qd, in3] >> mux3[:c0, :c1, :c2]
+          dec.sel_a >> [mux0.a, mux1.a, mux2.a, mux3.a]
+          dec.sel_b >> [mux0.b, mux1.b, mux2.b, mux3.b]
+          [mux0.y, mux1.y, mux2.y, mux3.y] >> [alu.a0, alu.a1, alu.a2, alu.a3]
 
-          register_c.qa >> led4
-          register_c.qb >> led3
-          register_c.qc >> led2
-          register_c.qd >> led1
-
-          pc.qa >> rom.a0
-          pc.qb >> rom.a1
-          pc.qc >> rom.a2
-          pc.qd >> rom.a3
-          rom.d0 >> alu.b0
-          rom.d1 >> alu.b1
-          rom.d2 >> alu.b2
-          rom.d3 >> alu.b3
-          rom.d4 >> dec.op0
-          rom.d5 >> dec.op1
-          rom.d6 >> dec.op2
-          rom.d7 >> dec.op3
-          dec.ld0 >> register_a.ld
-          dec.ld1 >> register_b.ld
-          dec.ld2 >> register_c.ld
-          dec.ld3 >> pc.ld
+          register_c[:qa, :qb, :qc, :qd] >> [led4, led3, led2, led1]
+          pc[:qa, :qb, :qc, :qd] >> rom[:a0, :a1, :a2, :a3]
+          rom[:d0, :d1, :d2, :d3] >> alu[:b0, :b1, :b2, :b3]
+          rom[:d4, :d5, :d6, :d7] >> dec[:op0, :op1, :op2, :op3]
+          dec[:ld0, :ld1, :ld2, :ld3] >> [register_a.ld, register_b.ld, register_c.ld, pc.ld]
           dff.q >> dec.c_flag
 
           [register_a, register_b, pc, rom, dec]
@@ -74,14 +49,14 @@ module Logicuit
           p_b = "(#{@b || "0000"})"
 
           register_a, register_b, pc, rom, dec = components
-          @a = a = "#{register_a.qd}#{register_a.qc}#{register_a.qb}#{register_a.qa}"
-          @b = b = "#{register_b.qd}#{register_b.qc}#{register_b.qb}#{register_b.qa}"
-          p = "#{pc.qd}#{pc.qc}#{pc.qb}#{pc.qa}"
-          o = "#{led1}#{led2}#{led3}#{led4}"
-          i = "#{in3}#{in2}#{in1}#{in0}"
-          m = "#{rom.d3}#{rom.d2}#{rom.d1}#{rom.d0}"
+          @a = a = register_a[:qd, :qc, :qb, :qa].to_s
+          @b = b = register_b[:qd, :qc, :qb, :qa].to_s
+          p = pc[:qd, :qc, :qb, :qa]
+          o = self[:led1, :led2, :led3, :led4]
+          i = self[:in3, :in2, :in1, :in0]
+          m = rom[:d3, :d2, :d1, :d0]
           c = "-(#{dec.c_flag})"
-          loc = p.to_i(2)
+          loc = p.to_s.to_i(2)
 
           l1 = led1.current ? "*" : " "
           l2 = led2.current ? "*" : " "

data/lib/logicuit/circuits/{combinational → td4}/decoder.rb

@@ -2,19 +2,17 @@
 
 module Logicuit
   module Circuits
-    module Combinational
+    module Td4
       # Decoder class
-      class Decoder < Base
-        tag :DEC
+      class Decoder < DSL
+        inputs :op3, :op2, :op1, :op0, :c_flag
 
-        define_inputs :op3, :op2, :op1, :op0, :c_flag
-
-        define_outputs sel_b: ->(_, _, op1, _, _) { op1 },
-                       sel_a: ->(op3, _, _, op0, _) { op3 || op0 },
-                       ld0: ->(op3, op2, _, _, _) { op3 || op2 },
-                       ld1: ->(op3, op2, _, _, _) { op3 || !op2 },
-                       ld2: ->(op3, op2, _, _, _) { !op3 || op2 },
-                       ld3: ->(op3, op2, _, op0, c_flag) { !op3 || !op2 || (!op0 && c_flag) }
+        outputs sel_b: -> { op1 },
+                sel_a: -> { op3 || op0 },
+                ld0: -> { op3 || op2 },
+                ld1: -> { op3 || !op2 },
+                ld2: -> { !op3 || op2 },
+                ld3: -> { !op3 || !op2 || (!op0 && c_flag) }
 
         truth_table <<~TRUTH_TABLE
           | OP3 | OP2 | OP1 | OP0 | C_FLAG | SEL_B | SEL_A | LD0 | LD1 | LD2 | LD3 |

data/lib/logicuit/circuits/{rom/timer.rb → td4/rom.rb}

@@ -2,15 +2,17 @@
 
 module Logicuit
   module Circuits
-    module Rom
-      # TImer
-      class Timer < Base
-        define_inputs :a3, :a2, :a1, :a0
+    module Td4
+      # Timer
+      class Rom < DSL
+        inputs :a3, :a2, :a1, :a0
 
-        define_outputs :d7, :d6, :d5, :d4, :d3, :d2, :d1, :d0
+        outputs :d7, :d6, :d5, :d4, :d3, :d2, :d1, :d0
 
         def evaluate
-          output = case "#{a3}#{a2}#{a1}#{a0}"
+          return unless initialized
+
+          output = case self[:a3, :a2, :a1, :a0].to_s
                    in "0000" then "10110111"
                    in "0001" then "00000001"
                    in "0010" then "11100001"
@@ -28,9 +30,7 @@ module Logicuit
                    in "1110" then "10111000"
                    in "1111" then "11111111"
                    end
-          output.split("").zip([d7, d6, d5, d4, d3, d2, d1, d0]).each do |v, o|
-            v == "1" ? o.on : o.off
-          end
+          self[:d7, :d6, :d5, :d4, :d3, :d2, :d1, :d0].set output
         end
 
         truth_table <<~TRUTH_TABLE

data/lib/logicuit/{base.rb → dsl.rb}

@@ -3,79 +3,61 @@
 # Logicuit module
 module Logicuit
   # base class for all gates and circuits
-  class Base
-    def self.tag(*tags)
-      tags.each do |tag|
-        registry[tag] = self
-      end
-    end
-
-    @@registry = {} # rubocop:disable Style/ClassVars
-
-    def self.registry
-      @@registry
-    end
-
+  class DSL
     def initialize(*args)
       @input_targets = []
+      @inputs_as_bool_struct = nil
       @output_targets = []
       @clock = false
       @components = []
-      define_inputs(*args) if respond_to?(:define_inputs)
-      define_outputs if respond_to?(:define_outputs)
-      assembling if respond_to?(:assembling)
-      evaluate if respond_to?(:evaluate)
+      inputs(*args)
+      outputs
+      assembling
+      @initialized = true
+      evaluate
     end
 
+    def inputs(*args); end
+    def outputs; end
+    def assembling; end
     def evaluate(*args); end
 
-    attr_reader :input_targets, :output_targets, :clock, :components
+    attr_reader :input_targets, :output_targets, :clock, :components, :initialized
 
-    def self.define_inputs(*args, **kwargs)
+    def self.inputs(*args, **kwargs)
       # define getter methods for inputs
-      args.each do |input|
-        define_method(input) do
-          instance_variable_get("@#{input}")
-        end
-      end
+      attr_reader(*args)
 
       # define initializer for inputs
-      define_method(:define_inputs) do |*instance_method_args|
-        instance_variable_set("@clock", true) if kwargs&.key?(:clock)
+      define_method(:inputs) do |*instance_method_args|
+        @clock = true if kwargs&.key?(:clock)
         args.each_with_index do |input, index|
           signal = Signals::Signal.new(instance_method_args[index] == 1)
-          signal.on_change << self unless clock
+          signal >> self unless clock
           instance_variable_set("@#{input}", signal)
           @input_targets << input
         end
-        Signals::Clock.on_tick << self if clock
+        Signals::Clock >> self if clock
+        @inputs_as_bool_struct = Struct.new(*@input_targets)
       end
+    end
 
-      # define bulk_setter for inputs
-      define_method(:bulk_set) do |str|
-        args.zip(str.gsub(/\s/, "").split("")).each do |input, value|
-          next if value.nil?
-
-          signal = send(input)
-          if value == "1"
-            signal.on
-          else
-            signal.off
-          end
-        end
+    def [](*keys)
+      if keys.size == 1
+        send(keys.first)
+      elsif keys.size > 1
+        Signals::SignalGroup.new(*(keys.map { |key| send(key) }))
+      else
+        raise ArgumentError, "Invalid number of arguments"
       end
     end
 
-    def self.define_outputs(*args, **kwargs)
+    def self.outputs(*args, **kwargs)
       # define getter methods for outputs
-      (args + kwargs.keys).each do |output|
-        define_method(output) do
-          instance_variable_get("@#{output}")
-        end
-      end
+      attr_reader(*(args + kwargs.keys))
 
       # define initializer for outputs
-      define_method(:define_outputs) do
+      define_method(:outputs) do
         (args + kwargs.keys).each do |output|
           instance_variable_set("@#{output}", Signals::Signal.new(false))
           @output_targets << output
@@ -86,6 +68,8 @@ module Logicuit
       return if kwargs.empty?
 
       define_method(:evaluate) do |*override_args|
+        return unless initialized
+
         kwargs.each do |output, evaluator|
           signal = instance_variable_get("@#{output}")
           e_args = if override_args.empty?
@@ -95,7 +79,7 @@ module Logicuit
                    else
                      override_args
                    end
-          if evaluator.call(*e_args)
+          if @inputs_as_bool_struct.new(*e_args).instance_exec(&evaluator)
             signal.on
           else
             signal.off
@@ -104,13 +88,10 @@ module Logicuit
       end
     end
 
-    def self.assembling
+    def self.assembling(&block)
       define_method(:assembling) do
-        (yield(*(@input_targets + @output_targets).map do |target|
-          instance_variable_get("@#{target}")
-        end) || []).each do |component|
-          @components << component
-        end
+        ret = instance_eval(&block)
+        ret.each { @components << _1 } if ret.is_a?(Array)
       end
     end
 
@@ -147,12 +128,12 @@ module Logicuit
               [:ref, v.to_sym]
             end
           end
-        end.select do |values| # rubocop:disable Style/MultilineBlockChain
+        end.select do |values|
           headers.size == values.size
-        end.map do |values| # rubocop:disable Style/MultilineBlockChain
+        end.map do |values|
           array = [values]
-          while array.any? { it.any? { |v| v == :any } }
-            target_index = array.find_index { it.any? { |v| v == :any } }
+          while array.any? { _1.any? { |v| v == :any } }
+            target_index = array.find_index { _1.any? { |v| v == :any } }
             target = array[target_index]
             prop_index = target.find_index { |v| v == :any }
             array.delete_at(target_index)
@@ -163,63 +144,40 @@ module Logicuit
             end)
           end
           array
-        end.flatten!(1).map do |values| # rubocop:disable Style/MultilineBlockChain
+        end.flatten!(1).map do |values|
           headers.zip(values).to_h
         end
         table
       end
     end
-  end
 
-  def self.run(sym, hz: 1, noclear: false) # rubocop:disable Naming/MethodParameterName
-    circuit = Base.registry[sym.upcase.to_sym].new
-
-    render = lambda {
-      system("clear") unless noclear
-      puts circuit
-      puts
-      puts "tick: #{Signals::Clock.tick_count}" if circuit.clock
-      if circuit.respond_to?(:instructions)
-        puts "instructions: #{circuit.instructions.join "|"}"
-      elsif circuit.input_targets.any?
-        puts "input: #{circuit.input_targets.join ","}?"
-      end
-    }
-
-    if circuit.clock && hz.nonzero?
-      Thread.new do
-        loop do
-          render.call
-          sleep 1.0 / hz
-          Signals::Clock.tick
-        end
-      end
-    else
-      render.call
-    end
+    def self.verify_against_truth_table
+      new.truth_table.each do |row|
+        args = row.values_at(*new.input_targets).map { _1 ? 1 : 0 }
+        subject = new(*args)
 
-    while (input = gets.chomp)
-      if circuit.respond_to?(:execute) && circuit.execute(input)
-        Signals::Clock.tick
-        render.call # rubocop:disable Style/IdenticalConditionalBranches
-      else
-        key = input.to_sym
-        unless circuit.respond_to? key
-          if circuit.clock && hz.zero?
-            Signals::Clock.tick
-            render.call
-          end
-          next
-        end
+        previous_values = row.reject do |_k, v|
+          v == :clock
+        end.keys.reduce({}) { |acc, key| acc.merge(key => subject.send(key).current) }
+
+        Signals::Clock.tick if row.values.find :clock
+
+        row.each do |key, value|
+          next if value == :clock
+
+          if value.is_a?(Array) && value.first == :ref
+            expected = previous_values[value.last]
 
-        signal = circuit.send(key)
-        if signal.current
-          signal.off
-        else
-          signal.on
+            raise "#{self}.new(#{args.join(", ")}).#{key} should be #{expected}" unless expected == subject.send(key).current
+          else
+            raise "#{self}.new(#{args.join(", ")}).#{key} should be #{value}" unless value == subject.send(key).current
+          end
         end
-        render.call # rubocop:disable Style/IdenticalConditionalBranches
       end
     end
+
+    def self.run(opts = {})
+      ::Logicuit.run(new, **opts)
+    end
   end
 end

data/lib/logicuit/gates/and.rb

@@ -3,18 +3,16 @@
 module Logicuit
   module Gates
     # AND gate
-    class And < Base
-      tag :AND
-
+    class And < DSL
       diagram <<~DIAGRAM
-        (A)-|
+        (A)-|   |
             |AND|-(Y)
-        (B)-|
+        (B)-|   |
       DIAGRAM
 
-      define_inputs :a, :b
+      inputs :a, :b
 
-      define_outputs y: ->(a, b) { a && b }
+      outputs y: -> { a && b }
 
       truth_table <<~TRUTH_TABLE
         | A | B | Y |