logicuit 0.1.5 → 0.3.0

data/lib/logicuit/circuits/sequential/program_counter.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # Program Counter
+      class ProgramCounter < DSL
+        diagram <<~DIAGRAM
+          (A)---|  |---(QA)
+          (B)---|  |---(QB)
+          (C)---|PC|---(QC)
+          (D)---|  |---(QD)
+          (LD)--|  |
+        DIAGRAM
+
+        inputs :a, :b, :c, :d, :ld, clock: :ck
+
+        outputs :qa, :qb, :qc, :qd
+
+        assembling do
+          # inputs :cin, :a0, :b0, :a1, :b1, :a2, :b2, :a3, :b3
+          fadd = Combinational::FullAdder4bit.new(0, 0, 1, 0, 0, 0, 0, 0, 0)
+
+          [[a, qa, :a0, :s0], [b, qb, :a1, :s1], [c, qc, :a2, :s2],
+           [d, qd, :a3, :s3]].each do |input, output, fadd_in, fadd_out|
+            dff = Sequential::DFlipFlop.new
+            mux = Combinational::Multiplexer2to1.new
+            input >> mux.c0
+            dff.q >> fadd.send(fadd_in)
+            fadd.send(fadd_out) >> mux.c1
+            ld    >> mux.a
+            mux.y >> dff.d
+            dff.q >> output
+          end
+        end
+      end
+    end
+  end
+end

data/lib/logicuit/circuits/sequential/register_4bit.rb

@@ -0,0 +1,56 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # 4 bit register
+      class Register4bit < DSL
+        diagram <<~DIAGRAM
+                  +---------------------+
+                  +-|   |               |
+          (A)-------|MUX|-------|DFF|---+---(QA)
+                +---|   |   +---|   |
+                |           |
+                | +---------------------+
+                | +-|   |   |           |
+          (B)-------|MUX|-------|DFF|---+---(QB)
+                +---|   |   +---|   |
+                |           |
+                | +---------------------+
+                | +-|   |   |           |
+          (C)-------|MUX|-------|DFF|---+---(QC)
+                +---|   |   +---|   |
+                |           |
+                | +---------------------+
+                | +-|   |   |           |
+          (D)-------|MUX|-------|DFF|---+---(QD)
+                +---|   |   +---|   |
+          (LD)--+     (CK)--+
+        DIAGRAM
+
+        inputs :a, :b, :c, :d, :ld, clock: :ck
+
+        outputs :qa, :qb, :qc, :qd
+
+        assembling do
+          [[a, qa], [b, qb], [c, qc], [d, qd]].each do |input, output|
+            dff = Sequential::DFlipFlop.new
+            mux = Combinational::Multiplexer2to1.new
+            input >> mux.c0
+            dff.q >> mux.c1
+            ld    >> mux.a
+            mux.y >> dff.d
+            dff.q >> output
+          end
+        end
+
+        truth_table <<~TRUTH_TABLE
+          | CK | A | B | C | D | LD | QA | QB | QC | QD |
+          | -- | - | - | - | - | -- | -- | -- | -- | -- |
+          |  ^ | x | x | x | x |  0 |  A |  B |  C |  D |
+          |  ^ | x | x | x | x |  1 | QA | QB | QC | QD |
+        TRUTH_TABLE
+      end
+    end
+  end
+end

data/lib/logicuit/circuits/td4/cpu.rb

@@ -0,0 +1,95 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module Td4
+      # TD4 CPU
+      class Cpu < DSL
+        using Logicuit::ArrayAsSignalGroup
+
+        inputs :in0, :in1, :in2, :in3, clock: :ck
+
+        outputs :led1, :led2, :led3, :led4
+
+        assembling do
+          register_a, register_b, register_c = (:a..:c).map { Sequential::Register4bit.new }
+          pc = Sequential::ProgramCounter.new
+          rom = Rom.new
+          dec = Decoder.new
+          mux0, mux1, mux2, mux3 = (0..3).map { Combinational::Multiplexer4to1.new }
+          alu = Combinational::FullAdder4bit.new
+          dff = Sequential::DFlipFlop.new
+
+          alu.s0 >> [register_a.a, register_b.a, register_c.a, pc.a]
+          alu.s1 >> [register_a.b, register_b.b, register_c.b, pc.b]
+          alu.s2 >> [register_a.c, register_b.c, register_c.c, pc.c]
+          alu.s3 >> [register_a.d, register_b.d, register_c.d, pc.d]
+          alu.c >> dff.d
+
+          [register_a.qa, register_b.qa, in0] >> mux0[:c0, :c1, :c2]
+          [register_a.qb, register_b.qb, in1] >> mux1[:c0, :c1, :c2]
+          [register_a.qc, register_b.qc, in2] >> mux2[:c0, :c1, :c2]
+          [register_a.qd, register_b.qd, in3] >> mux3[:c0, :c1, :c2]
+          dec.sel_a >> [mux0.a, mux1.a, mux2.a, mux3.a]
+          dec.sel_b >> [mux0.b, mux1.b, mux2.b, mux3.b]
+          [mux0.y, mux1.y, mux2.y, mux3.y] >> [alu.a0, alu.a1, alu.a2, alu.a3]
+
+          register_c[:qa, :qb, :qc, :qd] >> [led4, led3, led2, led1]
+          pc[:qa, :qb, :qc, :qd] >> rom[:a0, :a1, :a2, :a3]
+          rom[:d0, :d1, :d2, :d3] >> alu[:b0, :b1, :b2, :b3]
+          rom[:d4, :d5, :d6, :d7] >> dec[:op0, :op1, :op2, :op3]
+          dec[:ld0, :ld1, :ld2, :ld3] >> [register_a.ld, register_b.ld, register_c.ld, pc.ld]
+          dff.q >> dec.c_flag
+
+          [register_a, register_b, pc, rom, dec]
+        end
+
+        def to_s
+          p_a = "(#{@a || "0000"})"
+          p_b = "(#{@b || "0000"})"
+
+          register_a, register_b, pc, rom, dec = components
+          @a = a = register_a[:qd, :qc, :qb, :qa].to_s
+          @b = b = register_b[:qd, :qc, :qb, :qa].to_s
+          p = pc[:qd, :qc, :qb, :qa]
+          o = self[:led1, :led2, :led3, :led4]
+          i = self[:in3, :in2, :in1, :in0]
+          m = rom[:d3, :d2, :d1, :d0]
+          c = "-(#{dec.c_flag})"
+          loc = p.to_s.to_i(2)
+
+          l1 = led1.current ? "*" : " "
+          l2 = led2.current ? "*" : " "
+          l3 = led3.current ? "*" : " "
+          l4 = led4.current ? "*" : " "
+
+          <<~OUTPUT
+
+              #{l1 * 7}#{" " * 7}#{l2 * 7}#{" " * 7}#{l3 * 7}#{" " * 7}#{l4 * 7}
+             #{l1 * 9}#{" " * 5}#{l2 * 9}#{" " * 5}#{l3 * 9}#{" " * 5}#{l4 * 9}
+            #{l1 * 11}#{" " * 3}#{l2 * 11}#{" " * 3}#{l3 * 11}#{" " * 3}#{l4 * 11}
+             #{l1 * 9}#{" " * 5}#{l2 * 9}#{" " * 5}#{l3 * 9}#{" " * 5}#{l4 * 9}
+              #{l1 * 7}#{" " * 7}#{l2 * 7}#{" " * 7}#{l3 * 7}#{" " * 7}#{l4 * 7}
+
+            +-----------------------------------------------+     #{loc ==  0 ? ">" : " "} OUT 0111
+            |                                               |     #{loc ==  1 ? ">" : " "} ADD A,0001
+            +--->|rg_a|#{p_a}----->|   |                    |     #{loc ==  2 ? ">" : " "} JNC 0001
+            |    |#{a}|            |   |                    |     #{loc ==  3 ? ">" : " "} ADD A,0001
+            |                      |   |                    |     #{loc ==  4 ? ">" : " "} JNC 0011
+            +--->|rg_b|#{p_b}----->|   |----------->|   |---+     #{loc ==  5 ? ">" : " "} OUT 0110
+            |    |#{b}|            |   |            |   |         #{loc ==  6 ? ">" : " "} ADD A,0001
+            |                      |SEL|            |ALU|         #{loc ==  7 ? ">" : " "} JNC 0110
+            +--->| out|  |  in|--->|   |            |   |         #{loc ==  8 ? ">" : " "} ADD A,0001
+            |    |#{o}|  |#{i}|    |   |  |  im|--->|   |-#{c}    #{loc ==  9 ? ">" : " "} JNC 1000
+            |                      |   |  |#{m}|                  #{loc == 10 ? ">" : " "} OUT 0000
+            +--->|  pc|  (0000)--->|   |                          #{loc == 11 ? ">" : " "} OUT 0100
+                 |#{p}|                                           #{loc == 12 ? ">" : " "} ADD A,0001
+                                                                  #{loc == 13 ? ">" : " "} JNC 1010
+                                                                  #{loc == 14 ? ">" : " "} OUT 1000
+                                                                  #{loc == 15 ? ">" : " "} JMP 1111
+          OUTPUT
+        end
+      end
+    end
+  end
+end

data/lib/logicuit/circuits/td4/decoder.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module Td4
+      # Decoder class
+      class Decoder < DSL
+        inputs :op3, :op2, :op1, :op0, :c_flag
+
+        outputs sel_b: -> { op1 },
+                sel_a: -> { op3 || op0 },
+                ld0: -> { op3 || op2 },
+                ld1: -> { op3 || !op2 },
+                ld2: -> { !op3 || op2 },
+                ld3: -> { !op3 || !op2 || (!op0 && c_flag) }
+
+        truth_table <<~TRUTH_TABLE
+          | OP3 | OP2 | OP1 | OP0 | C_FLAG | SEL_B | SEL_A | LD0 | LD1 | LD2 | LD3 |
+          | --- | --- | --- | --- | ------ | ----- | ----- | --- | --- | --- | --- |
+          |   0 |   0 |   0 |   0 |      x |     0 |     0 |   0 |   1 |   1 |   1 | # ADD A,Im
+          |   0 |   0 |   0 |   1 |      x |     0 |     1 |   0 |   1 |   1 |   1 | # MOV A,B
+          |   0 |   0 |   1 |   0 |      x |     1 |     0 |   0 |   1 |   1 |   1 | # IN  A
+          |   0 |   0 |   1 |   1 |      x |     1 |     1 |   0 |   1 |   1 |   1 | # MOV A,Im
+          |   0 |   1 |   0 |   0 |      x |     0 |     0 |   1 |   0 |   1 |   1 | # MOV B,A
+          |   0 |   1 |   0 |   1 |      x |     0 |     1 |   1 |   0 |   1 |   1 | # ADD B,Im
+          |   0 |   1 |   1 |   0 |      x |     1 |     0 |   1 |   0 |   1 |   1 | # IN  B
+          |   0 |   1 |   1 |   1 |      x |     1 |     1 |   1 |   0 |   1 |   1 | # MOV B,Im
+          |   1 |   0 |   0 |   1 |      x |     0 |     1 |   1 |   1 |   0 |   1 | # OUT B
+          |   1 |   0 |   1 |   1 |      x |     1 |     1 |   1 |   1 |   0 |   1 | # OUT Im
+          |   1 |   1 |   1 |   0 |      0 |     1 |     1 |   1 |   1 |   1 |   0 | # JNC(C=0)
+          |   1 |   1 |   1 |   0 |      1 |     1 |     1 |   1 |   1 |   1 |   1 | # JNC(C=1)
+          |   1 |   1 |   1 |   1 |      x |     1 |     1 |   1 |   1 |   1 |   0 | # JMP
+        TRUTH_TABLE
+      end
+    end
+  end
+end

data/lib/logicuit/circuits/td4/rom.rb

@@ -0,0 +1,61 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module Td4
+      # Timer
+      class Rom < DSL
+        inputs :a3, :a2, :a1, :a0
+
+        outputs :d7, :d6, :d5, :d4, :d3, :d2, :d1, :d0
+
+        def evaluate
+          return unless initialized
+
+          output = case "#{a3}#{a2}#{a1}#{a0}"
+                   in "0000" then "10110111"
+                   in "0001" then "00000001"
+                   in "0010" then "11100001"
+                   in "0011" then "00000001"
+                   in "0100" then "11100011"
+                   in "0101" then "10110110"
+                   in "0110" then "00000001"
+                   in "0111" then "11100110"
+                   in "1000" then "00000001"
+                   in "1001" then "11101000"
+                   in "1010" then "10110000"
+                   in "1011" then "10110100"
+                   in "1100" then "00000001"
+                   in "1101" then "11101010"
+                   in "1110" then "10111000"
+                   in "1111" then "11111111"
+                   end
+          output.split("").zip([d7, d6, d5, d4, d3, d2, d1, d0]).each do |v, o|
+            v == "1" ? o.on : o.off
+          end
+        end
+
+        truth_table <<~TRUTH_TABLE
+          | A3 | A2 | A1 | A0 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
+          | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
+          |  0 |  0 |  0 |  0 |  1 |  0 |  1 |  1 |  0 |  1 |  1 |  1 | # OUT 0111
+          |  0 |  0 |  0 |  1 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 | # ADD A,0001
+          |  0 |  0 |  1 |  0 |  1 |  1 |  1 |  0 |  0 |  0 |  0 |  1 | # JNC 0001
+          |  0 |  0 |  1 |  1 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 | # ADD A,0001
+          |  0 |  1 |  0 |  0 |  1 |  1 |  1 |  0 |  0 |  0 |  1 |  1 | # JNC 0011
+          |  0 |  1 |  0 |  1 |  1 |  0 |  1 |  1 |  0 |  1 |  1 |  0 | # OUT 0110
+          |  0 |  1 |  1 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 | # ADD A,0001
+          |  0 |  1 |  1 |  1 |  1 |  1 |  1 |  0 |  0 |  1 |  1 |  0 | # JNC 0110
+          |  1 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 | # ADD A,0001
+          |  1 |  0 |  0 |  1 |  1 |  1 |  1 |  0 |  1 |  0 |  0 |  0 | # JNC 1000
+          |  1 |  0 |  1 |  0 |  1 |  0 |  1 |  1 |  0 |  0 |  0 |  0 | # OUT 0000
+          |  1 |  0 |  1 |  1 |  1 |  0 |  1 |  1 |  0 |  1 |  0 |  0 | # OUT 0100
+          |  1 |  1 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 | # ADD A,0001
+          |  1 |  1 |  0 |  1 |  1 |  1 |  1 |  0 |  1 |  0 |  1 |  0 | # JNC 1010
+          |  1 |  1 |  1 |  0 |  1 |  0 |  1 |  1 |  1 |  0 |  0 |  0 | # OUT 1000
+          |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 | # JMP 1111
+        TRUTH_TABLE
+      end
+    end
+  end
+end

data/lib/logicuit/dsl.rb

@@ -0,0 +1,158 @@
+# frozen_string_literal: true
+
+# Logicuit module
+module Logicuit
+  # base class for all gates and circuits
+  class DSL
+    def initialize(*args)
+      @input_targets = []
+      @inputs_as_bool_struct = nil
+      @output_targets = []
+      @clock = false
+      @components = []
+      inputs(*args)
+      outputs
+      assembling
+      @initialized = true
+      evaluate
+    end
+
+    def inputs(*args); end
+    def outputs; end
+    def assembling; end
+    def evaluate(*args); end
+
+    attr_reader :input_targets, :output_targets, :clock, :components, :initialized
+
+    def self.inputs(*args, **kwargs)
+      # define getter methods for inputs
+      attr_reader(*args)
+
+      # define initializer for inputs
+      define_method(:inputs) do |*instance_method_args|
+        @clock = true if kwargs&.key?(:clock)
+        args.each_with_index do |input, index|
+          signal = Signals::Signal.new(instance_method_args[index] == 1)
+          signal >> self unless clock
+          instance_variable_set("@#{input}", signal)
+          @input_targets << input
+        end
+        Signals::Clock >> self if clock
+        @inputs_as_bool_struct = Struct.new(*@input_targets)
+      end
+    end
+
+    def [](*keys)
+      if keys.size == 1
+        send(keys.first)
+      elsif keys.size > 1
+        Signals::SignalGroup.new(*(keys.map { |key| send(key) }))
+      else
+        raise ArgumentError, "Invalid number of arguments"
+      end
+    end
+
+    def self.outputs(*args, **kwargs)
+      # define getter methods for outputs
+      attr_reader(*(args + kwargs.keys))
+
+      # define initializer for outputs
+      define_method(:outputs) do
+        (args + kwargs.keys).each do |output|
+          instance_variable_set("@#{output}", Signals::Signal.new(false))
+          @output_targets << output
+        end
+      end
+
+      # define evaluate method
+      return if kwargs.empty?
+
+      define_method(:evaluate) do |*override_args|
+        return unless initialized
+
+        kwargs.each do |output, evaluator|
+          signal = instance_variable_get("@#{output}")
+          e_args = if override_args.empty?
+                     @input_targets.map do |input|
+                       instance_variable_get("@#{input}").current
+                     end
+                   else
+                     override_args
+                   end
+          if @inputs_as_bool_struct.new(*e_args).instance_exec(&evaluator)
+            signal.on
+          else
+            signal.off
+          end
+        end
+      end
+    end
+
+    def self.assembling(&block)
+      define_method(:assembling) do
+        ret = instance_eval(&block)
+        ret.each { @components << it } if ret.is_a?(Array)
+      end
+    end
+
+    def self.diagram(source)
+      define_method(:to_s) do
+        source_ = @input_targets.reduce(source) do |result, input|
+          result.gsub(/\(#{input}\)/i, "(#{instance_variable_get("@#{input}")})#{"-" * (input.size - 1)}")
+        end
+        @output_targets.reduce(source_) do |result, output|
+          result.gsub(/\(#{output}\)/i, "#{"-" * (output.size - 1)}(#{instance_variable_get("@#{output}")})")
+        end
+      end
+    end
+
+    def self.truth_table(source)
+      define_method(:truth_table) do
+        rows = source.strip.split("\n").map { |row| row.gsub(/#.*$/, "") }
+        headers = rows.shift.split("|").map(&:strip).reject(&:empty?).map(&:downcase).map(&:to_sym)
+        rows.shift # devide line
+        table = rows.map do |row|
+          row.split("|").map(&:strip).reject(&:empty?).map(&:downcase).map do |v|
+            case v
+            when "^"
+              :clock
+            when "x"
+              :any
+            when "1"
+              true
+            when "0"
+              false
+            else
+              raise "Invalid value in truth table: #{v}" unless headers.include?(v.to_sym)
+
+              [:ref, v.to_sym]
+            end
+          end
+        end.select do |values|
+          headers.size == values.size
+        end.map do |values|
+          array = [values]
+          while array.any? { it.any? { |v| v == :any } }
+            target_index = array.find_index { it.any? { |v| v == :any } }
+            target = array[target_index]
+            prop_index = target.find_index { |v| v == :any }
+            array.delete_at(target_index)
+            array.insert(target_index, *[true, false].map do |v|
+              target.dup.tap do |a|
+                a[prop_index] = v
+              end
+            end)
+          end
+          array
+        end.flatten!(1).map do |values|
+          headers.zip(values).to_h
+        end
+        table
+      end
+    end
+
+    def self.run(opts = {})
+      ::Logicuit.run(new, **opts)
+    end
+  end
+end

data/lib/logicuit/gates/and.rb

@@ -3,18 +3,16 @@
 module Logicuit
   module Gates
     # AND gate
-    class And < Base
-      tag :AND
-
+    class And < DSL
       diagram <<~DIAGRAM
-        (A)-|
+        (A)-|   |
             |AND|-(Y)
-        (B)-|
+        (B)-|   |
       DIAGRAM
 
-      define_inputs :a, :b
+      inputs :a, :b
 
-      define_outputs y: ->(a, b) { a && b }
+      outputs y: -> { a && b }
 
       truth_table <<~TRUTH_TABLE
         | A | B | Y |

data/lib/logicuit/gates/nand.rb

@@ -3,18 +3,16 @@
 module Logicuit
   module Gates
     # NAND gate
-    class Nand < Base
-      tag :NAND
-
+    class Nand < DSL
       diagram <<~DIAGRAM
-        (A)-|
+        (A)-|    |
             |NAND|-(Y)
-        (B)-|
+        (B)-|    |
       DIAGRAM
 
-      define_inputs :a, :b
+      inputs :a, :b
 
-      define_outputs y: ->(a, b) { !(a && b) }
+      outputs y: -> { !(a && b) }
 
       truth_table <<~TRUTH_TABLE
         | A | B | Y |

data/lib/logicuit/gates/not.rb

@@ -3,16 +3,14 @@
 module Logicuit
   module Gates
     # NOT gate
-    class Not < Base
-      tag :NOT
-
+    class Not < DSL
       diagram <<~DIAGRAM
         (A)-|NOT|-(Y)
       DIAGRAM
 
-      define_inputs :a
+      inputs :a
 
-      define_outputs y: ->(a) { !a } # rubocop:disable Style/SymbolProc
+      outputs y: -> { !a }
 
       truth_table <<~TRUTH_TABLE
         | A | Y |

data/lib/logicuit/gates/or.rb

@@ -3,18 +3,16 @@
 module Logicuit
   module Gates
     # OR gate
-    class Or < Base
-      tag :OR
-
+    class Or < DSL
       diagram <<~DIAGRAM
-        (A)-|
+        (A)-|  |
             |OR|-(Y)
-        (B)-|
+        (B)-|  |
       DIAGRAM
 
-      define_inputs :a, :b
+      inputs :a, :b
 
-      define_outputs y: ->(a, b) { a || b }
+      outputs y: -> { a || b }
 
       truth_table <<~TRUTH_TABLE
         | A | B | Y |

data/lib/logicuit/gates/xor.rb

@@ -3,18 +3,16 @@
 module Logicuit
   module Gates
     # XOR gate
-    class Xor < Base
-      tag :XOR
-
+    class Xor < DSL
       diagram <<~DIAGRAM
-        (A)-|
+        (A)-|   |
             |XOR|-(Y)
-        (B)-|
+        (B)-|   |
       DIAGRAM
 
-      define_inputs :a, :b
+      inputs :a, :b
 
-      define_outputs y: ->(a, b) { (a && !b) || (!a && b) }
+      outputs y: -> { (a && !b) || (!a && b) }
 
       truth_table <<~TRUTH_TABLE
         | A | B | Y |

data/lib/logicuit/runner.rb

@@ -0,0 +1,45 @@
+# frozen_string_literal: true
+
+# Logicuit module
+module Logicuit
+  def self.run(circuit, hz: 1, noclear: false)
+    render = lambda {
+      system("clear") unless noclear
+      puts circuit
+      puts
+      puts "tick: #{Signals::Clock.tick_count}" if circuit.clock
+      puts "input: #{circuit.input_targets.join ","}?" if circuit.input_targets.any?
+    }
+
+    if circuit.clock && hz.nonzero?
+      Thread.new do
+        loop do
+          render.call
+          sleep 1.0 / hz
+          Signals::Clock.tick
+        end
+      end
+    else
+      render.call
+    end
+
+    while (input = gets.chomp)
+      key = input.to_sym
+      unless circuit.respond_to? key
+        if circuit.clock && hz.zero?
+          Signals::Clock.tick
+          render.call
+        end
+        next
+      end
+
+      signal = circuit.send(key)
+      if signal.current
+        signal.off
+      else
+        signal.on
+      end
+      render.call
+    end
+  end
+end

data/lib/logicuit/signals/clock.rb

@@ -5,31 +5,39 @@ module Logicuit
     # Clock
     class Clock
       def initialize
-        @on_tick = []
+        @downstreams = []
         @tick_count = 0
       end
 
-      attr_reader :on_tick, :tick_count
+      attr_reader :downstreams, :tick_count
 
       def tick
         @tick_count += 1
-        @on_tick.each(&:evaluate)
+        # Call the `evaluate` method for all components.
+        # However, the input argument values should be bound to the values at the time `tick` is called.
+        @downstreams.map do |component|
+          args = component.input_targets.map { |input| component.instance_variable_get("@#{input}").current }
+          -> { component.evaluate(*args) }
+        end.each(&:call)
       end
 
-      def self.instance
-        @instance ||= new
-      end
+      class << self
+        def instance
+          @instance ||= new
+        end
 
-      def self.on_tick
-        instance.on_tick
-      end
+        def connects_to(component)
+          instance.downstreams << component
+        end
+        alias >> connects_to
 
-      def self.tick
-        instance.tick
-      end
+        def tick
+          instance.tick
+        end
 
-      def self.tick_count
-        instance.tick_count
+        def tick_count
+          instance.tick_count
+        end
       end
     end
   end