laag-nasm 2.13.03.2

data/vendor/repo.or.cz/nasm/test/imacro.asm

@@ -0,0 +1,8 @@
+;Testname=test; Arguments=-fbin -oimacro.bin; Files=stdout stderr imacro.bin
+
+%imacro Zero 1
+	xor %1,%1
+%endmacro
+
+	Zero eax
+	zero eax

data/vendor/repo.or.cz/nasm/test/imm.asm

@@ -0,0 +1,23 @@
+	bits 64
+
+	mov eax,1
+	mov eax,-1
+	mov eax,0x11111111
+	mov ecx,2
+	add ecx,-6
+	add ecx,strict dword -6
+	add ecx,4
+	add ecx,strict dword 4
+	add ecx,10000
+	xor ecx,0xffffffff
+	xor ecx,dword 0xffffffff
+	xor ecx,strict dword 0xffffffff
+	xor ecx,-1
+	xor ecx,dword -1
+	xor ecx,strict dword -1
+	add edx,byte ($-$$)
+%ifnidn __OUTPUT_FORMAT__,bin
+	extern foo, bar
+	add eax,byte foo
+	add edx,byte (bar-$$)
+%endif

data/vendor/repo.or.cz/nasm/test/imm64.asm

@@ -0,0 +1,61 @@
+;Testname=imm64-O0; Arguments=-O0 -fbin -oimm64.bin; Files=stdout stderr imm64.bin
+;Testname=imm64-O1; Arguments=-O1 -fbin -oimm64.bin; Files=stdout stderr imm64.bin
+;Testname=imm64-Ox; Arguments=-Ox -fbin -oimm64.bin; Files=stdout stderr imm64.bin
+
+	bits 64
+	mov rax,11223344h
+	mov rax,dword 11223344h
+	mov eax,11223344h
+	mov [rax],dword 11223344h		; 32-bit operation
+	mov qword [rax],11223344h
+	mov qword [rax],dword 11223344h
+
+	mov rax,0_ffffffff_8899aabbh
+	mov rax,dword 0_ffffffff_8899aabbh
+	mov eax,0_ffffffff_8899aabbh
+	mov [rax],dword 0_ffffffff_8899aabbh	; 32-bit operation
+	mov qword [rax],0_ffffffff_8899aabbh
+	mov qword [rax],dword 0_ffffffff_8899aabbh
+
+	mov rax,7fffffffh
+	mov rax,80000000h
+	mov rax,0_ffffffffh
+	mov rax,1_00000000h
+	mov rax,0_ffffffff_7fffffffh
+	mov rax,0_ffffffff_80000000h
+
+	mov rax,0_11223344_8899aabbh
+	mov rax,dword 0_11223344_8899aabbh
+	mov eax,0_11223344_8899aabbh
+	mov [rax],dword 0_11223344_8899aabbh	; 32-bit operation
+	mov qword [rax],0_11223344_8899aabbh
+	mov qword [rax],dword 0_11223344_8899aabbh
+	
+	mov rax,strict 11223344h
+	mov rax,strict dword 11223344h
+	mov eax,strict 11223344h
+	mov [rax],strict dword 11223344h		; 32-bit operation
+	mov qword [rax],strict 11223344h
+	mov qword [rax],strict dword 11223344h
+
+	mov rax,strict 0_ffffffff_8899aabbh
+	mov rax,strict dword 0_ffffffff_8899aabbh
+	mov eax,strict 0_ffffffff_8899aabbh
+	mov [rax],strict dword 0_ffffffff_8899aabbh	; 32-bit operation
+	mov qword [rax],strict 0_ffffffff_8899aabbh
+	mov qword [rax],strict dword 0_ffffffff_8899aabbh
+
+	mov rax,strict 7fffffffh
+	mov rax,strict 80000000h
+	mov rax,strict 0_ffffffffh
+	mov rax,strict 1_00000000h
+	mov rax,strict 0_ffffffff_7fffffffh
+	mov rax,strict 0_ffffffff_80000000h
+
+	mov rax,strict 0_11223344_8899aabbh
+	mov rax,strict dword 0_11223344_8899aabbh
+	mov eax,strict 0_11223344_8899aabbh
+	mov [rax],strict dword 0_11223344_8899aabbh	; 32-bit operation
+	mov qword [rax],strict 0_11223344_8899aabbh
+	mov qword [rax],strict dword 0_11223344_8899aabbh
+	

data/vendor/repo.or.cz/nasm/test/immwarn.asm

@@ -0,0 +1,91 @@
+;Testname=onowarn; Arguments=-Ox -DOPT=1 -DWARN=0 -fbin -oimmwarn.bin; Files=stdout stderr immwarn.bin
+;Testname=owarn; Arguments=-Ox -DOPT=1 -DWARN=1 -fbin -oimmwarn.bin; Files=stdout stderr immwarn.bin
+;Testname=nowarn; Arguments=-O0 -DOPT=0 -DWARN=0 -fbin -oimmwarn.bin; Files=stdout stderr immwarn.bin
+;Testname=warn; Arguments=-O0 -DOPT=1 -DWARN=1 -fbin -oimmwarn.bin; Files=stdout stderr immwarn.bin
+
+%ifndef WARN
+  %define WARN 1
+%endif
+
+	bits 16
+	push 1
+%if WARN
+	push 0ffffffffh
+%endif
+	push -1
+	push 0ffffh
+	push byte 0FFFFh
+
+	add ax,0FFFFh
+%if WARN
+	add ax,0FFFFFFFFh
+%endif
+	add ax,-1
+	add ax,byte 0FFFFh
+%if WARN
+	add ax,byte 0FFFFFFFFh
+%endif
+	add ax,-1
+
+	add cx,0FFFFh
+%if WARN
+	add cx,0FFFFFFFFh
+%endif
+	add cx,-1
+	add cx,byte 0FFFFh
+%if WARN
+	add cx,byte 0FFFFFFFFh
+%endif
+	add cx,-1
+
+	bits 32
+	push 1
+	push 0ffffffffh
+	push -1
+	push 0ffffh
+
+	push byte 1
+%if WARN
+	push byte 0ffffh
+%endif
+	push byte -1
+
+	push word 1
+	push word 0ffffh
+	push word -1
+
+	push dword 1
+	push dword 0ffffffffh
+	push dword -1
+
+	add eax,0FFFFh
+	add eax,0FFFFFFFFh
+	add eax,-1
+
+	add ecx,0FFFFh
+	add ecx,0FFFFFFFFh
+	add ecx,-1
+
+	bits 64
+	mov eax,7fffffffh
+	mov eax,80000000h
+	mov rax,7fffffffh
+	mov rax,80000000h
+%if WARN
+	mov rax,dword 80000000h
+%endif
+	add rcx,0FFFFh
+%if WARN
+	add rcx,0FFFFFFFFh
+%endif
+	add rcx,-1
+
+	add ecx,0FFFFh
+	add ecx,0FFFFFFFFh
+	add ecx,-1
+
+	push byte 1
+%if WARN
+	push byte 0ffffffffh
+%endif
+	push byte -1

data/vendor/repo.or.cz/nasm/test/imul.asm

@@ -0,0 +1,117 @@
+;Testname=nowarn; Arguments=-fbin -oimul.bin; Files=stdout stderr imul.bin
+;Testname=warn; Arguments=-DWARN -fbin -oimul.bin; Files=stdout stderr imul.bin
+
+%macro test 1-3 5 -2
+	bits %1
+
+%undef MEM
+%if %1 == 16
+  %define MEM [di]
+%elif %1 == 32
+  %define MEM [edi]
+%elif %1 == 64
+  %define MEM [rdi]
+%endif
+
+	imul al
+	imul byte MEM
+	imul ax
+	imul word MEM
+	imul eax
+	imul dword MEM
+%if %1 == 64
+	imul rdx
+	imul qword MEM
+%endif
+	
+	imul ax,cx
+	imul ax,MEM
+	imul ax,word MEM
+	imul eax,ecx
+	imul eax,MEM
+	imul eax,dword MEM
+%if %1 == 64
+	imul rax,rcx
+	imul rax,MEM
+	imul rax,qword MEM
+%endif
+
+	imul ax,cx,%2
+	imul ax,cx,byte %2
+	imul ax,MEM,%2
+	imul ax,word MEM,%2
+	imul eax,ecx,%2
+	imul eax,ecx,byte %2
+	imul eax,MEM,%2
+	imul eax,dword MEM,%2
+%if %1 == 64
+	imul rax,rcx,%2
+	imul rax,rcx,byte %2
+	imul rax,MEM,%2
+	imul rax,qword MEM,%2
+%endif
+
+	imul ax,%2
+	imul ax,byte %2
+	imul eax,%2
+	imul eax,byte %2
+%if %1 == 64
+	imul rax,%2
+	imul rax,byte %2
+%endif
+
+	imul ax,cx,0x1234
+	imul ax,MEM,0x1234
+	imul ax,word MEM,0x1234
+	imul eax,ecx,0x12345678
+	imul eax,MEM,0x12345678
+	imul eax,dword MEM,0x12345678
+%if %1 == 64
+	imul rax,rcx,0x12345678
+	imul rax,MEM,0x12345678
+	imul rax,qword MEM,0x12345678
+%endif
+
+	imul ax,0x1234
+	imul eax,0x12345678
+%if %1 == 64
+	imul rax,0x12345678
+%endif
+
+	imul ax,cx,0xfffe
+	imul ax,MEM,0xfffe
+	imul ax,word MEM,0xfffe
+	imul ax,cx,0xfe
+	imul ax,MEM,0xfe
+	imul ax,word MEM,0xfe
+	imul eax,ecx,0xfffffffe
+	imul eax,MEM,0xfffffffe
+	imul eax,dword MEM,0xfffffffe
+	imul eax,ecx,0xfffe
+	imul eax,MEM,0xfffe
+	imul eax,dword MEM,0xfffe
+%if %1 == 64
+	imul rax,rcx,%3
+	imul rax,MEM,%3
+	imul rax,qword MEM,%3
+	imul rax,rcx,0xfffe
+	imul rax,MEM,0xfffe
+	imul rax,qword MEM,0xfffe
+%endif
+
+	imul ax,0xfffe
+	imul eax,0xfffffffe
+%if %1 == 64
+	imul rax,%3
+%endif
+%endmacro
+
+	test 16
+	test 32
+	test 64
+
+%ifdef WARN
+	test 16,0x999
+	test 32,0x999999
+	test 64,0x999999999,0xfffffffe
+%endif

data/vendor/repo.or.cz/nasm/test/inc1.asm

@@ -0,0 +1,6 @@
+; This file is part of the include test.
+; See inctest.asm for build instructions.
+
+message:  db 'hello, world',13,10,'$'
+
+%include "inc2.asm"

data/vendor/repo.or.cz/nasm/test/inc2.asm

@@ -0,0 +1,8 @@
+; This file is part of the include test.
+; See inctest.asm for build instructions.
+
+_main:	  mov dx,message
+	  mov ah,9
+	  int 21h
+	  mov ax,4c00h
+	  int 21h

data/vendor/repo.or.cz/nasm/test/incbin.asm

@@ -0,0 +1,7 @@
+	db '*** ONCE ***', 0Ah
+	incbin "incbin.data",32
+
+	section more start=0x1000000
+	db '*** TWELVE ***', 0Ah
+	times 12 incbin "incbin.data",32
+	db '<END>', 0Ah

data/vendor/repo.or.cz/nasm/test/incbin.data

@@ -0,0 +1,2 @@
+This is the wrong line of text.
+This is the right line of text.

data/vendor/repo.or.cz/nasm/test/inctest.asm

@@ -0,0 +1,15 @@
+;Testname=test; Arguments=-fbin -oinctest.com; Files=stdout stderr inctest.com
+
+; This file, plus inc1.asm and inc2.asm, test NASM's file inclusion
+; mechanism.
+;
+; This produces a DOS .COM file: to assemble, use
+;    nasm -f bin inctest.asm -o inctest.com
+; and when run, it should print `hello, world'.
+
+	  BITS 16
+	  ORG 0x100
+
+	  jmp _main
+
+%include "inc1.asm"

data/vendor/repo.or.cz/nasm/test/insnlbl.asm

@@ -0,0 +1,12 @@
+;Testname=test; Arguments=-fbin -oinsnlbl.bin; Files=stdout stderr insnlbl.bin
+
+;
+; Test "instruction as label" -- make opcodes legal as labels if
+; they are followed by a colon.
+;
+
+do:	jmp dq+2
+	dw do, add, sub, dq
+add:	jmp add-2
+sub:	jmp do+2
+dq:	dw $-sub

data/vendor/repo.or.cz/nasm/test/invlpga.asm

@@ -0,0 +1,11 @@
+;Testname=unoptimized; Arguments=-fbin -oinvlpga.bin;     Files=stdout stderr invlpga.bin
+;Testname=optimized;   Arguments=-fbin -oinvlpga.bin -Ox; Files=stdout stderr invlpga.bin
+
+	bits 32
+	invlpga
+	invlpga ax,ecx
+	invlpga eax,ecx
+	bits 64
+	invlpga
+	invlpga eax,ecx
+	invlpga rax,ecx

data/vendor/repo.or.cz/nasm/test/jmp64.asm

@@ -0,0 +1,19 @@
+;Testname=test; Arguments=-fbin -ojmp64.bin; Files=stdout stderr jmp64.bin
+
+	bits 64
+	jmp rcx
+	jmp [rax]
+	jmp qword [rax]
+	jmp near [rax]
+	jmp near qword [rax]
+	jmp far [rax]
+	jmp far dword [rax]
+	jmp far qword [rax]
+	call rcx
+	call [rax]
+	call qword [rax]
+	call near [rax]
+	call near qword [rax]
+	call far [rax]
+	call far dword [rax]
+	call far qword [rax]

data/vendor/repo.or.cz/nasm/test/lar_lsl.asm

@@ -0,0 +1,124 @@
+;Testname=test; Arguments=-fbin -olar_lsl.bin; Files=stdout stderr lar_lsl.bin
+
+; LAR/LSL
+;---------
+
+; 1x ; = invalid due to lack of REX
+; 3x ; = invalid due to Mw
+
+%macro m 1
+
+  bits 16
+
+	%1  ax, ax
+	%1  ax,eax
+;	%1  ax,rax
+
+	%1 eax, ax
+	%1 eax,eax
+;	%1 eax,rax
+
+;	%1 rax, ax
+;	%1 rax,eax
+;	%1 rax,rax
+
+	%1  ax,      [0]
+	%1  ax, word [0]
+;;;	%1  ax,dword [0]
+;	%1  ax,qword [0]
+
+	%1 eax,      [0]
+	%1 eax, word [0]
+;;;	%1 eax,dword [0]
+;	%1 eax,qword [0]
+
+;	%1 rax,      [0]
+;	%1 rax, word [0]
+;	%1 rax,dword [0]
+;	%1 rax,qword [0]
+
+  bits 32
+
+	%1  ax, ax
+	%1  ax,eax
+;	%1  ax,rax
+
+	%1 eax, ax
+	%1 eax,eax
+;	%1 eax,rax
+
+;	%1 rax, ax
+;	%1 rax,eax
+;	%1 rax,rax
+
+	%1  ax,      [0]
+	%1  ax, word [0]
+;;;	%1  ax,dword [0]
+;	%1  ax,qword [0]
+
+	%1 eax,      [0]
+	%1 eax, word [0]
+;;;	%1 eax,dword [0]
+;	%1 eax,qword [0]
+
+;	%1 rax,      [0]
+;	%1 rax, word [0]
+;	%1 rax,dword [0]
+;	%1 rax,qword [0]
+
+  bits 64
+
+	%1  ax, ax
+	%1  ax,eax
+	%1  ax,rax	; $TODO: shouldn't emit REX.W $
+
+	%1 eax, ax
+	%1 eax,eax
+	%1 eax,rax	; $TODO: shouldn't emit REX.W $
+
+	%1 rax, ax
+	%1 rax,eax
+	%1 rax,rax
+
+	%1  ax,      [0]
+	%1  ax, word [0]
+;;;	%1  ax,dword [0]
+;;;	%1  ax,qword [0]
+
+	%1 eax,      [0]
+	%1 eax, word [0]
+;;;	%1 eax,dword [0]
+;;;	%1 eax,qword [0]
+
+	%1 rax,      [0]
+	%1 rax, word [0]
+;;;	%1 rax,dword [0]
+;;;	%1 rax,qword [0]
+
+%endmacro
+
+m lar
+
+m lsl
+
+bits 16
+lar ax,[ si]
+lar ax,[esi]
+bits 32
+lar ax,[ si]
+lar ax,[esi]
+bits 64
+lar ax,[esi]
+lar ax,[rsi]
+
+bits 16
+lsl ax,[ si]
+lsl ax,[esi]
+bits 32
+lsl ax,[ si]
+lsl ax,[esi]
+bits 64
+lar ax,[esi]
+lsl ax,[rsi]
+
+; EOF