kompiler 0.3.0.pre.1 → 0.3.0.pre.2

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 94839a8d70f8124e207b1c57efcefd4b97bc0b981a38f9319fddce27510954c7
-  data.tar.gz: 257358df8104b1e130361095b6d2c25f6fdac542918af69687313cc00a7bd4d2
+  metadata.gz: 0c7b411e21f2b93443cb22e7461437c8ab98df8acc4fd56538d64c8fc0d7c828
+  data.tar.gz: 05747db808c1d5accc8b42ee6681b2a617feb89437bf244e389420740a3d4da0
 SHA512:
-  metadata.gz: 91804940ae6a1182841aa27d781c410ecae3644500c64907119409ae019e192c75d79bc3ef661ea8aac56b27113fce6ca2bb54c487cd0684f702a42913e445c7
-  data.tar.gz: 6e05374e4e6b0f279aedc8e3087d21bc0bfbc919b431453fd7f1382a0fa39777a37f3e65cfd646576cb806fc0cc07f119649ae080ad6d3b495d372e60c93ca8c
+  metadata.gz: 0a302052eb6c01c1f6812e98b8492fc455077746effb6e6d6133a411eb179b157ecf3bc1a4bcd38e85e1a1dc2aea52dee4cfd7088b9212b73df6f0912ac9d1fc
+  data.tar.gz: af2d6fb1f53eae49d7121fc90048d1bc5766316bc302fd910bc1702cf4dab3f43fd09ee01433fbb11f8ec4419de7191a0cc02fd64bb43f8c998173c78acc0237

data/lib/kompiler/architectures/armv8a/instructions.rb

@@ -11,32 +11,44 @@ end
 	
 @instructions = [
 	{	keyword: "mov",
-		operands: [{type: "register", restrictions: {reg_size: 64}}, {type: "immediate", restrictions: {}}],
+		name: "Move (immediate)",
+		description: "Moves an immediate value to the destination register",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Destination"}, {type: "immediate", restrictions: {}, name: "Immediate value"}],
 		mc_constructor: [
 			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5],
 			["get_bits", ["get_operand", 1], 0, 16],
-			["bits", 0,0, 1,0,1,0,0,1, 0,1, 1]
+			["bits", 0,0, 1,0,1,0,0,1, 0,1],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], 0],
 		],
 		bitsize: 32
 	},
 	{	keyword: "mov",
-		operands: [{type: "register", restrictions: {reg_size: 64}}, {type: "register", restrictions: {reg_size: 64}}],
+		name: "Move (register)",
+		description: "Copies the value in the source register to the destination register",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Destination"}, {type: "register", restrictions: {reg_type: "gpr"}, name: "Source"}],
 		mc_constructor: [
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "mov Error: Register sizes are not the same"]],
 			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5], # Rd
 			["bits", 1,1,1,1,1], # rn
 			["bits", 0,0,0,0,0,0], # imm6
 			["get_bits", ["encode_gp_register", ["get_operand", 1]], 0, 5], # Rm
-			["bits", 0, 0,0, 0,1,0,1,0,1,0, 1]
+			["bits", 0, 0,0, 0,1,0,1,0,1,0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], 0],
 		],
 		bitsize: 32
 	},
 	{	keyword: "mov_sp",
-		operands: [{type: "register", restrictions: {reg_size: 64}}, {type: "register", restrictions: {reg_size: 64}}],
+		name: "Move (to/from SP)",
+		description: "Move between a general-purpose register and the stack pointer.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}}, {type: "register", restrictions: {reg_type: "gpr"}}],
 		mc_constructor: [
+			# Get the non-SP register
+			["if_eq_else", ["downcase_str", ["get_key", ["get_operand", 0], :reg_name]], "sp", ["set_var", "non_sp_reg", ["get_operand", 1]], ["set_var", "non_sp_reg", ["get_operand", 0]]],
 			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5], # Rd
 			["get_bits", ["encode_gp_register", ["get_operand", 1]], 0, 5], # Rn
 			["get_bits", 0, 0, 12], # imm12 as ones
-			["bits", 0, 0,1,0,0,0,1, 0, 0, 1]
+			["bits", 0, 0,1,0,0,0,1, 0, 0],
+			["case", ["get_key", ["get_var", "non_sp_reg"], :reg_size], 64, ["bits", 1], 32, ["bits", 0], 0],
 		],
 		bitsize: 32
 	},
@@ -64,23 +76,17 @@ end
 		],
 		bitsize: 32
 	},
-	{	keyword: "mov",
-		operands: [{type: "register", restrictions: {reg_size: 32}}, {type: "immediate", restrictions: {}}],
-		mc_constructor: [
-			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5],
-			["get_bits", ["get_operand", 1], 0, 16],
-			["bits", 0,0, 1,0,1,0,0,1, 0,1, 0]
-		],
-		bitsize: 32
-	},
 	{
 		keyword: "add",
-		operands: [{type: "register", restrictions: {reg_size: 64}}, {type: "register", restrictions: {reg_size: 64}}, {type: "immediate", restrictions: {}}],
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}}, {type: "register", restrictions: {reg_type: "gpr"}}, {type: "immediate"}],
 		mc_constructor: [
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "add Error: Register sizes are not the same"]],
+
 			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5],
 			["get_bits", ["encode_gp_register", ["get_operand", 1]], 0, 5],
 			["get_bits", ["get_operand", 2], 0, 12],
-			["bits", 0, 0,1,0,0,0,1,0,0,1]
+			["bits", 0, 0,1,0,0,0,1,0,0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []], # sf
 		],
 		bitsize: 32
 	},
@@ -89,15 +95,20 @@ end
 		keyword: "add",
 		name: "ADD (registers)",
 		description: "Adds two source registers and writes the result to the destination register",
-		operands: [{type: "register", restrictions: {reg_size: 64}}, {type: "register", restrictions: {reg_size: 64}}, {type: "register", restrictions: {reg_size: 64}}],
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}}, {type: "register", restrictions: {reg_type: "gpr"}}, {type: "register", restrictions: {reg_type: "gpr"}}],
 		mc_constructor: [
+			# Make sure register sizes are the same
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "add Error: Register sizes are not the same"]],
+			["if_eq_else", ["get_key", ["get_operand", 1], :reg_size], ["get_key", ["get_operand", 2], :reg_size], [], ["raise_error", "add Error: Register sizes are not the same"]],
+
 			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5], # Rd
 			["get_bits", ["encode_gp_register", ["get_operand", 1]], 0, 5], # Rn
 			["get_bits", 0, 0, 6], # imm6
 			["get_bits", ["encode_gp_register", ["get_operand", 2]], 0, 5], # Rm
 			["bits", 0],
 			["bits", 0,0], # shift
-			["bits", 1,1,0,1,0, 0, 0, 1], # sf at the end
+			["bits", 1,1,0,1,0, 0, 0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []], # sf
 		],
 		bitsize: 32
 	},
@@ -141,7 +152,9 @@ end
 	
 	{
 		keyword: "adr",
-		operands: [{type: "register", restrictions: {reg_size: 64}}, {type: "label"}],
+		name: "Address (label)",
+		description: "Writes the address of the specified label to the destination register through PC-relative computations.",
+		operands: [{type: "register", restrictions: {reg_size: 64}, name: "Destination"}, {type: "label", name: "Label"}],
 		mc_constructor: [
 			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5],
 			["get_bits", ["subtract", ["get_label_address", ["get_operand", 1]], ["get_current_address"]], 2, 19],
@@ -151,6 +164,20 @@ end
 		],
 		bitsize: 32
 	},
+	{
+		keyword: "adr",
+		name: "Address (immediate)",
+		description: "Adds an immediate value to the PC Value, and writes the result to the destination register.",
+		operands: [{type: "register", restrictions: {reg_size: 64}, name: "Destination"}, {type: "immediate", name: "Immediate Offset"}],
+		mc_constructor: [
+			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5],
+			["get_bits", ["get_operand", 1], 2, 19],
+			["bits", 0,0,0,0,1],
+			["get_bits", ["get_operand", 1], 0, 2],
+			["bits", 0],
+		],
+		bitsize: 32
+	},
 	{
 		keyword: "b",
 		operands: [{type: "immediate"}],
@@ -281,19 +308,38 @@ end
 		bitsize: 32
 	},
 	
-	
-	
 	{
-		# LDR immediate
 		keyword: "ldr",
-		operands: [{type: "register", restrictions: {reg_size: 64}}, {type: "label"}],
+		name: "Load Register (literal, immediate)",
+		description: "Calculates an adress from the PC value and an immediate offset, loads a word from memory, and writes it to a register.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}}, {type: "immediate"}],
+		mc_constructor: [
+			["if_eq_else", ["modulo", ["get_operand", 1], 4], 0, [], ["raise_error", "ldr (immediate) Error: Immediate offset is not divisible by four."]], # Check if the immediate offset is right
+
+			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5],
+			["get_bits", ["divide", ["get_operand", 1], 4], 0, 19],
+			["bits", 0,0,0,1,1,0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 32, ["bits", 0], 64, ["bits", 1], 0], # opc size bit
+			["bits", 0], # opc second bit
+		],
+		bitsize: 32
+	},
+	{
+		keyword: "ldr",
+		name: "Load Register (literal, label)",
+		description: "Loads a word from memory at the address specified by the label, and writes it to a register.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}}, {type: "label"}],
 		mc_constructor: [
-			["if_eq_else", ["modulo", ["subtract", ["get_label_address", ["get_operand", 1]], ["get_current_address"]], 4], 0, [], ["raise_error", "Can't represent address for LDR - offset not divisible by 4 bytes."]], # Check if address is accessible
+			["set_var", "immediate_offset", ["subtract", ["get_label_address", ["get_operand", 1]], ["get_current_address"]]],
+			
+			["if_eq_else", ["modulo", ["get_var", "immediate_offset"], 4], 0, [], ["raise_error", "ldr (label) Error: Label not accessible (not divisible by four)."]], # Check if address is accessible
 			
 			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5],
-			["get_bits", ["divide", ["subtract", ["get_label_address", ["get_operand", 1]], ["get_current_address"]], 4], 0, 19],
-
-			["bits", 0,0,0,1,1,0,1,0],
+			["get_bits", ["divide", ["get_var", "immediate_offset"], 4], 0, 19],
+	
+			["bits", 0,0,0,1,1,0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 32, ["bits", 0], 64, ["bits", 1], 0], # opc size bit
+			["bits", 0], # opc second bit
 		],
 		bitsize: 32
 	},
@@ -317,7 +363,7 @@ end
 	{
 		keyword: "ldr_unsigned",
 		name: "Load Register (immediate), unsigned offset",
-		description: "Loads 4 or 8 bytes from memory at the address in the second register with an unsigned immediate offset, and writes it to the destination register",
+		description: "Loads 4 or 8 bytes from memory at the address in the second register, with an unsigned immediate offset added, and writes it to the destination register.",
 		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Destination"}, {type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Source address"}, {type: "immediate", name: "Offset"}],
 		mc_constructor: [
 			["case", ["get_key", ["get_operand", 0], :reg_size],
@@ -340,6 +386,38 @@ end
 		],
 		bitsize: 32
 	},
+	{
+		keyword: "ldr_post_index",
+		name: "Load Register (immediate), post-index",
+		description: "Loads 4 or 8 bytes from memory at the address in the second register, with an immediate value added permanently after reading, and writes it to the destination register.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Destination"}, {type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Source address"}, {type: "immediate", name: "Address Offset"}],
+		mc_constructor: [
+			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5],
+			["get_bits", ["encode_gp_register", ["get_operand", 1]], 0, 5],
+			["bits", 1,0],
+			["get_bits", ["get_operand", 2], 0, 9],
+			["bits", 0, 1,0, 0,0, 0, 1,1,1],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []],
+			["bits", 1],
+		],
+		bitsize: 32
+	},
+	{
+		keyword: "ldr_pre_index",
+		name: "Load Register (immediate), pre-index",
+		description: "Loads 4 or 8 bytes from memory at the address in the second register, with an immediate value added permanently before reading, and writes it to the destination register.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Destination"}, {type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Source address"}, {type: "immediate", name: "Address Offset"}],
+		mc_constructor: [
+			["get_bits", ["encode_gp_register", ["get_operand", 0]], 0, 5],
+			["get_bits", ["encode_gp_register", ["get_operand", 1]], 0, 5],
+			["bits", 1,1],
+			["get_bits", ["get_operand", 2], 0, 9],
+			["bits", 0, 1,0, 0,0, 0, 1,1,1],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []],
+			["bits", 1],
+		],
+		bitsize: 32
+	},
 	
 	{
 		keyword: "ldrb",
@@ -613,11 +691,11 @@ end
 		bitsize: 32,
 		mc_constructor: [
 			# Check for register sizes
-			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "stp Error: Register sizes are not the same"]],
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "stp_signed Error: Register sizes are not the same"]],
 			# Establish the immediate offset alignment using the register size
 			["set_var", "imm_alignment", ["case", ["get_key", ["get_operand", 0], :reg_size], 32, 4, 64, 8, 0]],
 			# Check if the immediate offset is properly aligned
-			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "stp Error: The immediate offset is not properly aligned"]],
+			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "stp_signed Error: The immediate offset is not properly aligned"]],
 
 			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
 			["get_bits", ["get_key", ["get_operand", 2], :reg_value], 0, 5],
@@ -635,11 +713,11 @@ end
 		bitsize: 32,
 		mc_constructor: [
 			# Check for register sizes
-			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "stp Error: Register sizes are not the same"]],
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "stp_pre_index Error: Register sizes are not the same"]],
 			# Establish the immediate offset alignment using the register size
 			["set_var", "imm_alignment", ["case", ["get_key", ["get_operand", 0], :reg_size], 32, 4, 64, 8, 0]],
 			# Check if the immediate offset is properly aligned
-			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "stp Error: The immediate offset is not properly aligned"]],
+			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "stp_pre_index Error: The immediate offset is not properly aligned"]],
 	
 			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
 			["get_bits", ["get_key", ["get_operand", 2], :reg_value], 0, 5],
@@ -657,11 +735,11 @@ end
 		bitsize: 32,
 		mc_constructor: [
 			# Check for register sizes
-			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "stp Error: Register sizes are not the same"]],
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "stp_post_index Error: Register sizes are not the same"]],
 			# Establish the immediate offset alignment using the register size
 			["set_var", "imm_alignment", ["case", ["get_key", ["get_operand", 0], :reg_size], 32, 4, 64, 8, 0]],
 			# Check if the immediate offset is properly aligned
-			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "stp Error: The immediate offset is not properly aligned"]],
+			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "stp_post_index Error: The immediate offset is not properly aligned"]],
 	
 			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
 			["get_bits", ["get_key", ["get_operand", 2], :reg_value], 0, 5],
@@ -846,6 +924,37 @@ end
 		bitsize: 32
 	},
 	
+	{
+		keyword: "sev",
+		name: "Send Event",
+		description: "A hint instruction that causes an event to be signalled to all cores in a multiprocessor system.",
+		operands: [],
+		mc_constructor: [
+			["bits", 1,1,1,1,1, 0,0,1, 0,0,0,0, 0,1,0,0, 1,1,0, 0,0, 0, 0,0,1,0,1,0,1,0,1,1]
+		],
+		bitsize: 32
+	},
+	{
+		keyword: "wfe",
+		name: "Wait For Event",
+		description: "A hint instruction that indicates that the PE can enter a low-power state and remain there until a wakeup event occurs. Wakeup events include the event signaled using SEV.",
+		operands: [],
+		mc_constructor: [
+			["bits", 1,1,1,1,1, 0,1,0, 0,0,0,0, 0,1,0,0, 1,1,0, 0,0, 0, 0,0,1,0,1,0,1,0,1,1]
+		],
+		bitsize: 32
+	},
+	{
+		keyword: "wfi",
+		name: "Wait For Interrupt",
+		description: "A hint instruction that indicates that the PE can enter a low-power state and remain there until a wakeup event occurs.",
+		operands: [],
+		mc_constructor: [
+			["bits", 1,1,1,1,1, 1,1,0, 0,0,0,0, 0,1,0,0, 1,1,0, 0,0, 0, 0,0,1,0,1,0,1,0,1,1]
+		],
+		bitsize: 32
+	},
+	
 	
 	#
 	# B.cond instructions

data/lib/kompiler/architectures/armv8a/sys_registers.rb

@@ -17,6 +17,42 @@ end
 	{reg_name: "vbar_el2", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b100, "CRn"=>0b1100, "CRm"=>0, "op2"=>0}, rw_type: "rw"},
 	{reg_name: "vbar_el3", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b110, "CRn"=>0b1100, "CRm"=>0, "op2"=>0}, rw_type: "rw"},
 
+	{reg_name: "currentEL", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b000, "CRn"=>0b0100, "CRm"=>0b0010, "op2"=>0b010}},
+	
+	{reg_name: "SPSR_EL1", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b000, "CRn"=>0b0100, "CRm"=>0b0000, "op2"=>0b000}},
+	{reg_name: "SPSR_EL12", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b101, "CRn"=>0b0100, "CRm"=>0b0000, "op2"=>0b000}},
+	{reg_name: "SPSR_EL2", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b100, "CRn"=>0b0100, "CRm"=>0b0000, "op2"=>0b000}},
+	{reg_name: "SPSR_EL3", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b110, "CRn"=>0b0100, "CRm"=>0b0000, "op2"=>0b000}},
+	
+	{reg_name: "ELR_EL1", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b000, "CRn"=>0b0100, "CRm"=>0b0000, "op2"=>0b001}},
+	{reg_name: "ELR_EL12", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b101, "CRn"=>0b0100, "CRm"=>0b0000, "op2"=>0b001}},
+	{reg_name: "ELR_EL2", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b100, "CRn"=>0b0100, "CRm"=>0b0000, "op2"=>0b001}},
+	{reg_name: "ELR_EL3", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b110, "CRn"=>0b0100, "CRm"=>0b0000, "op2"=>0b001}},
+	
+	{reg_name: "SCTLR_EL1", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b000, "CRn"=>0b0001, "CRm"=>0b0000, "op2"=>0b000}},
+	{reg_name: "SCTLR_EL12", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b101, "CRn"=>0b0001, "CRm"=>0b0000, "op2"=>0b000}},
+	{reg_name: "SCTLR_EL2", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b100, "CRn"=>0b0001, "CRm"=>0b0000, "op2"=>0b000}},
+	{reg_name: "SCTLR_EL3", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b110, "CRn"=>0b0001, "CRm"=>0b0000, "op2"=>0b000}},
+	
+	{reg_name: "SCTLR2_EL1", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b000, "CRn"=>0b0001, "CRm"=>0b0000, "op2"=>0b011}},
+	{reg_name: "SCTLR2_EL12", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b101, "CRn"=>0b0001, "CRm"=>0b0000, "op2"=>0b011}},
+	{reg_name: "SCTLR2_EL2", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b100, "CRn"=>0b0001, "CRm"=>0b0000, "op2"=>0b011}},
+	{reg_name: "SCTLR2_EL3", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b110, "CRn"=>0b0001, "CRm"=>0b0000, "op2"=>0b011}},
+	
+	{reg_name: "HCR_EL2", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b100, "CRn"=>0b0001, "CRm"=>0b0001, "op2"=>0b000}},
+	
+	{reg_name: "ESR_EL1", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b000, "CRn"=>0b0101, "CRm"=>0b0010, "op2"=>0b000}},
+	{reg_name: "ESR_EL2", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b100, "CRn"=>0b0101, "CRm"=>0b0010, "op2"=>0b000}},
+	{reg_name: "ESR_EL3", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b110, "CRn"=>0b0101, "CRm"=>0b0010, "op2"=>0b000}},
+	
+	{reg_name: "SPSel", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b000, "CRn"=>0b0100, "CRm"=>0b0010, "op2"=>0b000}},
+
+
+	{reg_name: "SP_EL0", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b000, "CRn"=>0b0100, "CRm"=>0b0001, "op2"=>0b000}},
+	{reg_name: "SP_EL1", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b100, "CRn"=>0b0100, "CRm"=>0b0001, "op2"=>0b000}},
+	{reg_name: "SP_EL2", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b110, "CRn"=>0b0100, "CRm"=>0b0001, "op2"=>0b000}},
+	
+	{reg_name: "ISR_EL1", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b000, "CRn"=>0b1100, "CRm"=>0b0001, "op2"=>0b000}},
 	
 	# Special registers for the MSR (immediate) instruction (some of them were previously defined already)
 	{reg_name: "SPSel", reg_type: "pstate_reg"},

data/lib/kompiler/parsers.rb

@@ -303,8 +303,8 @@ def self.parse_instruction_line(line)
 			i += 1
 		end
 		
-		# After operand content was collected, add it to the list of operands
-		operand_strings << operand_content
+		# After operand content was collected, add it to the list of operands if the content isn't empty
+		operand_strings << operand_content if operand_content.size != 0
 	end	
 	
 	# Parse operand strings into operand types and values

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: kompiler
 version: !ruby/object:Gem::Version
-  version: 0.3.0.pre.1
+  version: 0.3.0.pre.2
 platform: ruby
 authors:
 - Kyryl Shyshko
 autorequire:
 bindir: bin
 cert_chain: []
-date: 2024-12-13 00:00:00.000000000 Z
+date: 2024-12-23 00:00:00.000000000 Z
 dependencies: []
 description: 'Kompiler is a low-level, modular and extendable compiler for any architecture.
   By default Kompiler supports ARMv8-a, but other architecture extensions can be downloaded