kompiler 0.2.0 → 0.3.0.pre.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: 57ea6ace09f3b1a5c3d0914d9edbbd02a83a5002b5c55ecde398f593cdcbb211
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+  data.tar.gz: 257358df8104b1e130361095b6d2c25f6fdac542918af69687313cc00a7bd4d2
 SHA512:
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+  data.tar.gz: 6e05374e4e6b0f279aedc8e3087d21bc0bfbc919b431453fd7f1382a0fa39777a37f3e65cfd646576cb806fc0cc07f119649ae080ad6d3b495d372e60c93ca8c

data/lib/kompiler/architecture.rb

@@ -3,26 +3,26 @@
 
 module Kompiler
 
-class Architecture
+module Architecture
+
+@instructions = []
+@registers = []
 
-@@instructions = []
-@@registers = []
-	
 def self.set_arch instructions, registers
-	@@instructions = instructions
-	@@registers = registers
+	@instructions = instructions
+	@registers = registers
 end
 
-def self.load_arch(arch_name)
-	require "kompiler/arch/#{arch_name.downcase}/load"
-end
+# def self.load_arch(arch_name)
+# 	require "kompiler/arch/#{arch_name.downcase}/load"
+# end
 
 def self.instructions
-	@@instructions
+	@instructions
 end
 
 def self.registers
-	@@registers
+	@registers
 end
 
 end

data/lib/kompiler/architectures/armv8a/instructions.rb

@@ -3,13 +3,13 @@
 
 module Kompiler
 
-class ARMv8A
+module ARMv8A
 	
 def self.instructions
-	@@instructions
+	@instructions
 end
 	
-@@instructions = [
+@instructions = [
 	{	keyword: "mov",
 		operands: [{type: "register", restrictions: {reg_size: 64}}, {type: "immediate", restrictions: {}}],
 		mc_constructor: [
@@ -354,6 +354,91 @@ end
 		],
 		bitsize: 32
 	},
+	
+	{
+		keyword: "ldp",
+		name: "Load Pair",
+		description: "Loads data for two registers from memory at the address specified by the third register, and writes the data to two general-purpose registers.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Destination Register 1"}, {type: "register", restrictions: {reg_type: "gpr"}, name: "Destination Register 2"}, {type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Address Register"}],
+		bitsize: 32,
+		mc_constructor: [
+			# Check for register sizes
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "ldp Error: Register sizes are not the same"]],
+			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 2], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 1], :reg_value], 0, 5],
+			["get_bits", 0, 0, 7], # imm7
+			["bits", 1, 0,1,0, 0, 1,0,1, 0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []] # opc
+		]
+	},
+	{
+		keyword: "ldp_signed",
+		name: "Load Pair (signed offset)",
+		description: "Loads data for two registers from memory at the address specified by the third register, with a signed immediate offset added, and writes the data to two general-purpose registers.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 1"}, {type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 2"}, {type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Address Register"}, {type: "immediate", name: "Address Offset"}],
+		bitsize: 32,
+		mc_constructor: [
+			# Check for register sizes
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "ldp_signed Error: Register sizes are not the same"]],
+			# Establish the immediate offset alignment using the register size
+			["set_var", "imm_alignment", ["case", ["get_key", ["get_operand", 0], :reg_size], 32, 4, 64, 8, 0]],
+			# Check if the immediate offset is properly aligned
+			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "ldp_signed Error: The immediate offset is not properly aligned"]],
+	
+			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 2], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 1], :reg_value], 0, 5],
+			["get_bits", ["divide", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, 7], # imm7
+			["bits", 1, 0,1,0, 0, 1,0,1, 0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []] # opc
+		]
+	},
+	{
+		keyword: "ldp_pre_index",
+		name: "Load Pair (pre-index, signed offset)",
+		description: "Loads data for two registers from memory at the address specified by the third register, with a signed immediate offset added permanently before reading, and writes the data to two general-purpose registers.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 1"}, {type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 2"}, {type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Address Register"}, {type: "immediate", name: "Address Offset"}],
+		bitsize: 32,
+		mc_constructor: [
+			# Check for register sizes
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "ldp_pre_index Error: Register sizes are not the same"]],
+			# Establish the immediate offset alignment using the register size
+			["set_var", "imm_alignment", ["case", ["get_key", ["get_operand", 0], :reg_size], 32, 4, 64, 8, 0]],
+			# Check if the immediate offset is properly aligned
+			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "ldp_pre_index Error: The immediate offset is not properly aligned"]],
+	
+			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 2], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 1], :reg_value], 0, 5],
+			["get_bits", ["divide", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, 7], # imm7
+			["bits", 1, 1,1,0, 0, 1,0,1, 0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []] # opc
+		]
+	},
+	{
+		keyword: "ldp_post_index",
+		name: "Load Pair (post-index, signed offset)",
+		description: "Loads data for two registers from memory at the address specified by the third register, with a signed immediate offset added permanently after reading, and writes the data to two general-purpose registers.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 1"}, {type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 2"}, {type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Address Register"}, {type: "immediate", name: "Address Offset"}],
+		bitsize: 32,
+		mc_constructor: [
+			# Check for register sizes
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "ldp_post_index Error: Register sizes are not the same"]],
+			# Establish the immediate offset alignment using the register size
+			["set_var", "imm_alignment", ["case", ["get_key", ["get_operand", 0], :reg_size], 32, 4, 64, 8, 0]],
+			# Check if the immediate offset is properly aligned
+			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "ldp_post_index Error: The immediate offset is not properly aligned"]],
+	
+			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 2], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 1], :reg_value], 0, 5],
+			["get_bits", ["divide", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, 7], # imm7
+			["bits", 1, 1,0,0, 0, 1,0,1, 0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []] # opc
+		]
+	},
+	
 	{
 		keyword: "strh",
 		operands: [{type: "register", restrictions: {reg_size: 32}}, {type: "register", restrictions: {reg_size: 64}}],
@@ -503,6 +588,90 @@ end
 		bitsize: 32
 	},
 	
+	{
+		keyword: "stp",
+		name: "Store Pair",
+		description: "Stores the contents of two general-purpose registers at the address specified by the third register.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 1"}, {type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 2"}, {type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Address Register"}],
+		bitsize: 32,
+		mc_constructor: [
+			# Check for register sizes
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "stp Error: Register sizes are not the same"]],
+			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 2], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 1], :reg_value], 0, 5],
+			["get_bits", 0, 0, 7], # imm7
+			["bits", 0, 0,1,0, 0, 1,0,1, 0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []] # opc
+		]
+	},
+	{
+		keyword: "stp_signed",
+		name: "Store Pair (signed offset)",
+		description: "Stores the contents of two general-purpose registers at the address specified by the third register, with a signed immediate offset added.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 1"}, {type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 2"}, {type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Address Register"}, {type: "immediate", name: "Address Offset"}],
+		bitsize: 32,
+		mc_constructor: [
+			# Check for register sizes
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "stp Error: Register sizes are not the same"]],
+			# Establish the immediate offset alignment using the register size
+			["set_var", "imm_alignment", ["case", ["get_key", ["get_operand", 0], :reg_size], 32, 4, 64, 8, 0]],
+			# Check if the immediate offset is properly aligned
+			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "stp Error: The immediate offset is not properly aligned"]],
+
+			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 2], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 1], :reg_value], 0, 5],
+			["get_bits", ["divide", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, 7], # imm7
+			["bits", 0, 0,1,0, 0, 1,0,1, 0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []] # opc
+		]
+	},
+	{
+		keyword: "stp_pre_index",
+		name: "Store Pair (pre-index, signed offset)",
+		description: "Stores the contents of two general-purpose registers at the address specified by the third register, with a permanent signed immediate offset added before writing.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 1"}, {type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 2"}, {type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Address Register"}, {type: "immediate", name: "Address Offset"}],
+		bitsize: 32,
+		mc_constructor: [
+			# Check for register sizes
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "stp Error: Register sizes are not the same"]],
+			# Establish the immediate offset alignment using the register size
+			["set_var", "imm_alignment", ["case", ["get_key", ["get_operand", 0], :reg_size], 32, 4, 64, 8, 0]],
+			# Check if the immediate offset is properly aligned
+			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "stp Error: The immediate offset is not properly aligned"]],
+	
+			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 2], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 1], :reg_value], 0, 5],
+			["get_bits", ["divide", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, 7], # imm7
+			["bits", 0, 1,1,0, 0, 1,0,1, 0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []] # opc
+		]
+	},
+	{
+		keyword: "stp_post_index",
+		name: "Store Pair (post-index, signed offset)",
+		description: "Stores the contents of two general-purpose registers at the address specified by the third register, with a permanent signed immediate offset added after writing.",
+		operands: [{type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 1"}, {type: "register", restrictions: {reg_type: "gpr"}, name: "Content Register 2"}, {type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Address Register"}, {type: "immediate", name: "Address Offset"}],
+		bitsize: 32,
+		mc_constructor: [
+			# Check for register sizes
+			["if_eq_else", ["get_key", ["get_operand", 0], :reg_size], ["get_key", ["get_operand", 1], :reg_size], [], ["raise_error", "stp Error: Register sizes are not the same"]],
+			# Establish the immediate offset alignment using the register size
+			["set_var", "imm_alignment", ["case", ["get_key", ["get_operand", 0], :reg_size], 32, 4, 64, 8, 0]],
+			# Check if the immediate offset is properly aligned
+			["if_eq_else", ["modulo", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, [], ["raise_error", "stp Error: The immediate offset is not properly aligned"]],
+	
+			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 2], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_operand", 1], :reg_value], 0, 5],
+			["get_bits", ["divide", ["get_operand", 3], ["get_var", "imm_alignment"]], 0, 7], # imm7
+			["bits", 0, 1,0,0, 0, 1,0,1, 0],
+			["case", ["get_key", ["get_operand", 0], :reg_size], 64, ["bits", 1], 32, ["bits", 0], []] # opc
+		]
+	},
+	
 		
 	{
 		keyword: "cmp",

data/lib/kompiler/architectures/armv8a/load.rb

@@ -2,7 +2,9 @@
 # Licensed under the Apache License, Version 2.0. See LICENSE file for details.
 
 require 'kompiler/architectures/armv8a/instructions.rb'
+require 'kompiler/architectures/armv8a/sys_instructions.rb'
 require 'kompiler/architectures/armv8a/registers.rb'
+require 'kompiler/architectures/armv8a/sys_registers.rb'
 
 
-Kompiler::Architecture.set_arch(Kompiler::ARMv8A.instructions, Kompiler::ARMv8A.registers)
+Kompiler::Architecture.set_arch(Kompiler::ARMv8A.instructions + Kompiler::ARMv8A.sys_instructions, Kompiler::ARMv8A.registers + Kompiler::ARMv8A.sys_registers)

data/lib/kompiler/architectures/armv8a/registers.rb

@@ -3,13 +3,13 @@
 
 module Kompiler
 
-class ARMv8A
+module ARMv8A
 
 def self.registers
-	@@registers
+	@registers
 end	
 
-@@registers = [
+@registers = [
 	{:reg_name=>"w0", :reg_value=>0, :reg_size=>32, :reg_type=>"gpr"},
 	{:reg_name=>"w1", :reg_value=>1, :reg_size=>32, :reg_type=>"gpr"},
 	{:reg_name=>"w2", :reg_value=>2, :reg_size=>32, :reg_type=>"gpr"},
@@ -26,6 +26,22 @@ end
 	{:reg_name=>"w13", :reg_value=>13, :reg_size=>32, :reg_type=>"gpr"},
 	{:reg_name=>"w14", :reg_value=>14, :reg_size=>32, :reg_type=>"gpr"},
 	{:reg_name=>"w15", :reg_value=>15, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w16", :reg_value=>16, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w17", :reg_value=>17, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w18", :reg_value=>18, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w19", :reg_value=>19, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w20", :reg_value=>20, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w21", :reg_value=>21, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w22", :reg_value=>22, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w23", :reg_value=>23, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w24", :reg_value=>24, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w25", :reg_value=>25, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w26", :reg_value=>26, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w27", :reg_value=>27, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w28", :reg_value=>28, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w29", :reg_value=>29, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w30", :reg_value=>30, :reg_size=>32, :reg_type=>"gpr"},
+	{:reg_name=>"w31", :reg_value=>31, :reg_size=>32, :reg_type=>"gpr"},
 	{:reg_name=>"x0", :reg_value=>0, :reg_size=>64, :reg_type=>"gpr"},
 	{:reg_name=>"x1", :reg_value=>1, :reg_size=>64, :reg_type=>"gpr"},
 	{:reg_name=>"x2", :reg_value=>2, :reg_size=>64, :reg_type=>"gpr"},

data/lib/kompiler/architectures/armv8a/sys_instructions.rb

@@ -0,0 +1,97 @@
+# Copyright 2024 Kyrylo Shyshko
+# Licensed under the Apache License, Version 2.0. See LICENSE file for details.
+
+module Kompiler
+
+module ARMv8A
+	
+def self.sys_instructions
+	@sys_instructions
+end
+	
+@sys_instructions = [
+	{
+		keyword: "mrs",
+		name: "Move from system register",
+		description: "Moves the contents of a system register to a 64-bit general-purpose register",
+		operands: [{type: "register", restrictions: {reg_type: "gpr", reg_size: 64}, name: "Destination general-purpose register"}, {type: "register", restrictions: {reg_type: "sr"}, name: "Source system register"}],
+		mc_constructor: [
+			["set_var", "sr_encoding", ["get_key", ["get_operand", 1], :reg_encoding]],
+			["get_bits", ["get_key", ["get_operand", 0], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_var", "sr_encoding"], "op2"], 0, 3],
+			["get_bits", ["get_key", ["get_var", "sr_encoding"], "CRm"], 0, 4],
+			["get_bits", ["get_key", ["get_var", "sr_encoding"], "CRn"], 0, 4],
+			["get_bits", ["get_key", ["get_var", "sr_encoding"], "op1"], 0, 3],
+			["get_bits", ["get_key", ["get_var", "sr_encoding"], "op0"], 0, 2],
+			["bits", 1], # L
+			["bits", 0,0,1,0,1,0,1,0,1,1]
+		],
+		bitsize: 32
+	},
+	{
+		keyword: "msr",
+		name: "Move general-purpose register to system register",
+		description: "Writes the contents of a general-purpose register to a system register",
+		operands: [{type: "register", restrictions: {reg_type: "sr"}, name: "Destination system register"}, {type: "register", restrictions: {reg_type: "gpr"}, name: "Source general-purpose register"}],
+		mc_constructor: [
+			["set_var", "sr_encoding", ["get_key", ["get_operand", 0], :reg_encoding]],
+			["get_bits", ["get_key", ["get_operand", 1], :reg_value], 0, 5],
+			["get_bits", ["get_key", ["get_var", "sr_encoding"], "op2"], 0, 3],
+			["get_bits", ["get_key", ["get_var", "sr_encoding"], "CRm"], 0, 4],
+			["get_bits", ["get_key", ["get_var", "sr_encoding"], "CRn"], 0, 4],
+			["get_bits", ["get_key", ["get_var", "sr_encoding"], "op1"], 0, 3],
+			["get_bits", ["get_key", ["get_var", "sr_encoding"], "op0"], 0, 2],
+			["bits", 0], # L
+			["bits", 0,0,1,0,1,0,1,0,1,1]
+		],
+		bitsize: 32
+	},
+	{
+		keyword: "msr",
+		name: "Move immediate value to special register",
+		description: "Moves an immediate value to selected bits of the PSTATE",
+		operands: [{type: "register", name: "Destination system register"}, {type: "immediate", name: "Immediate value"}],
+		mc_constructor: [
+			# Case for PSTATE special register encodings
+			["case", ["downcase_str", ["get_key", ["get_operand_hash", 0], :definition]],
+				"spsel", 	["concat", ["set_var", "op1", 0b000], ["set_var", "op2", 0b101]],
+				"daifset", 	["concat", ["set_var", "op1", 0b011], ["set_var", "op2", 0b110]],
+				"daifclr",	["concat", ["set_var", "op1", 0b011], ["set_var", "op2", 0b111]],
+				"uao", 		["concat", ["set_var", "op1", 0b000], ["set_var", "op2", 0b011]],
+				"pan", 		["concat", ["set_var", "op1", 0b000], ["set_var", "op2", 0b100]],
+				"allint", 	["concat", ["set_var", "op1", 0b001], ["set_var", "op2", 0b000], ["if_eq_else", ["bit_and", ["get_operand", 1], 0b001], ["get_operand", 1], [], ["raise_warning", "msr ALLINT Warning: The immediate value is not valid for the instruction - Continuing build."]] ],
+				"pm", 		["concat", ["set_var", "op1", 0b001], ["set_var", "op2", 0b000], ["if_eq_else", ["bit_and", ["get_operand", 1], 0b011], ["get_operand", 1], [], ["raise_warning", "msr PM Warning: The immediate value is not valid for the instruction - Continuing build."]]],
+				"ssbs", 	["concat", ["set_var", "op1", 0b011], ["set_var", "op2", 0b001]],
+				"dit", 		["concat", ["set_var", "op1", 0b011], ["set_var", "op2", 0b010]],
+				"svcrsm",	["concat", ["set_var", "op1", 0b011], ["set_var", "op2", 0b011], ["if_eq_else", ["bit_and", ["get_operand", 1], 0b0011], ["get_operand", 1], [], ["raise_warning", "msr SVCRSM Warning: The immediate value is not valid for the instruction - Continuing build."]]],
+				"svcrza", 	["concat", ["set_var", "op1", 0b011], ["set_var", "op2", 0b011], ["if_eq_else", ["bit_and", ["get_operand", 1], 0b0101], ["get_operand", 1], [], ["raise_warning", "msr SVCRZA Warning: The immediate value is not valid for the instruction - Continuing build."]]],
+				"svcrsmza", ["concat", ["set_var", "op1", 0b011], ["set_var", "op2", 0b011], ["if_eq_else", ["bit_and", ["get_operand", 1], 0b0111], ["get_operand", 1], [], ["raise_warning", "msr SVCRSMZA Warning: The immediate value is not valid for the instruction - Continuing build."]]],
+				"tco", 		["concat", ["set_var", "op1", 0b011], ["set_var", "op2", 0b100]],
+				["raise_error", "msr Error: The specified PSTATE special register was not found - Program build not possible."]
+			],
+			["bits", 1,1,1,1,1],
+			["get_bits", ["get_var", "op2"], 0, 3],
+			["get_bits", ["get_operand", 1], 0, 4],
+			["bits", 0,0,1,0],
+			["get_bits", ["get_var", "op1"], 0, 3],
+			["bits", 0,0, 0, 0,0,1,0,1,0,1,0,1,1],
+		],
+		bitsize: 32
+	},
+	
+	
+	{
+		keyword: "eret",
+		name: "Exception Return",
+		description: "Restores PSTATE from SPSR, and branches to the address held in ELR. ",
+		operands: [],
+		mc_constructor: [
+			["bits", 0,0,0,0,0, 1,1,1,1,1, 0, 0, 0,0,0,0, 1,1,1,1,1, 0,0,1, 0, 1,1,0,1,0,1,1],
+		],
+		bitsize: 32
+	},
+]
+
+end # Kompiler::ARMv8A
+
+end # Kompiler

data/lib/kompiler/architectures/armv8a/sys_registers.rb

@@ -0,0 +1,39 @@
+# Copyright 2024 Kyrylo Shyshko
+# Licensed under the Apache License, Version 2.0. See LICENSE file for details.
+
+module Kompiler
+
+module ARMv8A
+
+def self.sys_registers
+	@sys_registers
+end	
+
+@sys_registers = [
+	{reg_name: "mpidr_el0", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>3, "op1"=>0, "CRn"=>0, "CRm"=>0, "op2"=>5}, rw_type: "ro"},
+	
+	{reg_name: "vbar_el1", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0, "CRn"=>0b1100, "CRm"=>0, "op2"=>0}, rw_type: "rw"},
+	{reg_name: "vbar_el12", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b101, "CRn"=>0b1100, "CRm"=>0, "op2"=>0}, rw_type: "rw"},
+	{reg_name: "vbar_el2", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b100, "CRn"=>0b1100, "CRm"=>0, "op2"=>0}, rw_type: "rw"},
+	{reg_name: "vbar_el3", reg_size: 64, reg_type: "sr", reg_encoding: {"op0"=>0b11, "op1"=>0b110, "CRn"=>0b1100, "CRm"=>0, "op2"=>0}, rw_type: "rw"},
+
+	
+	# Special registers for the MSR (immediate) instruction (some of them were previously defined already)
+	{reg_name: "SPSel", reg_type: "pstate_reg"},
+	{reg_name: "DAIFSet", reg_type: "pstate_reg"},
+	{reg_name: "DAIFClr", reg_type: "pstate_reg"},
+	{reg_name: "UAO", reg_type: "pstate_reg"},
+	{reg_name: "PAN", reg_type: "pstate_reg"},
+	{reg_name: "ALLINT", reg_type: "pstate_reg"},
+	{reg_name: "PM", reg_type: "pstate_reg"},
+	{reg_name: "SSBS", reg_type: "pstate_reg"},
+	{reg_name: "DIT", reg_type: "pstate_reg"},
+	{reg_name: "SVCRSM", reg_type: "pstate_reg"},
+	{reg_name: "SVCRZA", reg_type: "pstate_reg"},
+	{reg_name: "SVCRSMZA", reg_type: "pstate_reg"},
+	{reg_name: "TCO", reg_type: "pstate_reg"},
+]
+
+end # Kompiler::ARMv8A
+
+end # Kompiler

data/lib/kompiler/compiler_functions.rb

@@ -168,7 +168,7 @@ def self.construct_program_mc(parsed_lines, labels)
 	lines_bytes = ""
 	
 	
-	program_state = {labels: labels, current_address: 0}
+	program_state = {labels: labels, current_address: 0, instruction_variables: {}}
 	
 	parsed_lines.each do |line|
 		case line[:type]
@@ -179,6 +179,7 @@ def self.construct_program_mc(parsed_lines, labels)
 			mc_constructor = line[:instruction][:mc_constructor]
 			
 			instr_bits = Kompiler::MachineCode_AST.build_mc(mc_constructor, program_state)			
+			program_state[:instruction_variables] = Hash.new # Clear the instruction variables after running the instruction
 
 			instr_bytes = bits_to_bytes(instr_bits)
 			
@@ -259,4 +260,4 @@ end
 
 end # Kompiler::CompilerFunctions
 
-end # Kompiler
+end # Kompiler

data/lib/kompiler/directives.rb

@@ -3,13 +3,13 @@
 
 module Kompiler
 
-class Directives
+module Directives
 
 def self.directives
-	@@DIRECTIVES
+	@directives
 end
 
-@@DIRECTIVES = [
+@directives = [
 	{
 		keyword: "zeros",
 		func: lambda do |operands, state|

data/lib/kompiler/mc_builder.rb

@@ -3,10 +3,11 @@
 
 module Kompiler
 
-class MachineCode_AST
+module MachineCode_AST
 
-MC_AST_NODES = [
+@MC_AST_NODES = [
 	{name: "get_operand", n_args: 1, func: lambda {|args, state| state[:operands][args[0]][:value]} },
+	{name: "get_operand_hash", n_args: 1, func: lambda {|args, state| state[:operands][args[0]] } },
 	{name: "get_bits", n_args: 3, func: lambda {|args, state| (args[1]...(args[1] + args[2])).map{|bit_i| args[0][bit_i]} } },
 	{name: "get_bits_signed", n_args: 3, func: lambda do |args, state|
 		if args[1] == 0
@@ -38,9 +39,21 @@ MC_AST_NODES = [
 		end
 		eval_mc_node_arg(args.last, state)
 	end},
-	{name: "raise_error", n_args: 1, func: lambda {|args, state| raise args[0] } },
-	{name: "get_key", n_args: 2, func: lambda {|args, state| args[0][args[1]] }},
+	
+	{name: "raise_error", n_args: 1, func: lambda {|args, state| raise args[0]; [] } },
+	{name: "raise_warning", n_args: 1, func: lambda {|args, state| puts args[0]; [] } },
+	
+	{name: "get_key", n_args: 2, func: lambda {|args, state| args[0].keys.include?(args[1]) ? args[0][args[1]] : raise("MC Constructor get_key Error: The key \"#{args[1]}\" doesn't exist - Program build not possible. This is likely a problem with the ISA configuration, not the program being compiled.") }},
 	{name: "concat", n_args: "any", func: lambda {|args, state| args.flatten}},
+	{name: "set_var", n_args: 2, func: lambda {|args, state| state[:instruction_variables][args[0]] = args[1]; [] }},
+	{name: "get_var", n_args: 1, func: lambda {|args, state| state[:instruction_variables].keys.include?(args[0]) ? state[:instruction_variables][args[0]] : raise("Instruction variable \"#{args[0]}\" not found: Program build not possible. This is likely a program with the ISA configuration, not the program being compiled.") }},
+	
+	# String manipulations
+	{name: "downcase_str", n_args: 1, func: lambda {|args, state| args[0].downcase }},
+	
+	# Bit manipulations
+	{name: "bit_and", n_args: 2, func: lambda {|args, state| args[0] & args[1] }},
+	{name: "bit_or", n_args: 2, func: lambda {|args, state| args[0] | args[1] }},
 ]
 
 def self.is_ast_node(val)
@@ -57,7 +70,8 @@ def self.run_mc_ast(node, state)
 	node_name = node[0]
 	node_args = node[1..]
 	
-	node_logic = MC_AST_NODES.filter{|any_node| any_node[:name] == node_name}[0]
+	
+	node_logic = @MC_AST_NODES.filter{|any_node| any_node[:name] == node_name}[0]
 	
 	if !node_logic
 		raise "MC Node \"#{node_name}\" wasn't found. Cannot build the program"
@@ -97,4 +111,4 @@ end
 
 end # Kompiler::MC_AST
 
-end # Kompiler
+end # Kompiler

data/lib/kompiler/parsers.rb

@@ -86,7 +86,10 @@ end
 
 def self.check_register_operand(str)
 	Kompiler::Architecture.registers.each do |register|
-		return [true, register] if str == register[:reg_name]
+		# Downcase both the string and the register if the register name is not case sensitive (the default)
+		processed_str = register[:case_sensitive] ? str : str.downcase
+		processed_reg_name = register[:case_sensitive] ? register[:reg_name] : register[:reg_name].downcase
+		return [true, register] if processed_str == processed_reg_name
 	end
 	return [false, nil]
 end
@@ -172,16 +175,16 @@ end
 def self.check_immediate_operand(operand_str)
 	
 	is_bin, bin_value = check_binary_operand(operand_str)
-	return [true, {type: "immediate", value: bin_value, def_type: "binary"}] if is_bin
+	return [true, {type: "immediate", value: bin_value, def_type: "binary", definition: operand_str}] if is_bin
 	
 	is_decimal, decimal_value = check_decimal_operand(operand_str)
-	return [true, {type: "immediate", value: decimal_value, def_type: "decimal"}] if is_decimal
+	return [true, {type: "immediate", value: decimal_value, def_type: "decimal", definition: operand_str}] if is_decimal
 	
 	is_hex, hex_value = check_hex_operand(operand_str)
-	return [true, {type: "immediate", value: hex_value, def_type: "hex"}] if is_hex
+	return [true, {type: "immediate", value: hex_value, def_type: "hex", definition: operand_str}] if is_hex
 	
 	is_char, char_value = check_char_operand(operand_str)
-	return [true, {type: "immediate", value: char_value, def_type: "char"}] if is_char
+	return [true, {type: "immediate", value: char_value, def_type: "char", definition: operand_str}] if is_char
 	
 	return [false, nil]
 end
@@ -208,11 +211,11 @@ def self.parse_operand_str(operand_str)
 	
 	# Check if the operand is a register
 	is_register, register = check_register_operand(operand_str)
-	return {type: "register", value: register, register: register} if is_register
+	return {type: "register", value: register, register: register, definition: operand_str} if is_register
 	
 	# Check if the operand is a string
 	is_string = operand_str[0] == "\""
-	return {type: "string", value: operand_str[1...-1], string: operand_str[1...-1]} if is_string
+	return {type: "string", value: operand_str[1...-1], string: operand_str[1...-1], definition: operand_str} if is_string
 	
 	# Checks if it's an immediate
 	is_immediate, immediate_val = check_immediate_operand(operand_str)
@@ -225,7 +228,7 @@ def self.parse_operand_str(operand_str)
 	
 	# The operand is a label if it doesn't start with a number and doesn't include spaces
 	is_label = check_label_operand(operand_str)
-	return {type: "label", value: operand_str} if is_label
+	return {type: "label", value: operand_str, definition: operand_str} if is_label
 	
 	
 	# If no checks succeeded, return false
@@ -319,128 +322,37 @@ end
 
 
 
-
-
-# def self.parse_instruction_line(line)
-# 	keyword = ""
-# 	i = 0
-# 	
-# 	# Loop until a non-whitespace character
-# 	while i < line.size
-# 		break if ![" ", "\t"].include?(line[i])
-# 		i += 1
-# 	end
-# 
-# 	# Loop to get the keyword
-# 	loop do
-# 		# Exit out of the loop if the character is a whitespace
-# 		break if [" ", "\t"].include?(line[i]) || i >= line.size
-# 		# Add the character if not a whitespace
-# 		keyword << line[i]
-# 		# Proceed to the next character
-# 		i += 1	
-# 	end
-# 
-# 	operand_strings = []
-# 	
-# 	# Loop for operands
-# 	loop do
-# 		break if i >= line.size
-# 
-# 		# Whitespace - skip
-# 		if [" ", "\t"].include? line[i]
-# 			i += 1
-# 			next
-# 		end
-# 
-# 		# If a string operand - parse the string
-# 		if line[i] == "\""
-# 
-# 			str_content, parsed_size = parse_str(line[i..])
-# 			operand_strings << line[i...(i + parsed_size)]
-# 			i += parsed_size
-# 
-# 		# If anything else - parse until whitespace, comma or end of line
-# 		else
-# 			content = ""
-# 
-# 			while i < line.size
-# 				break if [" ", ","].include? line[i]
-# 				content << line[i]
-# 				i += 1
-# 			end
-# 			
-# 			operand_strings << content
-# 		end
-# 
-# 
-# 		# After operand parsed
-# 		# Loop to meet a comma or end of line
-# 		# Give error if stuff except whitespace
-# 
-# 		while i < line.size
-# 			# If comma, move to next character and repeat the bigger operand loop
-# 			if line[i] == ","
-# 				i += 1
-# 				break
-# 			end
-# 			# If non-whitespace, raise an error
-# 			# raise "Error: Unparsed content - exiting" if ![" ", "\t"].include?(line[i])
-# 			return false if ![" ", "\t"].include?(line[i])
-# 			i += 1
-# 		end
-# 	end
-# 	
-# 	# If end of line not reached, return an error
-# 	if i != line.size
-# 		return false
-# 	end
-# 
-# 	
-# 	# Parse operand strings into operand types and values
-# 	
-# 	operands = []
-# 	
-# 	operand_strings.each do |operand_str|
-# 		operand = parse_operand_str(operand_str)
-# 		return false if operand == false
-# 		operands << operand
-# 	end
-# 	
-# 	return [keyword, operands]
-# end
-
-
-
 def self.check_operand_match(operand_description, operand)
 
 	# If operand type doesn't not match, return false
 	return false if operand[:type] != operand_description[:type]
 
-	# If no operand restrictions, return true
-	return true if !operand_description.keys.include?(:restrictions)
+	# Get the restrictions
+	operand_restrictions = operand_description[:restrictions]
+	return true if !operand_restrictions # If no restrictions, return true
 
-	case operand_description[:type]
+	# Get the operand's values / encoding
+	case operand[:type]
 	when "register"
-	
-		# Check register type match
-		if operand_description[:restrictions].keys.include?(:reg_type)
-			return false if operand[:register][:reg_type] != operand_description[:restrictions][:reg_type]
-		end
-	
-		# Check register size match
-		if operand_description[:restrictions].keys.include?(:reg_size)
-			return false if operand[:register][:reg_size] != operand_description[:restrictions][:reg_size]
-		end
-		
+		operand_encoding = operand[:value]
 	when "immediate"
-		
-		
-		
-	when "label"
-		
-		
-		
+		operand_encoding = operand[:value]
+	when "string"
+		operand_encoding = Hash.new
+	end
+
+	# Loop through each restriction to see if the operand matches it
+	operand_restrictions.each do |r_key, r_spec|
+		# Get the restricted value of the operand
+		op_value = operand_encoding[r_key]
+
+		# Check if it matches the restriction specification
+		# If an array, the OR algorithm works (the operand key value must be one of the specified values in the r_spec list)
+		if r_spec.is_a? Array
+			return false if !r_spec.include?(op_value)
+		else # If not an array, just check of equality
+			return false if op_value != r_spec
+		end
 	end
 	
 	
@@ -448,6 +360,9 @@ def self.check_operand_match(operand_description, operand)
 	return true
 end
 
+ 
+
+
 
 # Returns array of [status, operands]
 # If status = false, operands = nil; otherwise, status = true, operands = instruction operands
@@ -531,4 +446,4 @@ end
 end # End Kompiler::Parsers
 
 
-end # End Kompiler
+end # End Kompiler

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: kompiler
 version: !ruby/object:Gem::Version
-  version: 0.2.0
+  version: 0.3.0.pre.1
 platform: ruby
 authors:
 - Kyryl Shyshko
 autorequire:
 bindir: bin
 cert_chain: []
-date: 2024-12-04 00:00:00.000000000 Z
+date: 2024-12-13 00:00:00.000000000 Z
 dependencies: []
 description: 'Kompiler is a low-level, modular and extendable compiler for any architecture.
   By default Kompiler supports ARMv8-a, but other architecture extensions can be downloaded
@@ -30,6 +30,8 @@ files:
 - lib/kompiler/architectures/armv8a/instructions.rb
 - lib/kompiler/architectures/armv8a/load.rb
 - lib/kompiler/architectures/armv8a/registers.rb
+- lib/kompiler/architectures/armv8a/sys_instructions.rb
+- lib/kompiler/architectures/armv8a/sys_registers.rb
 - lib/kompiler/compiler_functions.rb
 - lib/kompiler/directives.rb
 - lib/kompiler/mc_builder.rb