johnson 2.0.0.pre0 → 2.0.0.pre1

data/vendor/tracemonkey/nanojit/NativeX64.h

@@ -0,0 +1,392 @@
+/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: nil; tab-width: 4 -*- */
+/* vi: set ts=4 sw=4 expandtab: (add to ~/.vimrc: set modeline modelines=5) */
+/* ***** BEGIN LICENSE BLOCK *****
+ * Version: MPL 1.1/GPL 2.0/LGPL 2.1
+ *
+ * The contents of this file are subject to the Mozilla Public License Version
+ * 1.1 (the "License"); you may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at
+ * http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS" basis,
+ * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
+ * for the specific language governing rights and limitations under the
+ * License.
+ *
+ * The Original Code is [Open Source Virtual Machine].
+ *
+ * The Initial Developer of the Original Code is
+ * Adobe System Incorporated.
+ * Portions created by the Initial Developer are Copyright (C) 2008
+ * the Initial Developer. All Rights Reserved.
+ *
+ * Contributor(s):
+ *   Adobe AS3 Team
+ *
+ * Alternatively, the contents of this file may be used under the terms of
+ * either the GNU General Public License Version 2 or later (the "GPL"), or
+ * the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
+ * in which case the provisions of the GPL or the LGPL are applicable instead
+ * of those above. If you wish to allow use of your version of this file only
+ * under the terms of either the GPL or the LGPL, and not to allow others to
+ * use your version of this file under the terms of the MPL, indicate your
+ * decision by deleting the provisions above and replace them with the notice
+ * and other provisions required by the GPL or the LGPL. If you do not delete
+ * the provisions above, a recipient may use your version of this file under
+ * the terms of any one of the MPL, the GPL or the LGPL.
+ *
+ * ***** END LICENSE BLOCK ***** */
+
+#ifndef __nanojit_NativeX64__
+#define __nanojit_NativeX64__
+
+#ifndef NANOJIT_64BIT
+#error "NANOJIT_64BIT must be defined for X64 backend"
+#endif
+
+#ifdef PERFM
+#define DOPROF
+#include "../vprof/vprof.h"
+#define count_instr() _nvprof("x64",1)
+#define count_prolog() _nvprof("x64-prolog",1); count_instr();
+#define count_imt() _nvprof("x64-imt",1) count_instr()
+#else
+#define count_instr()
+#define count_prolog()
+#define count_imt()
+#endif
+
+namespace nanojit
+{
+#define NJ_MAX_STACK_ENTRY              256
+#define NJ_ALIGN_STACK                  16
+
+    enum Register {
+        RAX = 0, // 1st int return, # of sse varargs
+        RCX = 1, // 4th int arg
+        RDX = 2, // 3rd int arg 2nd return
+        RBX = 3, // saved
+        RSP = 4, // stack ptr
+        RBP = 5, // frame ptr, saved, sib reqd
+        RSI = 6, // 2nd int arg
+        RDI = 7, // 1st int arg
+        R8  = 8, // 5th int arg
+        R9  = 9, // 6th int arg
+        R10 = 10, // scratch
+        R11 = 11, // scratch
+        R12 = 12, // saved
+        R13 = 13, // saved, sib reqd like rbp
+        R14 = 14, // saved
+        R15 = 15, // saved
+
+        XMM0  = 16, // 1st double arg, return
+        XMM1  = 17, // 2nd double arg, return
+        XMM2  = 18, // 3rd double arg
+        XMM3  = 19, // 4th double arg
+        XMM4  = 20, // 5th double arg
+        XMM5  = 21, // 6th double arg
+        XMM6  = 22, // 7th double arg
+        XMM7  = 23, // 8th double arg
+        XMM8  = 24, // scratch
+        XMM9  = 25, // scratch
+        XMM10 = 26, // scratch
+        XMM11 = 27, // scratch
+        XMM12 = 28, // scratch
+        XMM13 = 29, // scratch
+        XMM14 = 30, // scratch
+        XMM15 = 31, // scratch
+
+        FP = RBP,
+        UnknownReg = 32,
+        FirstReg = RAX,
+        LastReg = XMM15
+    };
+
+/*
+ * Micro-templating variable-length opcodes, idea first
+ * describe by Mike Pall of Luajit.
+ *
+ * X86-64 opcode encodings:  LSB encodes the length of the
+ * opcode in bytes, remaining bytes are encoded as 1-7 bytes
+ * in a single uint64_t value.  The value is written as a single
+ * store into the code stream, and the code pointer is decremented
+ * by the length.  each successive instruction partially overlaps
+ * the previous one.
+ *
+ * emit methods below are able to encode mod/rm, sib, rex, and
+ * register and small immediate values into these opcode values
+ * without much branchy code.
+ *
+ * these opcodes encapsulate all the const parts of the instruction.
+ * for example, the alu-immediate opcodes (add, sub, etc) encode
+ * part of their opcode in the R field of the mod/rm byte;  this
+ * hardcoded value is in the constant below, and the R argument
+ * to emitrr() is 0.  In a few cases, a whole instruction is encoded
+ * this way (eg callrax).
+ *
+ * when a disp32, imm32, or imm64 suffix can't fit in an 8-byte
+ * opcode, then it is written into the code separately and not counted
+ * in the opcode length.
+ */
+
+    enum X64Opcode
+#if defined(_MSC_VER) && _MSC_VER >= 1400
+#pragma warning(disable:4480) // nonstandard extension used: specifying underlying type for enum
+          : uint64_t
+#endif
+    {
+        // 64bit opcode constants
+        //              msb        lsb len
+        X64_addqrr  = 0xC003480000000003LL, // 64bit add r += b
+        X64_addqri  = 0xC081480000000003LL, // 64bit add r += int64(imm32)
+        X64_addqr8  = 0x00C0834800000004LL, // 64bit add r += int64(imm8)
+        X64_andqri  = 0xE081480000000003LL, // 64bit and r &= int64(imm32)
+        X64_andqr8  = 0x00E0834800000004LL, // 64bit and r &= int64(imm8)
+        X64_orqri   = 0xC881480000000003LL, // 64bit or  r |= int64(imm32)
+        X64_orqr8   = 0x00C8834800000004LL, // 64bit or  r |= int64(imm8)
+        X64_xorqri  = 0xF081480000000003LL, // 64bit xor r ^= int64(imm32)
+        X64_xorqr8  = 0x00F0834800000004LL, // 64bit xor r ^= int64(imm8)
+        X64_addlri  = 0xC081400000000003LL, // 32bit add r += imm32
+        X64_addlr8  = 0x00C0834000000004LL, // 32bit add r += imm8
+        X64_andlri  = 0xE081400000000003LL, // 32bit and r &= imm32
+        X64_andlr8  = 0x00E0834000000004LL, // 32bit and r &= imm8
+        X64_orlri   = 0xC881400000000003LL, // 32bit or  r |= imm32
+        X64_orlr8   = 0x00C8834000000004LL, // 32bit or  r |= imm8
+        X64_sublri  = 0xE881400000000003LL, // 32bit sub r -= imm32
+        X64_sublr8  = 0x00E8834000000004LL, // 32bit sub r -= imm8
+        X64_xorlri  = 0xF081400000000003LL, // 32bit xor r ^= imm32
+        X64_xorlr8  = 0x00F0834000000004LL, // 32bit xor r ^= imm8
+        X64_addrr   = 0xC003400000000003LL, // 32bit add r += b
+        X64_andqrr  = 0xC023480000000003LL, // 64bit and r &= b
+        X64_andrr   = 0xC023400000000003LL, // 32bit and r &= b
+        X64_call    = 0x00000000E8000005LL, // near call
+        X64_callrax = 0xD0FF000000000002LL, // indirect call to addr in rax (no REX)
+        X64_cmovqno = 0xC0410F4800000004LL, // 64bit conditional mov if (no overflow) r = b
+        X64_cmovqb  = 0xC0420F4800000004LL, // 64bit conditional mov if (uint <) r = b
+        X64_cmovqae = 0xC0430F4800000004LL, // 64bit conditional mov if (uint >=) r = b
+        X64_cmovqne = 0xC0450F4800000004LL, // 64bit conditional mov if (c) r = b
+        X64_cmovqbe = 0xC0460F4800000004LL, // 64bit conditional mov if (uint <=) r = b
+        X64_cmovqa  = 0xC0470F4800000004LL, // 64bit conditional mov if (uint >) r = b
+        X64_cmovql  = 0xC04C0F4800000004LL, // 64bit conditional mov if (int <) r = b
+        X64_cmovqge = 0xC04D0F4800000004LL, // 64bit conditional mov if (int >=) r = b
+        X64_cmovqle = 0xC04E0F4800000004LL, // 64bit conditional mov if (int <=) r = b
+        X64_cmovqg  = 0xC04F0F4800000004LL, // 64bit conditional mov if (int >) r = b
+        X64_cmovno  = 0xC0410F4000000004LL, // 32bit conditional mov if (no overflow) r = b
+        X64_cmovb   = 0xC0420F4000000004LL, // 32bit conditional mov if (uint <) r = b
+        X64_cmovae  = 0xC0430F4000000004LL, // 32bit conditional mov if (uint >=) r = b
+        X64_cmovne  = 0xC0450F4000000004LL, // 32bit conditional mov if (c) r = b
+        X64_cmovbe  = 0xC0460F4000000004LL, // 32bit conditional mov if (uint <=) r = b
+        X64_cmova   = 0xC0470F4000000004LL, // 32bit conditional mov if (uint >) r = b
+        X64_cmovl   = 0xC04C0F4000000004LL, // 32bit conditional mov if (int <) r = b
+        X64_cmovge  = 0xC04D0F4000000004LL, // 32bit conditional mov if (int >=) r = b
+        X64_cmovle  = 0xC04E0F4000000004LL, // 32bit conditional mov if (int <=) r = b
+        X64_cmovg   = 0xC04F0F4000000004LL, // 32bit conditional mov if (int >) r = b
+        X64_cmov_64 = 0x0000000800000000LL, // OR with 32-bit cmov to promote to 64-bit
+        X64_cmplr   = 0xC03B400000000003LL, // 32bit compare r,b
+        X64_cmpqr   = 0xC03B480000000003LL, // 64bit compare r,b
+        X64_cmplri  = 0xF881400000000003LL, // 32bit compare r,imm32
+        X64_cmpqri  = 0xF881480000000003LL, // 64bit compare r,int64(imm32)
+        X64_cmplr8  = 0x00F8834000000004LL, // 32bit compare r,imm8
+        X64_cmpqr8  = 0x00F8834800000004LL, // 64bit compare r,int64(imm8)
+        X64_cvtsi2sd= 0xC02A0F40F2000005LL, // convert int32 to double r = (double) b
+        X64_cvtsq2sd= 0xC02A0F48F2000005LL, // convert int64 to double r = (double) b
+        X64_divsd   = 0xC05E0F40F2000005LL, // divide scalar double r /= b
+        X64_mulsd   = 0xC0590F40F2000005LL, // multiply scalar double r *= b
+        X64_addsd   = 0xC0580F40F2000005LL, // add scalar double r += b
+        X64_idiv    = 0xF8F7400000000003LL, // 32bit signed div (rax = rdx:rax/r, rdx=rdx:rax%r)
+        X64_imul    = 0xC0AF0F4000000004LL, // 32bit signed mul r *= b
+        X64_imuli   = 0xC069400000000003LL, // 32bit signed mul r = b * imm32
+        X64_imul8   = 0x00C06B4000000004LL, // 32bit signed mul r = b * imm8
+        X64_jmp     = 0x00000000E9000005LL, // jump near rel32
+        X64_jmp8    = 0x00EB000000000002LL, // jump near rel8
+        X64_jo      = 0x00000000800F0006LL, // jump near if overflow
+        X64_jb      = 0x00000000820F0006LL, // jump near if below (uint <)
+        X64_jae     = 0x00000000830F0006LL, // jump near if above or equal (uint >=)
+        X64_ja      = 0x00000000870F0006LL, // jump near if above (uint >)
+        X64_jbe     = 0x00000000860F0006LL, // jump near if below or equal (uint <=)
+        X64_je      = 0x00000000840F0006LL, // near jump if equal
+        X64_jne     = 0x00000000850F0006LL, // jump near if not equal
+        X64_jl      = 0x000000008C0F0006LL, // jump near if less (int <)
+        X64_jge     = 0x000000008D0F0006LL, // jump near if greater or equal (int >=)
+        X64_jg      = 0x000000008F0F0006LL, // jump near if greater (int >)
+        X64_jle     = 0x000000008E0F0006LL, // jump near if less or equal (int <=)
+        X64_jp      = 0x000000008A0F0006LL, // jump near if parity (PF == 1)
+        X64_jnp     = 0x000000008B0F0006LL, // jump near if not parity (PF == 0)
+        X64_jneg    = 0x0000000001000000LL, // xor with this mask to negate the condition
+        X64_jo8     = 0x0070000000000002LL, // jump near if overflow
+        X64_jb8     = 0x0072000000000002LL, // jump near if below (uint <)
+        X64_jae8    = 0x0073000000000002LL, // jump near if above or equal (uint >=)
+        X64_ja8     = 0x0077000000000002LL, // jump near if above (uint >)
+        X64_jbe8    = 0x0076000000000002LL, // jump near if below or equal (uint <=)
+        X64_je8     = 0x0074000000000002LL, // near jump if equal
+        X64_jne8    = 0x0075000000000002LL, // jump near if not equal
+        X64_jl8     = 0x007C000000000002LL, // jump near if less (int <)
+        X64_jge8    = 0x007D000000000002LL, // jump near if greater or equal (int >=)
+        X64_jg8     = 0x007F000000000002LL, // jump near if greater (int >)
+        X64_jle8    = 0x007E000000000002LL, // jump near if less or equal (int <=)
+        X64_jp8     = 0x007A000000000002LL, // jump near if parity (PF == 1)
+        X64_jnp8    = 0x007B000000000002LL, // jump near if not parity (PF == 0)
+        X64_jneg8   = 0x0001000000000000LL, // xor with this mask to negate the condition
+        X64_leaqrm  = 0x00000000808D4807LL, // 64bit load effective addr reg <- disp32+base
+        X64_learm   = 0x00000000808D4007LL, // 32bit load effective addr reg <- disp32+base
+        X64_movlr   = 0xC08B400000000003LL, // 32bit mov r <- b
+        X64_movlmr  = 0x0000000080894007LL, // 32bit store r -> [b+d32]
+        X64_movlrm  = 0x00000000808B4007LL, // 32bit load r <- [b+d32]
+        X64_movqmr  = 0x0000000080894807LL, // 64bit store gpr -> [b+d32]
+        X64_movqspr = 0x0024448948000005LL, // 64bit store gpr -> [rsp+d32] (sib required)
+        X64_movqr   = 0xC08B480000000003LL, // 64bit mov r <- b
+        X64_movqi   = 0xB848000000000002LL, // 64bit mov r <- imm64
+        X64_movi    = 0xB840000000000002LL, // 32bit mov r <- imm32
+        X64_movqi32 = 0xC0C7480000000003LL, // 64bit mov r <- int64(imm32)
+        X64_movapsr = 0xC0280F4000000004LL, // 128bit mov xmm <- xmm
+        X64_movqrx  = 0xC07E0F4866000005LL, // 64bit mov b <- xmm-r
+        X64_movqxr  = 0xC06E0F4866000005LL, // 64bit mov b -> xmm-r
+        X64_movqrm  = 0x00000000808B4807LL, // 64bit load r <- [b+d32]
+        X64_movsdrr = 0xC0100F40F2000005LL, // 64bit mov xmm-r <- xmm-b (upper 64bits unchanged)
+        X64_movsdrm = 0x80100F40F2000005LL, // 64bit load xmm-r <- [b+d32] (upper 64 cleared)
+        X64_movsdmr = 0x80110F40F2000005LL, // 64bit store xmm-r -> [b+d32]
+        X64_movsxdr = 0xC063480000000003LL, // sign extend i32 to i64 r = (int64)(int32) b
+        X64_movzx8  = 0xC0B60F4000000004LL, // zero extend i8 to i64 r = (uint64)(uint8) b
+        X64_movzx8m = 0x80B60F4000000004LL, // zero extend i8 load to i32 r <- [b+d32]
+        X64_movzx16m= 0x80B70F4000000004LL, // zero extend i16 load to i32 r <- [b+d32]
+        X64_neg     = 0xD8F7400000000003LL, // 32bit two's compliment b = -b
+        X64_nop1    = 0x9000000000000001LL, // one byte NOP
+        X64_nop2    = 0x9066000000000002LL, // two byte NOP
+        X64_nop3    = 0x001F0F0000000003LL, // three byte NOP
+        X64_nop4    = 0x00401F0F00000004LL, // four byte NOP
+        X64_nop5    = 0x0000441F0F000005LL, // five byte NOP
+        X64_nop6    = 0x0000441F0F660006LL, // six byte NOP
+        X64_nop7    = 0x00000000801F0F07LL, // seven byte NOP
+        X64_not     = 0xD0F7400000000003LL, // 32bit ones compliment b = ~b
+        X64_orlrr   = 0xC00B400000000003LL, // 32bit or r |= b
+        X64_orqrr   = 0xC00B480000000003LL, // 64bit or r |= b
+        X64_popr    = 0x5840000000000002LL, // 64bit pop r <- [rsp++]
+        X64_pushr   = 0x5040000000000002LL, // 64bit push r -> [--rsp]
+        X64_pxor    = 0xC0EF0F4066000005LL, // 128bit xor xmm-r ^= xmm-b
+        X64_ret     = 0xC300000000000001LL, // near return from called procedure
+        X64_sete    = 0xC0940F4000000004LL, // set byte if equal (ZF == 1)
+        X64_seto    = 0xC0900F4000000004LL, // set byte if overflow (OF == 1)
+        X64_setc    = 0xC0920F4000000004LL, // set byte if carry (CF == 1)
+        X64_setl    = 0xC09C0F4000000004LL, // set byte if less (int <) (SF != OF)
+        X64_setle   = 0xC09E0F4000000004LL, // set byte if less or equal (int <=) (ZF == 1 || SF != OF)
+        X64_setg    = 0xC09F0F4000000004LL, // set byte if greater (int >) (ZF == 0 && SF == OF)
+        X64_setge   = 0xC09D0F4000000004LL, // set byte if greater or equal (int >=) (SF == OF)
+        X64_seta    = 0xC0970F4000000004LL, // set byte if above (uint >) (CF == 0 && ZF == 0)
+        X64_setae   = 0xC0930F4000000004LL, // set byte if above or equal (uint >=) (CF == 0)
+        X64_setb    = 0xC0920F4000000004LL, // set byte if below (uint <) (CF == 1)
+        X64_setbe   = 0xC0960F4000000004LL, // set byte if below or equal (uint <=) (ZF == 1 || CF == 1)
+        X64_subsd   = 0xC05C0F40F2000005LL, // subtract scalar double r -= b
+        X64_shl     = 0xE0D3400000000003LL, // 32bit left shift r <<= rcx
+        X64_shlq    = 0xE0D3480000000003LL, // 64bit left shift r <<= rcx
+        X64_shr     = 0xE8D3400000000003LL, // 32bit uint right shift r >>= rcx
+        X64_shrq    = 0xE8D3480000000003LL, // 64bit uint right shift r >>= rcx
+        X64_sar     = 0xF8D3400000000003LL, // 32bit int right shift r >>= rcx
+        X64_sarq    = 0xF8D3480000000003LL, // 64bit int right shift r >>= rcx
+        X64_shli    = 0x00E0C14000000004LL, // 32bit left shift r <<= imm8
+        X64_shlqi   = 0x00E0C14800000004LL, // 64bit left shift r <<= imm8
+        X64_sari    = 0x00F8C14000000004LL, // 32bit int right shift r >>= imm8
+        X64_sarqi   = 0x00F8C14800000004LL, // 64bit int right shift r >>= imm8
+        X64_shri    = 0x00E8C14000000004LL, // 32bit uint right shift r >>= imm8
+        X64_shrqi   = 0x00E8C14800000004LL, // 64bit uint right shift r >>= imm8
+        X64_subqrr  = 0xC02B480000000003LL, // 64bit sub r -= b
+        X64_subrr   = 0xC02B400000000003LL, // 32bit sub r -= b
+        X64_subqri  = 0xE881480000000003LL, // 64bit sub r -= int64(imm32)
+        X64_subqr8  = 0x00E8834800000004LL, // 64bit sub r -= int64(imm8)
+        X64_ucomisd = 0xC02E0F4066000005LL, // unordered compare scalar double
+        X64_xorqrr  = 0xC033480000000003LL, // 64bit xor r &= b
+        X64_xorrr   = 0xC033400000000003LL, // 32bit xor r &= b
+        X64_xorpd   = 0xC0570F4066000005LL, // 128bit xor xmm (two packed doubles)
+        X64_xorps   = 0xC0570F4000000004LL, // 128bit xor xmm (four packed singles), one byte shorter
+        X64_xorpsm  = 0x05570F4000000004LL, // 128bit xor xmm, [rip+disp32]
+        X64_xorpsa  = 0x2504570F40000005LL, // 128bit xor xmm, [disp32]
+
+        X86_and8r   = 0xC022000000000002LL, // and rl,rh
+        X86_sete    = 0xC0940F0000000003LL, // no-rex version of X64_sete
+        X86_setnp   = 0xC09B0F0000000003LL  // no-rex set byte if odd parity (ordered fcmp result) (PF == 0)
+    };
+
+    typedef uint32_t RegisterMask;
+
+    static const RegisterMask GpRegs = 0xffff;
+    static const RegisterMask FpRegs = 0xffff0000;
+    static const bool CalleeRegsNeedExplicitSaving = true;
+#ifdef _MSC_VER
+    static const RegisterMask SavedRegs = 1<<RBX | 1<<RSI | 1<<RDI | 1<<R12 | 1<<R13 | 1<<R14 | 1<<R15;
+    static const int NumSavedRegs = 7; // rbx, rsi, rdi, r12-15
+    static const int NumArgRegs = 4;
+#else
+    static const RegisterMask SavedRegs = 1<<RBX | 1<<R12 | 1<<R13 | 1<<R14 | 1<<R15;
+    static const int NumSavedRegs = 5; // rbx, r12-15
+    static const int NumArgRegs = 6;
+#endif
+
+    static inline bool isValidDisplacement(int32_t d) {
+        return true;
+    }
+    static inline bool IsFpReg(Register r) {
+        return ((1<<r) & FpRegs) != 0;
+    }
+    static inline bool IsGpReg(Register r) {
+        return ((1<<r) & GpRegs) != 0;
+    }
+
+    verbose_only( extern const char* regNames[]; )
+
+    #define DECLARE_PLATFORM_STATS()
+    #define DECLARE_PLATFORM_REGALLOC()
+
+    #define DECLARE_PLATFORM_ASSEMBLER()                                    \
+        const static Register argRegs[NumArgRegs], retRegs[1];              \
+        void underrunProtect(ptrdiff_t bytes);                              \
+        void nativePageReset();                                             \
+        void nativePageSetup();                                             \
+        void asm_qbinop(LIns*);                                             \
+        void MR(Register, Register);\
+        void JMP(NIns*);\
+        void JMPl(NIns*);\
+        void emit(uint64_t op);\
+        void emit8(uint64_t op, int64_t val);\
+        void emit32(uint64_t op, int64_t val);\
+        void emitrr(uint64_t op, Register r, Register b);\
+        void emitrr8(uint64_t op, Register r, Register b);\
+        void emitr(uint64_t op, Register b) { emitrr(op, (Register)0, b); }\
+        void emitr8(uint64_t op, Register b) { emitrr8(op, (Register)0, b); }\
+        void emitprr(uint64_t op, Register r, Register b);\
+        void emitrm(uint64_t op, Register r, int32_t d, Register b);\
+        void emitrm_wide(uint64_t op, Register r, int32_t d, Register b);\
+        uint64_t emit_disp32(uint64_t op, int32_t d);\
+        void emitprm(uint64_t op, Register r, int32_t d, Register b);\
+        void emitrr_imm(uint64_t op, Register r, Register b, int32_t imm);\
+        void emitr_imm(uint64_t op, Register r, int32_t imm) { emitrr_imm(op, (Register)0, r, imm); }\
+        void emitr_imm8(uint64_t op, Register b, int32_t imm8);\
+        void emit_int(Register r, int32_t v);\
+        void emit_quad(Register r, uint64_t v);\
+        void asm_regarg(ArgSize, LIns*, Register);\
+        void asm_stkarg(ArgSize, LIns*, int);\
+        void asm_shift(LIns*);\
+        void asm_shift_imm(LIns*);\
+        void asm_arith_imm(LIns*);\
+        void regalloc_unary(LIns *ins, RegisterMask allow, Register &rr, Register &ra);\
+        void regalloc_binary(LIns *ins, RegisterMask allow, Register &rr, Register &ra, Register &rb);\
+        void regalloc_load(LIns *ins, Register &rr, int32_t &d, Register &rb);\
+        void dis(NIns *p, int bytes);\
+        void asm_cmp(LIns*);\
+        void asm_cmp_imm(LIns*);\
+        void fcmp(LIns*, LIns*);\
+        NIns* asm_fbranch(bool, LIns*, NIns*);\
+        void asm_div_mod(LIns *i);\
+        int max_stk_used;
+
+    #define swapptrs()  { NIns* _tins = _nIns; _nIns=_nExitIns; _nExitIns=_tins; }
+
+    const int LARGEST_UNDERRUN_PROT = 32;  // largest value passed to underrunProtect
+
+    typedef uint8_t NIns;
+
+    inline Register nextreg(Register r) {
+        return Register(r+1);
+    }
+
+} // namespace nanojit
+
+#endif // __nanojit_NativeX64__

data/vendor/tracemonkey/nanojit/Nativei386.cpp

@@ -1,4 +1,5 @@
-/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: t; tab-width: 4 -*- */
+/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: nil; tab-width: 4 -*- */
+/* vi: set ts=4 sw=4 expandtab: (add to ~/.vimrc: set modeline modelines=5) */
 /* ***** BEGIN LICENSE BLOCK *****
  * Version: MPL 1.1/GPL 2.0/LGPL 2.1
  *
@@ -37,6 +38,7 @@
  * the terms of any one of the MPL, the GPL or the LGPL.
  *
  * ***** END LICENSE BLOCK ***** */
+#include "nanojit.h"
 
 #ifdef _MAC
 // for MakeDataExecutable
@@ -48,19 +50,20 @@
 #include <errno.h>
 #include <stdlib.h>
 #endif
-#include "nanojit.h"
 
 namespace nanojit
 {
-	#ifdef FEATURE_NANOJIT
+    #if defined FEATURE_NANOJIT && defined NANOJIT_IA32
+
+    #ifdef NJ_VERBOSE
+        const char *regNames[] = {
+            "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
+            "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7",
+            "f0"
+        };
+    #endif
 
-	#ifdef NJ_VERBOSE
-		const char *regNames[] = {
-			"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
-			"xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7",
-			"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7"
-		};
-	#endif
+    #define TODO(x) do{ verbose_only(outputf(#x);) NanoAssertMsgf(false, "%s", #x); } while(0)
 
     const Register Assembler::argRegs[] = { ECX, EDX };
     const Register Assembler::retRegs[] = { EAX, EDX };
@@ -74,108 +77,111 @@ namespace nanojit
     };
 
 
-	void Assembler::nInit(AvmCore* core)
-	{
-		(void) core;
-        OSDep::getDate();
-	}
+    void Assembler::nInit(AvmCore* core)
+    {
+        (void) core;
+        VMPI_getDate();
+    }
+
+    void Assembler::nBeginAssembly() {
+    }
 
-	NIns* Assembler::genPrologue()
-	{
-		/**
-		 * Prologue
-		 */
-		uint32_t stackNeeded = STACK_GRANULARITY * _activation.highwatermark;
+    NIns* Assembler::genPrologue()
+    {
+        /**
+         * Prologue
+         */
+        uint32_t stackNeeded = STACK_GRANULARITY * _activation.tos;
 
-		uint32_t stackPushed =
+        uint32_t stackPushed =
             STACK_GRANULARITY + // returnaddr
-            STACK_GRANULARITY + // ebp
-			STACK_GRANULARITY;  // dummy
-		
-		if (!_thisfrag->lirbuf->explicitSavedRegs)
-			stackPushed += NumSavedRegs * STACK_GRANULARITY;
-		
-		uint32_t aligned = alignUp(stackNeeded + stackPushed, NJ_ALIGN_STACK);
-		uint32_t amt = aligned - stackPushed;
-
-		// Reserve stackNeeded bytes, padded
-		// to preserve NJ_ALIGN_STACK-byte alignment.
-		if (amt) 
-			SUBi(SP, amt);
-
-		verbose_only( outputAddr=true; asm_output("[frag entry]"); )
+            STACK_GRANULARITY; // ebp
+
+        uint32_t aligned = alignUp(stackNeeded + stackPushed, NJ_ALIGN_STACK);
+        uint32_t amt = aligned - stackPushed;
+
+        // Reserve stackNeeded bytes, padded
+        // to preserve NJ_ALIGN_STACK-byte alignment.
+        if (amt)
+        {
+            SUBi(SP, amt);
+        }
+
+        verbose_only( outputAddr=true; asm_output("[frag entry]"); )
         NIns *fragEntry = _nIns;
-		MR(FP, SP); // Establish our own FP.
+        MR(FP, SP); // Establish our own FP.
         PUSHr(FP); // Save caller's FP.
 
-		if (!_thisfrag->lirbuf->explicitSavedRegs) {
-			PUSHr(FP); // dummy
-			for (int i = 0; i < NumSavedRegs; ++i)
-				PUSHr(savedRegs[i]);
-		}
-
-		return fragEntry;
-	}
+        return fragEntry;
+    }
 
-	void Assembler::nFragExit(LInsp guard)
-	{
-		SideExit *exit = guard->record()->exit;
-		bool trees = _frago->core()->config.tree_opt;
+    void Assembler::nFragExit(LInsp guard)
+    {
+        SideExit *exit = guard->record()->exit;
+        bool trees = config.tree_opt;
         Fragment *frag = exit->target;
         GuardRecord *lr = 0;
-		bool destKnown = (frag && frag->fragEntry);
-		// Generate jump to epilog and initialize lr.
-		// If the guard is LIR_xtbl, use a jump table with epilog in every entry
-		if (guard->isop(LIR_xtbl)) {
-			lr = guard->record();
-			Register r = EBX;
-			SwitchInfo* si = guard->record()->exit->switchInfo;
-			emitJumpTable(si, _epilogue);
-			JMP_indirect(r);
-			LEAmi4(r, si->table, r);
-		} else {
-			// If the guard already exists, use a simple jump.
-			if (destKnown && !trees) {
-				JMP(frag->fragEntry);
-				lr = 0;
-			} else {  // target doesn't exist. Use 0 jump offset and patch later
-				lr = guard->record();
-				JMP_long(_epilogue);
-				lr->jmp = _nIns;
-			}
-		}
-		// first restore ESP from EBP, undoing SUBi(SP,amt) from genPrologue
+        bool destKnown = (frag && frag->fragEntry);
+
+        // Generate jump to epilog and initialize lr.
+        // If the guard is LIR_xtbl, use a jump table with epilog in every entry
+        if (guard->isop(LIR_xtbl)) {
+            lr = guard->record();
+            Register r = EDX;
+            SwitchInfo* si = guard->record()->exit->switchInfo;
+            if (!_epilogue)
+                _epilogue = genEpilogue();
+            emitJumpTable(si, _epilogue);
+            JMP_indirect(r);
+            LEAmi4(r, si->table, r);
+        } else {
+            // If the guard already exists, use a simple jump.
+            if (destKnown && !trees) {
+                JMP(frag->fragEntry);
+                lr = 0;
+            } else {  // Target doesn't exist. Jump to an epilogue for now. This can be patched later.
+                if (!_epilogue)
+                    _epilogue = genEpilogue();
+                lr = guard->record();
+                JMP_long(_epilogue);
+                lr->jmp = _nIns;
+            }
+        }
+
+        // profiling for the exit
+        verbose_only(
+           if (_logc->lcbits & LC_FragProfile) {
+              INCLi( &guard->record()->profCount );
+           }
+        )
+
+        // Restore ESP from EBP, undoing SUBi(SP,amt) in the prologue
         MR(SP,FP);
 
-		// return value is GuardRecord*
+        // return value is GuardRecord*
         LDi(EAX, int(lr));
-	}
+    }
 
     NIns *Assembler::genEpilogue()
     {
         RET();
-
-		if (!_thisfrag->lirbuf->explicitSavedRegs) {
-			for (int i = NumSavedRegs - 1; i >= 0; --i)
-				POPr(savedRegs[i]);
-			POPr(FP); // dummy
-		}
-
         POPr(FP); // Restore caller's FP.
-        MR(SP,FP); // pop the stack frame
+
         return  _nIns;
     }
-	
-	void Assembler::asm_call(LInsp ins)
-	{
+
+    void Assembler::asm_call(LInsp ins)
+    {
         const CallInfo* call = ins->callInfo();
-		// must be signed, not unsigned
-		uint32_t iargs = call->count_iargs();
-		int32_t fargs = call->count_args() - iargs - call->isIndirect();
+        // must be signed, not unsigned
+        uint32_t iargs = call->count_iargs();
+        int32_t fargs = call->count_args() - iargs;
 
-        bool imt = call->isInterface();
-        if (imt)
+        bool indirect = call->isIndirect();
+        if (indirect) {
+            // target arg isn't pushed, its consumed in the call
             iargs --;
+        }
 
         uint32_t max_regs = max_abi_regs[call->_abi];
         if (max_regs > iargs)
@@ -183,291 +189,255 @@ namespace nanojit
 
         int32_t istack = iargs-max_regs;  // first 2 4B args are in registers
         int32_t extra = 0;
-		const int32_t pushsize = 4*istack + 8*fargs; // actual stack space used
+        const int32_t pushsize = 4*istack + 8*fargs; // actual stack space used
 
 #if _MSC_VER
-        // msc is slack, and MIR doesn't do anything extra, so lets use this
-        // call-site alignment to at least have code size parity with MIR.
+        // msc only provides 4-byte alignment, anything more than 4 on windows
+        // x86-32 requires dynamic ESP alignment in prolog/epilog and static
+        // esp-alignment here.
         uint32_t align = 4;//NJ_ALIGN_STACK;
 #else
         uint32_t align = NJ_ALIGN_STACK;
 #endif
 
         if (pushsize) {
-		    // stack re-alignment 
-		    // only pop our adjustment amount since callee pops args in FASTCALL mode
-		    extra = alignUp(pushsize, align) - pushsize;
+            // stack re-alignment
+            // only pop our adjustment amount since callee pops args in FASTCALL mode
+            extra = alignUp(pushsize, align) - pushsize;
             if (call->_abi == ABI_CDECL) {
-				// with CDECL only, caller pops args
+                // with CDECL only, caller pops args
                 ADDi(SP, extra+pushsize);
             } else if (extra > 0) {
-				ADDi(SP, extra);
+                ADDi(SP, extra);
             }
         }
 
-        bool indirect = false;
-        if (ins->isop(LIR_call) || ins->isop(LIR_fcall)) {
-    		CALL(call);
+        NanoAssert(ins->isop(LIR_pcall) || ins->isop(LIR_fcall));
+        if (!indirect) {
+            CALL(call);
         }
         else {
             // indirect call.  x86 Calling conventions don't use EAX as an
             // argument, and do use EAX as a return value.  We need a register
             // for the address to call, so we use EAX since it will always be
             // available
-            NanoAssert(ins->isop(LIR_calli) || ins->isop(LIR_fcalli));
             CALLr(call, EAX);
-            indirect = true;
         }
 
-		// make sure fpu stack is empty before call (restoreCallerSaved)
-		NanoAssert(_allocator.isFree(FST0));
-		// note: this code requires that ref arguments (ARGSIZE_Q)
+        // make sure fpu stack is empty before call (restoreCallerSaved)
+        NanoAssert(_allocator.isFree(FST0));
+        // note: this code requires that ref arguments (ARGSIZE_Q)
         // be one of the first two arguments
-		// pre-assign registers to the first N 4B args based on the calling convention
-		uint32_t n = 0;
+        // pre-assign registers to the first N 4B args based on the calling convention
+        uint32_t n = 0;
 
-        ArgSize sizes[2*MAXARGS];
+        ArgSize sizes[MAXARGS];
         uint32_t argc = call->get_sizes(sizes);
         if (indirect) {
             argc--;
-            asm_arg(ARGSIZE_LO, ins->arg(argc), EAX);
-        }
-
-        if (imt) {
-            // interface thunk calling convention: put iid in EDX
-            NanoAssert(call->_abi == ABI_CDECL);
-            argc--;
-            asm_arg(ARGSIZE_LO, ins->arg(argc), EDX);
+            asm_arg(ARGSIZE_P, ins->arg(argc), EAX);
         }
 
-		for(uint32_t i=0; i < argc; i++)
-		{
-			uint32_t j = argc-i-1;
+        for(uint32_t i=0; i < argc; i++)
+        {
+            uint32_t j = argc-i-1;
             ArgSize sz = sizes[j];
             Register r = UnknownReg;
-            if (n < max_regs && sz != ARGSIZE_F) { 
-		        r = argRegs[n++]; // tell asm_arg what reg to use
+            if (n < max_regs && sz != ARGSIZE_F) {
+                r = argRegs[n++]; // tell asm_arg what reg to use
             }
             asm_arg(sz, ins->arg(j), r);
-		}
-
-		if (extra > 0)
-			SUBi(SP, extra);
-	}
-
-	void Assembler::nMarkExecute(Page* page, int flags)
-	{
-		NanoAssert(sizeof(Page) == NJ_PAGE_SIZE);
-		#if defined WIN32 || defined WIN64
-			DWORD dwIgnore;
-			static const DWORD kProtFlags[4] = 
-			{
-				PAGE_READONLY,			// 0
-				PAGE_READWRITE,			// PAGE_WRITE
-				PAGE_EXECUTE_READ,		// PAGE_EXEC
-				PAGE_EXECUTE_READWRITE	// PAGE_EXEC|PAGE_WRITE
-			};
-			DWORD prot = kProtFlags[flags & (PAGE_WRITE|PAGE_EXEC)];
-			BOOL res = VirtualProtect(page, NJ_PAGE_SIZE, prot, &dwIgnore);
-			if (!res)
-			{
-				// todo: we can't abort or assert here, we have to fail gracefully.
-				NanoAssertMsg(false, "FATAL ERROR: VirtualProtect() failed\n");
-			}
-		#elif defined AVMPLUS_UNIX || defined AVMPLUS_MAC
-			static const int kProtFlags[4] = 
-			{
-				PROT_READ,						// 0
-				PROT_READ|PROT_WRITE,			// PAGE_WRITE
-				PROT_READ|PROT_EXEC,			// PAGE_EXEC
-				PROT_READ|PROT_WRITE|PROT_EXEC	// PAGE_EXEC|PAGE_WRITE
-			};
-			int prot = kProtFlags[flags & (PAGE_WRITE|PAGE_EXEC)];
-			intptr_t addr = (intptr_t)page;
-			addr &= ~((uintptr_t)NJ_PAGE_SIZE - 1);
-			NanoAssert(addr == (intptr_t)page);
-			#if defined SOLARIS
-			if (mprotect((char *)addr, NJ_PAGE_SIZE, prot) == -1) 
-			#else
-			if (mprotect((void *)addr, NJ_PAGE_SIZE, prot) == -1) 
-			#endif
-			{
-				// todo: we can't abort or assert here, we have to fail gracefully.
-				NanoAssertMsg(false, "FATAL ERROR: mprotect(PROT_EXEC) failed\n");
-                abort();
-            }
-        #else
-			(void)page;
-		#endif
-	}
-			
-	Register Assembler::nRegisterAllocFromSet(int set)
-	{
-		Register r;
-		RegAlloc &regs = _allocator;
-	#ifdef WIN32
-		_asm
-		{
-			mov ecx, regs
-			bsf eax, set					// i = first bit set
-			btr RegAlloc::free[ecx], eax	// free &= ~rmask(i)
-			mov r, eax
-		}
-	#elif defined WIN64
-		unsigned long tr, fr;
-		_BitScanForward(&tr, set);
-		_bittestandreset(&fr, tr);
-		regs.free = fr;
-		r = tr;
-	#else
-		asm(
-			"bsf	%1, %%eax\n\t"
-			"btr	%%eax, %2\n\t"
-			"movl	%%eax, %0\n\t"
-			: "=m"(r) : "m"(set), "m"(regs.free) : "%eax", "memory" );
-	#endif /* WIN32 */
-		return r;
-	}
-
-	void Assembler::nRegisterResetAll(RegAlloc& a)
-	{
-		// add scratch registers to our free list for the allocator
-		a.clear();
-		a.used = 0;
-		a.free = SavedRegs | ScratchRegs;
+        }
+
+        if (extra > 0)
+            SUBi(SP, extra);
+    }
+
+    Register Assembler::nRegisterAllocFromSet(RegisterMask set)
+    {
+        Register r;
+        RegAlloc &regs = _allocator;
+    #ifdef WIN32
+        _asm
+        {
+            mov ecx, regs
+            bsf eax, set                    // i = first bit set
+            btr RegAlloc::free[ecx], eax    // free &= ~rmask(i)
+            mov r, eax
+        }
+    #elif defined WIN64
+        unsigned long tr, fr;
+        _BitScanForward(&tr, set);
+        _bittestandreset(&fr, tr);
+        regs.free = fr;
+        r = tr;
+    #else
+        asm(
+            "bsf    %1, %%eax\n\t"
+            "btr    %%eax, %2\n\t"
+            "movl   %%eax, %0\n\t"
+            : "=m"(r) : "m"(set), "m"(regs.free) : "%eax", "memory" );
+    #endif /* WIN32 */
+        return r;
+    }
+
+    void Assembler::nRegisterResetAll(RegAlloc& a)
+    {
+        // add scratch registers to our free list for the allocator
+        a.clear();
+        a.free = SavedRegs | ScratchRegs;
         if (!config.sse2)
             a.free &= ~XmmRegs;
-		debug_only( a.managed = a.free; )
-	}
-
-	NIns* Assembler::nPatchBranch(NIns* branch, NIns* targ)
-	{
-        NIns* was = 0;
-		intptr_t offset = intptr_t(targ) - intptr_t(branch);
-		if (branch[0] == JMP32) {
-            was = branch + *(int32_t*)&branch[1] + 5;
-		    *(int32_t*)&branch[1] = offset - 5;
+        debug_only( a.managed = a.free; )
+    }
+
+    void Assembler::nPatchBranch(NIns* branch, NIns* targ)
+    {
+        intptr_t offset = intptr_t(targ) - intptr_t(branch);
+        if (branch[0] == JMP32) {
+            *(int32_t*)&branch[1] = offset - 5;
             VALGRIND_DISCARD_TRANSLATIONS(&branch[1], sizeof(int32_t));
-		} else if (branch[0] == JCC32) {
-            was = branch + *(int32_t*)&branch[2] + 6;
-		    *(int32_t*)&branch[2] = offset - 6;
+        } else if (branch[0] == JCC32) {
+            *(int32_t*)&branch[2] = offset - 6;
             VALGRIND_DISCARD_TRANSLATIONS(&branch[2], sizeof(int32_t));
-		} else
-		    NanoAssertMsg(0, "Unknown branch type in nPatchBranch");
-        return was;
-	}
-
-	RegisterMask Assembler::hint(LIns* i, RegisterMask allow)
-	{
-		uint32_t op = i->opcode();
-		int prefer = allow;
-        if (op == LIR_call || op == LIR_calli) {
-			prefer &= rmask(retRegs[0]);
-        }
-        else if (op == LIR_fcall || op == LIR_fcalli) {
+        } else
+            NanoAssertMsg(0, "Unknown branch type in nPatchBranch");
+    }
+
+    RegisterMask Assembler::hint(LIns* i, RegisterMask allow)
+    {
+        uint32_t op = i->opcode();
+        int prefer = allow;
+        if (op == LIR_icall) {
+            prefer &= rmask(retRegs[0]);
+        }
+        else if (op == LIR_fcall) {
             prefer &= rmask(FST0);
         }
         else if (op == LIR_param) {
-            uint32_t max_regs = max_abi_regs[_thisfrag->lirbuf->abi];
-            if (i->imm8() < max_regs)
-    			prefer &= rmask(Register(i->imm8()));
+            if (i->paramKind() == 0) {
+                uint32_t max_regs = max_abi_regs[_thisfrag->lirbuf->abi];
+                if (i->paramArg() < max_regs)
+                    prefer &= rmask(argRegs[i->paramArg()]);
+            } else {
+                if (i->paramArg() < NumSavedRegs)
+                    prefer &= rmask(savedRegs[i->paramArg()]);
+            }
         }
         else if (op == LIR_callh || (op == LIR_rsh && i->oprnd1()->opcode()==LIR_callh)) {
             prefer &= rmask(retRegs[1]);
         }
         else if (i->isCmp()) {
-			prefer &= AllowableFlagRegs;
+            prefer &= AllowableFlagRegs;
         }
         else if (i->isconst()) {
             prefer &= ScratchRegs;
         }
-		return (_allocator.free & prefer) ? prefer : allow;
-	}
+        return (_allocator.free & prefer) ? prefer : allow;
+    }
 
     void Assembler::asm_qjoin(LIns *ins)
     {
-		int d = findMemFor(ins);
-		AvmAssert(d);
-		LIns* lo = ins->oprnd1();
-		LIns* hi = ins->oprnd2();
-
-        Reservation *resv = getresv(ins);
-        Register rr = resv->reg;
+        int d = findMemFor(ins);
+        AvmAssert(d);
+        LIns* lo = ins->oprnd1();
+        LIns* hi = ins->oprnd2();
 
-        if (rr != UnknownReg && (rmask(rr) & FpRegs))
-            evict(rr);
+        Register rr = ins->getReg();
+        if (isKnownReg(rr) && (rmask(rr) & FpRegs))
+            evict(rr, ins);
 
         if (hi->isconst())
-		{
-			STi(FP, d+4, hi->constval());
-		}
-		else
-		{
-			Register r = findRegFor(hi, GpRegs);
-			ST(FP, d+4, r);
-		}
+        {
+            STi(FP, d+4, hi->imm32());
+        }
+        else
+        {
+            Register r = findRegFor(hi, GpRegs);
+            ST(FP, d+4, r);
+        }
 
         if (lo->isconst())
-		{
-			STi(FP, d, lo->constval());
-		}
-		else
-		{
-			// okay if r gets recycled.
-			Register r = findRegFor(lo, GpRegs);
-			ST(FP, d, r);
-		}
-
-        freeRsrcOf(ins, false);	// if we had a reg in use, emit a ST to flush it to mem
+        {
+            STi(FP, d, lo->imm32());
+        }
+        else
+        {
+            // okay if r gets recycled.
+            Register r = findRegFor(lo, GpRegs);
+            ST(FP, d, r);
+        }
+
+        freeRsrcOf(ins, false); // if we had a reg in use, emit a ST to flush it to mem
+    }
+
+    void Assembler::asm_load(int d, Register r)
+    {
+        if (rmask(r) & FpRegs)
+        {
+            if (rmask(r) & XmmRegs) {
+                SSE_LDQ(r, d, FP);
+            } else {
+                FLDQ(d, FP);
+            }
+        }
+        else
+        {
+            LD(r, d, FP);
+        }
     }
 
-	void Assembler::asm_load(int d, Register r)
-	{
-		if (rmask(r) & FpRegs)
-		{
-			if (rmask(r) & XmmRegs) {
-				SSE_LDQ(r, d, FP);
-			} else {
-				FLDQ(d, FP); 
-			}
-		}
-		else
-		{
-			LD(r, d, FP);
-		}
-	}
-	
-	void Assembler::asm_restore(LInsp i, Reservation *resv, Register r)
-	{
+    void Assembler::asm_restore(LInsp i, Reservation* /*unused*/, Register r)
+    {
+        uint32_t arg;
+        uint32_t abi_regcount;
         if (i->isop(LIR_alloc)) {
-			verbose_only( if (_verbose) { outputForEOL("  <= remat %s size %d", _thisfrag->lirbuf->names->formatRef(i), i->size()); } )
-            LEA(r, disp(resv), FP);
+            verbose_only( if (_logc->lcbits & LC_RegAlloc) {
+                            outputForEOL("  <= remat %s size %d",
+                            _thisfrag->lirbuf->names->formatRef(i), i->size()); } )
+            LEA(r, disp(i), FP);
         }
         else if (i->isconst()) {
-            if (!resv->arIndex) {
-                reserveFree(i);
+            if (!i->getArIndex()) {
+                i->markAsClear();
+            }
+            LDi(r, i->imm32());
+        }
+        else if (i->isop(LIR_param) && i->paramKind() == 0 &&
+            (arg = i->paramArg()) >= (abi_regcount = max_abi_regs[_thisfrag->lirbuf->abi])) {
+            // incoming arg is on stack, can restore it from there instead of spilling
+            if (!i->getArIndex()) {
+                i->markAsClear();
             }
-            LDi(r, i->constval());
+            // compute position of argument relative to ebp.  higher argument
+            // numbers are at higher positive offsets.  the first abi_regcount
+            // arguments are in registers, rest on stack.  +8 accomodates the
+            // return address and saved ebp value.  assuming abi_regcount == 0:
+            //    low-addr  ebp
+            //    [frame...][saved-ebp][return-addr][arg0][arg1]...
+            int d = (arg - abi_regcount) * sizeof(intptr_t) + 8;
+            LD(r, d, FP);
         }
         else {
             int d = findMemFor(i);
-			verbose_only( if (_verbose) { outputForEOL("  <= restore %s", _thisfrag->lirbuf->names->formatRef(i)); } )
-			asm_load(d,r);
+            verbose_only( if (_logc->lcbits & LC_RegAlloc) {
+                            outputForEOL("  <= restore %s",
+                            _thisfrag->lirbuf->names->formatRef(i)); } )
+            asm_load(d,r);
         }
-	}
+    }
 
     void Assembler::asm_store32(LIns *value, int dr, LIns *base)
     {
         if (value->isconst())
         {
-			Register rb = getBaseReg(base, dr, GpRegs);
-            int c = value->constval();
-			STi(rb, dr, c);
+            Register rb = getBaseReg(base, dr, GpRegs);
+            int c = value->imm32();
+            STi(rb, dr, c);
         }
         else
         {
-		    // make sure what is in a register
-		    Reservation *rA, *rB;
+            // make sure what is in a register
             Register ra, rb;
             if (base->isop(LIR_alloc)) {
                 rb = FP;
@@ -475,164 +445,156 @@ namespace nanojit
                 ra = findRegFor(value, GpRegs);
             } else if (base->isconst()) {
                 // absolute address
-                dr += base->constval();
+                dr += base->imm32();
                 ra = findRegFor(value, GpRegs);
                 rb = UnknownReg;
             } else {
-    		    findRegFor2(GpRegs, value, rA, base, rB);
-		        ra = rA->reg;
-		        rb = rB->reg;
+                findRegFor2b(GpRegs, value, ra, base, rb);
             }
-		    ST(rb, dr, ra);
+            ST(rb, dr, ra);
         }
     }
 
-	void Assembler::asm_spill(Register rr, int d, bool pop, bool quad)
-	{
-		(void)quad;
-		if (d)
-		{
-			// save to spill location
+    void Assembler::asm_spill(Register rr, int d, bool pop, bool quad)
+    {
+        (void)quad;
+        if (d)
+        {
+            // save to spill location
             if (rmask(rr) & FpRegs)
-			{
+            {
                 if (rmask(rr) & XmmRegs) {
                     SSE_STQ(d, FP, rr);
                 } else {
-					FSTQ((pop?1:0), d, FP);
+                    FSTQ((pop?1:0), d, FP);
                 }
-			}
-			else
-			{
-				ST(FP, d, rr);
-			}
-		}
-		else if (pop && (rmask(rr) & x87Regs))
-		{
-			// pop the fpu result since it isn't used
-			FSTP(FST0);
-		}
-	}
-
-	void Assembler::asm_load64(LInsp ins)
-	{
-		LIns* base = ins->oprnd1();
-		int db = ins->oprnd2()->constval();
-		Reservation *resv = getresv(ins);
-		Register rr = resv->reg;
-
-		if (rr != UnknownReg && rmask(rr) & XmmRegs)
-		{
-			freeRsrcOf(ins, false);
-			Register rb = getBaseReg(base, db, GpRegs);
-			SSE_LDQ(rr, db, rb);
-		}
-		else
-		{
-			int dr = disp(resv);
-			Register rb;
+            }
+            else
+            {
+                ST(FP, d, rr);
+            }
+        }
+        else if (pop && (rmask(rr) & x87Regs))
+        {
+            // pop the fpu result since it isn't used
+            FSTP(FST0);
+        }
+    }
+
+    void Assembler::asm_load64(LInsp ins)
+    {
+        LIns* base = ins->oprnd1();
+        int db = ins->disp();
+        Register rr = ins->getReg();
+
+        if (isKnownReg(rr) && rmask(rr) & XmmRegs)
+        {
+            freeRsrcOf(ins, false);
+            Register rb = getBaseReg(base, db, GpRegs);
+            SSE_LDQ(rr, db, rb);
+        }
+        else
+        {
+            int dr = disp(ins);
+            Register rb;
             if (base->isop(LIR_alloc)) {
                 rb = FP;
                 db += findMemFor(base);
             } else {
                 rb = findRegFor(base, GpRegs);
             }
-			resv->reg = UnknownReg;
-
-			// don't use an fpu reg to simply load & store the value.
-			if (dr)
-				asm_mmq(FP, dr, rb, db);
-
-			freeRsrcOf(ins, false);
-
-			if (rr != UnknownReg)
-			{
-				NanoAssert(rmask(rr)&FpRegs);
-				_allocator.retire(rr);
-				FLDQ(db, rb);
-			}
-		}
-	}
-
-	void Assembler::asm_store64(LInsp value, int dr, LInsp base)
-	{
-		if (value->isconstq())
-		{
-			// if a constant 64-bit value just store it now rather than
-			// generating a pointless store/load/store sequence
-			Register rb;
+            ins->setReg(UnknownReg);
+
+            // don't use an fpu reg to simply load & store the value.
+            if (dr)
+                asm_mmq(FP, dr, rb, db);
+
+            freeRsrcOf(ins, false);
+
+            if (isKnownReg(rr))
+            {
+                NanoAssert(rmask(rr)&FpRegs);
+                _allocator.retire(rr);
+                FLDQ(db, rb);
+            }
+        }
+    }
+
+    void Assembler::asm_store64(LInsp value, int dr, LInsp base)
+    {
+        if (value->isconstq())
+        {
+            // if a constant 64-bit value just store it now rather than
+            // generating a pointless store/load/store sequence
+            Register rb;
             if (base->isop(LIR_alloc)) {
                 rb = FP;
                 dr += findMemFor(base);
             } else {
                 rb = findRegFor(base, GpRegs);
             }
-			const int32_t* p = (const int32_t*) (value-2);
-			STi(rb, dr+4, p[1]);
-			STi(rb, dr, p[0]);
+            STi(rb, dr+4, value->imm64_1());
+            STi(rb, dr,   value->imm64_0());
             return;
-		}
+        }
 
         if (value->isop(LIR_ldq) || value->isop(LIR_ldqc) || value->isop(LIR_qjoin))
-		{
-			// value is 64bit struct or int64_t, or maybe a double.
-			// it may be live in an FPU reg.  Either way, don't
-			// put it in an FPU reg just to load & store it.
+        {
+            // value is 64bit struct or int64_t, or maybe a double.
+            // it may be live in an FPU reg.  Either way, don't
+            // put it in an FPU reg just to load & store it.
 
-			// a) if we know it's not a double, this is right.
-			// b) if we guarded that its a double, this store could be on
-			// the side exit, copying a non-double.
-			// c) maybe its a double just being stored.  oh well.
+            // a) if we know it's not a double, this is right.
+            // b) if we guarded that its a double, this store could be on
+            // the side exit, copying a non-double.
+            // c) maybe its a double just being stored.  oh well.
 
-			if (config.sse2) {
+            if (config.sse2) {
                 Register rv = findRegFor(value, XmmRegs);
-		Register rb;
-		if (base->isop(LIR_alloc)) {
-		    rb = FP;
-		    dr += findMemFor(base);
-		} else {
-		    rb = findRegFor(base, GpRegs);
-		}
+                Register rb;
+                if (base->isop(LIR_alloc)) {
+                    rb = FP;
+                    dr += findMemFor(base);
+                } else {
+                    rb = findRegFor(base, GpRegs);
+                }
                 SSE_STQ(dr, rb, rv);
-				return;
+                return;
             }
 
-			int da = findMemFor(value);
-		    Register rb;
-		    if (base->isop(LIR_alloc)) {
-					rb = FP;
-					dr += findMemFor(base);
-		    } else {
-					rb = findRegFor(base, GpRegs);
-		    }
-		    asm_mmq(rb, dr, FP, da);
+            int da = findMemFor(value);
+            Register rb;
+            if (base->isop(LIR_alloc)) {
+                rb = FP;
+                dr += findMemFor(base);
+            } else {
+                rb = findRegFor(base, GpRegs);
+            }
+            asm_mmq(rb, dr, FP, da);
             return;
-		}
-
-		Register rb;
-		if (base->isop(LIR_alloc)) {
-		    rb = FP;
-		    dr += findMemFor(base);
-		} else {
-		    rb = findRegFor(base, GpRegs);
-		}
-
-		// if value already in a reg, use that, otherwise
-		// try to get it into XMM regs before FPU regs.
-		Reservation* rA = getresv(value);
-		Register rv;
-		int pop = !rA || rA->reg==UnknownReg;
-		if (pop) {
-		    rv = findRegFor(value, config.sse2 ? XmmRegs : FpRegs);
-		} else {
-		    rv = rA->reg;
-		}
-
-		if (rmask(rv) & XmmRegs) {
+        }
+
+        Register rb;
+        if (base->isop(LIR_alloc)) {
+            rb = FP;
+            dr += findMemFor(base);
+        } else {
+            rb = findRegFor(base, GpRegs);
+        }
+
+        // if value already in a reg, use that, otherwise
+        // try to get it into XMM regs before FPU regs.
+        bool pop = value->isUnusedOrHasUnknownReg();
+        Register rv = ( pop
+                      ? findRegFor(value, config.sse2 ? XmmRegs : FpRegs)
+                      : value->getReg() );
+
+        if (rmask(rv) & XmmRegs) {
             SSE_STQ(dr, rb, rv);
-		} else {
-			FSTQ(pop, dr, rb);
-		}
-	}
+        } else {
+            FSTQ(pop?1:0, dr, rb);
+        }
+    }
 
     /**
      * copy 64 bits: (rd+dd) <- (rs+ds)
@@ -662,645 +624,697 @@ namespace nanojit
         }
     }
 
-	NIns* Assembler::asm_branch(bool branchOnFalse, LInsp cond, NIns* targ, bool isfar)
-	{
-		NIns* at = 0;
-		LOpcode condop = cond->opcode();
-		NanoAssert(cond->isCond());
-
-		if (condop >= LIR_feq && condop <= LIR_fge)
-		{
-			return asm_jmpcc(branchOnFalse, cond, targ);
-		}
-
-		// produce the branch
-		if (branchOnFalse)
-		{
-			if (condop == LIR_eq)
-				JNE(targ, isfar);
-			else if (condop == LIR_ov)
-				JNO(targ, isfar);
-			else if (condop == LIR_cs)
-				JNC(targ, isfar);
-			else if (condop == LIR_lt)
-				JNL(targ, isfar);
-			else if (condop == LIR_le)
-				JNLE(targ, isfar);
-			else if (condop == LIR_gt)
-				JNG(targ, isfar);
-			else if (condop == LIR_ge)
-				JNGE(targ, isfar);
-			else if (condop == LIR_ult)
-				JNB(targ, isfar);
-			else if (condop == LIR_ule)
-				JNBE(targ, isfar);
-			else if (condop == LIR_ugt)
-				JNA(targ, isfar);
-			else //if (condop == LIR_uge)
-				JNAE(targ, isfar);
-		}
-		else // op == LIR_xt
-		{
-			if (condop == LIR_eq)
-				JE(targ, isfar);
-			else if (condop == LIR_ov)
-				JO(targ, isfar);
-			else if (condop == LIR_cs)
-				JC(targ, isfar);
-			else if (condop == LIR_lt)
-				JL(targ, isfar);
-			else if (condop == LIR_le)
-				JLE(targ, isfar);
-			else if (condop == LIR_gt)
-				JG(targ, isfar);
-			else if (condop == LIR_ge)
-				JGE(targ, isfar);
-			else if (condop == LIR_ult)
-				JB(targ, isfar);
-			else if (condop == LIR_ule)
-				JBE(targ, isfar);
-			else if (condop == LIR_ugt)
-				JA(targ, isfar);
-			else //if (condop == LIR_uge)
-				JAE(targ, isfar);
-		}
-		at = _nIns;
-		asm_cmp(cond);
-		return at;
-	}
-
-	void Assembler::asm_switch(LIns* ins, NIns* exit)
-	{
-		LIns* diff = ins->oprnd1();
-		findSpecificRegFor(diff, EBX);
-		JMP(exit);
-   	}
-
-	void Assembler::asm_cmp(LIns *cond)
-	{
+    NIns* Assembler::asm_branch(bool branchOnFalse, LInsp cond, NIns* targ)
+    {
+        NIns* at = 0;
         LOpcode condop = cond->opcode();
-        
-        // LIR_ov and LIR_cs recycle the flags set by arithmetic ops
-        if ((condop == LIR_ov) || (condop == LIR_cs))
+        NanoAssert(cond->isCond());
+        if (condop >= LIR_feq && condop <= LIR_fge)
+        {
+            return asm_jmpcc(branchOnFalse, cond, targ);
+        }
+        // produce the branch
+        if (branchOnFalse)
+        {
+            if (condop == LIR_eq)
+                JNE(targ);
+            else if (condop == LIR_ov)
+                JNO(targ);
+            else if (condop == LIR_lt)
+                JNL(targ);
+            else if (condop == LIR_le)
+                JNLE(targ);
+            else if (condop == LIR_gt)
+                JNG(targ);
+            else if (condop == LIR_ge)
+                JNGE(targ);
+            else if (condop == LIR_ult)
+                JNB(targ);
+            else if (condop == LIR_ule)
+                JNBE(targ);
+            else if (condop == LIR_ugt)
+                JNA(targ);
+            else //if (condop == LIR_uge)
+                JNAE(targ);
+        }
+        else // op == LIR_xt
+        {
+            if (condop == LIR_eq)
+                JE(targ);
+            else if (condop == LIR_ov)
+                JO(targ);
+            else if (condop == LIR_lt)
+                JL(targ);
+            else if (condop == LIR_le)
+                JLE(targ);
+            else if (condop == LIR_gt)
+                JG(targ);
+            else if (condop == LIR_ge)
+                JGE(targ);
+            else if (condop == LIR_ult)
+                JB(targ);
+            else if (condop == LIR_ule)
+                JBE(targ);
+            else if (condop == LIR_ugt)
+                JA(targ);
+            else //if (condop == LIR_uge)
+                JAE(targ);
+        }
+        at = _nIns;
+        asm_cmp(cond);
+        return at;
+    }
+
+    void Assembler::asm_switch(LIns* ins, NIns* exit)
+    {
+        LIns* diff = ins->oprnd1();
+        findSpecificRegFor(diff, EDX);
+        JMP(exit);
+    }
+
+    // This generates a 'test' or 'cmp' instruction for a condition, which
+    // causes the condition codes to be set appropriately.  It's used with
+    // conditional branches, conditional moves, and when generating
+    // conditional values.  For example:
+    //
+    //   LIR:   eq1 = eq a, 0
+    //   LIR:   xf1: xf eq1 -> ...
+    //   asm:       test edx, edx       # generated by this function
+    //   asm:       je ...
+    //
+    // If this is the only use of eq1, then on entry 'cond' is *not* marked as
+    // used, and we do not allocate a register for it.  That's because its
+    // result ends up in the condition codes rather than a normal register.
+    // This doesn't get recorded in the regstate and so the asm code that
+    // consumes the result (eg. a conditional branch like 'je') must follow
+    // shortly after.
+    //
+    // If eq1 is instead used again later, we will also generate code
+    // (eg. in asm_cond()) to compute it into a normal register, something
+    // like this:
+    //
+    //   LIR:   eq1 = eq a, 0
+    //   LIR:       test edx, edx
+    //   asm:       sete ebx
+    //   asm:       movzx ebx, ebx        
+    //
+    // In this case we end up computing the condition twice, but that's ok, as
+    // it's just as short as testing eq1's value in the code generated for the
+    // guard.
+    //
+    void Assembler::asm_cmp(LIns *cond)
+    {
+        LOpcode condop = cond->opcode();
+
+        // LIR_ov recycles the flags set by arithmetic ops
+        if (condop == LIR_ov)
             return;
-        
+
         LInsp lhs = cond->oprnd1();
-		LInsp rhs = cond->oprnd2();
-		Reservation *rA, *rB;
-
-		NanoAssert((!lhs->isQuad() && !rhs->isQuad()) || (lhs->isQuad() && rhs->isQuad()));
-
-		// Not supported yet.
-		NanoAssert(!lhs->isQuad() && !rhs->isQuad());
-
-		// ready to issue the compare
-		if (rhs->isconst())
-		{
-			int c = rhs->constval();
-			if (c == 0 && cond->isop(LIR_eq)) {
-				Register r = findRegFor(lhs, GpRegs);
-				TEST(r,r);
-			}
-			else if (!rhs->isQuad()) {
-				Register r = getBaseReg(lhs, c, GpRegs);
-				CMPi(r, c);
-			}
-		}
-		else
-		{
-			findRegFor2(GpRegs, lhs, rA, rhs, rB);
-			Register ra = rA->reg;
-			Register rb = rB->reg;
-			CMP(ra, rb);
-		}
-	}
-
-	void Assembler::asm_loop(LInsp ins, NInsList& loopJumps)
-	{
-		JMP_long(0);
-        loopJumps.add(_nIns);
-
-		// If the target we are looping to is in a different fragment, we have to restore
-		// SP since we will target fragEntry and not loopEntry.
-	    if (ins->record()->exit->target != _thisfrag)
-	        MR(SP,FP);
-	}	
-
-	void Assembler::asm_fcond(LInsp ins)
-	{
-		// only want certain regs 
-		Register r = prepResultReg(ins, AllowableFlagRegs);
-		asm_setcc(r, ins);
-
-		// SETcc only sets low 8 bits, so extend 
-		MOVZX8(r,r);
-		SETNP(r);
-
-		asm_fcmp(ins);
-	}
-				
-	void Assembler::asm_cond(LInsp ins)
-	{
-		// only want certain regs 
-		LOpcode op = ins->opcode();			
-		Register r = prepResultReg(ins, AllowableFlagRegs);
-		// SETcc only sets low 8 bits, so extend 
-		MOVZX8(r,r);
-		if (op == LIR_eq)
-			SETE(r);
-		else if (op == LIR_ov)
-			SETO(r);
-		else if (op == LIR_cs)
-			SETC(r);
-		else if (op == LIR_lt)
-			SETL(r);
-		else if (op == LIR_le)
-			SETLE(r);
-		else if (op == LIR_gt)
-			SETG(r);
-		else if (op == LIR_ge)
-			SETGE(r);
-		else if (op == LIR_ult)
-			SETB(r);
-		else if (op == LIR_ule)
-			SETBE(r);
-		else if (op == LIR_ugt)
-			SETA(r);
-		else // if (op == LIR_uge)
-			SETAE(r);
-		asm_cmp(ins);
-	}
-	
-	void Assembler::asm_arith(LInsp ins)
-	{
-		LOpcode op = ins->opcode();			
-		LInsp lhs = ins->oprnd1();
-		LInsp rhs = ins->oprnd2();
-
-		Register rb = UnknownReg;
-		RegisterMask allow = GpRegs;
-		bool forceReg = (op == LIR_mul || !rhs->isconst());
-
-        /* Even if lhs == rhs && forceReg, shift instructions require ECX on the rhs. */
-		if ((lhs != rhs || (op == LIR_lsh || op == LIR_rsh || op == LIR_ush)) && forceReg)
-		{
-			if ((rb = asm_binop_rhs_reg(ins)) == UnknownReg) {
-				rb = findRegFor(rhs, allow);
-			}
-			allow &= ~rmask(rb);
-		}
-		else if ((op == LIR_add||op == LIR_addp) && lhs->isop(LIR_alloc) && rhs->isconst()) {
-			// add alloc+const, use lea
-			Register rr = prepResultReg(ins, allow);
-			int d = findMemFor(lhs) + rhs->constval();
-			LEA(rr, d, FP);
-			return;
-		}
-
-		Register rr = prepResultReg(ins, allow);
-		Reservation* rA = getresv(lhs);
-		Register ra;
-		// if this is last use of lhs in reg, we can re-use result reg
-		if (rA == 0 || (ra = rA->reg) == UnknownReg)
-			ra = findSpecificRegFor(lhs, rr);
-		// else, rA already has a register assigned.
-
-		if (forceReg)
-		{
-			if (lhs == rhs)
-				rb = ra;
-
-			switch (op) {
-			case LIR_add:
-			case LIR_addp:
-				ADD(rr, rb);
-				break;
-			case LIR_sub:
-				SUB(rr, rb);
-				break;
-			case LIR_mul:
-				MUL(rr, rb);
-				break;
-			case LIR_and:
-				AND(rr, rb);
-				break;
-			case LIR_or:
-				OR(rr, rb);
-				break;
-			case LIR_xor:
-				XOR(rr, rb);
-				break;
-			case LIR_lsh:
-				SHL(rr, rb);
-				break;
-			case LIR_rsh:
-				SAR(rr, rb);
-				break;
-			case LIR_ush:
-				SHR(rr, rb);
-				break;
-			default:
-				NanoAssertMsg(0, "Unsupported");
-			}
-		}
-		else
-		{
-			int c = rhs->constval();
-			switch (op) {
-			case LIR_addp:
-				// this doesn't set cc's, only use it when cc's not required.
-				LEA(rr, c, ra);
-				ra = rr; // suppress mov
-				break;
-			case LIR_add:
-				ADDi(rr, c); 
-				break;
-			case LIR_sub:
-				SUBi(rr, c);
-				break;
-			case LIR_and:
-				ANDi(rr, c);
-				break;
-			case LIR_or:
-				ORi(rr, c);
-				break;
-			case LIR_xor:
-				XORi(rr, c);
-				break;
-			case LIR_lsh:
-				SHLi(rr, c);
-				break;
-			case LIR_rsh:
-				SARi(rr, c);
-				break;
-			case LIR_ush:
-				SHRi(rr, c);
-				break;
-			default:
-				NanoAssertMsg(0, "Unsupported");
-				break;
-			}
-		}
-
-		if ( rr != ra ) 
-			MR(rr,ra);
-	}
-	
-	void Assembler::asm_neg_not(LInsp ins)
-	{
-		LOpcode op = ins->opcode();			
-		Register rr = prepResultReg(ins, GpRegs);
-
-		LIns* lhs = ins->oprnd1();
-		Reservation *rA = getresv(lhs);
-		// if this is last use of lhs in reg, we can re-use result reg
-		Register ra;
-		if (rA == 0 || (ra=rA->reg) == UnknownReg)
-			ra = findSpecificRegFor(lhs, rr);
-		// else, rA already has a register assigned.
-
-		if (op == LIR_not)
-			NOT(rr); 
-		else
-			NEG(rr); 
-
-		if ( rr != ra ) 
-			MR(rr,ra); 
-	}
-				
-	void Assembler::asm_ld(LInsp ins)
-	{
-		LOpcode op = ins->opcode();			
-		LIns* base = ins->oprnd1();
-		LIns* disp = ins->oprnd2();
-		Register rr = prepResultReg(ins, GpRegs);
-		int d = disp->constval();
-
-		if (base->isconst()) {
-			intptr_t addr = base->constval();
-			addr += d;
-			if (op == LIR_ldcb)
-				LD8Zdm(rr, addr);
-			else if (op == LIR_ldcs)
-				LD16Zdm(rr, addr);
-			else
-				LDdm(rr, addr);
-			return;
-		}
-
-		/* Search for add(X,Y) */
-		if (base->opcode() == LIR_piadd) {
-			int scale = 0;
-			LIns *lhs = base->oprnd1();
-			LIns *rhs = base->oprnd2();
-
-			/* See if we can bypass any SHLs, by searching for 
-			 * add(X, shl(Y,Z)) -> mov r, [X+Y*Z]
-			 */
-			if (rhs->opcode() == LIR_pilsh && rhs->oprnd2()->isconst()) {
-				scale = rhs->oprnd2()->constval();
-				if (scale >= 1 && scale <= 3)
-					rhs = rhs->oprnd1();
-				else
-					scale = 0;
-			}
-
-			Register rleft;
-			Reservation *rL = getresv(lhs);
-
-			/* Does LHS have a register yet? If not, re-use the result reg.
-			 * @todo -- If LHS is const, we could eliminate a register use.  
-			 */
-			if (rL == NULL || rL->reg == UnknownReg)
-				rleft = findSpecificRegFor(lhs, rr);
-			else
-				rleft = rL->reg;
-
-			Register rright = UnknownReg;
-			Reservation *rR = getresv(rhs);
-
-			/* Does RHS have a register yet? If not, try to re-use the result reg. */
-			if (rr != rleft && (rR == NULL || rR->reg == UnknownReg))
-				rright = findSpecificRegFor(rhs, rr);
-			if (rright == UnknownReg)
-				rright = findRegFor(rhs, GpRegs & ~(rmask(rleft)));
-
-			if (op == LIR_ldcb)
-				LD8Zsib(rr, d, rleft, rright, scale);
-			else if (op == LIR_ldcs)
-				LD16Zsib(rr, d, rleft, rright, scale);
-			else
-				LDsib(rr, d, rleft, rright, scale);
-
-			return;
-		}
-
-		Register ra = getBaseReg(base, d, GpRegs);
-		if (op == LIR_ldcb)
-			LD8Z(rr, d, ra);
-		else if (op == LIR_ldcs)
-		    LD16Z(rr, d, ra);
-		else 
-			LD(rr, d, ra); 
-	}
-
-	void Assembler::asm_cmov(LInsp ins)
-	{
-		LOpcode op = ins->opcode();			
-		LIns* condval = ins->oprnd1();
-		NanoAssert(condval->isCmp());
-
-		LIns* values = ins->oprnd2();
-
-		NanoAssert(values->opcode() == LIR_2);
-		LIns* iftrue = values->oprnd1();
-		LIns* iffalse = values->oprnd2();
-
-		NanoAssert(op == LIR_qcmov || (!iftrue->isQuad() && !iffalse->isQuad()));
-		
-		const Register rr = prepResultReg(ins, GpRegs);
-
-		// this code assumes that neither LD nor MR nor MRcc set any of the condition flags.
-		// (This is true on Intel, is it true on all architectures?)
-		const Register iffalsereg = findRegFor(iffalse, GpRegs & ~rmask(rr));
-		if (op == LIR_cmov) {
-			switch (condval->opcode())
-			{
-				// note that these are all opposites...
-				case LIR_eq:	MRNE(rr, iffalsereg);	break;
-				case LIR_ov:    MRNO(rr, iffalsereg);   break;
-				case LIR_cs:    MRNC(rr, iffalsereg);   break;
-				case LIR_lt:	MRGE(rr, iffalsereg);	break;
-				case LIR_le:	MRG(rr, iffalsereg);	break;
-				case LIR_gt:	MRLE(rr, iffalsereg);	break;
-				case LIR_ge:	MRL(rr, iffalsereg);	break;
-				case LIR_ult:	MRAE(rr, iffalsereg);	break;
-				case LIR_ule:	MRA(rr, iffalsereg);	break;
-				case LIR_ugt:	MRBE(rr, iffalsereg);	break;
-				case LIR_uge:	MRB(rr, iffalsereg);	break;
-			    default: debug_only( NanoAssert(0); ) break;
-			}
-		} else if (op == LIR_qcmov) {
-			NanoAssert(0);
-		}
-		/*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr);
-		asm_cmp(condval);
-	}
-				
-	void Assembler::asm_qhi(LInsp ins)
-	{
-		Register rr = prepResultReg(ins, GpRegs);
-		LIns *q = ins->oprnd1();
-		int d = findMemFor(q);
-		LD(rr, d+4, FP);
-	}
-
-	void Assembler::asm_param(LInsp ins)
-	{
-		uint32_t a = ins->imm8();
-		uint32_t kind = ins->imm8b();
-		if (kind == 0) {
-			// ordinary param
-			AbiKind abi = _thisfrag->lirbuf->abi;
-			uint32_t abi_regcount = max_abi_regs[abi];
-			if (a < abi_regcount) {
-				// incoming arg in register
-				prepResultReg(ins, rmask(argRegs[a]));
-			} else {
-				// incoming arg is on stack, and EBP points nearby (see genPrologue)
-				Register r = prepResultReg(ins, GpRegs);
-				int d = (a - abi_regcount) * sizeof(intptr_t) + 8;
-				LD(r, d, FP); 
-			}
-		}
-		else {
-			// saved param
-			prepResultReg(ins, rmask(savedRegs[a]));
-		}
-	}
-
-	void Assembler::asm_short(LInsp ins)
-	{
-		Register rr = prepResultReg(ins, GpRegs);
-		int32_t val = ins->imm16();
-		if (val == 0)
-			XOR(rr,rr);
-		else
-			LDi(rr, val);
-	}
-
-	void Assembler::asm_int(LInsp ins)
-	{
-		Register rr = prepResultReg(ins, GpRegs);
-		int32_t val = ins->imm32();
-		if (val == 0)
-			XOR(rr,rr);
-		else
-			LDi(rr, val);
-	}
-
-	void Assembler::asm_quad(LInsp ins)
-	{
-    	Reservation *rR = getresv(ins);
-		Register rr = rR->reg;
-		if (rr != UnknownReg)
-		{
-			// @todo -- add special-cases for 0 and 1
-			_allocator.retire(rr);
-			rR->reg = UnknownReg;
-			NanoAssert((rmask(rr) & FpRegs) != 0);
-
-			const double d = ins->constvalf();
-            const uint64_t q = ins->constvalq();
-			if (rmask(rr) & XmmRegs) {
-				if (q == 0.0) {
+        LInsp rhs = cond->oprnd2();
+
+        NanoAssert((!lhs->isQuad() && !rhs->isQuad()) || (lhs->isQuad() && rhs->isQuad()));
+
+        // Not supported yet.
+        NanoAssert(!lhs->isQuad() && !rhs->isQuad());
+
+        // ready to issue the compare
+        if (rhs->isconst())
+        {
+            int c = rhs->imm32();
+            if (c == 0 && cond->isop(LIR_eq)) {
+                Register r = findRegFor(lhs, GpRegs);
+                TEST(r,r);
+            } else if (!rhs->isQuad()) {
+                Register r = getBaseReg(lhs, c, GpRegs);
+                CMPi(r, c);
+            }
+        }
+        else
+        {
+            Register ra, rb;
+            findRegFor2b(GpRegs, lhs, ra, rhs, rb);
+            CMP(ra, rb);
+        }
+    }
+
+    void Assembler::asm_fcond(LInsp ins)
+    {
+        // only want certain regs
+        Register r = prepResultReg(ins, AllowableFlagRegs);
+        asm_setcc(r, ins);
+
+        // SETcc only sets low 8 bits, so extend
+        MOVZX8(r,r);
+        SETNP(r);
+
+        asm_fcmp(ins);
+    }
+
+    void Assembler::asm_cond(LInsp ins)
+    {
+        // only want certain regs
+        LOpcode op = ins->opcode();
+        Register r = prepResultReg(ins, AllowableFlagRegs);
+        // SETcc only sets low 8 bits, so extend
+        MOVZX8(r,r);
+        if (op == LIR_eq)
+            SETE(r);
+        else if (op == LIR_ov)
+            SETO(r);
+        else if (op == LIR_lt)
+            SETL(r);
+        else if (op == LIR_le)
+            SETLE(r);
+        else if (op == LIR_gt)
+            SETG(r);
+        else if (op == LIR_ge)
+            SETGE(r);
+        else if (op == LIR_ult)
+            SETB(r);
+        else if (op == LIR_ule)
+            SETBE(r);
+        else if (op == LIR_ugt)
+            SETA(r);
+        else // if (op == LIR_uge)
+            SETAE(r);
+        asm_cmp(ins);
+    }
+
+    void Assembler::asm_arith(LInsp ins)
+    {
+        LOpcode op = ins->opcode();
+        LInsp lhs = ins->oprnd1();
+
+        if (op == LIR_mod) {
+            asm_div_mod(ins);
+            return;
+        }
+
+        LInsp rhs = ins->oprnd2();
+
+        bool forceReg;
+        RegisterMask allow = GpRegs;
+        Register rb = UnknownReg;
+
+        switch (op) {
+        case LIR_div:
+            // Nb: if the div feeds into a mod it will be handled by
+            // asm_div_mod() rather than here.
+            forceReg = true;
+            rb = findRegFor(rhs, (GpRegs ^ (rmask(EAX)|rmask(EDX))));
+            allow = rmask(EAX);
+            evictIfActive(EDX);
+            break;
+        case LIR_mul:
+            forceReg = true;
+            break;
+        case LIR_lsh:
+        case LIR_rsh:
+        case LIR_ush:
+            forceReg = !rhs->isconst();
+            if (forceReg) {
+                rb = findSpecificRegFor(rhs, ECX);
+                allow &= ~rmask(rb);
+            }
+            break;
+        case LIR_add:
+        case LIR_addp:
+            if (lhs->isop(LIR_alloc) && rhs->isconst()) {
+                // add alloc+const, use lea
+                Register rr = prepResultReg(ins, allow);
+                int d = findMemFor(lhs) + rhs->imm32();
+                LEA(rr, d, FP);
+                return;
+            }
+            /* fall through */
+        default:
+            forceReg = !rhs->isconst();
+            break;
+        }
+
+        // if we need a register for the rhs and don't have one yet, get it
+        if (forceReg && lhs != rhs && !isKnownReg(rb)) {
+            rb = findRegFor(rhs, allow);
+            allow &= ~rmask(rb);
+        }
+
+        Register rr = prepResultReg(ins, allow);
+        // if this is last use of lhs in reg, we can re-use result reg
+        // else, lhs already has a register assigned.
+        Register ra = ( lhs->isUnusedOrHasUnknownReg()
+                      ? findSpecificRegFor(lhs, rr)
+                      : lhs->getReg() );
+
+        if (forceReg)
+        {
+            if (lhs == rhs)
+                rb = ra;
+
+            switch (op) {
+            case LIR_add:
+            case LIR_addp:
+                ADD(rr, rb);
+                break;
+            case LIR_sub:
+                SUB(rr, rb);
+                break;
+            case LIR_mul:
+                MUL(rr, rb);
+                break;
+            case LIR_and:
+                AND(rr, rb);
+                break;
+            case LIR_or:
+                OR(rr, rb);
+                break;
+            case LIR_xor:
+                XOR(rr, rb);
+                break;
+            case LIR_lsh:
+                SHL(rr, rb);
+                break;
+            case LIR_rsh:
+                SAR(rr, rb);
+                break;
+            case LIR_ush:
+                SHR(rr, rb);
+                break;
+            case LIR_div:
+                DIV(rb);
+                CDQ();
+                break;
+            default:
+                NanoAssertMsg(0, "Unsupported");
+            }
+        }
+        else
+        {
+            int c = rhs->imm32();
+            switch (op) {
+            case LIR_addp:
+                // this doesn't set cc's, only use it when cc's not required.
+                LEA(rr, c, ra);
+                ra = rr; // suppress mov
+                break;
+            case LIR_add:
+                ADDi(rr, c);
+                break;
+            case LIR_sub:
+                SUBi(rr, c);
+                break;
+            case LIR_and:
+                ANDi(rr, c);
+                break;
+            case LIR_or:
+                ORi(rr, c);
+                break;
+            case LIR_xor:
+                XORi(rr, c);
+                break;
+            case LIR_lsh:
+                SHLi(rr, c);
+                break;
+            case LIR_rsh:
+                SARi(rr, c);
+                break;
+            case LIR_ush:
+                SHRi(rr, c);
+                break;
+            default:
+                NanoAssertMsg(0, "Unsupported");
+                break;
+            }
+        }
+
+        if ( rr != ra )
+            MR(rr,ra);
+    }
+
+    // This is called when we have a mod(div(divLhs, divRhs)) sequence.
+    void Assembler::asm_div_mod(LInsp mod)
+    {
+        LInsp div = mod->oprnd1();
+
+        // LIR_mod expects the LIR_div to be near (no interference from the register allocator)
+
+        NanoAssert(mod->isop(LIR_mod));
+        NanoAssert(div->isop(LIR_div));
+
+        LInsp divLhs = div->oprnd1();
+        LInsp divRhs = div->oprnd2();
+
+        prepResultReg(mod, rmask(EDX));
+        prepResultReg(div, rmask(EAX));
+
+        Register rDivRhs = findRegFor(divRhs, (GpRegs ^ (rmask(EAX)|rmask(EDX))));
+
+        Register rDivLhs = ( divLhs->isUnusedOrHasUnknownReg()
+                           ? findSpecificRegFor(divLhs, EAX)
+                           : divLhs->getReg() );
+
+        DIV(rDivRhs);
+        CDQ();     // sign-extend EAX into EDX:EAX
+
+        if ( EAX != rDivLhs )
+            MR(EAX, rDivLhs);
+    }
+
+    void Assembler::asm_neg_not(LInsp ins)
+    {
+        LOpcode op = ins->opcode();
+        Register rr = prepResultReg(ins, GpRegs);
+
+        LIns* lhs = ins->oprnd1();
+        // if this is last use of lhs in reg, we can re-use result reg
+        // else, lhs already has a register assigned.
+        Register ra = ( lhs->isUnusedOrHasUnknownReg()
+                      ? findSpecificRegFor(lhs, rr)
+                      : lhs->getReg() );
+
+        if (op == LIR_not)
+            NOT(rr);
+        else
+            NEG(rr);
+
+        if ( rr != ra )
+            MR(rr,ra);
+    }
+
+    void Assembler::asm_ld(LInsp ins)
+    {
+        LOpcode op = ins->opcode();
+        LIns* base = ins->oprnd1();
+        int32_t d = ins->disp();
+        Register rr = prepResultReg(ins, GpRegs);
+
+        if (base->isconst()) {
+            intptr_t addr = base->imm32();
+            addr += d;
+            if (op == LIR_ldcb)
+                LD8Zdm(rr, addr);
+            else if (op == LIR_ldcs)
+                LD16Zdm(rr, addr);
+            else
+                LDdm(rr, addr);
+            return;
+        }
+
+        /* Search for add(X,Y) */
+        if (base->opcode() == LIR_piadd) {
+            int scale = 0;
+            LIns *lhs = base->oprnd1();
+            LIns *rhs = base->oprnd2();
+
+            /* See if we can bypass any SHLs, by searching for
+             * add(X, shl(Y,Z)) -> mov r, [X+Y*Z]
+             */
+            if (rhs->opcode() == LIR_pilsh && rhs->oprnd2()->isconst()) {
+                scale = rhs->oprnd2()->imm32();
+                if (scale >= 1 && scale <= 3)
+                    rhs = rhs->oprnd1();
+                else
+                    scale = 0;
+            }
+
+            /* Does LHS have a register yet? If not, re-use the result reg.
+             * @todo -- If LHS is const, we could eliminate a register use.
+             */
+            Register rleft = ( lhs->isUnusedOrHasUnknownReg()
+                             ? findSpecificRegFor(lhs, rr)
+                             : lhs->getReg() );
+
+            /* Does RHS have a register yet? If not, try to re-use the result reg. */
+            Register rright = ( rr != rleft && rhs->isUnusedOrHasUnknownReg()
+                              ? findSpecificRegFor(rhs, rr)
+                              : findRegFor(rhs, GpRegs & ~(rmask(rleft))) );
+
+            if (op == LIR_ldcb)
+                LD8Zsib(rr, d, rleft, rright, scale);
+            else if (op == LIR_ldcs)
+                LD16Zsib(rr, d, rleft, rright, scale);
+            else
+                LDsib(rr, d, rleft, rright, scale);
+
+            return;
+        }
+
+        Register ra = getBaseReg(base, d, GpRegs);
+        if (op == LIR_ldcb)
+            LD8Z(rr, d, ra);
+        else if (op == LIR_ldcs)
+            LD16Z(rr, d, ra);
+        else
+            LD(rr, d, ra);
+    }
+
+    void Assembler::asm_cmov(LInsp ins)
+    {
+        LOpcode op = ins->opcode();
+        LIns* condval = ins->oprnd1();
+        LIns* iftrue  = ins->oprnd2();
+        LIns* iffalse = ins->oprnd3();
+
+        NanoAssert(condval->isCmp());
+        NanoAssert(op == LIR_qcmov || (!iftrue->isQuad() && !iffalse->isQuad()));
+
+        const Register rr = prepResultReg(ins, GpRegs);
+
+        // this code assumes that neither LD nor MR nor MRcc set any of the condition flags.
+        // (This is true on Intel, is it true on all architectures?)
+        const Register iffalsereg = findRegFor(iffalse, GpRegs & ~rmask(rr));
+        if (op == LIR_cmov) {
+            switch (condval->opcode())
+            {
+                // note that these are all opposites...
+                case LIR_eq:    MRNE(rr, iffalsereg);   break;
+                case LIR_ov:    MRNO(rr, iffalsereg);   break;
+                case LIR_lt:    MRGE(rr, iffalsereg);   break;
+                case LIR_le:    MRG(rr, iffalsereg);    break;
+                case LIR_gt:    MRLE(rr, iffalsereg);   break;
+                case LIR_ge:    MRL(rr, iffalsereg);    break;
+                case LIR_ult:   MRAE(rr, iffalsereg);   break;
+                case LIR_ule:   MRA(rr, iffalsereg);    break;
+                case LIR_ugt:   MRBE(rr, iffalsereg);   break;
+                case LIR_uge:   MRB(rr, iffalsereg);    break;
+                default: NanoAssert(0); break;
+            }
+        } else if (op == LIR_qcmov) {
+            NanoAssert(0);
+        }
+        /*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr);
+        asm_cmp(condval);
+    }
+
+    void Assembler::asm_qhi(LInsp ins)
+    {
+        Register rr = prepResultReg(ins, GpRegs);
+        LIns *q = ins->oprnd1();
+        int d = findMemFor(q);
+        LD(rr, d+4, FP);
+    }
+
+    void Assembler::asm_param(LInsp ins)
+    {
+        uint32_t a = ins->paramArg();
+        uint32_t kind = ins->paramKind();
+        if (kind == 0) {
+            // ordinary param
+            AbiKind abi = _thisfrag->lirbuf->abi;
+            uint32_t abi_regcount = max_abi_regs[abi];
+            if (a < abi_regcount) {
+                // incoming arg in register
+                prepResultReg(ins, rmask(argRegs[a]));
+            } else {
+                // incoming arg is on stack, and EBP points nearby (see genPrologue)
+                Register r = prepResultReg(ins, GpRegs);
+                int d = (a - abi_regcount) * sizeof(intptr_t) + 8;
+                LD(r, d, FP);
+            }
+        }
+        else {
+            // saved param
+            prepResultReg(ins, rmask(savedRegs[a]));
+        }
+    }
+
+    void Assembler::asm_int(LInsp ins)
+    {
+        Register rr = prepResultReg(ins, GpRegs);
+        int32_t val = ins->imm32();
+        if (val == 0)
+            XOR(rr,rr);
+        else
+            LDi(rr, val);
+    }
+
+    void Assembler::asm_quad(LInsp ins)
+    {
+        Register rr = ins->getReg();
+        if (isKnownReg(rr))
+        {
+            // @todo -- add special-cases for 0 and 1
+            _allocator.retire(rr);
+            ins->setReg(UnknownReg);
+            NanoAssert((rmask(rr) & FpRegs) != 0);
+
+            const double d = ins->imm64f();
+            const uint64_t q = ins->imm64();
+            if (rmask(rr) & XmmRegs) {
+                if (q == 0.0) {
                     // test (int64)0 since -0.0 == 0.0
-					SSE_XORPDr(rr, rr);
-				} else if (d == 1.0) {
-					// 1.0 is extremely frequent and worth special-casing!
-					static const double k_ONE = 1.0;
-					LDSDm(rr, &k_ONE);
-				} else {
-					findMemFor(ins);
-					const int d = disp(rR);
-					SSE_LDQ(rr, d, FP);
-				}
-			} else {
-				if (q == 0.0) {
+                    SSE_XORPDr(rr, rr);
+                } else if (d == 1.0) {
+                    // 1.0 is extremely frequent and worth special-casing!
+                    static const double k_ONE = 1.0;
+                    LDSDm(rr, &k_ONE);
+                } else if (d && d == (int)d) {
+                    // can fit in 32bits? then use cvt which is faster
+                    Register gr = registerAlloc(GpRegs);
+                    SSE_CVTSI2SD(rr, gr);
+                    SSE_XORPDr(rr,rr);  // zero rr to ensure no dependency stalls
+                    LDi(gr, (int)d);
+                    _allocator.addFree(gr);
+                } else {
+                    findMemFor(ins);
+                    const int d = disp(ins);
+                    SSE_LDQ(rr, d, FP);
+                }
+            } else {
+                if (q == 0.0) {
                     // test (int64)0 since -0.0 == 0.0
-					FLDZ();
-				} else if (d == 1.0) {
-					FLD1();
-				} else {
-					findMemFor(ins);
-					int d = disp(rR);
-					FLDQ(d,FP);
-				}
-			}
-		}
-
-		// @todo, if we used xor, ldsd, fldz, etc above, we don't need mem here
-		int d = disp(rR);
-		freeRsrcOf(ins, false);
-		if (d)
-		{
-			const int32_t* p = (const int32_t*) (ins-2);
-			STi(FP,d+4,p[1]);
-			STi(FP,d,p[0]);
-		}
-	}
-	
-	void Assembler::asm_qlo(LInsp ins)
-	{
-		LIns *q = ins->oprnd1();
-
-		if (!config.sse2)
-		{
-			Register rr = prepResultReg(ins, GpRegs);
-			int d = findMemFor(q);
-			LD(rr, d, FP);
-		}
-		else
-		{
-			Reservation *resv = getresv(ins);
-			Register rr = resv->reg;
-			if (rr == UnknownReg) {
-				// store quad in spill loc
-				int d = disp(resv);
-				freeRsrcOf(ins, false);
-				Register qr = findRegFor(q, XmmRegs);
-				SSE_MOVDm(d, FP, qr);
-			} else {
-				freeRsrcOf(ins, false);
-				Register qr = findRegFor(q, XmmRegs);
-				SSE_MOVD(rr,qr);
-			}
-		}
-	}
-
-	void Assembler::asm_fneg(LInsp ins)
-	{
-		if (config.sse2)
-		{
-			LIns *lhs = ins->oprnd1();
-
-			Register rr = prepResultReg(ins, XmmRegs);
-			Reservation *rA = getresv(lhs);
-			Register ra;
-
-			// if this is last use of lhs in reg, we can re-use result reg
-			if (rA == 0 || (ra = rA->reg) == UnknownReg) {
-				ra = findSpecificRegFor(lhs, rr);
-			} else if ((rmask(ra) & XmmRegs) == 0) {
-				/* We need this case on AMD64, because it's possible that 
-				 * an earlier instruction has done a quadword load and reserved a 
-				 * GPR.  If so, ask for a new register.
-				 */
-				ra = findRegFor(lhs, XmmRegs);
-			}
-			// else, rA already has a register assigned.
+                    FLDZ();
+                } else if (d == 1.0) {
+                    FLD1();
+                } else {
+                    findMemFor(ins);
+                    int d = disp(ins);
+                    FLDQ(d,FP);
+                }
+            }
+        }
+
+        // @todo, if we used xor, ldsd, fldz, etc above, we don't need mem here
+        int d = disp(ins);
+        freeRsrcOf(ins, false);
+        if (d)
+        {
+            STi(FP,d+4,ins->imm64_1());
+            STi(FP,d,  ins->imm64_0());
+        }
+    }
+
+    void Assembler::asm_qlo(LInsp ins)
+    {
+        LIns *q = ins->oprnd1();
+
+        if (!config.sse2)
+        {
+            Register rr = prepResultReg(ins, GpRegs);
+            int d = findMemFor(q);
+            LD(rr, d, FP);
+        }
+        else
+        {
+            Register rr = ins->getReg();
+            if (!isKnownReg(rr)) {
+                // store quad in spill loc
+                int d = disp(ins);
+                freeRsrcOf(ins, false);
+                Register qr = findRegFor(q, XmmRegs);
+                SSE_MOVDm(d, FP, qr);
+            } else {
+                freeRsrcOf(ins, false);
+                Register qr = findRegFor(q, XmmRegs);
+                SSE_MOVD(rr,qr);
+            }
+        }
+    }
+
+    void Assembler::asm_fneg(LInsp ins)
+    {
+        if (config.sse2)
+        {
+            LIns *lhs = ins->oprnd1();
+
+            Register rr = prepResultReg(ins, XmmRegs);
+            Register ra;
+
+            // if this is last use of lhs in reg, we can re-use result reg
+            // else, lhs already has a register assigned.
+            if (lhs->isUnusedOrHasUnknownReg()) {
+                ra = findSpecificRegFor(lhs, rr);
+            } else {
+                ra = lhs->getReg();
+                if ((rmask(ra) & XmmRegs) == 0) {
+                    /* We need this case on AMD64, because it's possible that
+                     * an earlier instruction has done a quadword load and reserved a
+                     * GPR.  If so, ask for a new register.
+                     */
+                    ra = findRegFor(lhs, XmmRegs);
+                }
+            }
 
 #if defined __SUNPRO_CC
-			// from Sun Studio C++ Readme: #pragma align inside namespace requires mangled names
-			static uint32_t temp[] = {0, 0, 0, 0, 0, 0, 0};
-			static uint32_t *negateMask = (uint32_t *)alignUp(temp, 16);
-			negateMask[1] = 0x80000000;
+            // from Sun Studio C++ Readme: #pragma align inside namespace requires mangled names
+            static uint32_t temp[] = {0, 0, 0, 0, 0, 0, 0};
+            static uint32_t *negateMask = (uint32_t *)alignUp(temp, 16);
+            negateMask[1] = 0x80000000;
 #else
-			static const AVMPLUS_ALIGN16(uint32_t) negateMask[] = {0,0x80000000,0,0};
+            static const AVMPLUS_ALIGN16(uint32_t) negateMask[] = {0,0x80000000,0,0};
 #endif
-			SSE_XORPD(rr, negateMask);
+            SSE_XORPD(rr, negateMask);
 
-			if (rr != ra)
-				SSE_MOVSD(rr, ra);
-		}
-		else
-		{
-			Register rr = prepResultReg(ins, FpRegs);
+            if (rr != ra)
+                SSE_MOVSD(rr, ra);
+        }
+        else
+        {
+            Register rr = prepResultReg(ins, FpRegs);
 
-			LIns* lhs = ins->oprnd1();
+            LIns* lhs = ins->oprnd1();
 
-			// lhs into reg, prefer same reg as result
-			Reservation* rA = getresv(lhs);
-			// if this is last use of lhs in reg, we can re-use result reg
-			if (rA == 0 || rA->reg == UnknownReg)
-				findSpecificRegFor(lhs, rr);
-			// else, rA already has a different reg assigned
+            // lhs into reg, prefer same reg as result
 
-			NanoAssert(getresv(lhs)!=0 && getresv(lhs)->reg==FST0);
-			// assume that the lhs is in ST(0) and rhs is on stack
-			FCHS();
+            // if this is last use of lhs in reg, we can re-use result reg
+            // else, lhs already has a different reg assigned
+            if (lhs->isUnusedOrHasUnknownReg())
+                findSpecificRegFor(lhs, rr);
 
-			// if we had more than one fpu reg, this is where
-			// we would move ra into rr if rr != ra.
-		}
-	}
+            NanoAssert(lhs->getReg()==FST0);
+            // assume that the lhs is in ST(0) and rhs is on stack
+            FCHS();
+
+            // if we had more than one fpu reg, this is where
+            // we would move ra into rr if rr != ra.
+        }
+    }
 
     void Assembler::asm_arg(ArgSize sz, LInsp p, Register r)
     {
-        if (sz == ARGSIZE_Q) 
+        if (sz == ARGSIZE_Q)
         {
-			// ref arg - use lea
-			if (r != UnknownReg)
-			{
-				// arg in specific reg
-				int da = findMemFor(p);
-				LEA(r, da, FP);
-			}
-			else
-			{
-				NanoAssert(0); // not supported
-			}
-		}
-        else if (sz == ARGSIZE_LO)
-		{
-			if (r != UnknownReg) {
-				// arg goes in specific register
+            // ref arg - use lea
+            if (isKnownReg(r))
+            {
+                // arg in specific reg
+                int da = findMemFor(p);
+                LEA(r, da, FP);
+            }
+            else
+            {
+                NanoAssert(0); // not supported
+            }
+        }
+        else if (sz == ARGSIZE_I || sz == ARGSIZE_U)
+        {
+            if (isKnownReg(r)) {
+                // arg goes in specific register
                 if (p->isconst()) {
-					LDi(r, p->constval());
+                    LDi(r, p->imm32());
                 } else {
-            		Reservation* rA = getresv(p);
-                    if (rA) {
-                        if (rA->reg == UnknownReg) {
+                    if (p->isUsed()) {
+                        if (!p->hasKnownReg()) {
                             // load it into the arg reg
                             int d = findMemFor(p);
                             if (p->isop(LIR_alloc)) {
@@ -1310,252 +1324,249 @@ namespace nanojit
                             }
                         } else {
                             // it must be in a saved reg
-                            MR(r, rA->reg);
+                            MR(r, p->getReg());
                         }
-                    } 
+                    }
                     else {
                         // this is the last use, so fine to assign it
                         // to the scratch reg, it's dead after this point.
-    					findSpecificRegFor(p, r);
+                        findSpecificRegFor(p, r);
                     }
                 }
-			}
+            }
             else {
-				asm_pusharg(p);
-			}
-		}
+                asm_pusharg(p);
+            }
+        }
         else
-		{
+        {
             NanoAssert(sz == ARGSIZE_F);
-			asm_farg(p);
-		}
+            asm_farg(p);
+        }
     }
 
-	void Assembler::asm_pusharg(LInsp p)
-	{
-		// arg goes on stack
-		Reservation* rA = getresv(p);
-		if (rA == 0 && p->isconst())
-		{
-			// small const we push directly
-			PUSHi(p->constval());
-		}
-		else if (rA == 0 || p->isop(LIR_alloc))
-		{
-			Register ra = findRegFor(p, GpRegs);
-			PUSHr(ra);
-		}
-		else if (rA->reg == UnknownReg)
-		{
-			PUSHm(disp(rA), FP);
-		}
-		else
-		{
-			PUSHr(rA->reg);
-		}
-	}
-
-	void Assembler::asm_farg(LInsp p)
-	{
+    void Assembler::asm_pusharg(LInsp p)
+    {
+        // arg goes on stack
+        if (!p->isUsed() && p->isconst())
+        {
+            // small const we push directly
+            PUSHi(p->imm32());
+        }
+        else if (!p->isUsed() || p->isop(LIR_alloc))
+        {
+            Register ra = findRegFor(p, GpRegs);
+            PUSHr(ra);
+        }
+        else if (!p->hasKnownReg())
+        {
+            PUSHm(disp(p), FP);
+        }
+        else
+        {
+            PUSHr(p->getReg());
+        }
+    }
+
+    void Assembler::asm_farg(LInsp p)
+    {
         NanoAssert(p->isQuad());
-		Register r = findRegFor(p, FpRegs);
-		if (rmask(r) & XmmRegs) {
-			SSE_STQ(0, SP, r); 
-		} else {
-			FSTPQ(0, SP);
-			/* It's possible that the same LIns* with r=FST0 will appear in the argument list more 
-			 * than once.  In this case FST0 will not have been evicted and the multiple pop 
-			 * actions will unbalance the FPU stack.  A quick fix is to always evict FST0 manually.
-			 */
-			evict(FST0);
-		}
+        Register r = findRegFor(p, FpRegs);
+        if (rmask(r) & XmmRegs) {
+            SSE_STQ(0, SP, r);
+        } else {
+            FSTPQ(0, SP);
+            /* It's possible that the same LIns* with r=FST0 will appear in the argument list more
+             * than once.  In this case FST0 will not have been evicted and the multiple pop
+             * actions will unbalance the FPU stack.  A quick fix is to always evict FST0 manually.
+             */
+            evictIfActive(FST0);
+        }
         SUBi(ESP,8);
-	}
-
-	void Assembler::asm_fop(LInsp ins)
-	{
-		LOpcode op = ins->opcode();
-		if (config.sse2)
-		{
-			LIns *lhs = ins->oprnd1();
-			LIns *rhs = ins->oprnd2();
-
-			RegisterMask allow = XmmRegs;
-			Register rb = UnknownReg;
-			if (lhs != rhs) {
-				rb = findRegFor(rhs,allow);
-				allow &= ~rmask(rb);
-			}
-
-			Register rr = prepResultReg(ins, allow);
-			Reservation *rA = getresv(lhs);
-			Register ra;
-
-			// if this is last use of lhs in reg, we can re-use result reg
-			if (rA == 0 || (ra = rA->reg) == UnknownReg) {
-				ra = findSpecificRegFor(lhs, rr);
-			} else if ((rmask(ra) & XmmRegs) == 0) {
-				/* We need this case on AMD64, because it's possible that 
-				 * an earlier instruction has done a quadword load and reserved a 
-				 * GPR.  If so, ask for a new register.
-				 */
-				ra = findRegFor(lhs, XmmRegs);
-			}
-            else {
-    			// rA already has a register assigned but maybe not from the allow set
+    }
+
+    void Assembler::asm_fop(LInsp ins)
+    {
+        LOpcode op = ins->opcode();
+        if (config.sse2)
+        {
+            LIns *lhs = ins->oprnd1();
+            LIns *rhs = ins->oprnd2();
+
+            RegisterMask allow = XmmRegs;
+            Register rb = UnknownReg;
+            if (lhs != rhs) {
+                rb = findRegFor(rhs,allow);
+                allow &= ~rmask(rb);
+            }
+
+            Register rr = prepResultReg(ins, allow);
+            Register ra;
+
+            // if this is last use of lhs in reg, we can re-use result reg
+            if (lhs->isUnusedOrHasUnknownReg()) {
+                ra = findSpecificRegFor(lhs, rr);
+            } else if ((rmask(lhs->getReg()) & XmmRegs) == 0) {
+                // We need this case on AMD64, because it's possible that
+                // an earlier instruction has done a quadword load and reserved a
+                // GPR.  If so, ask for a new register.
+                ra = findRegFor(lhs, XmmRegs);
+            } else {
+                // lhs already has a register assigned but maybe not from the allow set
                 ra = findRegFor(lhs, allow);
             }
 
-			if (lhs == rhs)
-				rb = ra;
-
-			if (op == LIR_fadd)
-				SSE_ADDSD(rr, rb);
-			else if (op == LIR_fsub)
-				SSE_SUBSD(rr, rb);
-			else if (op == LIR_fmul)
-				SSE_MULSD(rr, rb);
-			else //if (op == LIR_fdiv)
-				SSE_DIVSD(rr, rb);
-
-			if (rr != ra)
-				SSE_MOVSD(rr, ra);
-		}
-		else
-		{
-			// we swap lhs/rhs on purpose here, works out better
-			// if you only have one fpu reg.  use divr/subr.
-			LIns* rhs = ins->oprnd1();
-			LIns* lhs = ins->oprnd2();
-			Register rr = prepResultReg(ins, rmask(FST0));
-
-			// make sure rhs is in memory
-			int db = findMemFor(rhs);
-
-			// lhs into reg, prefer same reg as result
-			Reservation* rA = getresv(lhs);
-			// last use of lhs in reg, can reuse rr
-			if (rA == 0 || rA->reg == UnknownReg)
-				findSpecificRegFor(lhs, rr);
-			// else, rA already has a different reg assigned
-
-			NanoAssert(getresv(lhs)!=0 && getresv(lhs)->reg==FST0);
-			// assume that the lhs is in ST(0) and rhs is on stack
-			if (op == LIR_fadd)
-				{ FADD(db, FP); }
-			else if (op == LIR_fsub)
-				{ FSUBR(db, FP); }
-			else if (op == LIR_fmul)
-				{ FMUL(db, FP); }
-			else if (op == LIR_fdiv)
-				{ FDIVR(db, FP); }
-		}
-	}
-
-	void Assembler::asm_i2f(LInsp ins)
-	{
-		// where our result goes
-		Register rr = prepResultReg(ins, FpRegs);
-		if (rmask(rr) & XmmRegs) 
-		{
-			// todo support int value in memory
-			Register gr = findRegFor(ins->oprnd1(), GpRegs);
-			SSE_CVTSI2SD(rr, gr);
-		} 
-		else 
-		{
-			int d = findMemFor(ins->oprnd1());
-			FILD(d, FP);
-		}
-	}
-
-	Register Assembler::asm_prep_fcall(Reservation *rR, LInsp ins)
-	{
-		if (rR) {
-    		Register rr;
-			if ((rr=rR->reg) != UnknownReg && (rmask(rr) & XmmRegs))
-				evict(rr);
-		}
-		return prepResultReg(ins, rmask(FST0));
-	}
-
-	void Assembler::asm_u2f(LInsp ins)
-	{
-		// where our result goes
-		Register rr = prepResultReg(ins, FpRegs);
-		if (rmask(rr) & XmmRegs) 
-		{
-			// don't call findRegFor, we want a reg we can stomp on for a very short time,
-			// not a reg that will continue to be associated with the LIns
-			Register gr = registerAlloc(GpRegs);
-
-			// technique inspired by gcc disassembly 
-			// Edwin explains it:
-			//
-			// gr is 0..2^32-1
-			//
-			//	   sub gr,0x80000000
-			//
-			// now gr is -2^31..2^31-1, i.e. the range of int, but not the same value
-			// as before
-			//
-			//	   cvtsi2sd rr,gr
-			//
-			// rr is now a double with the int value range
-			//
-			//     addsd rr, 2147483648.0
-			//
-			// adding back double(0x80000000) makes the range 0..2^32-1.  
-			
-			static const double k_NEGONE = 2147483648.0;
-			SSE_ADDSDm(rr, &k_NEGONE);
-
-			SSE_CVTSI2SD(rr, gr);
-
-			Reservation* resv = getresv(ins->oprnd1());
-			Register xr;
-			if (resv && (xr = resv->reg) != UnknownReg && (rmask(xr) & GpRegs))
-			{
-				LEA(gr, 0x80000000, xr);
-			}
-			else
-			{
-				const int d = findMemFor(ins->oprnd1());
-				SUBi(gr, 0x80000000);
-				LD(gr, d, FP);
-			}
-			
-			// ok, we're done with it
-			_allocator.addFree(gr); 
-		} 
-		else 
-		{
+            if (lhs == rhs)
+                rb = ra;
+
+            if (op == LIR_fadd)
+                SSE_ADDSD(rr, rb);
+            else if (op == LIR_fsub)
+                SSE_SUBSD(rr, rb);
+            else if (op == LIR_fmul)
+                SSE_MULSD(rr, rb);
+            else //if (op == LIR_fdiv)
+                SSE_DIVSD(rr, rb);
+
+            if (rr != ra)
+                SSE_MOVSD(rr, ra);
+        }
+        else
+        {
+            // we swap lhs/rhs on purpose here, works out better
+            // if you only have one fpu reg.  use divr/subr.
+            LIns* rhs = ins->oprnd1();
+            LIns* lhs = ins->oprnd2();
+            Register rr = prepResultReg(ins, rmask(FST0));
+
+            // make sure rhs is in memory
+            int db = findMemFor(rhs);
+
+            // lhs into reg, prefer same reg as result
+
+            // last use of lhs in reg, can reuse rr
+            // else, lhs already has a different reg assigned
+            if (lhs->isUnusedOrHasUnknownReg())
+                findSpecificRegFor(lhs, rr);
+
+            NanoAssert(lhs->getReg()==FST0);
+            // assume that the lhs is in ST(0) and rhs is on stack
+            if (op == LIR_fadd)
+                { FADD(db, FP); }
+            else if (op == LIR_fsub)
+                { FSUBR(db, FP); }
+            else if (op == LIR_fmul)
+                { FMUL(db, FP); }
+            else if (op == LIR_fdiv)
+                { FDIVR(db, FP); }
+        }
+    }
+
+    void Assembler::asm_i2f(LInsp ins)
+    {
+        // where our result goes
+        Register rr = prepResultReg(ins, FpRegs);
+        if (rmask(rr) & XmmRegs)
+        {
+            // todo support int value in memory
+            Register gr = findRegFor(ins->oprnd1(), GpRegs);
+            SSE_CVTSI2SD(rr, gr);
+            SSE_XORPDr(rr,rr);  // zero rr to ensure no dependency stalls
+        }
+        else
+        {
+            int d = findMemFor(ins->oprnd1());
+            FILD(d, FP);
+        }
+    }
+
+    Register Assembler::asm_prep_fcall(Reservation* /*unused*/, LInsp ins)
+    {
+        Register rr;
+        if (ins->isUsed() && (rr = ins->getReg(), isKnownReg(rr)) && (rmask(rr) & XmmRegs)) {
+            evict(rr, ins);
+        }
+        return prepResultReg(ins, rmask(FST0));
+    }
+
+    void Assembler::asm_u2f(LInsp ins)
+    {
+        // where our result goes
+        Register rr = prepResultReg(ins, FpRegs);
+        if (rmask(rr) & XmmRegs)
+        {
+            // don't call findRegFor, we want a reg we can stomp on for a very short time,
+            // not a reg that will continue to be associated with the LIns
+            Register gr = registerAlloc(GpRegs);
+
+            // technique inspired by gcc disassembly
+            // Edwin explains it:
+            //
+            // gr is 0..2^32-1
+            //
+            //     sub gr,0x80000000
+            //
+            // now gr is -2^31..2^31-1, i.e. the range of int, but not the same value
+            // as before
+            //
+            //     cvtsi2sd rr,gr
+            //
+            // rr is now a double with the int value range
+            //
+            //     addsd rr, 2147483648.0
+            //
+            // adding back double(0x80000000) makes the range 0..2^32-1.
+
+            static const double k_NEGONE = 2147483648.0;
+            SSE_ADDSDm(rr, &k_NEGONE);
+
+            SSE_CVTSI2SD(rr, gr);
+            SSE_XORPDr(rr,rr);  // zero rr to ensure no dependency stalls
+
+            LIns* op1 = ins->oprnd1();
+            Register xr;
+            if (op1->isUsed() && (xr = op1->getReg(), isKnownReg(xr)) && (rmask(xr) & GpRegs))
+            {
+                LEA(gr, 0x80000000, xr);
+            }
+            else
+            {
+                const int d = findMemFor(ins->oprnd1());
+                SUBi(gr, 0x80000000);
+                LD(gr, d, FP);
+            }
+
+            // ok, we're done with it
+            _allocator.addFree(gr);
+        }
+        else
+        {
             const int disp = -8;
             const Register base = SP;
-			Register gr = findRegFor(ins->oprnd1(), GpRegs);
-			NanoAssert(rr == FST0);
-			FILDQ(disp, base);
-			STi(base, disp+4, 0);	// high 32 bits = 0
-			ST(base, disp, gr);		// low 32 bits = unsigned value
-		}
-	}
-
-	void Assembler::asm_nongp_copy(Register r, Register s)
-	{
-		if ((rmask(r) & XmmRegs) && (rmask(s) & XmmRegs)) {
-			SSE_MOVSD(r, s);
-		} else if ((rmask(r) & GpRegs) && (rmask(s) & XmmRegs)) {
-			SSE_MOVD(r, s);
-		} else {
-			if (rmask(r) & XmmRegs) {
-				// x87 -> xmm
-				NanoAssertMsg(false, "Should not move data from GPR to XMM");
-			} else {
-				// xmm -> x87
-				NanoAssertMsg(false, "Should not move data from GPR/XMM to x87 FPU");
-			}
-		}
-	}
+            Register gr = findRegFor(ins->oprnd1(), GpRegs);
+            NanoAssert(rr == FST0);
+            FILDQ(disp, base);
+            STi(base, disp+4, 0);   // high 32 bits = 0
+            ST(base, disp, gr);     // low 32 bits = unsigned value
+        }
+    }
+
+    void Assembler::asm_nongp_copy(Register r, Register s)
+    {
+        if ((rmask(r) & XmmRegs) && (rmask(s) & XmmRegs)) {
+            SSE_MOVSD(r, s);
+        } else if ((rmask(r) & GpRegs) && (rmask(s) & XmmRegs)) {
+            SSE_MOVD(r, s);
+        } else {
+            if (rmask(r) & XmmRegs) {
+                // x87 -> xmm
+                NanoAssertMsg(false, "Should not move data from GPR to XMM");
+            } else {
+                // xmm -> x87
+                NanoAssertMsg(false, "Should not move data from GPR/XMM to x87 FPU");
+            }
+        }
+    }
 
     NIns * Assembler::asm_jmpcc(bool branchOnFalse, LIns *cond, NIns *targ)
     {
@@ -1573,24 +1584,24 @@ namespace nanojit
             }
 
             if (c == LIR_fgt) {
-                if (branchOnFalse) { JNA(targ, false); } else { JA(targ, false); }
+                if (branchOnFalse) { JNA(targ); } else { JA(targ); }
             }
             else { // if (c == LIR_fge)
-                if (branchOnFalse) { JNAE(targ, false); } else { JAE(targ, false); }
+                if (branchOnFalse) { JNAE(targ); } else { JAE(targ); }
             }
             NIns *at = _nIns;
-            Reservation *rA, *rB;
-            findRegFor2(XmmRegs, lhs, rA, rhs, rB);
-            SSE_UCOMISD(rA->reg, rB->reg);
+            Register ra, rb;
+            findRegFor2b(XmmRegs, lhs, ra, rhs, rb);
+            SSE_UCOMISD(ra, rb);
             return at;
         }
 
-    	if (branchOnFalse)
-			JP(targ, false);
-		else
-			JNP(targ, false);
-		NIns *at = _nIns;
-		asm_fcmp(cond);
+        if (branchOnFalse)
+            JP(targ);
+        else
+            JNP(targ);
+        NIns *at = _nIns;
+        asm_fcmp(cond);
         return at;
     }
 
@@ -1598,7 +1609,7 @@ namespace nanojit
     {
         LOpcode c = cond->opcode();
         if (config.sse2 && c != LIR_feq) {
-    		MOVZX8(r,r);
+            MOVZX8(r,r);
             LIns *lhs = cond->oprnd1();
             LIns *rhs = cond->oprnd2();
             if (c == LIR_flt) {
@@ -1615,31 +1626,31 @@ namespace nanojit
             else { // if (c == LIR_fge)
                 SETAE(r);
             }
-            Reservation *rA, *rB;
-            findRegFor2(XmmRegs, lhs, rA, rhs, rB);
-            SSE_UCOMISD(rA->reg, rB->reg);
+            Register ra, rb;
+            findRegFor2b(XmmRegs, lhs, ra, rhs, rb);
+            SSE_UCOMISD(ra, rb);
             return;
         }
-		// SETcc only sets low 8 bits, so extend 
-		MOVZX8(r,r);
-		SETNP(r);
+        // SETcc only sets low 8 bits, so extend
+        MOVZX8(r,r);
+        SETNP(r);
         asm_fcmp(cond);
     }
 
-	void Assembler::asm_fcmp(LIns *cond)
-	{
-		LOpcode condop = cond->opcode();
-		NanoAssert(condop >= LIR_feq && condop <= LIR_fge);
-	    LIns* lhs = cond->oprnd1();
-	    LIns* rhs = cond->oprnd2();
+    void Assembler::asm_fcmp(LIns *cond)
+    {
+        LOpcode condop = cond->opcode();
+        NanoAssert(condop >= LIR_feq && condop <= LIR_fge);
+        LIns* lhs = cond->oprnd1();
+        LIns* rhs = cond->oprnd2();
 
         int mask;
-	    if (condop == LIR_feq)
-		    mask = 0x44;
-	    else if (condop == LIR_fle)
-		    mask = 0x41;
-	    else if (condop == LIR_flt)
-		    mask = 0x05;
+        if (condop == LIR_feq)
+            mask = 0x44;
+        else if (condop == LIR_fle)
+            mask = 0x41;
+        else if (condop == LIR_flt)
+            mask = 0x05;
         else if (condop == LIR_fge) {
             // swap, use le
             condop = LIR_fle;
@@ -1649,7 +1660,7 @@ namespace nanojit
             // swap, use lt
             condop = LIR_flt;
             LIns* t = lhs; lhs = rhs; rhs = t;
-		    mask = 0x05;
+            mask = 0x05;
         }
 
         if (config.sse2)
@@ -1663,86 +1674,103 @@ namespace nanojit
                 // nan check
                 Register r = findRegFor(lhs, XmmRegs);
                 SSE_UCOMISD(r, r);
-            } 
+            }
             else {
-                evict(EAX);
+                evictIfActive(EAX);
                 TEST_AH(mask);
                 LAHF();
-
-                Reservation *rA, *rB;
-                findRegFor2(XmmRegs, lhs, rA, rhs, rB);
-                SSE_UCOMISD(rA->reg, rB->reg);
+                Register ra, rb;
+                findRegFor2b(XmmRegs, lhs, ra, rhs, rb);
+                SSE_UCOMISD(ra, rb);
             }
         }
         else
         {
-            evict(EAX);
+            evictIfActive(EAX);
             TEST_AH(mask);
-		    FNSTSW_AX();
-		    NanoAssert(lhs->isQuad() && rhs->isQuad());
-		    Reservation *rA;
-		    if (lhs != rhs)
-		    {
-			    // compare two different numbers
-			    int d = findMemFor(rhs);
-			    rA = getresv(lhs);
-			    int pop = !rA || rA->reg == UnknownReg; 
-			    findSpecificRegFor(lhs, FST0);
-			    // lhs is in ST(0) and rhs is on stack
-			    FCOM(pop, d, FP);
-		    }
-		    else
-		    {
-			    // compare n to itself, this is a NaN test.
-			    rA = getresv(lhs);
-			    int pop = !rA || rA->reg == UnknownReg; 
-			    findSpecificRegFor(lhs, FST0);
-			    // value in ST(0)
-			    if (pop)
-				    FCOMPP();
-			    else
-				    FCOMP();
-			    FLDr(FST0); // DUP
-		    }
-        }
-	}
-	
-	void Assembler::nativePageReset()
-	{
-	}
-
-	Register Assembler::asm_binop_rhs_reg(LInsp ins)
-	{
-		LOpcode op = ins->opcode();
-		LIns *rhs = ins->oprnd2();
-
-		if (op == LIR_lsh || op == LIR_rsh || op == LIR_ush)
-			return findSpecificRegFor(rhs, ECX);
-
-		return UnknownReg;	
-	}
-
-	void Assembler::nativePageSetup()
-	{
-		if (!_nIns)		 _nIns	   = pageAlloc();
-		if (!_nExitIns)  _nExitIns = pageAlloc(true);
-	}
-	
-	// enough room for n bytes
+            FNSTSW_AX();
+            NanoAssert(lhs->isQuad() && rhs->isQuad());
+            if (lhs != rhs)
+            {
+                // compare two different numbers
+                int d = findMemFor(rhs);
+                int pop = lhs->isUnusedOrHasUnknownReg();
+                findSpecificRegFor(lhs, FST0);
+                // lhs is in ST(0) and rhs is on stack
+                FCOM(pop, d, FP);
+            }
+            else
+            {
+                // compare n to itself, this is a NaN test.
+                int pop = lhs->isUnusedOrHasUnknownReg();
+                findSpecificRegFor(lhs, FST0);
+                // value in ST(0)
+                if (pop)
+                    FCOMPP();
+                else
+                    FCOMP();
+                FLDr(FST0); // DUP
+            }
+        }
+    }
+
+    // Increment the 32-bit profiling counter at pCtr, without
+    // changing any registers.
+    verbose_only(
+    void Assembler::asm_inc_m32(uint32_t* pCtr)
+    {
+       INCLi(pCtr);
+    }
+    )
+
+    void Assembler::nativePageReset()
+    {}
+
+    void Assembler::nativePageSetup()
+    {
+        if (!_nIns)
+            codeAlloc(codeStart, codeEnd, _nIns verbose_only(, codeBytes));
+        if (!_nExitIns)
+            codeAlloc(exitStart, exitEnd, _nExitIns verbose_only(, exitBytes));
+    }
+
+    // enough room for n bytes
     void Assembler::underrunProtect(int n)
     {
-		NanoAssertMsg(n<=LARGEST_UNDERRUN_PROT, "constant LARGEST_UNDERRUN_PROT is too small"); 
-        NIns *eip = this->_nIns;
-        Page *p = (Page*)pageTop(eip-1);
-        NIns *top = (NIns*) &p->code[0];
-        if (eip - n < top) {
+        NIns *eip = _nIns;
+        NanoAssertMsg(n<=LARGEST_UNDERRUN_PROT, "constant LARGEST_UNDERRUN_PROT is too small");
+        if (eip - n < (_inExit ? exitStart : codeStart)) {
             // We are done with the current page.  Tell Valgrind that new code
             // has been generated.
-            VALGRIND_DISCARD_TRANSLATIONS(pageTop(p), NJ_PAGE_SIZE);
-			_nIns = pageAlloc(_inExit);
+            if (_inExit)
+                codeAlloc(exitStart, exitEnd, _nIns verbose_only(, exitBytes));
+            else
+                codeAlloc(codeStart, codeEnd, _nIns verbose_only(, codeBytes));
             JMP(eip);
         }
     }
-	
-	#endif /* FEATURE_NANOJIT */
+
+    void Assembler::asm_ret(LInsp ins)
+    {
+        genEpilogue();
+
+        // Restore ESP from EBP, undoing SUBi(SP,amt) in the prologue
+        MR(SP,FP);
+
+        assignSavedRegs();
+        LIns *val = ins->oprnd1();
+        if (ins->isop(LIR_ret)) {
+            findSpecificRegFor(val, retRegs[0]);
+        } else {
+            findSpecificRegFor(val, FST0);
+            fpu_pop();
+        }
+    }
+
+    void Assembler::asm_promote(LIns *) {
+        // i2q or u2q
+        TODO(asm_promote);
+    }
+
+    #endif /* FEATURE_NANOJIT */
 }