johnson 2.0.0.pre0 → 2.0.0.pre1

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Files changed (3954) hide show
  1. data/CHANGELOG.rdoc +6 -0
  2. data/Manifest.txt +3709 -33
  3. data/Rakefile +19 -0
  4. data/ext/tracemonkey/extconf.rb +16 -2
  5. data/ext/tracemonkey/immutable_node.cc +3 -1
  6. data/ext/tracemonkey/js.cc +474 -0
  7. data/ext/tracemonkey/runtime.cc +3 -1
  8. data/ext/tracemonkey/split_global.cc +0 -373
  9. data/ext/tracemonkey/split_global.h +3 -0
  10. data/lib/johnson.rb +1 -1
  11. data/test/generic/parser_test.rb +27 -5
  12. data/test/johnson/generic/nodes/array_literal_test.rb +1 -1
  13. data/test/johnson/generic/nodes/ternary_test.rb +1 -1
  14. data/test/johnson/tracemonkey/split_global_test.html +18 -0
  15. data/vendor/tracemonkey/Makefile.in +100 -74
  16. data/vendor/tracemonkey/Makefile.ref +0 -13
  17. data/vendor/tracemonkey/README.html +2 -3
  18. data/vendor/tracemonkey/aclocal.m4 +3 -0
  19. data/vendor/tracemonkey/analysis-tests/Makefile.in +110 -0
  20. data/vendor/tracemonkey/analysis-tests/green-accessred.cpp +11 -0
  21. data/vendor/tracemonkey/analysis-tests/green-callred.cpp +12 -0
  22. data/vendor/tracemonkey/analysis-tests/green-callredptr.cpp +8 -0
  23. data/vendor/tracemonkey/analysis-tests/green-tored-badpath.cpp +14 -0
  24. data/vendor/tracemonkey/analysis-tests/green-tored.cpp +12 -0
  25. data/vendor/tracemonkey/analysis-tests/green-toredptr.cpp +12 -0
  26. data/vendor/tracemonkey/analysis-tests/misdeclared-red-funcptr.cpp +5 -0
  27. data/vendor/tracemonkey/analysis-tests/misdeclared-red-funcptr2.cpp +5 -0
  28. data/vendor/tracemonkey/analysis-tests/red-accessred.cpp +11 -0
  29. data/vendor/tracemonkey/analysis-tests/red-callgreen.cpp +8 -0
  30. data/vendor/tracemonkey/analysis-tests/red-callred.cpp +8 -0
  31. data/vendor/tracemonkey/analysis-tests/red-togreenptr-arg.cpp +11 -0
  32. data/vendor/tracemonkey/analysis-tests/red-togreenptr-field.cpp +15 -0
  33. data/vendor/tracemonkey/analysis-tests/red-togreenptr-initializer-array.cpp +8 -0
  34. data/vendor/tracemonkey/analysis-tests/red-togreenptr-initializer-cast.cpp +7 -0
  35. data/vendor/tracemonkey/analysis-tests/red-togreenptr-initializer-nested.cpp +18 -0
  36. data/vendor/tracemonkey/analysis-tests/red-togreenptr-initializer-struct.cpp +12 -0
  37. data/vendor/tracemonkey/analysis-tests/red-togreenptr-initializer.cpp +7 -0
  38. data/vendor/tracemonkey/analysis-tests/red-togreenptr-return.cpp +9 -0
  39. data/vendor/tracemonkey/analysis-tests/red-togreenptr.cpp +10 -0
  40. data/vendor/tracemonkey/bench.sh +1 -1
  41. data/vendor/tracemonkey/build/autoconf/acoutput-fast.pl +0 -0
  42. data/vendor/tracemonkey/build/autoconf/config.sub +154 -63
  43. data/vendor/tracemonkey/build/autoconf/make-makefile +10 -3
  44. data/vendor/tracemonkey/build/autoconf/mozprog.m4 +76 -0
  45. data/vendor/tracemonkey/build/autoconf/nspr.m4 +25 -6
  46. data/vendor/tracemonkey/build/unix/mddepend.pl +2 -0
  47. data/vendor/tracemonkey/build/win32/pgomerge.py +0 -0
  48. data/vendor/tracemonkey/builtins.tbl +1 -1
  49. data/vendor/tracemonkey/config.mk +3 -5
  50. data/vendor/tracemonkey/config/Makefile.in +8 -5
  51. data/vendor/tracemonkey/config/autoconf.mk.in +5 -14
  52. data/vendor/tracemonkey/config/config.mk +28 -35
  53. data/vendor/tracemonkey/config/milestone.txt +1 -1
  54. data/vendor/tracemonkey/config/mkdepend/Makefile.in +2 -3
  55. data/vendor/tracemonkey/config/nsinstall.exe.manifest +17 -0
  56. data/vendor/tracemonkey/config/nsinstall_win.c +708 -0
  57. data/vendor/tracemonkey/config/rules.mk +153 -191
  58. data/vendor/tracemonkey/config/static-checking.js +21 -30
  59. data/vendor/tracemonkey/config/system-headers +17 -31
  60. data/vendor/tracemonkey/config/version.mk +2 -2
  61. data/vendor/tracemonkey/config/version_win.pl +5 -12
  62. data/vendor/tracemonkey/configure +1175 -1071
  63. data/vendor/tracemonkey/configure.in +237 -309
  64. data/vendor/tracemonkey/dtoa.c +0 -4
  65. data/vendor/tracemonkey/imacro_asm.js.in +8 -0
  66. data/vendor/tracemonkey/imacros.c.out +217 -267
  67. data/vendor/tracemonkey/imacros.jsasm +56 -98
  68. data/vendor/tracemonkey/jitstats.tbl +58 -16
  69. data/vendor/tracemonkey/js-config.h.in +8 -6
  70. data/vendor/tracemonkey/js.msg +1 -1
  71. data/vendor/tracemonkey/jsapi-tests/Makefile.in +76 -0
  72. data/vendor/tracemonkey/jsapi-tests/README +160 -0
  73. data/vendor/tracemonkey/jsapi-tests/selfTest.cpp +20 -0
  74. data/vendor/tracemonkey/jsapi-tests/testDebugger.cpp +25 -0
  75. data/vendor/tracemonkey/jsapi-tests/testDefineGetterSetterNonEnumerable.cpp +51 -0
  76. data/vendor/tracemonkey/jsapi-tests/testExtendedEq.cpp +45 -0
  77. data/vendor/tracemonkey/jsapi-tests/testIntString.cpp +13 -0
  78. data/vendor/tracemonkey/jsapi-tests/testIsAboutToBeFinalized.cpp +89 -0
  79. data/vendor/tracemonkey/jsapi-tests/testPropCache.cpp +31 -0
  80. data/vendor/tracemonkey/jsapi-tests/testSameValue.cpp +21 -0
  81. data/vendor/tracemonkey/jsapi-tests/testXDR.cpp +55 -0
  82. data/vendor/tracemonkey/jsapi-tests/tests.cpp +79 -0
  83. data/vendor/tracemonkey/jsapi-tests/tests.h +239 -0
  84. data/vendor/tracemonkey/jsapi.cpp +264 -336
  85. data/vendor/tracemonkey/jsapi.h +163 -57
  86. data/vendor/tracemonkey/jsarena.cpp +8 -8
  87. data/vendor/tracemonkey/jsarray.cpp +551 -602
  88. data/vendor/tracemonkey/jsarray.h +58 -57
  89. data/vendor/tracemonkey/jsatom.cpp +59 -56
  90. data/vendor/tracemonkey/jsatom.h +0 -6
  91. data/vendor/tracemonkey/jsatominlines.h +95 -0
  92. data/vendor/tracemonkey/jsbit.h +26 -1
  93. data/vendor/tracemonkey/jsbool.cpp +18 -11
  94. data/vendor/tracemonkey/jsbool.h +7 -11
  95. data/vendor/tracemonkey/jsbuiltins.cpp +91 -66
  96. data/vendor/tracemonkey/jsbuiltins.h +146 -76
  97. data/vendor/tracemonkey/jscntxt.cpp +141 -73
  98. data/vendor/tracemonkey/jscntxt.h +415 -106
  99. data/vendor/tracemonkey/jscompat.h +3 -4
  100. data/vendor/tracemonkey/jsconfig.mk +0 -12
  101. data/vendor/tracemonkey/jscpucfg.cpp +1 -1
  102. data/vendor/tracemonkey/jsdate.cpp +373 -181
  103. data/vendor/tracemonkey/jsdate.h +5 -1
  104. data/vendor/tracemonkey/jsdbgapi.cpp +595 -84
  105. data/vendor/tracemonkey/jsdbgapi.h +13 -4
  106. data/vendor/tracemonkey/jsdhash.cpp +42 -15
  107. data/vendor/tracemonkey/jsdhash.h +19 -0
  108. data/vendor/tracemonkey/jsdtoa.cpp +7 -7
  109. data/vendor/tracemonkey/{jsdtracef.c → jsdtracef.cpp} +56 -93
  110. data/vendor/tracemonkey/jsdtracef.h +2 -2
  111. data/vendor/tracemonkey/jsemit.cpp +92 -82
  112. data/vendor/tracemonkey/jsemit.h +3 -6
  113. data/vendor/tracemonkey/jsexn.cpp +46 -62
  114. data/vendor/tracemonkey/jsfile.cpp +91 -71
  115. data/vendor/tracemonkey/jsfun.cpp +535 -549
  116. data/vendor/tracemonkey/jsfun.h +104 -20
  117. data/vendor/tracemonkey/jsgc.cpp +275 -255
  118. data/vendor/tracemonkey/jsgc.h +46 -54
  119. data/vendor/tracemonkey/jshash.cpp +5 -5
  120. data/vendor/tracemonkey/jshash.h +3 -1
  121. data/vendor/tracemonkey/jsinterp.cpp +350 -4490
  122. data/vendor/tracemonkey/jsinterp.h +50 -39
  123. data/vendor/tracemonkey/jsinttypes.h +139 -0
  124. data/vendor/tracemonkey/jsinvoke.cpp +1 -1
  125. data/vendor/tracemonkey/jsiter.cpp +65 -58
  126. data/vendor/tracemonkey/jsiter.h +2 -2
  127. data/vendor/tracemonkey/jskwgen.cpp +2 -2
  128. data/vendor/tracemonkey/jslibmath.h +17 -0
  129. data/vendor/tracemonkey/jslock.cpp +73 -71
  130. data/vendor/tracemonkey/jslock.h +21 -18
  131. data/vendor/tracemonkey/jslog2.cpp +1 -1
  132. data/vendor/tracemonkey/jsmath.cpp +69 -109
  133. data/vendor/tracemonkey/jsmath.h +18 -8
  134. data/vendor/tracemonkey/jsnum.cpp +129 -106
  135. data/vendor/tracemonkey/jsnum.h +202 -55
  136. data/vendor/tracemonkey/jsobj.cpp +1108 -1076
  137. data/vendor/tracemonkey/jsobj.h +441 -204
  138. data/vendor/tracemonkey/jsobjinlines.h +59 -0
  139. data/vendor/tracemonkey/json.cpp +170 -263
  140. data/vendor/tracemonkey/json.h +2 -13
  141. data/vendor/tracemonkey/jsopcode.cpp +141 -89
  142. data/vendor/tracemonkey/jsopcode.h +23 -4
  143. data/vendor/tracemonkey/jsopcode.tbl +7 -1
  144. data/vendor/tracemonkey/jsoplengen.cpp +1 -1
  145. data/vendor/tracemonkey/jsops.cpp +4213 -0
  146. data/vendor/tracemonkey/jsotypes.h +0 -4
  147. data/vendor/tracemonkey/jsparse.cpp +147 -262
  148. data/vendor/tracemonkey/jsparse.h +12 -10
  149. data/vendor/tracemonkey/jsprf.cpp +11 -11
  150. data/vendor/tracemonkey/jsprvtd.h +40 -33
  151. data/vendor/tracemonkey/jspubtd.h +3 -6
  152. data/vendor/tracemonkey/jsregexp.cpp +1260 -455
  153. data/vendor/tracemonkey/jsregexp.h +17 -8
  154. data/vendor/tracemonkey/jsscan.cpp +151 -324
  155. data/vendor/tracemonkey/jsscan.h +25 -82
  156. data/vendor/tracemonkey/jsscope.cpp +385 -300
  157. data/vendor/tracemonkey/jsscope.h +290 -117
  158. data/vendor/tracemonkey/jsscript.cpp +135 -153
  159. data/vendor/tracemonkey/jsscript.h +52 -68
  160. data/vendor/tracemonkey/jsscriptinlines.h +69 -0
  161. data/vendor/tracemonkey/jsshell.msg +2 -0
  162. data/vendor/tracemonkey/jsstack.js +213 -7
  163. data/vendor/tracemonkey/jsstdint.h +58 -40
  164. data/vendor/tracemonkey/jsstr.cpp +1247 -954
  165. data/vendor/tracemonkey/jsstr.h +410 -95
  166. data/vendor/tracemonkey/{jsstddef.h → jsstrinlines.h} +30 -42
  167. data/vendor/tracemonkey/jstask.cpp +126 -0
  168. data/vendor/tracemonkey/jstask.h +88 -0
  169. data/vendor/tracemonkey/jstl.h +262 -0
  170. data/vendor/tracemonkey/jstracer.cpp +6806 -3438
  171. data/vendor/tracemonkey/jstracer.h +675 -169
  172. data/vendor/tracemonkey/jstypes.h +29 -49
  173. data/vendor/tracemonkey/jsutil.cpp +3 -3
  174. data/vendor/tracemonkey/jsutil.h +127 -5
  175. data/vendor/tracemonkey/jsvector.h +775 -0
  176. data/vendor/tracemonkey/jswince.asm +40 -2
  177. data/vendor/tracemonkey/jsxdrapi.cpp +24 -30
  178. data/vendor/tracemonkey/jsxdrapi.h +1 -1
  179. data/vendor/tracemonkey/jsxml.cpp +542 -712
  180. data/vendor/tracemonkey/jsxml.h +3 -11
  181. data/vendor/tracemonkey/lirasm/Makefile.in +78 -0
  182. data/vendor/tracemonkey/lirasm/lirasm.cpp +1159 -0
  183. data/vendor/tracemonkey/lirasm/testlirc.sh +27 -0
  184. data/vendor/tracemonkey/lirasm/tests/add.in +4 -0
  185. data/vendor/tracemonkey/lirasm/tests/add.out +1 -0
  186. data/vendor/tracemonkey/lirasm/tests/addsub.in +5 -0
  187. data/vendor/tracemonkey/lirasm/tests/addsub.out +1 -0
  188. data/vendor/tracemonkey/lirasm/tests/call1.in +11 -0
  189. data/vendor/tracemonkey/lirasm/tests/call1.out +2 -0
  190. data/vendor/tracemonkey/lirasm/tests/call2.in +5 -0
  191. data/vendor/tracemonkey/lirasm/tests/call2.out +1 -0
  192. data/vendor/tracemonkey/lirasm/tests/floatingpoint.in +4 -0
  193. data/vendor/tracemonkey/lirasm/tests/floatingpoint.out +1 -0
  194. data/vendor/tracemonkey/lirasm/tests/loadstore.in +9 -0
  195. data/vendor/tracemonkey/lirasm/tests/loadstore.out +1 -0
  196. data/vendor/tracemonkey/lirasm/tests/multfrag1.in +26 -0
  197. data/vendor/tracemonkey/lirasm/tests/multfrag1.out +2 -0
  198. data/vendor/tracemonkey/lirasm/tests/multfrag2.in +14 -0
  199. data/vendor/tracemonkey/lirasm/tests/multfrag2.out +1 -0
  200. data/vendor/tracemonkey/lirasm/tests/multfrag3.in +15 -0
  201. data/vendor/tracemonkey/lirasm/tests/multfrag3.out +1 -0
  202. data/vendor/tracemonkey/liveconnect/jsj.c +5 -5
  203. data/vendor/tracemonkey/liveconnect/jsj_JSObject.c +2 -4
  204. data/vendor/tracemonkey/liveconnect/jsj_JavaArray.c +2 -4
  205. data/vendor/tracemonkey/liveconnect/jsj_JavaClass.c +3 -5
  206. data/vendor/tracemonkey/liveconnect/jsj_JavaObject.c +4 -24
  207. data/vendor/tracemonkey/liveconnect/jsj_private.h +4 -4
  208. data/vendor/tracemonkey/liveconnect/jsj_utils.c +18 -2
  209. data/vendor/tracemonkey/liveconnect/nsCLiveconnect.cpp +30 -4
  210. data/vendor/tracemonkey/nanojit/{TraceTreeDrawer.h → Allocator.cpp} +56 -48
  211. data/vendor/tracemonkey/nanojit/Allocator.h +117 -0
  212. data/vendor/tracemonkey/nanojit/Assembler.cpp +1378 -1442
  213. data/vendor/tracemonkey/nanojit/Assembler.h +250 -280
  214. data/vendor/tracemonkey/nanojit/CodeAlloc.cpp +506 -0
  215. data/vendor/tracemonkey/nanojit/CodeAlloc.h +201 -0
  216. data/vendor/tracemonkey/nanojit/Containers.cpp +95 -0
  217. data/vendor/tracemonkey/nanojit/Containers.h +463 -0
  218. data/vendor/tracemonkey/nanojit/Fragmento.cpp +35 -604
  219. data/vendor/tracemonkey/nanojit/Fragmento.h +84 -183
  220. data/vendor/tracemonkey/nanojit/LIR.cpp +1969 -2050
  221. data/vendor/tracemonkey/nanojit/LIR.h +1351 -720
  222. data/vendor/tracemonkey/nanojit/LIRopcode.tbl +173 -159
  223. data/vendor/tracemonkey/nanojit/Native.h +61 -48
  224. data/vendor/tracemonkey/nanojit/NativeARM.cpp +1509 -849
  225. data/vendor/tracemonkey/nanojit/NativeARM.h +362 -286
  226. data/vendor/tracemonkey/nanojit/NativePPC.cpp +1296 -0
  227. data/vendor/tracemonkey/nanojit/NativePPC.h +587 -0
  228. data/vendor/tracemonkey/nanojit/NativeSparc.cpp +146 -224
  229. data/vendor/tracemonkey/nanojit/NativeSparc.h +235 -229
  230. data/vendor/tracemonkey/nanojit/NativeX64.cpp +1434 -0
  231. data/vendor/tracemonkey/nanojit/NativeX64.h +392 -0
  232. data/vendor/tracemonkey/nanojit/Nativei386.cpp +1395 -1367
  233. data/vendor/tracemonkey/nanojit/Nativei386.h +519 -514
  234. data/vendor/tracemonkey/nanojit/RegAlloc.cpp +37 -130
  235. data/vendor/tracemonkey/nanojit/RegAlloc.h +90 -49
  236. data/vendor/tracemonkey/nanojit/avmplus.cpp +249 -32
  237. data/vendor/tracemonkey/nanojit/avmplus.h +121 -667
  238. data/vendor/tracemonkey/nanojit/manifest.mk +79 -0
  239. data/vendor/tracemonkey/nanojit/nanojit.h +179 -157
  240. data/vendor/tracemonkey/plify_jsdhash.sed +10 -6
  241. data/vendor/tracemonkey/prmjtime.cpp +97 -55
  242. data/vendor/tracemonkey/prmjtime.h +1 -1
  243. data/vendor/tracemonkey/{config/revdepth.pl → ref-config/HP-UXB.11.31.mk} +28 -14
  244. data/vendor/tracemonkey/resource.h +1 -1
  245. data/vendor/tracemonkey/shell/js.cpp +358 -201
  246. data/vendor/tracemonkey/tests/Makefile.in +78 -0
  247. data/vendor/tracemonkey/tests/Patterns.pm +257 -0
  248. data/vendor/tracemonkey/tests/README-jsDriver.html +325 -0
  249. data/vendor/tracemonkey/tests/SisyphusMakefile +58 -0
  250. data/vendor/tracemonkey/tests/bisect.sh +488 -0
  251. data/vendor/tracemonkey/tests/browser.js +964 -0
  252. data/vendor/tracemonkey/tests/changes.sh +122 -0
  253. data/vendor/tracemonkey/tests/config.mk +113 -0
  254. data/vendor/tracemonkey/tests/config.sh +138 -0
  255. data/vendor/tracemonkey/tests/detect-universe.sh +126 -0
  256. data/vendor/tracemonkey/tests/dikdik-n.tests +3 -0
  257. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.1.js +85 -0
  258. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.2.js +86 -0
  259. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.3.js +56 -0
  260. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.4-01.js +61 -0
  261. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.4-02.js +58 -0
  262. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.4-03.js +60 -0
  263. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.4-04.js +56 -0
  264. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.4-05.js +57 -0
  265. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.4-06.js +61 -0
  266. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.4-07.js +78 -0
  267. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.4-08.js +158 -0
  268. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.4.js +140 -0
  269. data/vendor/tracemonkey/tests/e4x/Expressions/11.1.5.js +62 -0
  270. data/vendor/tracemonkey/tests/e4x/Expressions/11.2.1.js +173 -0
  271. data/vendor/tracemonkey/tests/e4x/Expressions/11.2.2.js +106 -0
  272. data/vendor/tracemonkey/tests/e4x/Expressions/11.2.3.js +61 -0
  273. data/vendor/tracemonkey/tests/e4x/Expressions/11.2.4.js +117 -0
  274. data/vendor/tracemonkey/tests/e4x/Expressions/11.3.1.js +272 -0
  275. data/vendor/tracemonkey/tests/e4x/Expressions/11.3.2.js +52 -0
  276. data/vendor/tracemonkey/tests/e4x/Expressions/11.4.1.js +139 -0
  277. data/vendor/tracemonkey/tests/e4x/Expressions/11.5.1.js +101 -0
  278. data/vendor/tracemonkey/tests/e4x/Expressions/11.6.1.js +429 -0
  279. data/vendor/tracemonkey/tests/e4x/Expressions/11.6.2.js +326 -0
  280. data/vendor/tracemonkey/tests/e4x/Expressions/11.6.3.js +119 -0
  281. data/vendor/tracemonkey/tests/e4x/Expressions/jstests.list +30 -0
  282. data/vendor/tracemonkey/tests/e4x/Expressions/regress-301545.js +55 -0
  283. data/vendor/tracemonkey/tests/e4x/Expressions/regress-302531.js +63 -0
  284. data/vendor/tracemonkey/tests/e4x/Expressions/regress-340024.js +61 -0
  285. data/vendor/tracemonkey/tests/e4x/Expressions/regress-366123.js +67 -0
  286. data/vendor/tracemonkey/tests/e4x/Expressions/regress-496113.js +65 -0
  287. data/vendor/tracemonkey/tests/e4x/Expressions/shell.js +1 -0
  288. data/vendor/tracemonkey/tests/e4x/GC/jstests.list +11 -0
  289. data/vendor/tracemonkey/tests/e4x/GC/regress-280844-1.js +59 -0
  290. data/vendor/tracemonkey/tests/e4x/GC/regress-280844-2.js +71 -0
  291. data/vendor/tracemonkey/tests/e4x/GC/regress-292455.js +79 -0
  292. data/vendor/tracemonkey/tests/e4x/GC/regress-313952-01.js +68 -0
  293. data/vendor/tracemonkey/tests/e4x/GC/regress-313952-02.js +77 -0
  294. data/vendor/tracemonkey/tests/e4x/GC/regress-324117.js +98 -0
  295. data/vendor/tracemonkey/tests/e4x/GC/regress-324278.js +86 -0
  296. data/vendor/tracemonkey/tests/e4x/GC/regress-339785.js +92 -0
  297. data/vendor/tracemonkey/tests/e4x/GC/regress-357063-01.js +73 -0
  298. data/vendor/tracemonkey/tests/e4x/GC/regress-357063-02.js +69 -0
  299. data/vendor/tracemonkey/tests/e4x/GC/shell.js +1 -0
  300. data/vendor/tracemonkey/tests/e4x/Global/13.1.2.1.js +559 -0
  301. data/vendor/tracemonkey/tests/e4x/Global/jstests.list +2 -0
  302. data/vendor/tracemonkey/tests/e4x/Global/shell.js +1 -0
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  3719. data/vendor/tracemonkey/trace-test/tests/basic/testInterpreterReentry7.js +11 -0
  3720. data/vendor/tracemonkey/trace-test/tests/basic/testInvalidCharCodeAt.js +12 -0
  3721. data/vendor/tracemonkey/trace-test/tests/basic/testInvertNullAfterNegateNull.js +7 -0
  3722. data/vendor/tracemonkey/trace-test/tests/basic/testLambdaCtor.js +14 -0
  3723. data/vendor/tracemonkey/trace-test/tests/basic/testLambdaInitedVar.js +8 -0
  3724. data/vendor/tracemonkey/trace-test/tests/basic/testLengthInString.js +12 -0
  3725. data/vendor/tracemonkey/trace-test/tests/basic/testLengthOnNonNativeProto.js +20 -0
  3726. data/vendor/tracemonkey/trace-test/tests/basic/testLetWithUnstableGlobal.js +11 -0
  3727. data/vendor/tracemonkey/trace-test/tests/basic/testLirBufOOM.js +34 -0
  3728. data/vendor/tracemonkey/trace-test/tests/basic/testLogicalNotNaN.js +8 -0
  3729. data/vendor/tracemonkey/trace-test/tests/basic/testLongNumToString.js +7 -0
  3730. data/vendor/tracemonkey/trace-test/tests/basic/testLoopWithUndefined1.js +12 -0
  3731. data/vendor/tracemonkey/trace-test/tests/basic/testLoopWithUndefined2.js +20 -0
  3732. data/vendor/tracemonkey/trace-test/tests/basic/testLoopingAccumulator.js +21 -0
  3733. data/vendor/tracemonkey/trace-test/tests/basic/testMatchAsCondition.js +8 -0
  3734. data/vendor/tracemonkey/trace-test/tests/basic/testMatchStringObject.js +8 -0
  3735. data/vendor/tracemonkey/trace-test/tests/basic/testMethodInit.js +15 -0
  3736. data/vendor/tracemonkey/trace-test/tests/basic/testMethodInitSafety.js +14 -0
  3737. data/vendor/tracemonkey/trace-test/tests/basic/testMethodSet.js +18 -0
  3738. data/vendor/tracemonkey/trace-test/tests/basic/testModuloWithNegative1.js +11 -0
  3739. data/vendor/tracemonkey/trace-test/tests/basic/testModuloWithNegative2.js +7 -0
  3740. data/vendor/tracemonkey/trace-test/tests/basic/testMoreArgcThanNargs.js +14 -0
  3741. data/vendor/tracemonkey/trace-test/tests/basic/testMoreClosures.js +14 -0
  3742. data/vendor/tracemonkey/trace-test/tests/basic/testMulOverflow.js +6 -0
  3743. data/vendor/tracemonkey/trace-test/tests/basic/testMultipleArgumentsObjects.js +12 -0
  3744. data/vendor/tracemonkey/trace-test/tests/basic/testNEWINIT.js +8 -0
  3745. data/vendor/tracemonkey/trace-test/tests/basic/testNEWINIT_DOUBLE.js +6 -0
  3746. data/vendor/tracemonkey/trace-test/tests/basic/testNativeArgsRooting.js +14 -0
  3747. data/vendor/tracemonkey/trace-test/tests/basic/testNativeLog.js +8 -0
  3748. data/vendor/tracemonkey/trace-test/tests/basic/testNativeMax.js +20 -0
  3749. data/vendor/tracemonkey/trace-test/tests/basic/testNativeSetter.js +14 -0
  3750. data/vendor/tracemonkey/trace-test/tests/basic/testNegZero1.js +9 -0
  3751. data/vendor/tracemonkey/trace-test/tests/basic/testNegativeArrayLength.js +10 -0
  3752. data/vendor/tracemonkey/trace-test/tests/basic/testNegativeGETELEMIndex.js +6 -0
  3753. data/vendor/tracemonkey/trace-test/tests/basic/testNestedClosures.js +23 -0
  3754. data/vendor/tracemonkey/trace-test/tests/basic/testNestedDeepBail.js +19 -0
  3755. data/vendor/tracemonkey/trace-test/tests/basic/testNestedEscapingLambdas.js +31 -0
  3756. data/vendor/tracemonkey/trace-test/tests/basic/testNestedExitStackOuter.js +29 -0
  3757. data/vendor/tracemonkey/trace-test/tests/basic/testNestedForIn.js +9 -0
  3758. data/vendor/tracemonkey/trace-test/tests/basic/testNewArrayCount.js +11 -0
  3759. data/vendor/tracemonkey/trace-test/tests/basic/testNewArrayCount2.js +7 -0
  3760. data/vendor/tracemonkey/trace-test/tests/basic/testNewDate.js +17 -0
  3761. data/vendor/tracemonkey/trace-test/tests/basic/testNewString.js +27 -0
  3762. data/vendor/tracemonkey/trace-test/tests/basic/testNewWithNonNativeProto.js +14 -0
  3763. data/vendor/tracemonkey/trace-test/tests/basic/testNonStubGetter.js +7 -0
  3764. data/vendor/tracemonkey/trace-test/tests/basic/testNot.js +8 -0
  3765. data/vendor/tracemonkey/trace-test/tests/basic/testNullCallee.js +16 -0
  3766. data/vendor/tracemonkey/trace-test/tests/basic/testNullRelCmp.js +6 -0
  3767. data/vendor/tracemonkey/trace-test/tests/basic/testNullToString.js +18 -0
  3768. data/vendor/tracemonkey/trace-test/tests/basic/testNumToString.js +18 -0
  3769. data/vendor/tracemonkey/trace-test/tests/basic/testNumberToString.js +6 -0
  3770. data/vendor/tracemonkey/trace-test/tests/basic/testObjectLength.js +15 -0
  3771. data/vendor/tracemonkey/trace-test/tests/basic/testObjectOrderedCmp.js +7 -0
  3772. data/vendor/tracemonkey/trace-test/tests/basic/testObjectOrderedCmp2.js +7 -0
  3773. data/vendor/tracemonkey/trace-test/tests/basic/testObjectToNumber.js +8 -0
  3774. data/vendor/tracemonkey/trace-test/tests/basic/testObjectToString.js +8 -0
  3775. data/vendor/tracemonkey/trace-test/tests/basic/testObjectVsPrototype.js +12 -0
  3776. data/vendor/tracemonkey/trace-test/tests/basic/testOwnPropertyWithInOperator.js +12 -0
  3777. data/vendor/tracemonkey/trace-test/tests/basic/testPrimitiveConstructorPrototype.js +7 -0
  3778. data/vendor/tracemonkey/trace-test/tests/basic/testPropagatedFunArgs.js +34 -0
  3779. data/vendor/tracemonkey/trace-test/tests/basic/testRUNLOOPCorrectness.js +15 -0
  3780. data/vendor/tracemonkey/trace-test/tests/basic/testReallyDeepNestedExit.js +38 -0
  3781. data/vendor/tracemonkey/trace-test/tests/basic/testRebranding.js +10 -0
  3782. data/vendor/tracemonkey/trace-test/tests/basic/testRebranding2.js +21 -0
  3783. data/vendor/tracemonkey/trace-test/tests/basic/testRegExpTest.js +10 -0
  3784. data/vendor/tracemonkey/trace-test/tests/basic/testRegexpGet.js +8 -0
  3785. data/vendor/tracemonkey/trace-test/tests/basic/testReplace2.js +7 -0
  3786. data/vendor/tracemonkey/trace-test/tests/basic/testResumeOp.js +8 -0
  3787. data/vendor/tracemonkey/trace-test/tests/basic/testReverseArgTypes.js +5 -0
  3788. data/vendor/tracemonkey/trace-test/tests/basic/testSetPropNeitherMissNorHit.js +5 -0
  3789. data/vendor/tracemonkey/trace-test/tests/basic/testSetPropertyFail.js +22 -0
  3790. data/vendor/tracemonkey/trace-test/tests/basic/testSetProtoRegeneratesObjectShape.js +24 -0
  3791. data/vendor/tracemonkey/trace-test/tests/basic/testSetelemWithFloatIndex.js +4 -0
  3792. data/vendor/tracemonkey/trace-test/tests/basic/testShiftLeft.js +38 -0
  3793. data/vendor/tracemonkey/trace-test/tests/basic/testShiftRightArithmetic.js +35 -0
  3794. data/vendor/tracemonkey/trace-test/tests/basic/testShiftRightLogical.js +38 -0
  3795. data/vendor/tracemonkey/trace-test/tests/basic/testSideExitInConstructor.js +39 -0
  3796. data/vendor/tracemonkey/trace-test/tests/basic/testSlowArrayLength.js +15 -0
  3797. data/vendor/tracemonkey/trace-test/tests/basic/testSlowArrayPop.js +12 -0
  3798. data/vendor/tracemonkey/trace-test/tests/basic/testSlowArrayPopMultiFrame.js +24 -0
  3799. data/vendor/tracemonkey/trace-test/tests/basic/testSlowArrayPopNestedTrees.js +36 -0
  3800. data/vendor/tracemonkey/trace-test/tests/basic/testSlowNativeBail.js +10 -0
  3801. data/vendor/tracemonkey/trace-test/tests/basic/testSlowNativeCtor.js +7 -0
  3802. data/vendor/tracemonkey/trace-test/tests/basic/testStrict.js +11 -0
  3803. data/vendor/tracemonkey/trace-test/tests/basic/testString.js +18 -0
  3804. data/vendor/tracemonkey/trace-test/tests/basic/testStringConstructorWithExtraArg.js +6 -0
  3805. data/vendor/tracemonkey/trace-test/tests/basic/testStringLengthNoTinyId.js +64 -0
  3806. data/vendor/tracemonkey/trace-test/tests/basic/testStringObjectLength.js +7 -0
  3807. data/vendor/tracemonkey/trace-test/tests/basic/testStringResolve.js +9 -0
  3808. data/vendor/tracemonkey/trace-test/tests/basic/testStringToInt32.js +6 -0
  3809. data/vendor/tracemonkey/trace-test/tests/basic/testStringify.js +20 -0
  3810. data/vendor/tracemonkey/trace-test/tests/basic/testSubstring.js +7 -0
  3811. data/vendor/tracemonkey/trace-test/tests/basic/testSwitch.js +25 -0
  3812. data/vendor/tracemonkey/trace-test/tests/basic/testSwitchString.js +28 -0
  3813. data/vendor/tracemonkey/trace-test/tests/basic/testSwitchUndefined.js +15 -0
  3814. data/vendor/tracemonkey/trace-test/tests/basic/testTableSwitch1.js +22 -0
  3815. data/vendor/tracemonkey/trace-test/tests/basic/testTableSwitch2.js +27 -0
  3816. data/vendor/tracemonkey/trace-test/tests/basic/testThinForEach.js +10 -0
  3817. data/vendor/tracemonkey/trace-test/tests/basic/testThinLoopDemote.js +20 -0
  3818. data/vendor/tracemonkey/trace-test/tests/basic/testThrowingObjectEqUndefined.js +18 -0
  3819. data/vendor/tracemonkey/trace-test/tests/basic/testToStringBeforeValueOf.js +13 -0
  3820. data/vendor/tracemonkey/trace-test/tests/basic/testToUpperToLower.js +9 -0
  3821. data/vendor/tracemonkey/trace-test/tests/basic/testTrueShiftTrue.js +16 -0
  3822. data/vendor/tracemonkey/trace-test/tests/basic/testTypeUnstableForIn.js +10 -0
  3823. data/vendor/tracemonkey/trace-test/tests/basic/testTypeofHole.js +8 -0
  3824. data/vendor/tracemonkey/trace-test/tests/basic/testUnaryImacros.js +26 -0
  3825. data/vendor/tracemonkey/trace-test/tests/basic/testUndefinedBooleanCmp.js +24 -0
  3826. data/vendor/tracemonkey/trace-test/tests/basic/testUndefinedCmp.js +6 -0
  3827. data/vendor/tracemonkey/trace-test/tests/basic/testUndefinedPropertyAccess.js +15 -0
  3828. data/vendor/tracemonkey/trace-test/tests/basic/testUndemotableBinaryOp.js +6 -0
  3829. data/vendor/tracemonkey/trace-test/tests/basic/testUndemoteLateGlobalSlots.js +11 -0
  3830. data/vendor/tracemonkey/trace-test/tests/basic/testWeirdDateParse.js +46 -0
  3831. data/vendor/tracemonkey/trace-test/tests/basic/testWhileObjectOrNull.js +18 -0
  3832. data/vendor/tracemonkey/trace-test/tests/basic/test_JSOP_ARGCNT.js +27 -0
  3833. data/vendor/tracemonkey/trace-test/tests/basic/test_JSOP_ARGSUB.js +27 -0
  3834. data/vendor/tracemonkey/trace-test/tests/basic/testif.js +11 -0
  3835. data/vendor/tracemonkey/trace-test/tests/basic/testincops.js +24 -0
  3836. data/vendor/tracemonkey/trace-test/tests/basic/trees.js +10 -0
  3837. data/vendor/tracemonkey/trace-test/tests/basic/truthies.js +29 -0
  3838. data/vendor/tracemonkey/trace-test/tests/basic/typeofTest.js +8 -0
  3839. data/vendor/tracemonkey/trace-test/tests/basic/unboxint.js +8 -0
  3840. data/vendor/tracemonkey/trace-test/tests/basic/xprop.js +8 -0
  3841. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-3d-morph.js +5 -1
  3842. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-3d-raytrace.js +1 -3
  3843. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-access-binary-trees.js +1 -1
  3844. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-access-fannkuch.js +1 -1
  3845. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-access-nbody.js +1 -1
  3846. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-access-nsieve.js +1 -1
  3847. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-bitops-3bit-bits-in-byte.js +1 -1
  3848. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-bitops-bits-in-byte.js +1 -1
  3849. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-bitops-bitwise-and.js +1 -1
  3850. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-bitops-nsieve-bits.js +1 -1
  3851. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-controlflow-recursive.js +1 -1
  3852. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-date-format-tofte.js +1 -1
  3853. data/vendor/tracemonkey/trace-test/tests/sunspider/check-date-format-xparb.js +422 -0
  3854. data/vendor/tracemonkey/{correct → trace-test/tests/sunspider}/check-mont.js +1 -1
  3855. data/vendor/tracemonkey/trace-test/trace-test.py +330 -0
  3856. data/vendor/tracemonkey/tracevis/README +50 -0
  3857. data/vendor/tracemonkey/tracevis/acts.py +64 -0
  3858. data/vendor/tracemonkey/tracevis/binlog.py +140 -0
  3859. data/vendor/tracemonkey/tracevis/config.py +5 -0
  3860. data/vendor/tracemonkey/tracevis/tree.py +282 -0
  3861. data/vendor/tracemonkey/tracevis/vis.py +233 -0
  3862. data/vendor/tracemonkey/{config/revdepth-nt.pl → vprof/manifest.mk} +8 -17
  3863. data/vendor/tracemonkey/vprof/testVprofMT.c +125 -0
  3864. data/vendor/tracemonkey/vprof/vprof.h +10 -12
  3865. data/vendor/tracemonkey/xpconnect/idl/nsIXPCScriptable.idl +2 -2
  3866. data/vendor/tracemonkey/xpconnect/idl/nsIXPConnect.idl +43 -22
  3867. data/vendor/tracemonkey/xpconnect/idl/xpcIJSWeakReference.idl +0 -0
  3868. data/vendor/tracemonkey/xpconnect/idl/xpcexception.idl +12 -1
  3869. data/vendor/tracemonkey/xpconnect/loader/XPCOMUtils.jsm +49 -3
  3870. data/vendor/tracemonkey/xpconnect/loader/mozJSComponentLoader.cpp +10 -20
  3871. data/vendor/tracemonkey/xpconnect/shell/Makefile.in +2 -1
  3872. data/vendor/tracemonkey/xpconnect/shell/xpcshell.cpp +120 -40
  3873. data/vendor/tracemonkey/xpconnect/src/Makefile.in +10 -7
  3874. data/vendor/tracemonkey/xpconnect/src/XPCChromeObjectWrapper.cpp +769 -0
  3875. data/vendor/tracemonkey/xpconnect/src/XPCCrossOriginWrapper.cpp +25 -19
  3876. data/vendor/tracemonkey/xpconnect/src/XPCDispConvert.cpp +4 -0
  3877. data/vendor/tracemonkey/xpconnect/src/XPCDispInlines.h +4 -5
  3878. data/vendor/tracemonkey/xpconnect/src/XPCDispPrivate.h +2 -10
  3879. data/vendor/tracemonkey/xpconnect/src/XPCDispTypeInfo.cpp +7 -12
  3880. data/vendor/tracemonkey/xpconnect/src/XPCIDispatchExtension.cpp +0 -198
  3881. data/vendor/tracemonkey/xpconnect/src/XPCNativeWrapper.cpp +16 -9
  3882. data/vendor/tracemonkey/xpconnect/src/XPCNativeWrapper.h +1 -1
  3883. data/vendor/tracemonkey/xpconnect/src/XPCSafeJSObjectWrapper.cpp +143 -269
  3884. data/vendor/tracemonkey/xpconnect/src/XPCSystemOnlyWrapper.cpp +9 -1
  3885. data/vendor/tracemonkey/xpconnect/src/XPCWrapper.cpp +3 -2
  3886. data/vendor/tracemonkey/xpconnect/src/XPCWrapper.h +19 -4
  3887. data/vendor/tracemonkey/xpconnect/src/dom_quickstubs.qsconf +44 -48
  3888. data/vendor/tracemonkey/xpconnect/src/nsDispatchSupport.cpp +6 -3
  3889. data/vendor/tracemonkey/xpconnect/src/nsXPConnect.cpp +325 -202
  3890. data/vendor/tracemonkey/xpconnect/src/qsgen.py +67 -71
  3891. data/vendor/tracemonkey/xpconnect/src/xpcJSWeakReference.cpp +0 -0
  3892. data/vendor/tracemonkey/xpconnect/src/xpcJSWeakReference.h +0 -0
  3893. data/vendor/tracemonkey/xpconnect/src/xpccallcontext.cpp +82 -13
  3894. data/vendor/tracemonkey/xpconnect/src/xpccomponents.cpp +36 -28
  3895. data/vendor/tracemonkey/xpconnect/src/xpcconvert.cpp +139 -44
  3896. data/vendor/tracemonkey/xpconnect/src/xpcdebug.cpp +7 -0
  3897. data/vendor/tracemonkey/xpconnect/src/xpcexception.cpp +13 -7
  3898. data/vendor/tracemonkey/xpconnect/src/xpcforwards.h +0 -1
  3899. data/vendor/tracemonkey/xpconnect/src/xpcinlines.h +27 -10
  3900. data/vendor/tracemonkey/xpconnect/src/xpcjsid.cpp +47 -35
  3901. data/vendor/tracemonkey/xpconnect/src/xpcjsruntime.cpp +48 -67
  3902. data/vendor/tracemonkey/xpconnect/src/xpclog.cpp +35 -0
  3903. data/vendor/tracemonkey/xpconnect/src/xpclog.h +55 -0
  3904. data/vendor/tracemonkey/xpconnect/src/xpcprivate.h +322 -75
  3905. data/vendor/tracemonkey/xpconnect/src/xpcquickstubs.cpp +142 -114
  3906. data/vendor/tracemonkey/xpconnect/src/xpcquickstubs.h +25 -49
  3907. data/vendor/tracemonkey/xpconnect/src/xpcstring.cpp +14 -7
  3908. data/vendor/tracemonkey/xpconnect/src/xpcthreadcontext.cpp +6 -6
  3909. data/vendor/tracemonkey/xpconnect/src/xpcthrower.cpp +10 -3
  3910. data/vendor/tracemonkey/xpconnect/src/xpcvariant.cpp +9 -8
  3911. data/vendor/tracemonkey/xpconnect/src/xpcwrappedjs.cpp +15 -14
  3912. data/vendor/tracemonkey/xpconnect/src/xpcwrappedjsclass.cpp +109 -111
  3913. data/vendor/tracemonkey/xpconnect/src/xpcwrappednative.cpp +498 -118
  3914. data/vendor/tracemonkey/xpconnect/src/xpcwrappednativeinfo.cpp +5 -6
  3915. data/vendor/tracemonkey/xpconnect/src/xpcwrappednativejsops.cpp +188 -25
  3916. data/vendor/tracemonkey/xpconnect/src/xpcwrappednativeproto.cpp +6 -3
  3917. data/vendor/tracemonkey/xpconnect/src/xpcwrappednativescope.cpp +46 -27
  3918. data/vendor/tracemonkey/xpconnect/tests/TestXPC.cpp +118 -115
  3919. data/vendor/tracemonkey/xpconnect/tests/chrome/Makefile.in +2 -0
  3920. data/vendor/tracemonkey/xpconnect/tests/chrome/bug503926.xul +28 -0
  3921. data/vendor/tracemonkey/xpconnect/tests/chrome/test_bug503926.xul +43 -0
  3922. data/vendor/tracemonkey/xpconnect/tests/idispatch/Tests/jsDriver.pl +1 -61
  3923. data/vendor/tracemonkey/xpconnect/tests/js/old/xpctest_observer.js +1 -2
  3924. data/vendor/tracemonkey/xpconnect/tests/mochitest/Makefile.in +3 -0
  3925. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_bug390488.html +1 -1
  3926. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_bug393269.html +1 -1
  3927. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_bug396851.html +1 -1
  3928. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_bug428021.html +1 -1
  3929. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_bug446584.html +1 -1
  3930. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_bug448587.html +1 -1
  3931. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_bug462428.html +1 -1
  3932. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_bug478438.html +1 -1
  3933. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_bug484107.html +1 -1
  3934. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_bug502959.html +38 -0
  3935. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_bug503926.html +30 -0
  3936. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_cows.html +179 -0
  3937. data/vendor/tracemonkey/xpconnect/tests/mochitest/test_wrappers.html +9 -0
  3938. data/vendor/tracemonkey/xpconnect/tests/unit/test_iterate.js +54 -0
  3939. data/vendor/tracemonkey/xpconnect/tests/unit/test_js_weak_references.js +0 -0
  3940. data/vendor/tracemonkey/xpconnect/tests/unit/test_xpcomutils.js +135 -0
  3941. data/vendor/tracemonkey/xpconnect/tools/src/nsXPCToolsCompiler.cpp +1 -1
  3942. data/vendor/tracemonkey/xpconnect/tools/src/xpctools_private.h +1 -1
  3943. metadata +3711 -35
  3944. data/vendor/tracemonkey/build/autoconf/update-makefile.sh +0 -118
  3945. data/vendor/tracemonkey/correct.sh +0 -23
  3946. data/vendor/tracemonkey/correct/check-date-format-xparb.js +0 -421
  3947. data/vendor/tracemonkey/if.js +0 -13
  3948. data/vendor/tracemonkey/js3240.rc +0 -79
  3949. data/vendor/tracemonkey/jsOS240.def +0 -654
  3950. data/vendor/tracemonkey/math-partial-sums.js +0 -32
  3951. data/vendor/tracemonkey/md5.js +0 -289
  3952. data/vendor/tracemonkey/nanojit/NativeThumb.cpp +0 -1322
  3953. data/vendor/tracemonkey/nanojit/NativeThumb.h +0 -525
  3954. data/vendor/tracemonkey/nanojit/TraceTreeDrawer.cpp +0 -306
@@ -0,0 +1,392 @@
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+ /* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: nil; tab-width: 4 -*- */
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+ /* vi: set ts=4 sw=4 expandtab: (add to ~/.vimrc: set modeline modelines=5) */
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+ /* ***** BEGIN LICENSE BLOCK *****
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+ * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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+ *
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+ * The contents of this file are subject to the Mozilla Public License Version
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+ * 1.1 (the "License"); you may not use this file except in compliance with
8
+ * the License. You may obtain a copy of the License at
9
+ * http://www.mozilla.org/MPL/
10
+ *
11
+ * Software distributed under the License is distributed on an "AS IS" basis,
12
+ * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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+ * for the specific language governing rights and limitations under the
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+ * License.
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+ *
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+ * The Original Code is [Open Source Virtual Machine].
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+ *
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+ * The Initial Developer of the Original Code is
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+ * Adobe System Incorporated.
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+ * Portions created by the Initial Developer are Copyright (C) 2008
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+ * the Initial Developer. All Rights Reserved.
22
+ *
23
+ * Contributor(s):
24
+ * Adobe AS3 Team
25
+ *
26
+ * Alternatively, the contents of this file may be used under the terms of
27
+ * either the GNU General Public License Version 2 or later (the "GPL"), or
28
+ * the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
29
+ * in which case the provisions of the GPL or the LGPL are applicable instead
30
+ * of those above. If you wish to allow use of your version of this file only
31
+ * under the terms of either the GPL or the LGPL, and not to allow others to
32
+ * use your version of this file under the terms of the MPL, indicate your
33
+ * decision by deleting the provisions above and replace them with the notice
34
+ * and other provisions required by the GPL or the LGPL. If you do not delete
35
+ * the provisions above, a recipient may use your version of this file under
36
+ * the terms of any one of the MPL, the GPL or the LGPL.
37
+ *
38
+ * ***** END LICENSE BLOCK ***** */
39
+
40
+ #ifndef __nanojit_NativeX64__
41
+ #define __nanojit_NativeX64__
42
+
43
+ #ifndef NANOJIT_64BIT
44
+ #error "NANOJIT_64BIT must be defined for X64 backend"
45
+ #endif
46
+
47
+ #ifdef PERFM
48
+ #define DOPROF
49
+ #include "../vprof/vprof.h"
50
+ #define count_instr() _nvprof("x64",1)
51
+ #define count_prolog() _nvprof("x64-prolog",1); count_instr();
52
+ #define count_imt() _nvprof("x64-imt",1) count_instr()
53
+ #else
54
+ #define count_instr()
55
+ #define count_prolog()
56
+ #define count_imt()
57
+ #endif
58
+
59
+ namespace nanojit
60
+ {
61
+ #define NJ_MAX_STACK_ENTRY 256
62
+ #define NJ_ALIGN_STACK 16
63
+
64
+ enum Register {
65
+ RAX = 0, // 1st int return, # of sse varargs
66
+ RCX = 1, // 4th int arg
67
+ RDX = 2, // 3rd int arg 2nd return
68
+ RBX = 3, // saved
69
+ RSP = 4, // stack ptr
70
+ RBP = 5, // frame ptr, saved, sib reqd
71
+ RSI = 6, // 2nd int arg
72
+ RDI = 7, // 1st int arg
73
+ R8 = 8, // 5th int arg
74
+ R9 = 9, // 6th int arg
75
+ R10 = 10, // scratch
76
+ R11 = 11, // scratch
77
+ R12 = 12, // saved
78
+ R13 = 13, // saved, sib reqd like rbp
79
+ R14 = 14, // saved
80
+ R15 = 15, // saved
81
+
82
+ XMM0 = 16, // 1st double arg, return
83
+ XMM1 = 17, // 2nd double arg, return
84
+ XMM2 = 18, // 3rd double arg
85
+ XMM3 = 19, // 4th double arg
86
+ XMM4 = 20, // 5th double arg
87
+ XMM5 = 21, // 6th double arg
88
+ XMM6 = 22, // 7th double arg
89
+ XMM7 = 23, // 8th double arg
90
+ XMM8 = 24, // scratch
91
+ XMM9 = 25, // scratch
92
+ XMM10 = 26, // scratch
93
+ XMM11 = 27, // scratch
94
+ XMM12 = 28, // scratch
95
+ XMM13 = 29, // scratch
96
+ XMM14 = 30, // scratch
97
+ XMM15 = 31, // scratch
98
+
99
+ FP = RBP,
100
+ UnknownReg = 32,
101
+ FirstReg = RAX,
102
+ LastReg = XMM15
103
+ };
104
+
105
+ /*
106
+ * Micro-templating variable-length opcodes, idea first
107
+ * describe by Mike Pall of Luajit.
108
+ *
109
+ * X86-64 opcode encodings: LSB encodes the length of the
110
+ * opcode in bytes, remaining bytes are encoded as 1-7 bytes
111
+ * in a single uint64_t value. The value is written as a single
112
+ * store into the code stream, and the code pointer is decremented
113
+ * by the length. each successive instruction partially overlaps
114
+ * the previous one.
115
+ *
116
+ * emit methods below are able to encode mod/rm, sib, rex, and
117
+ * register and small immediate values into these opcode values
118
+ * without much branchy code.
119
+ *
120
+ * these opcodes encapsulate all the const parts of the instruction.
121
+ * for example, the alu-immediate opcodes (add, sub, etc) encode
122
+ * part of their opcode in the R field of the mod/rm byte; this
123
+ * hardcoded value is in the constant below, and the R argument
124
+ * to emitrr() is 0. In a few cases, a whole instruction is encoded
125
+ * this way (eg callrax).
126
+ *
127
+ * when a disp32, imm32, or imm64 suffix can't fit in an 8-byte
128
+ * opcode, then it is written into the code separately and not counted
129
+ * in the opcode length.
130
+ */
131
+
132
+ enum X64Opcode
133
+ #if defined(_MSC_VER) && _MSC_VER >= 1400
134
+ #pragma warning(disable:4480) // nonstandard extension used: specifying underlying type for enum
135
+ : uint64_t
136
+ #endif
137
+ {
138
+ // 64bit opcode constants
139
+ // msb lsb len
140
+ X64_addqrr = 0xC003480000000003LL, // 64bit add r += b
141
+ X64_addqri = 0xC081480000000003LL, // 64bit add r += int64(imm32)
142
+ X64_addqr8 = 0x00C0834800000004LL, // 64bit add r += int64(imm8)
143
+ X64_andqri = 0xE081480000000003LL, // 64bit and r &= int64(imm32)
144
+ X64_andqr8 = 0x00E0834800000004LL, // 64bit and r &= int64(imm8)
145
+ X64_orqri = 0xC881480000000003LL, // 64bit or r |= int64(imm32)
146
+ X64_orqr8 = 0x00C8834800000004LL, // 64bit or r |= int64(imm8)
147
+ X64_xorqri = 0xF081480000000003LL, // 64bit xor r ^= int64(imm32)
148
+ X64_xorqr8 = 0x00F0834800000004LL, // 64bit xor r ^= int64(imm8)
149
+ X64_addlri = 0xC081400000000003LL, // 32bit add r += imm32
150
+ X64_addlr8 = 0x00C0834000000004LL, // 32bit add r += imm8
151
+ X64_andlri = 0xE081400000000003LL, // 32bit and r &= imm32
152
+ X64_andlr8 = 0x00E0834000000004LL, // 32bit and r &= imm8
153
+ X64_orlri = 0xC881400000000003LL, // 32bit or r |= imm32
154
+ X64_orlr8 = 0x00C8834000000004LL, // 32bit or r |= imm8
155
+ X64_sublri = 0xE881400000000003LL, // 32bit sub r -= imm32
156
+ X64_sublr8 = 0x00E8834000000004LL, // 32bit sub r -= imm8
157
+ X64_xorlri = 0xF081400000000003LL, // 32bit xor r ^= imm32
158
+ X64_xorlr8 = 0x00F0834000000004LL, // 32bit xor r ^= imm8
159
+ X64_addrr = 0xC003400000000003LL, // 32bit add r += b
160
+ X64_andqrr = 0xC023480000000003LL, // 64bit and r &= b
161
+ X64_andrr = 0xC023400000000003LL, // 32bit and r &= b
162
+ X64_call = 0x00000000E8000005LL, // near call
163
+ X64_callrax = 0xD0FF000000000002LL, // indirect call to addr in rax (no REX)
164
+ X64_cmovqno = 0xC0410F4800000004LL, // 64bit conditional mov if (no overflow) r = b
165
+ X64_cmovqb = 0xC0420F4800000004LL, // 64bit conditional mov if (uint <) r = b
166
+ X64_cmovqae = 0xC0430F4800000004LL, // 64bit conditional mov if (uint >=) r = b
167
+ X64_cmovqne = 0xC0450F4800000004LL, // 64bit conditional mov if (c) r = b
168
+ X64_cmovqbe = 0xC0460F4800000004LL, // 64bit conditional mov if (uint <=) r = b
169
+ X64_cmovqa = 0xC0470F4800000004LL, // 64bit conditional mov if (uint >) r = b
170
+ X64_cmovql = 0xC04C0F4800000004LL, // 64bit conditional mov if (int <) r = b
171
+ X64_cmovqge = 0xC04D0F4800000004LL, // 64bit conditional mov if (int >=) r = b
172
+ X64_cmovqle = 0xC04E0F4800000004LL, // 64bit conditional mov if (int <=) r = b
173
+ X64_cmovqg = 0xC04F0F4800000004LL, // 64bit conditional mov if (int >) r = b
174
+ X64_cmovno = 0xC0410F4000000004LL, // 32bit conditional mov if (no overflow) r = b
175
+ X64_cmovb = 0xC0420F4000000004LL, // 32bit conditional mov if (uint <) r = b
176
+ X64_cmovae = 0xC0430F4000000004LL, // 32bit conditional mov if (uint >=) r = b
177
+ X64_cmovne = 0xC0450F4000000004LL, // 32bit conditional mov if (c) r = b
178
+ X64_cmovbe = 0xC0460F4000000004LL, // 32bit conditional mov if (uint <=) r = b
179
+ X64_cmova = 0xC0470F4000000004LL, // 32bit conditional mov if (uint >) r = b
180
+ X64_cmovl = 0xC04C0F4000000004LL, // 32bit conditional mov if (int <) r = b
181
+ X64_cmovge = 0xC04D0F4000000004LL, // 32bit conditional mov if (int >=) r = b
182
+ X64_cmovle = 0xC04E0F4000000004LL, // 32bit conditional mov if (int <=) r = b
183
+ X64_cmovg = 0xC04F0F4000000004LL, // 32bit conditional mov if (int >) r = b
184
+ X64_cmov_64 = 0x0000000800000000LL, // OR with 32-bit cmov to promote to 64-bit
185
+ X64_cmplr = 0xC03B400000000003LL, // 32bit compare r,b
186
+ X64_cmpqr = 0xC03B480000000003LL, // 64bit compare r,b
187
+ X64_cmplri = 0xF881400000000003LL, // 32bit compare r,imm32
188
+ X64_cmpqri = 0xF881480000000003LL, // 64bit compare r,int64(imm32)
189
+ X64_cmplr8 = 0x00F8834000000004LL, // 32bit compare r,imm8
190
+ X64_cmpqr8 = 0x00F8834800000004LL, // 64bit compare r,int64(imm8)
191
+ X64_cvtsi2sd= 0xC02A0F40F2000005LL, // convert int32 to double r = (double) b
192
+ X64_cvtsq2sd= 0xC02A0F48F2000005LL, // convert int64 to double r = (double) b
193
+ X64_divsd = 0xC05E0F40F2000005LL, // divide scalar double r /= b
194
+ X64_mulsd = 0xC0590F40F2000005LL, // multiply scalar double r *= b
195
+ X64_addsd = 0xC0580F40F2000005LL, // add scalar double r += b
196
+ X64_idiv = 0xF8F7400000000003LL, // 32bit signed div (rax = rdx:rax/r, rdx=rdx:rax%r)
197
+ X64_imul = 0xC0AF0F4000000004LL, // 32bit signed mul r *= b
198
+ X64_imuli = 0xC069400000000003LL, // 32bit signed mul r = b * imm32
199
+ X64_imul8 = 0x00C06B4000000004LL, // 32bit signed mul r = b * imm8
200
+ X64_jmp = 0x00000000E9000005LL, // jump near rel32
201
+ X64_jmp8 = 0x00EB000000000002LL, // jump near rel8
202
+ X64_jo = 0x00000000800F0006LL, // jump near if overflow
203
+ X64_jb = 0x00000000820F0006LL, // jump near if below (uint <)
204
+ X64_jae = 0x00000000830F0006LL, // jump near if above or equal (uint >=)
205
+ X64_ja = 0x00000000870F0006LL, // jump near if above (uint >)
206
+ X64_jbe = 0x00000000860F0006LL, // jump near if below or equal (uint <=)
207
+ X64_je = 0x00000000840F0006LL, // near jump if equal
208
+ X64_jne = 0x00000000850F0006LL, // jump near if not equal
209
+ X64_jl = 0x000000008C0F0006LL, // jump near if less (int <)
210
+ X64_jge = 0x000000008D0F0006LL, // jump near if greater or equal (int >=)
211
+ X64_jg = 0x000000008F0F0006LL, // jump near if greater (int >)
212
+ X64_jle = 0x000000008E0F0006LL, // jump near if less or equal (int <=)
213
+ X64_jp = 0x000000008A0F0006LL, // jump near if parity (PF == 1)
214
+ X64_jnp = 0x000000008B0F0006LL, // jump near if not parity (PF == 0)
215
+ X64_jneg = 0x0000000001000000LL, // xor with this mask to negate the condition
216
+ X64_jo8 = 0x0070000000000002LL, // jump near if overflow
217
+ X64_jb8 = 0x0072000000000002LL, // jump near if below (uint <)
218
+ X64_jae8 = 0x0073000000000002LL, // jump near if above or equal (uint >=)
219
+ X64_ja8 = 0x0077000000000002LL, // jump near if above (uint >)
220
+ X64_jbe8 = 0x0076000000000002LL, // jump near if below or equal (uint <=)
221
+ X64_je8 = 0x0074000000000002LL, // near jump if equal
222
+ X64_jne8 = 0x0075000000000002LL, // jump near if not equal
223
+ X64_jl8 = 0x007C000000000002LL, // jump near if less (int <)
224
+ X64_jge8 = 0x007D000000000002LL, // jump near if greater or equal (int >=)
225
+ X64_jg8 = 0x007F000000000002LL, // jump near if greater (int >)
226
+ X64_jle8 = 0x007E000000000002LL, // jump near if less or equal (int <=)
227
+ X64_jp8 = 0x007A000000000002LL, // jump near if parity (PF == 1)
228
+ X64_jnp8 = 0x007B000000000002LL, // jump near if not parity (PF == 0)
229
+ X64_jneg8 = 0x0001000000000000LL, // xor with this mask to negate the condition
230
+ X64_leaqrm = 0x00000000808D4807LL, // 64bit load effective addr reg <- disp32+base
231
+ X64_learm = 0x00000000808D4007LL, // 32bit load effective addr reg <- disp32+base
232
+ X64_movlr = 0xC08B400000000003LL, // 32bit mov r <- b
233
+ X64_movlmr = 0x0000000080894007LL, // 32bit store r -> [b+d32]
234
+ X64_movlrm = 0x00000000808B4007LL, // 32bit load r <- [b+d32]
235
+ X64_movqmr = 0x0000000080894807LL, // 64bit store gpr -> [b+d32]
236
+ X64_movqspr = 0x0024448948000005LL, // 64bit store gpr -> [rsp+d32] (sib required)
237
+ X64_movqr = 0xC08B480000000003LL, // 64bit mov r <- b
238
+ X64_movqi = 0xB848000000000002LL, // 64bit mov r <- imm64
239
+ X64_movi = 0xB840000000000002LL, // 32bit mov r <- imm32
240
+ X64_movqi32 = 0xC0C7480000000003LL, // 64bit mov r <- int64(imm32)
241
+ X64_movapsr = 0xC0280F4000000004LL, // 128bit mov xmm <- xmm
242
+ X64_movqrx = 0xC07E0F4866000005LL, // 64bit mov b <- xmm-r
243
+ X64_movqxr = 0xC06E0F4866000005LL, // 64bit mov b -> xmm-r
244
+ X64_movqrm = 0x00000000808B4807LL, // 64bit load r <- [b+d32]
245
+ X64_movsdrr = 0xC0100F40F2000005LL, // 64bit mov xmm-r <- xmm-b (upper 64bits unchanged)
246
+ X64_movsdrm = 0x80100F40F2000005LL, // 64bit load xmm-r <- [b+d32] (upper 64 cleared)
247
+ X64_movsdmr = 0x80110F40F2000005LL, // 64bit store xmm-r -> [b+d32]
248
+ X64_movsxdr = 0xC063480000000003LL, // sign extend i32 to i64 r = (int64)(int32) b
249
+ X64_movzx8 = 0xC0B60F4000000004LL, // zero extend i8 to i64 r = (uint64)(uint8) b
250
+ X64_movzx8m = 0x80B60F4000000004LL, // zero extend i8 load to i32 r <- [b+d32]
251
+ X64_movzx16m= 0x80B70F4000000004LL, // zero extend i16 load to i32 r <- [b+d32]
252
+ X64_neg = 0xD8F7400000000003LL, // 32bit two's compliment b = -b
253
+ X64_nop1 = 0x9000000000000001LL, // one byte NOP
254
+ X64_nop2 = 0x9066000000000002LL, // two byte NOP
255
+ X64_nop3 = 0x001F0F0000000003LL, // three byte NOP
256
+ X64_nop4 = 0x00401F0F00000004LL, // four byte NOP
257
+ X64_nop5 = 0x0000441F0F000005LL, // five byte NOP
258
+ X64_nop6 = 0x0000441F0F660006LL, // six byte NOP
259
+ X64_nop7 = 0x00000000801F0F07LL, // seven byte NOP
260
+ X64_not = 0xD0F7400000000003LL, // 32bit ones compliment b = ~b
261
+ X64_orlrr = 0xC00B400000000003LL, // 32bit or r |= b
262
+ X64_orqrr = 0xC00B480000000003LL, // 64bit or r |= b
263
+ X64_popr = 0x5840000000000002LL, // 64bit pop r <- [rsp++]
264
+ X64_pushr = 0x5040000000000002LL, // 64bit push r -> [--rsp]
265
+ X64_pxor = 0xC0EF0F4066000005LL, // 128bit xor xmm-r ^= xmm-b
266
+ X64_ret = 0xC300000000000001LL, // near return from called procedure
267
+ X64_sete = 0xC0940F4000000004LL, // set byte if equal (ZF == 1)
268
+ X64_seto = 0xC0900F4000000004LL, // set byte if overflow (OF == 1)
269
+ X64_setc = 0xC0920F4000000004LL, // set byte if carry (CF == 1)
270
+ X64_setl = 0xC09C0F4000000004LL, // set byte if less (int <) (SF != OF)
271
+ X64_setle = 0xC09E0F4000000004LL, // set byte if less or equal (int <=) (ZF == 1 || SF != OF)
272
+ X64_setg = 0xC09F0F4000000004LL, // set byte if greater (int >) (ZF == 0 && SF == OF)
273
+ X64_setge = 0xC09D0F4000000004LL, // set byte if greater or equal (int >=) (SF == OF)
274
+ X64_seta = 0xC0970F4000000004LL, // set byte if above (uint >) (CF == 0 && ZF == 0)
275
+ X64_setae = 0xC0930F4000000004LL, // set byte if above or equal (uint >=) (CF == 0)
276
+ X64_setb = 0xC0920F4000000004LL, // set byte if below (uint <) (CF == 1)
277
+ X64_setbe = 0xC0960F4000000004LL, // set byte if below or equal (uint <=) (ZF == 1 || CF == 1)
278
+ X64_subsd = 0xC05C0F40F2000005LL, // subtract scalar double r -= b
279
+ X64_shl = 0xE0D3400000000003LL, // 32bit left shift r <<= rcx
280
+ X64_shlq = 0xE0D3480000000003LL, // 64bit left shift r <<= rcx
281
+ X64_shr = 0xE8D3400000000003LL, // 32bit uint right shift r >>= rcx
282
+ X64_shrq = 0xE8D3480000000003LL, // 64bit uint right shift r >>= rcx
283
+ X64_sar = 0xF8D3400000000003LL, // 32bit int right shift r >>= rcx
284
+ X64_sarq = 0xF8D3480000000003LL, // 64bit int right shift r >>= rcx
285
+ X64_shli = 0x00E0C14000000004LL, // 32bit left shift r <<= imm8
286
+ X64_shlqi = 0x00E0C14800000004LL, // 64bit left shift r <<= imm8
287
+ X64_sari = 0x00F8C14000000004LL, // 32bit int right shift r >>= imm8
288
+ X64_sarqi = 0x00F8C14800000004LL, // 64bit int right shift r >>= imm8
289
+ X64_shri = 0x00E8C14000000004LL, // 32bit uint right shift r >>= imm8
290
+ X64_shrqi = 0x00E8C14800000004LL, // 64bit uint right shift r >>= imm8
291
+ X64_subqrr = 0xC02B480000000003LL, // 64bit sub r -= b
292
+ X64_subrr = 0xC02B400000000003LL, // 32bit sub r -= b
293
+ X64_subqri = 0xE881480000000003LL, // 64bit sub r -= int64(imm32)
294
+ X64_subqr8 = 0x00E8834800000004LL, // 64bit sub r -= int64(imm8)
295
+ X64_ucomisd = 0xC02E0F4066000005LL, // unordered compare scalar double
296
+ X64_xorqrr = 0xC033480000000003LL, // 64bit xor r &= b
297
+ X64_xorrr = 0xC033400000000003LL, // 32bit xor r &= b
298
+ X64_xorpd = 0xC0570F4066000005LL, // 128bit xor xmm (two packed doubles)
299
+ X64_xorps = 0xC0570F4000000004LL, // 128bit xor xmm (four packed singles), one byte shorter
300
+ X64_xorpsm = 0x05570F4000000004LL, // 128bit xor xmm, [rip+disp32]
301
+ X64_xorpsa = 0x2504570F40000005LL, // 128bit xor xmm, [disp32]
302
+
303
+ X86_and8r = 0xC022000000000002LL, // and rl,rh
304
+ X86_sete = 0xC0940F0000000003LL, // no-rex version of X64_sete
305
+ X86_setnp = 0xC09B0F0000000003LL // no-rex set byte if odd parity (ordered fcmp result) (PF == 0)
306
+ };
307
+
308
+ typedef uint32_t RegisterMask;
309
+
310
+ static const RegisterMask GpRegs = 0xffff;
311
+ static const RegisterMask FpRegs = 0xffff0000;
312
+ static const bool CalleeRegsNeedExplicitSaving = true;
313
+ #ifdef _MSC_VER
314
+ static const RegisterMask SavedRegs = 1<<RBX | 1<<RSI | 1<<RDI | 1<<R12 | 1<<R13 | 1<<R14 | 1<<R15;
315
+ static const int NumSavedRegs = 7; // rbx, rsi, rdi, r12-15
316
+ static const int NumArgRegs = 4;
317
+ #else
318
+ static const RegisterMask SavedRegs = 1<<RBX | 1<<R12 | 1<<R13 | 1<<R14 | 1<<R15;
319
+ static const int NumSavedRegs = 5; // rbx, r12-15
320
+ static const int NumArgRegs = 6;
321
+ #endif
322
+
323
+ static inline bool isValidDisplacement(int32_t d) {
324
+ return true;
325
+ }
326
+ static inline bool IsFpReg(Register r) {
327
+ return ((1<<r) & FpRegs) != 0;
328
+ }
329
+ static inline bool IsGpReg(Register r) {
330
+ return ((1<<r) & GpRegs) != 0;
331
+ }
332
+
333
+ verbose_only( extern const char* regNames[]; )
334
+
335
+ #define DECLARE_PLATFORM_STATS()
336
+ #define DECLARE_PLATFORM_REGALLOC()
337
+
338
+ #define DECLARE_PLATFORM_ASSEMBLER() \
339
+ const static Register argRegs[NumArgRegs], retRegs[1]; \
340
+ void underrunProtect(ptrdiff_t bytes); \
341
+ void nativePageReset(); \
342
+ void nativePageSetup(); \
343
+ void asm_qbinop(LIns*); \
344
+ void MR(Register, Register);\
345
+ void JMP(NIns*);\
346
+ void JMPl(NIns*);\
347
+ void emit(uint64_t op);\
348
+ void emit8(uint64_t op, int64_t val);\
349
+ void emit32(uint64_t op, int64_t val);\
350
+ void emitrr(uint64_t op, Register r, Register b);\
351
+ void emitrr8(uint64_t op, Register r, Register b);\
352
+ void emitr(uint64_t op, Register b) { emitrr(op, (Register)0, b); }\
353
+ void emitr8(uint64_t op, Register b) { emitrr8(op, (Register)0, b); }\
354
+ void emitprr(uint64_t op, Register r, Register b);\
355
+ void emitrm(uint64_t op, Register r, int32_t d, Register b);\
356
+ void emitrm_wide(uint64_t op, Register r, int32_t d, Register b);\
357
+ uint64_t emit_disp32(uint64_t op, int32_t d);\
358
+ void emitprm(uint64_t op, Register r, int32_t d, Register b);\
359
+ void emitrr_imm(uint64_t op, Register r, Register b, int32_t imm);\
360
+ void emitr_imm(uint64_t op, Register r, int32_t imm) { emitrr_imm(op, (Register)0, r, imm); }\
361
+ void emitr_imm8(uint64_t op, Register b, int32_t imm8);\
362
+ void emit_int(Register r, int32_t v);\
363
+ void emit_quad(Register r, uint64_t v);\
364
+ void asm_regarg(ArgSize, LIns*, Register);\
365
+ void asm_stkarg(ArgSize, LIns*, int);\
366
+ void asm_shift(LIns*);\
367
+ void asm_shift_imm(LIns*);\
368
+ void asm_arith_imm(LIns*);\
369
+ void regalloc_unary(LIns *ins, RegisterMask allow, Register &rr, Register &ra);\
370
+ void regalloc_binary(LIns *ins, RegisterMask allow, Register &rr, Register &ra, Register &rb);\
371
+ void regalloc_load(LIns *ins, Register &rr, int32_t &d, Register &rb);\
372
+ void dis(NIns *p, int bytes);\
373
+ void asm_cmp(LIns*);\
374
+ void asm_cmp_imm(LIns*);\
375
+ void fcmp(LIns*, LIns*);\
376
+ NIns* asm_fbranch(bool, LIns*, NIns*);\
377
+ void asm_div_mod(LIns *i);\
378
+ int max_stk_used;
379
+
380
+ #define swapptrs() { NIns* _tins = _nIns; _nIns=_nExitIns; _nExitIns=_tins; }
381
+
382
+ const int LARGEST_UNDERRUN_PROT = 32; // largest value passed to underrunProtect
383
+
384
+ typedef uint8_t NIns;
385
+
386
+ inline Register nextreg(Register r) {
387
+ return Register(r+1);
388
+ }
389
+
390
+ } // namespace nanojit
391
+
392
+ #endif // __nanojit_NativeX64__
@@ -1,4 +1,5 @@
1
- /* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: t; tab-width: 4 -*- */
1
+ /* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: nil; tab-width: 4 -*- */
2
+ /* vi: set ts=4 sw=4 expandtab: (add to ~/.vimrc: set modeline modelines=5) */
2
3
  /* ***** BEGIN LICENSE BLOCK *****
3
4
  * Version: MPL 1.1/GPL 2.0/LGPL 2.1
4
5
  *
@@ -37,6 +38,7 @@
37
38
  * the terms of any one of the MPL, the GPL or the LGPL.
38
39
  *
39
40
  * ***** END LICENSE BLOCK ***** */
41
+ #include "nanojit.h"
40
42
 
41
43
  #ifdef _MAC
42
44
  // for MakeDataExecutable
@@ -48,19 +50,20 @@
48
50
  #include <errno.h>
49
51
  #include <stdlib.h>
50
52
  #endif
51
- #include "nanojit.h"
52
53
 
53
54
  namespace nanojit
54
55
  {
55
- #ifdef FEATURE_NANOJIT
56
+ #if defined FEATURE_NANOJIT && defined NANOJIT_IA32
57
+
58
+ #ifdef NJ_VERBOSE
59
+ const char *regNames[] = {
60
+ "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
61
+ "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7",
62
+ "f0"
63
+ };
64
+ #endif
56
65
 
57
- #ifdef NJ_VERBOSE
58
- const char *regNames[] = {
59
- "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
60
- "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7",
61
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7"
62
- };
63
- #endif
66
+ #define TODO(x) do{ verbose_only(outputf(#x);) NanoAssertMsgf(false, "%s", #x); } while(0)
64
67
 
65
68
  const Register Assembler::argRegs[] = { ECX, EDX };
66
69
  const Register Assembler::retRegs[] = { EAX, EDX };
@@ -74,108 +77,111 @@ namespace nanojit
74
77
  };
75
78
 
76
79
 
77
- void Assembler::nInit(AvmCore* core)
78
- {
79
- (void) core;
80
- OSDep::getDate();
81
- }
80
+ void Assembler::nInit(AvmCore* core)
81
+ {
82
+ (void) core;
83
+ VMPI_getDate();
84
+ }
85
+
86
+ void Assembler::nBeginAssembly() {
87
+ }
82
88
 
83
- NIns* Assembler::genPrologue()
84
- {
85
- /**
86
- * Prologue
87
- */
88
- uint32_t stackNeeded = STACK_GRANULARITY * _activation.highwatermark;
89
+ NIns* Assembler::genPrologue()
90
+ {
91
+ /**
92
+ * Prologue
93
+ */
94
+ uint32_t stackNeeded = STACK_GRANULARITY * _activation.tos;
89
95
 
90
- uint32_t stackPushed =
96
+ uint32_t stackPushed =
91
97
  STACK_GRANULARITY + // returnaddr
92
- STACK_GRANULARITY + // ebp
93
- STACK_GRANULARITY; // dummy
94
-
95
- if (!_thisfrag->lirbuf->explicitSavedRegs)
96
- stackPushed += NumSavedRegs * STACK_GRANULARITY;
97
-
98
- uint32_t aligned = alignUp(stackNeeded + stackPushed, NJ_ALIGN_STACK);
99
- uint32_t amt = aligned - stackPushed;
100
-
101
- // Reserve stackNeeded bytes, padded
102
- // to preserve NJ_ALIGN_STACK-byte alignment.
103
- if (amt)
104
- SUBi(SP, amt);
105
-
106
- verbose_only( outputAddr=true; asm_output("[frag entry]"); )
98
+ STACK_GRANULARITY; // ebp
99
+
100
+ uint32_t aligned = alignUp(stackNeeded + stackPushed, NJ_ALIGN_STACK);
101
+ uint32_t amt = aligned - stackPushed;
102
+
103
+ // Reserve stackNeeded bytes, padded
104
+ // to preserve NJ_ALIGN_STACK-byte alignment.
105
+ if (amt)
106
+ {
107
+ SUBi(SP, amt);
108
+ }
109
+
110
+ verbose_only( outputAddr=true; asm_output("[frag entry]"); )
107
111
  NIns *fragEntry = _nIns;
108
- MR(FP, SP); // Establish our own FP.
112
+ MR(FP, SP); // Establish our own FP.
109
113
  PUSHr(FP); // Save caller's FP.
110
114
 
111
- if (!_thisfrag->lirbuf->explicitSavedRegs) {
112
- PUSHr(FP); // dummy
113
- for (int i = 0; i < NumSavedRegs; ++i)
114
- PUSHr(savedRegs[i]);
115
- }
116
-
117
- return fragEntry;
118
- }
115
+ return fragEntry;
116
+ }
119
117
 
120
- void Assembler::nFragExit(LInsp guard)
121
- {
122
- SideExit *exit = guard->record()->exit;
123
- bool trees = _frago->core()->config.tree_opt;
118
+ void Assembler::nFragExit(LInsp guard)
119
+ {
120
+ SideExit *exit = guard->record()->exit;
121
+ bool trees = config.tree_opt;
124
122
  Fragment *frag = exit->target;
125
123
  GuardRecord *lr = 0;
126
- bool destKnown = (frag && frag->fragEntry);
127
- // Generate jump to epilog and initialize lr.
128
- // If the guard is LIR_xtbl, use a jump table with epilog in every entry
129
- if (guard->isop(LIR_xtbl)) {
130
- lr = guard->record();
131
- Register r = EBX;
132
- SwitchInfo* si = guard->record()->exit->switchInfo;
133
- emitJumpTable(si, _epilogue);
134
- JMP_indirect(r);
135
- LEAmi4(r, si->table, r);
136
- } else {
137
- // If the guard already exists, use a simple jump.
138
- if (destKnown && !trees) {
139
- JMP(frag->fragEntry);
140
- lr = 0;
141
- } else { // target doesn't exist. Use 0 jump offset and patch later
142
- lr = guard->record();
143
- JMP_long(_epilogue);
144
- lr->jmp = _nIns;
145
- }
146
- }
147
- // first restore ESP from EBP, undoing SUBi(SP,amt) from genPrologue
124
+ bool destKnown = (frag && frag->fragEntry);
125
+
126
+ // Generate jump to epilog and initialize lr.
127
+ // If the guard is LIR_xtbl, use a jump table with epilog in every entry
128
+ if (guard->isop(LIR_xtbl)) {
129
+ lr = guard->record();
130
+ Register r = EDX;
131
+ SwitchInfo* si = guard->record()->exit->switchInfo;
132
+ if (!_epilogue)
133
+ _epilogue = genEpilogue();
134
+ emitJumpTable(si, _epilogue);
135
+ JMP_indirect(r);
136
+ LEAmi4(r, si->table, r);
137
+ } else {
138
+ // If the guard already exists, use a simple jump.
139
+ if (destKnown && !trees) {
140
+ JMP(frag->fragEntry);
141
+ lr = 0;
142
+ } else { // Target doesn't exist. Jump to an epilogue for now. This can be patched later.
143
+ if (!_epilogue)
144
+ _epilogue = genEpilogue();
145
+ lr = guard->record();
146
+ JMP_long(_epilogue);
147
+ lr->jmp = _nIns;
148
+ }
149
+ }
150
+
151
+ // profiling for the exit
152
+ verbose_only(
153
+ if (_logc->lcbits & LC_FragProfile) {
154
+ INCLi( &guard->record()->profCount );
155
+ }
156
+ )
157
+
158
+ // Restore ESP from EBP, undoing SUBi(SP,amt) in the prologue
148
159
  MR(SP,FP);
149
160
 
150
- // return value is GuardRecord*
161
+ // return value is GuardRecord*
151
162
  LDi(EAX, int(lr));
152
- }
163
+ }
153
164
 
154
165
  NIns *Assembler::genEpilogue()
155
166
  {
156
167
  RET();
157
-
158
- if (!_thisfrag->lirbuf->explicitSavedRegs) {
159
- for (int i = NumSavedRegs - 1; i >= 0; --i)
160
- POPr(savedRegs[i]);
161
- POPr(FP); // dummy
162
- }
163
-
164
168
  POPr(FP); // Restore caller's FP.
165
- MR(SP,FP); // pop the stack frame
169
+
166
170
  return _nIns;
167
171
  }
168
-
169
- void Assembler::asm_call(LInsp ins)
170
- {
172
+
173
+ void Assembler::asm_call(LInsp ins)
174
+ {
171
175
  const CallInfo* call = ins->callInfo();
172
- // must be signed, not unsigned
173
- uint32_t iargs = call->count_iargs();
174
- int32_t fargs = call->count_args() - iargs - call->isIndirect();
176
+ // must be signed, not unsigned
177
+ uint32_t iargs = call->count_iargs();
178
+ int32_t fargs = call->count_args() - iargs;
175
179
 
176
- bool imt = call->isInterface();
177
- if (imt)
180
+ bool indirect = call->isIndirect();
181
+ if (indirect) {
182
+ // target arg isn't pushed, its consumed in the call
178
183
  iargs --;
184
+ }
179
185
 
180
186
  uint32_t max_regs = max_abi_regs[call->_abi];
181
187
  if (max_regs > iargs)
@@ -183,291 +189,255 @@ namespace nanojit
183
189
 
184
190
  int32_t istack = iargs-max_regs; // first 2 4B args are in registers
185
191
  int32_t extra = 0;
186
- const int32_t pushsize = 4*istack + 8*fargs; // actual stack space used
192
+ const int32_t pushsize = 4*istack + 8*fargs; // actual stack space used
187
193
 
188
194
  #if _MSC_VER
189
- // msc is slack, and MIR doesn't do anything extra, so lets use this
190
- // call-site alignment to at least have code size parity with MIR.
195
+ // msc only provides 4-byte alignment, anything more than 4 on windows
196
+ // x86-32 requires dynamic ESP alignment in prolog/epilog and static
197
+ // esp-alignment here.
191
198
  uint32_t align = 4;//NJ_ALIGN_STACK;
192
199
  #else
193
200
  uint32_t align = NJ_ALIGN_STACK;
194
201
  #endif
195
202
 
196
203
  if (pushsize) {
197
- // stack re-alignment
198
- // only pop our adjustment amount since callee pops args in FASTCALL mode
199
- extra = alignUp(pushsize, align) - pushsize;
204
+ // stack re-alignment
205
+ // only pop our adjustment amount since callee pops args in FASTCALL mode
206
+ extra = alignUp(pushsize, align) - pushsize;
200
207
  if (call->_abi == ABI_CDECL) {
201
- // with CDECL only, caller pops args
208
+ // with CDECL only, caller pops args
202
209
  ADDi(SP, extra+pushsize);
203
210
  } else if (extra > 0) {
204
- ADDi(SP, extra);
211
+ ADDi(SP, extra);
205
212
  }
206
213
  }
207
214
 
208
- bool indirect = false;
209
- if (ins->isop(LIR_call) || ins->isop(LIR_fcall)) {
210
- CALL(call);
215
+ NanoAssert(ins->isop(LIR_pcall) || ins->isop(LIR_fcall));
216
+ if (!indirect) {
217
+ CALL(call);
211
218
  }
212
219
  else {
213
220
  // indirect call. x86 Calling conventions don't use EAX as an
214
221
  // argument, and do use EAX as a return value. We need a register
215
222
  // for the address to call, so we use EAX since it will always be
216
223
  // available
217
- NanoAssert(ins->isop(LIR_calli) || ins->isop(LIR_fcalli));
218
224
  CALLr(call, EAX);
219
- indirect = true;
220
225
  }
221
226
 
222
- // make sure fpu stack is empty before call (restoreCallerSaved)
223
- NanoAssert(_allocator.isFree(FST0));
224
- // note: this code requires that ref arguments (ARGSIZE_Q)
227
+ // make sure fpu stack is empty before call (restoreCallerSaved)
228
+ NanoAssert(_allocator.isFree(FST0));
229
+ // note: this code requires that ref arguments (ARGSIZE_Q)
225
230
  // be one of the first two arguments
226
- // pre-assign registers to the first N 4B args based on the calling convention
227
- uint32_t n = 0;
231
+ // pre-assign registers to the first N 4B args based on the calling convention
232
+ uint32_t n = 0;
228
233
 
229
- ArgSize sizes[2*MAXARGS];
234
+ ArgSize sizes[MAXARGS];
230
235
  uint32_t argc = call->get_sizes(sizes);
231
236
  if (indirect) {
232
237
  argc--;
233
- asm_arg(ARGSIZE_LO, ins->arg(argc), EAX);
234
- }
235
-
236
- if (imt) {
237
- // interface thunk calling convention: put iid in EDX
238
- NanoAssert(call->_abi == ABI_CDECL);
239
- argc--;
240
- asm_arg(ARGSIZE_LO, ins->arg(argc), EDX);
238
+ asm_arg(ARGSIZE_P, ins->arg(argc), EAX);
241
239
  }
242
240
 
243
- for(uint32_t i=0; i < argc; i++)
244
- {
245
- uint32_t j = argc-i-1;
241
+ for(uint32_t i=0; i < argc; i++)
242
+ {
243
+ uint32_t j = argc-i-1;
246
244
  ArgSize sz = sizes[j];
247
245
  Register r = UnknownReg;
248
- if (n < max_regs && sz != ARGSIZE_F) {
249
- r = argRegs[n++]; // tell asm_arg what reg to use
246
+ if (n < max_regs && sz != ARGSIZE_F) {
247
+ r = argRegs[n++]; // tell asm_arg what reg to use
250
248
  }
251
249
  asm_arg(sz, ins->arg(j), r);
252
- }
253
-
254
- if (extra > 0)
255
- SUBi(SP, extra);
256
- }
257
-
258
- void Assembler::nMarkExecute(Page* page, int flags)
259
- {
260
- NanoAssert(sizeof(Page) == NJ_PAGE_SIZE);
261
- #if defined WIN32 || defined WIN64
262
- DWORD dwIgnore;
263
- static const DWORD kProtFlags[4] =
264
- {
265
- PAGE_READONLY, // 0
266
- PAGE_READWRITE, // PAGE_WRITE
267
- PAGE_EXECUTE_READ, // PAGE_EXEC
268
- PAGE_EXECUTE_READWRITE // PAGE_EXEC|PAGE_WRITE
269
- };
270
- DWORD prot = kProtFlags[flags & (PAGE_WRITE|PAGE_EXEC)];
271
- BOOL res = VirtualProtect(page, NJ_PAGE_SIZE, prot, &dwIgnore);
272
- if (!res)
273
- {
274
- // todo: we can't abort or assert here, we have to fail gracefully.
275
- NanoAssertMsg(false, "FATAL ERROR: VirtualProtect() failed\n");
276
- }
277
- #elif defined AVMPLUS_UNIX || defined AVMPLUS_MAC
278
- static const int kProtFlags[4] =
279
- {
280
- PROT_READ, // 0
281
- PROT_READ|PROT_WRITE, // PAGE_WRITE
282
- PROT_READ|PROT_EXEC, // PAGE_EXEC
283
- PROT_READ|PROT_WRITE|PROT_EXEC // PAGE_EXEC|PAGE_WRITE
284
- };
285
- int prot = kProtFlags[flags & (PAGE_WRITE|PAGE_EXEC)];
286
- intptr_t addr = (intptr_t)page;
287
- addr &= ~((uintptr_t)NJ_PAGE_SIZE - 1);
288
- NanoAssert(addr == (intptr_t)page);
289
- #if defined SOLARIS
290
- if (mprotect((char *)addr, NJ_PAGE_SIZE, prot) == -1)
291
- #else
292
- if (mprotect((void *)addr, NJ_PAGE_SIZE, prot) == -1)
293
- #endif
294
- {
295
- // todo: we can't abort or assert here, we have to fail gracefully.
296
- NanoAssertMsg(false, "FATAL ERROR: mprotect(PROT_EXEC) failed\n");
297
- abort();
298
- }
299
- #else
300
- (void)page;
301
- #endif
302
- }
303
-
304
- Register Assembler::nRegisterAllocFromSet(int set)
305
- {
306
- Register r;
307
- RegAlloc &regs = _allocator;
308
- #ifdef WIN32
309
- _asm
310
- {
311
- mov ecx, regs
312
- bsf eax, set // i = first bit set
313
- btr RegAlloc::free[ecx], eax // free &= ~rmask(i)
314
- mov r, eax
315
- }
316
- #elif defined WIN64
317
- unsigned long tr, fr;
318
- _BitScanForward(&tr, set);
319
- _bittestandreset(&fr, tr);
320
- regs.free = fr;
321
- r = tr;
322
- #else
323
- asm(
324
- "bsf %1, %%eax\n\t"
325
- "btr %%eax, %2\n\t"
326
- "movl %%eax, %0\n\t"
327
- : "=m"(r) : "m"(set), "m"(regs.free) : "%eax", "memory" );
328
- #endif /* WIN32 */
329
- return r;
330
- }
331
-
332
- void Assembler::nRegisterResetAll(RegAlloc& a)
333
- {
334
- // add scratch registers to our free list for the allocator
335
- a.clear();
336
- a.used = 0;
337
- a.free = SavedRegs | ScratchRegs;
250
+ }
251
+
252
+ if (extra > 0)
253
+ SUBi(SP, extra);
254
+ }
255
+
256
+ Register Assembler::nRegisterAllocFromSet(RegisterMask set)
257
+ {
258
+ Register r;
259
+ RegAlloc &regs = _allocator;
260
+ #ifdef WIN32
261
+ _asm
262
+ {
263
+ mov ecx, regs
264
+ bsf eax, set // i = first bit set
265
+ btr RegAlloc::free[ecx], eax // free &= ~rmask(i)
266
+ mov r, eax
267
+ }
268
+ #elif defined WIN64
269
+ unsigned long tr, fr;
270
+ _BitScanForward(&tr, set);
271
+ _bittestandreset(&fr, tr);
272
+ regs.free = fr;
273
+ r = tr;
274
+ #else
275
+ asm(
276
+ "bsf %1, %%eax\n\t"
277
+ "btr %%eax, %2\n\t"
278
+ "movl %%eax, %0\n\t"
279
+ : "=m"(r) : "m"(set), "m"(regs.free) : "%eax", "memory" );
280
+ #endif /* WIN32 */
281
+ return r;
282
+ }
283
+
284
+ void Assembler::nRegisterResetAll(RegAlloc& a)
285
+ {
286
+ // add scratch registers to our free list for the allocator
287
+ a.clear();
288
+ a.free = SavedRegs | ScratchRegs;
338
289
  if (!config.sse2)
339
290
  a.free &= ~XmmRegs;
340
- debug_only( a.managed = a.free; )
341
- }
342
-
343
- NIns* Assembler::nPatchBranch(NIns* branch, NIns* targ)
344
- {
345
- NIns* was = 0;
346
- intptr_t offset = intptr_t(targ) - intptr_t(branch);
347
- if (branch[0] == JMP32) {
348
- was = branch + *(int32_t*)&branch[1] + 5;
349
- *(int32_t*)&branch[1] = offset - 5;
291
+ debug_only( a.managed = a.free; )
292
+ }
293
+
294
+ void Assembler::nPatchBranch(NIns* branch, NIns* targ)
295
+ {
296
+ intptr_t offset = intptr_t(targ) - intptr_t(branch);
297
+ if (branch[0] == JMP32) {
298
+ *(int32_t*)&branch[1] = offset - 5;
350
299
  VALGRIND_DISCARD_TRANSLATIONS(&branch[1], sizeof(int32_t));
351
- } else if (branch[0] == JCC32) {
352
- was = branch + *(int32_t*)&branch[2] + 6;
353
- *(int32_t*)&branch[2] = offset - 6;
300
+ } else if (branch[0] == JCC32) {
301
+ *(int32_t*)&branch[2] = offset - 6;
354
302
  VALGRIND_DISCARD_TRANSLATIONS(&branch[2], sizeof(int32_t));
355
- } else
356
- NanoAssertMsg(0, "Unknown branch type in nPatchBranch");
357
- return was;
358
- }
359
-
360
- RegisterMask Assembler::hint(LIns* i, RegisterMask allow)
361
- {
362
- uint32_t op = i->opcode();
363
- int prefer = allow;
364
- if (op == LIR_call || op == LIR_calli) {
365
- prefer &= rmask(retRegs[0]);
366
- }
367
- else if (op == LIR_fcall || op == LIR_fcalli) {
303
+ } else
304
+ NanoAssertMsg(0, "Unknown branch type in nPatchBranch");
305
+ }
306
+
307
+ RegisterMask Assembler::hint(LIns* i, RegisterMask allow)
308
+ {
309
+ uint32_t op = i->opcode();
310
+ int prefer = allow;
311
+ if (op == LIR_icall) {
312
+ prefer &= rmask(retRegs[0]);
313
+ }
314
+ else if (op == LIR_fcall) {
368
315
  prefer &= rmask(FST0);
369
316
  }
370
317
  else if (op == LIR_param) {
371
- uint32_t max_regs = max_abi_regs[_thisfrag->lirbuf->abi];
372
- if (i->imm8() < max_regs)
373
- prefer &= rmask(Register(i->imm8()));
318
+ if (i->paramKind() == 0) {
319
+ uint32_t max_regs = max_abi_regs[_thisfrag->lirbuf->abi];
320
+ if (i->paramArg() < max_regs)
321
+ prefer &= rmask(argRegs[i->paramArg()]);
322
+ } else {
323
+ if (i->paramArg() < NumSavedRegs)
324
+ prefer &= rmask(savedRegs[i->paramArg()]);
325
+ }
374
326
  }
375
327
  else if (op == LIR_callh || (op == LIR_rsh && i->oprnd1()->opcode()==LIR_callh)) {
376
328
  prefer &= rmask(retRegs[1]);
377
329
  }
378
330
  else if (i->isCmp()) {
379
- prefer &= AllowableFlagRegs;
331
+ prefer &= AllowableFlagRegs;
380
332
  }
381
333
  else if (i->isconst()) {
382
334
  prefer &= ScratchRegs;
383
335
  }
384
- return (_allocator.free & prefer) ? prefer : allow;
385
- }
336
+ return (_allocator.free & prefer) ? prefer : allow;
337
+ }
386
338
 
387
339
  void Assembler::asm_qjoin(LIns *ins)
388
340
  {
389
- int d = findMemFor(ins);
390
- AvmAssert(d);
391
- LIns* lo = ins->oprnd1();
392
- LIns* hi = ins->oprnd2();
393
-
394
- Reservation *resv = getresv(ins);
395
- Register rr = resv->reg;
341
+ int d = findMemFor(ins);
342
+ AvmAssert(d);
343
+ LIns* lo = ins->oprnd1();
344
+ LIns* hi = ins->oprnd2();
396
345
 
397
- if (rr != UnknownReg && (rmask(rr) & FpRegs))
398
- evict(rr);
346
+ Register rr = ins->getReg();
347
+ if (isKnownReg(rr) && (rmask(rr) & FpRegs))
348
+ evict(rr, ins);
399
349
 
400
350
  if (hi->isconst())
401
- {
402
- STi(FP, d+4, hi->constval());
403
- }
404
- else
405
- {
406
- Register r = findRegFor(hi, GpRegs);
407
- ST(FP, d+4, r);
408
- }
351
+ {
352
+ STi(FP, d+4, hi->imm32());
353
+ }
354
+ else
355
+ {
356
+ Register r = findRegFor(hi, GpRegs);
357
+ ST(FP, d+4, r);
358
+ }
409
359
 
410
360
  if (lo->isconst())
411
- {
412
- STi(FP, d, lo->constval());
413
- }
414
- else
415
- {
416
- // okay if r gets recycled.
417
- Register r = findRegFor(lo, GpRegs);
418
- ST(FP, d, r);
419
- }
420
-
421
- freeRsrcOf(ins, false); // if we had a reg in use, emit a ST to flush it to mem
361
+ {
362
+ STi(FP, d, lo->imm32());
363
+ }
364
+ else
365
+ {
366
+ // okay if r gets recycled.
367
+ Register r = findRegFor(lo, GpRegs);
368
+ ST(FP, d, r);
369
+ }
370
+
371
+ freeRsrcOf(ins, false); // if we had a reg in use, emit a ST to flush it to mem
372
+ }
373
+
374
+ void Assembler::asm_load(int d, Register r)
375
+ {
376
+ if (rmask(r) & FpRegs)
377
+ {
378
+ if (rmask(r) & XmmRegs) {
379
+ SSE_LDQ(r, d, FP);
380
+ } else {
381
+ FLDQ(d, FP);
382
+ }
383
+ }
384
+ else
385
+ {
386
+ LD(r, d, FP);
387
+ }
422
388
  }
423
389
 
424
- void Assembler::asm_load(int d, Register r)
425
- {
426
- if (rmask(r) & FpRegs)
427
- {
428
- if (rmask(r) & XmmRegs) {
429
- SSE_LDQ(r, d, FP);
430
- } else {
431
- FLDQ(d, FP);
432
- }
433
- }
434
- else
435
- {
436
- LD(r, d, FP);
437
- }
438
- }
439
-
440
- void Assembler::asm_restore(LInsp i, Reservation *resv, Register r)
441
- {
390
+ void Assembler::asm_restore(LInsp i, Reservation* /*unused*/, Register r)
391
+ {
392
+ uint32_t arg;
393
+ uint32_t abi_regcount;
442
394
  if (i->isop(LIR_alloc)) {
443
- verbose_only( if (_verbose) { outputForEOL(" <= remat %s size %d", _thisfrag->lirbuf->names->formatRef(i), i->size()); } )
444
- LEA(r, disp(resv), FP);
395
+ verbose_only( if (_logc->lcbits & LC_RegAlloc) {
396
+ outputForEOL(" <= remat %s size %d",
397
+ _thisfrag->lirbuf->names->formatRef(i), i->size()); } )
398
+ LEA(r, disp(i), FP);
445
399
  }
446
400
  else if (i->isconst()) {
447
- if (!resv->arIndex) {
448
- reserveFree(i);
401
+ if (!i->getArIndex()) {
402
+ i->markAsClear();
403
+ }
404
+ LDi(r, i->imm32());
405
+ }
406
+ else if (i->isop(LIR_param) && i->paramKind() == 0 &&
407
+ (arg = i->paramArg()) >= (abi_regcount = max_abi_regs[_thisfrag->lirbuf->abi])) {
408
+ // incoming arg is on stack, can restore it from there instead of spilling
409
+ if (!i->getArIndex()) {
410
+ i->markAsClear();
449
411
  }
450
- LDi(r, i->constval());
412
+ // compute position of argument relative to ebp. higher argument
413
+ // numbers are at higher positive offsets. the first abi_regcount
414
+ // arguments are in registers, rest on stack. +8 accomodates the
415
+ // return address and saved ebp value. assuming abi_regcount == 0:
416
+ // low-addr ebp
417
+ // [frame...][saved-ebp][return-addr][arg0][arg1]...
418
+ int d = (arg - abi_regcount) * sizeof(intptr_t) + 8;
419
+ LD(r, d, FP);
451
420
  }
452
421
  else {
453
422
  int d = findMemFor(i);
454
- verbose_only( if (_verbose) { outputForEOL(" <= restore %s", _thisfrag->lirbuf->names->formatRef(i)); } )
455
- asm_load(d,r);
423
+ verbose_only( if (_logc->lcbits & LC_RegAlloc) {
424
+ outputForEOL(" <= restore %s",
425
+ _thisfrag->lirbuf->names->formatRef(i)); } )
426
+ asm_load(d,r);
456
427
  }
457
- }
428
+ }
458
429
 
459
430
  void Assembler::asm_store32(LIns *value, int dr, LIns *base)
460
431
  {
461
432
  if (value->isconst())
462
433
  {
463
- Register rb = getBaseReg(base, dr, GpRegs);
464
- int c = value->constval();
465
- STi(rb, dr, c);
434
+ Register rb = getBaseReg(base, dr, GpRegs);
435
+ int c = value->imm32();
436
+ STi(rb, dr, c);
466
437
  }
467
438
  else
468
439
  {
469
- // make sure what is in a register
470
- Reservation *rA, *rB;
440
+ // make sure what is in a register
471
441
  Register ra, rb;
472
442
  if (base->isop(LIR_alloc)) {
473
443
  rb = FP;
@@ -475,164 +445,156 @@ namespace nanojit
475
445
  ra = findRegFor(value, GpRegs);
476
446
  } else if (base->isconst()) {
477
447
  // absolute address
478
- dr += base->constval();
448
+ dr += base->imm32();
479
449
  ra = findRegFor(value, GpRegs);
480
450
  rb = UnknownReg;
481
451
  } else {
482
- findRegFor2(GpRegs, value, rA, base, rB);
483
- ra = rA->reg;
484
- rb = rB->reg;
452
+ findRegFor2b(GpRegs, value, ra, base, rb);
485
453
  }
486
- ST(rb, dr, ra);
454
+ ST(rb, dr, ra);
487
455
  }
488
456
  }
489
457
 
490
- void Assembler::asm_spill(Register rr, int d, bool pop, bool quad)
491
- {
492
- (void)quad;
493
- if (d)
494
- {
495
- // save to spill location
458
+ void Assembler::asm_spill(Register rr, int d, bool pop, bool quad)
459
+ {
460
+ (void)quad;
461
+ if (d)
462
+ {
463
+ // save to spill location
496
464
  if (rmask(rr) & FpRegs)
497
- {
465
+ {
498
466
  if (rmask(rr) & XmmRegs) {
499
467
  SSE_STQ(d, FP, rr);
500
468
  } else {
501
- FSTQ((pop?1:0), d, FP);
469
+ FSTQ((pop?1:0), d, FP);
502
470
  }
503
- }
504
- else
505
- {
506
- ST(FP, d, rr);
507
- }
508
- }
509
- else if (pop && (rmask(rr) & x87Regs))
510
- {
511
- // pop the fpu result since it isn't used
512
- FSTP(FST0);
513
- }
514
- }
515
-
516
- void Assembler::asm_load64(LInsp ins)
517
- {
518
- LIns* base = ins->oprnd1();
519
- int db = ins->oprnd2()->constval();
520
- Reservation *resv = getresv(ins);
521
- Register rr = resv->reg;
522
-
523
- if (rr != UnknownReg && rmask(rr) & XmmRegs)
524
- {
525
- freeRsrcOf(ins, false);
526
- Register rb = getBaseReg(base, db, GpRegs);
527
- SSE_LDQ(rr, db, rb);
528
- }
529
- else
530
- {
531
- int dr = disp(resv);
532
- Register rb;
471
+ }
472
+ else
473
+ {
474
+ ST(FP, d, rr);
475
+ }
476
+ }
477
+ else if (pop && (rmask(rr) & x87Regs))
478
+ {
479
+ // pop the fpu result since it isn't used
480
+ FSTP(FST0);
481
+ }
482
+ }
483
+
484
+ void Assembler::asm_load64(LInsp ins)
485
+ {
486
+ LIns* base = ins->oprnd1();
487
+ int db = ins->disp();
488
+ Register rr = ins->getReg();
489
+
490
+ if (isKnownReg(rr) && rmask(rr) & XmmRegs)
491
+ {
492
+ freeRsrcOf(ins, false);
493
+ Register rb = getBaseReg(base, db, GpRegs);
494
+ SSE_LDQ(rr, db, rb);
495
+ }
496
+ else
497
+ {
498
+ int dr = disp(ins);
499
+ Register rb;
533
500
  if (base->isop(LIR_alloc)) {
534
501
  rb = FP;
535
502
  db += findMemFor(base);
536
503
  } else {
537
504
  rb = findRegFor(base, GpRegs);
538
505
  }
539
- resv->reg = UnknownReg;
540
-
541
- // don't use an fpu reg to simply load & store the value.
542
- if (dr)
543
- asm_mmq(FP, dr, rb, db);
544
-
545
- freeRsrcOf(ins, false);
546
-
547
- if (rr != UnknownReg)
548
- {
549
- NanoAssert(rmask(rr)&FpRegs);
550
- _allocator.retire(rr);
551
- FLDQ(db, rb);
552
- }
553
- }
554
- }
555
-
556
- void Assembler::asm_store64(LInsp value, int dr, LInsp base)
557
- {
558
- if (value->isconstq())
559
- {
560
- // if a constant 64-bit value just store it now rather than
561
- // generating a pointless store/load/store sequence
562
- Register rb;
506
+ ins->setReg(UnknownReg);
507
+
508
+ // don't use an fpu reg to simply load & store the value.
509
+ if (dr)
510
+ asm_mmq(FP, dr, rb, db);
511
+
512
+ freeRsrcOf(ins, false);
513
+
514
+ if (isKnownReg(rr))
515
+ {
516
+ NanoAssert(rmask(rr)&FpRegs);
517
+ _allocator.retire(rr);
518
+ FLDQ(db, rb);
519
+ }
520
+ }
521
+ }
522
+
523
+ void Assembler::asm_store64(LInsp value, int dr, LInsp base)
524
+ {
525
+ if (value->isconstq())
526
+ {
527
+ // if a constant 64-bit value just store it now rather than
528
+ // generating a pointless store/load/store sequence
529
+ Register rb;
563
530
  if (base->isop(LIR_alloc)) {
564
531
  rb = FP;
565
532
  dr += findMemFor(base);
566
533
  } else {
567
534
  rb = findRegFor(base, GpRegs);
568
535
  }
569
- const int32_t* p = (const int32_t*) (value-2);
570
- STi(rb, dr+4, p[1]);
571
- STi(rb, dr, p[0]);
536
+ STi(rb, dr+4, value->imm64_1());
537
+ STi(rb, dr, value->imm64_0());
572
538
  return;
573
- }
539
+ }
574
540
 
575
541
  if (value->isop(LIR_ldq) || value->isop(LIR_ldqc) || value->isop(LIR_qjoin))
576
- {
577
- // value is 64bit struct or int64_t, or maybe a double.
578
- // it may be live in an FPU reg. Either way, don't
579
- // put it in an FPU reg just to load & store it.
542
+ {
543
+ // value is 64bit struct or int64_t, or maybe a double.
544
+ // it may be live in an FPU reg. Either way, don't
545
+ // put it in an FPU reg just to load & store it.
580
546
 
581
- // a) if we know it's not a double, this is right.
582
- // b) if we guarded that its a double, this store could be on
583
- // the side exit, copying a non-double.
584
- // c) maybe its a double just being stored. oh well.
547
+ // a) if we know it's not a double, this is right.
548
+ // b) if we guarded that its a double, this store could be on
549
+ // the side exit, copying a non-double.
550
+ // c) maybe its a double just being stored. oh well.
585
551
 
586
- if (config.sse2) {
552
+ if (config.sse2) {
587
553
  Register rv = findRegFor(value, XmmRegs);
588
- Register rb;
589
- if (base->isop(LIR_alloc)) {
590
- rb = FP;
591
- dr += findMemFor(base);
592
- } else {
593
- rb = findRegFor(base, GpRegs);
594
- }
554
+ Register rb;
555
+ if (base->isop(LIR_alloc)) {
556
+ rb = FP;
557
+ dr += findMemFor(base);
558
+ } else {
559
+ rb = findRegFor(base, GpRegs);
560
+ }
595
561
  SSE_STQ(dr, rb, rv);
596
- return;
562
+ return;
597
563
  }
598
564
 
599
- int da = findMemFor(value);
600
- Register rb;
601
- if (base->isop(LIR_alloc)) {
602
- rb = FP;
603
- dr += findMemFor(base);
604
- } else {
605
- rb = findRegFor(base, GpRegs);
606
- }
607
- asm_mmq(rb, dr, FP, da);
565
+ int da = findMemFor(value);
566
+ Register rb;
567
+ if (base->isop(LIR_alloc)) {
568
+ rb = FP;
569
+ dr += findMemFor(base);
570
+ } else {
571
+ rb = findRegFor(base, GpRegs);
572
+ }
573
+ asm_mmq(rb, dr, FP, da);
608
574
  return;
609
- }
610
-
611
- Register rb;
612
- if (base->isop(LIR_alloc)) {
613
- rb = FP;
614
- dr += findMemFor(base);
615
- } else {
616
- rb = findRegFor(base, GpRegs);
617
- }
618
-
619
- // if value already in a reg, use that, otherwise
620
- // try to get it into XMM regs before FPU regs.
621
- Reservation* rA = getresv(value);
622
- Register rv;
623
- int pop = !rA || rA->reg==UnknownReg;
624
- if (pop) {
625
- rv = findRegFor(value, config.sse2 ? XmmRegs : FpRegs);
626
- } else {
627
- rv = rA->reg;
628
- }
629
-
630
- if (rmask(rv) & XmmRegs) {
575
+ }
576
+
577
+ Register rb;
578
+ if (base->isop(LIR_alloc)) {
579
+ rb = FP;
580
+ dr += findMemFor(base);
581
+ } else {
582
+ rb = findRegFor(base, GpRegs);
583
+ }
584
+
585
+ // if value already in a reg, use that, otherwise
586
+ // try to get it into XMM regs before FPU regs.
587
+ bool pop = value->isUnusedOrHasUnknownReg();
588
+ Register rv = ( pop
589
+ ? findRegFor(value, config.sse2 ? XmmRegs : FpRegs)
590
+ : value->getReg() );
591
+
592
+ if (rmask(rv) & XmmRegs) {
631
593
  SSE_STQ(dr, rb, rv);
632
- } else {
633
- FSTQ(pop, dr, rb);
634
- }
635
- }
594
+ } else {
595
+ FSTQ(pop?1:0, dr, rb);
596
+ }
597
+ }
636
598
 
637
599
  /**
638
600
  * copy 64 bits: (rd+dd) <- (rs+ds)
@@ -662,645 +624,697 @@ namespace nanojit
662
624
  }
663
625
  }
664
626
 
665
- NIns* Assembler::asm_branch(bool branchOnFalse, LInsp cond, NIns* targ, bool isfar)
666
- {
667
- NIns* at = 0;
668
- LOpcode condop = cond->opcode();
669
- NanoAssert(cond->isCond());
670
-
671
- if (condop >= LIR_feq && condop <= LIR_fge)
672
- {
673
- return asm_jmpcc(branchOnFalse, cond, targ);
674
- }
675
-
676
- // produce the branch
677
- if (branchOnFalse)
678
- {
679
- if (condop == LIR_eq)
680
- JNE(targ, isfar);
681
- else if (condop == LIR_ov)
682
- JNO(targ, isfar);
683
- else if (condop == LIR_cs)
684
- JNC(targ, isfar);
685
- else if (condop == LIR_lt)
686
- JNL(targ, isfar);
687
- else if (condop == LIR_le)
688
- JNLE(targ, isfar);
689
- else if (condop == LIR_gt)
690
- JNG(targ, isfar);
691
- else if (condop == LIR_ge)
692
- JNGE(targ, isfar);
693
- else if (condop == LIR_ult)
694
- JNB(targ, isfar);
695
- else if (condop == LIR_ule)
696
- JNBE(targ, isfar);
697
- else if (condop == LIR_ugt)
698
- JNA(targ, isfar);
699
- else //if (condop == LIR_uge)
700
- JNAE(targ, isfar);
701
- }
702
- else // op == LIR_xt
703
- {
704
- if (condop == LIR_eq)
705
- JE(targ, isfar);
706
- else if (condop == LIR_ov)
707
- JO(targ, isfar);
708
- else if (condop == LIR_cs)
709
- JC(targ, isfar);
710
- else if (condop == LIR_lt)
711
- JL(targ, isfar);
712
- else if (condop == LIR_le)
713
- JLE(targ, isfar);
714
- else if (condop == LIR_gt)
715
- JG(targ, isfar);
716
- else if (condop == LIR_ge)
717
- JGE(targ, isfar);
718
- else if (condop == LIR_ult)
719
- JB(targ, isfar);
720
- else if (condop == LIR_ule)
721
- JBE(targ, isfar);
722
- else if (condop == LIR_ugt)
723
- JA(targ, isfar);
724
- else //if (condop == LIR_uge)
725
- JAE(targ, isfar);
726
- }
727
- at = _nIns;
728
- asm_cmp(cond);
729
- return at;
730
- }
731
-
732
- void Assembler::asm_switch(LIns* ins, NIns* exit)
733
- {
734
- LIns* diff = ins->oprnd1();
735
- findSpecificRegFor(diff, EBX);
736
- JMP(exit);
737
- }
738
-
739
- void Assembler::asm_cmp(LIns *cond)
740
- {
627
+ NIns* Assembler::asm_branch(bool branchOnFalse, LInsp cond, NIns* targ)
628
+ {
629
+ NIns* at = 0;
741
630
  LOpcode condop = cond->opcode();
742
-
743
- // LIR_ov and LIR_cs recycle the flags set by arithmetic ops
744
- if ((condop == LIR_ov) || (condop == LIR_cs))
631
+ NanoAssert(cond->isCond());
632
+ if (condop >= LIR_feq && condop <= LIR_fge)
633
+ {
634
+ return asm_jmpcc(branchOnFalse, cond, targ);
635
+ }
636
+ // produce the branch
637
+ if (branchOnFalse)
638
+ {
639
+ if (condop == LIR_eq)
640
+ JNE(targ);
641
+ else if (condop == LIR_ov)
642
+ JNO(targ);
643
+ else if (condop == LIR_lt)
644
+ JNL(targ);
645
+ else if (condop == LIR_le)
646
+ JNLE(targ);
647
+ else if (condop == LIR_gt)
648
+ JNG(targ);
649
+ else if (condop == LIR_ge)
650
+ JNGE(targ);
651
+ else if (condop == LIR_ult)
652
+ JNB(targ);
653
+ else if (condop == LIR_ule)
654
+ JNBE(targ);
655
+ else if (condop == LIR_ugt)
656
+ JNA(targ);
657
+ else //if (condop == LIR_uge)
658
+ JNAE(targ);
659
+ }
660
+ else // op == LIR_xt
661
+ {
662
+ if (condop == LIR_eq)
663
+ JE(targ);
664
+ else if (condop == LIR_ov)
665
+ JO(targ);
666
+ else if (condop == LIR_lt)
667
+ JL(targ);
668
+ else if (condop == LIR_le)
669
+ JLE(targ);
670
+ else if (condop == LIR_gt)
671
+ JG(targ);
672
+ else if (condop == LIR_ge)
673
+ JGE(targ);
674
+ else if (condop == LIR_ult)
675
+ JB(targ);
676
+ else if (condop == LIR_ule)
677
+ JBE(targ);
678
+ else if (condop == LIR_ugt)
679
+ JA(targ);
680
+ else //if (condop == LIR_uge)
681
+ JAE(targ);
682
+ }
683
+ at = _nIns;
684
+ asm_cmp(cond);
685
+ return at;
686
+ }
687
+
688
+ void Assembler::asm_switch(LIns* ins, NIns* exit)
689
+ {
690
+ LIns* diff = ins->oprnd1();
691
+ findSpecificRegFor(diff, EDX);
692
+ JMP(exit);
693
+ }
694
+
695
+ // This generates a 'test' or 'cmp' instruction for a condition, which
696
+ // causes the condition codes to be set appropriately. It's used with
697
+ // conditional branches, conditional moves, and when generating
698
+ // conditional values. For example:
699
+ //
700
+ // LIR: eq1 = eq a, 0
701
+ // LIR: xf1: xf eq1 -> ...
702
+ // asm: test edx, edx # generated by this function
703
+ // asm: je ...
704
+ //
705
+ // If this is the only use of eq1, then on entry 'cond' is *not* marked as
706
+ // used, and we do not allocate a register for it. That's because its
707
+ // result ends up in the condition codes rather than a normal register.
708
+ // This doesn't get recorded in the regstate and so the asm code that
709
+ // consumes the result (eg. a conditional branch like 'je') must follow
710
+ // shortly after.
711
+ //
712
+ // If eq1 is instead used again later, we will also generate code
713
+ // (eg. in asm_cond()) to compute it into a normal register, something
714
+ // like this:
715
+ //
716
+ // LIR: eq1 = eq a, 0
717
+ // LIR: test edx, edx
718
+ // asm: sete ebx
719
+ // asm: movzx ebx, ebx
720
+ //
721
+ // In this case we end up computing the condition twice, but that's ok, as
722
+ // it's just as short as testing eq1's value in the code generated for the
723
+ // guard.
724
+ //
725
+ void Assembler::asm_cmp(LIns *cond)
726
+ {
727
+ LOpcode condop = cond->opcode();
728
+
729
+ // LIR_ov recycles the flags set by arithmetic ops
730
+ if (condop == LIR_ov)
745
731
  return;
746
-
732
+
747
733
  LInsp lhs = cond->oprnd1();
748
- LInsp rhs = cond->oprnd2();
749
- Reservation *rA, *rB;
750
-
751
- NanoAssert((!lhs->isQuad() && !rhs->isQuad()) || (lhs->isQuad() && rhs->isQuad()));
752
-
753
- // Not supported yet.
754
- NanoAssert(!lhs->isQuad() && !rhs->isQuad());
755
-
756
- // ready to issue the compare
757
- if (rhs->isconst())
758
- {
759
- int c = rhs->constval();
760
- if (c == 0 && cond->isop(LIR_eq)) {
761
- Register r = findRegFor(lhs, GpRegs);
762
- TEST(r,r);
763
- }
764
- else if (!rhs->isQuad()) {
765
- Register r = getBaseReg(lhs, c, GpRegs);
766
- CMPi(r, c);
767
- }
768
- }
769
- else
770
- {
771
- findRegFor2(GpRegs, lhs, rA, rhs, rB);
772
- Register ra = rA->reg;
773
- Register rb = rB->reg;
774
- CMP(ra, rb);
775
- }
776
- }
777
-
778
- void Assembler::asm_loop(LInsp ins, NInsList& loopJumps)
779
- {
780
- JMP_long(0);
781
- loopJumps.add(_nIns);
782
-
783
- // If the target we are looping to is in a different fragment, we have to restore
784
- // SP since we will target fragEntry and not loopEntry.
785
- if (ins->record()->exit->target != _thisfrag)
786
- MR(SP,FP);
787
- }
788
-
789
- void Assembler::asm_fcond(LInsp ins)
790
- {
791
- // only want certain regs
792
- Register r = prepResultReg(ins, AllowableFlagRegs);
793
- asm_setcc(r, ins);
794
-
795
- // SETcc only sets low 8 bits, so extend
796
- MOVZX8(r,r);
797
- SETNP(r);
798
-
799
- asm_fcmp(ins);
800
- }
801
-
802
- void Assembler::asm_cond(LInsp ins)
803
- {
804
- // only want certain regs
805
- LOpcode op = ins->opcode();
806
- Register r = prepResultReg(ins, AllowableFlagRegs);
807
- // SETcc only sets low 8 bits, so extend
808
- MOVZX8(r,r);
809
- if (op == LIR_eq)
810
- SETE(r);
811
- else if (op == LIR_ov)
812
- SETO(r);
813
- else if (op == LIR_cs)
814
- SETC(r);
815
- else if (op == LIR_lt)
816
- SETL(r);
817
- else if (op == LIR_le)
818
- SETLE(r);
819
- else if (op == LIR_gt)
820
- SETG(r);
821
- else if (op == LIR_ge)
822
- SETGE(r);
823
- else if (op == LIR_ult)
824
- SETB(r);
825
- else if (op == LIR_ule)
826
- SETBE(r);
827
- else if (op == LIR_ugt)
828
- SETA(r);
829
- else // if (op == LIR_uge)
830
- SETAE(r);
831
- asm_cmp(ins);
832
- }
833
-
834
- void Assembler::asm_arith(LInsp ins)
835
- {
836
- LOpcode op = ins->opcode();
837
- LInsp lhs = ins->oprnd1();
838
- LInsp rhs = ins->oprnd2();
839
-
840
- Register rb = UnknownReg;
841
- RegisterMask allow = GpRegs;
842
- bool forceReg = (op == LIR_mul || !rhs->isconst());
843
-
844
- /* Even if lhs == rhs && forceReg, shift instructions require ECX on the rhs. */
845
- if ((lhs != rhs || (op == LIR_lsh || op == LIR_rsh || op == LIR_ush)) && forceReg)
846
- {
847
- if ((rb = asm_binop_rhs_reg(ins)) == UnknownReg) {
848
- rb = findRegFor(rhs, allow);
849
- }
850
- allow &= ~rmask(rb);
851
- }
852
- else if ((op == LIR_add||op == LIR_addp) && lhs->isop(LIR_alloc) && rhs->isconst()) {
853
- // add alloc+const, use lea
854
- Register rr = prepResultReg(ins, allow);
855
- int d = findMemFor(lhs) + rhs->constval();
856
- LEA(rr, d, FP);
857
- return;
858
- }
859
-
860
- Register rr = prepResultReg(ins, allow);
861
- Reservation* rA = getresv(lhs);
862
- Register ra;
863
- // if this is last use of lhs in reg, we can re-use result reg
864
- if (rA == 0 || (ra = rA->reg) == UnknownReg)
865
- ra = findSpecificRegFor(lhs, rr);
866
- // else, rA already has a register assigned.
867
-
868
- if (forceReg)
869
- {
870
- if (lhs == rhs)
871
- rb = ra;
872
-
873
- switch (op) {
874
- case LIR_add:
875
- case LIR_addp:
876
- ADD(rr, rb);
877
- break;
878
- case LIR_sub:
879
- SUB(rr, rb);
880
- break;
881
- case LIR_mul:
882
- MUL(rr, rb);
883
- break;
884
- case LIR_and:
885
- AND(rr, rb);
886
- break;
887
- case LIR_or:
888
- OR(rr, rb);
889
- break;
890
- case LIR_xor:
891
- XOR(rr, rb);
892
- break;
893
- case LIR_lsh:
894
- SHL(rr, rb);
895
- break;
896
- case LIR_rsh:
897
- SAR(rr, rb);
898
- break;
899
- case LIR_ush:
900
- SHR(rr, rb);
901
- break;
902
- default:
903
- NanoAssertMsg(0, "Unsupported");
904
- }
905
- }
906
- else
907
- {
908
- int c = rhs->constval();
909
- switch (op) {
910
- case LIR_addp:
911
- // this doesn't set cc's, only use it when cc's not required.
912
- LEA(rr, c, ra);
913
- ra = rr; // suppress mov
914
- break;
915
- case LIR_add:
916
- ADDi(rr, c);
917
- break;
918
- case LIR_sub:
919
- SUBi(rr, c);
920
- break;
921
- case LIR_and:
922
- ANDi(rr, c);
923
- break;
924
- case LIR_or:
925
- ORi(rr, c);
926
- break;
927
- case LIR_xor:
928
- XORi(rr, c);
929
- break;
930
- case LIR_lsh:
931
- SHLi(rr, c);
932
- break;
933
- case LIR_rsh:
934
- SARi(rr, c);
935
- break;
936
- case LIR_ush:
937
- SHRi(rr, c);
938
- break;
939
- default:
940
- NanoAssertMsg(0, "Unsupported");
941
- break;
942
- }
943
- }
944
-
945
- if ( rr != ra )
946
- MR(rr,ra);
947
- }
948
-
949
- void Assembler::asm_neg_not(LInsp ins)
950
- {
951
- LOpcode op = ins->opcode();
952
- Register rr = prepResultReg(ins, GpRegs);
953
-
954
- LIns* lhs = ins->oprnd1();
955
- Reservation *rA = getresv(lhs);
956
- // if this is last use of lhs in reg, we can re-use result reg
957
- Register ra;
958
- if (rA == 0 || (ra=rA->reg) == UnknownReg)
959
- ra = findSpecificRegFor(lhs, rr);
960
- // else, rA already has a register assigned.
961
-
962
- if (op == LIR_not)
963
- NOT(rr);
964
- else
965
- NEG(rr);
966
-
967
- if ( rr != ra )
968
- MR(rr,ra);
969
- }
970
-
971
- void Assembler::asm_ld(LInsp ins)
972
- {
973
- LOpcode op = ins->opcode();
974
- LIns* base = ins->oprnd1();
975
- LIns* disp = ins->oprnd2();
976
- Register rr = prepResultReg(ins, GpRegs);
977
- int d = disp->constval();
978
-
979
- if (base->isconst()) {
980
- intptr_t addr = base->constval();
981
- addr += d;
982
- if (op == LIR_ldcb)
983
- LD8Zdm(rr, addr);
984
- else if (op == LIR_ldcs)
985
- LD16Zdm(rr, addr);
986
- else
987
- LDdm(rr, addr);
988
- return;
989
- }
990
-
991
- /* Search for add(X,Y) */
992
- if (base->opcode() == LIR_piadd) {
993
- int scale = 0;
994
- LIns *lhs = base->oprnd1();
995
- LIns *rhs = base->oprnd2();
996
-
997
- /* See if we can bypass any SHLs, by searching for
998
- * add(X, shl(Y,Z)) -> mov r, [X+Y*Z]
999
- */
1000
- if (rhs->opcode() == LIR_pilsh && rhs->oprnd2()->isconst()) {
1001
- scale = rhs->oprnd2()->constval();
1002
- if (scale >= 1 && scale <= 3)
1003
- rhs = rhs->oprnd1();
1004
- else
1005
- scale = 0;
1006
- }
1007
-
1008
- Register rleft;
1009
- Reservation *rL = getresv(lhs);
1010
-
1011
- /* Does LHS have a register yet? If not, re-use the result reg.
1012
- * @todo -- If LHS is const, we could eliminate a register use.
1013
- */
1014
- if (rL == NULL || rL->reg == UnknownReg)
1015
- rleft = findSpecificRegFor(lhs, rr);
1016
- else
1017
- rleft = rL->reg;
1018
-
1019
- Register rright = UnknownReg;
1020
- Reservation *rR = getresv(rhs);
1021
-
1022
- /* Does RHS have a register yet? If not, try to re-use the result reg. */
1023
- if (rr != rleft && (rR == NULL || rR->reg == UnknownReg))
1024
- rright = findSpecificRegFor(rhs, rr);
1025
- if (rright == UnknownReg)
1026
- rright = findRegFor(rhs, GpRegs & ~(rmask(rleft)));
1027
-
1028
- if (op == LIR_ldcb)
1029
- LD8Zsib(rr, d, rleft, rright, scale);
1030
- else if (op == LIR_ldcs)
1031
- LD16Zsib(rr, d, rleft, rright, scale);
1032
- else
1033
- LDsib(rr, d, rleft, rright, scale);
1034
-
1035
- return;
1036
- }
1037
-
1038
- Register ra = getBaseReg(base, d, GpRegs);
1039
- if (op == LIR_ldcb)
1040
- LD8Z(rr, d, ra);
1041
- else if (op == LIR_ldcs)
1042
- LD16Z(rr, d, ra);
1043
- else
1044
- LD(rr, d, ra);
1045
- }
1046
-
1047
- void Assembler::asm_cmov(LInsp ins)
1048
- {
1049
- LOpcode op = ins->opcode();
1050
- LIns* condval = ins->oprnd1();
1051
- NanoAssert(condval->isCmp());
1052
-
1053
- LIns* values = ins->oprnd2();
1054
-
1055
- NanoAssert(values->opcode() == LIR_2);
1056
- LIns* iftrue = values->oprnd1();
1057
- LIns* iffalse = values->oprnd2();
1058
-
1059
- NanoAssert(op == LIR_qcmov || (!iftrue->isQuad() && !iffalse->isQuad()));
1060
-
1061
- const Register rr = prepResultReg(ins, GpRegs);
1062
-
1063
- // this code assumes that neither LD nor MR nor MRcc set any of the condition flags.
1064
- // (This is true on Intel, is it true on all architectures?)
1065
- const Register iffalsereg = findRegFor(iffalse, GpRegs & ~rmask(rr));
1066
- if (op == LIR_cmov) {
1067
- switch (condval->opcode())
1068
- {
1069
- // note that these are all opposites...
1070
- case LIR_eq: MRNE(rr, iffalsereg); break;
1071
- case LIR_ov: MRNO(rr, iffalsereg); break;
1072
- case LIR_cs: MRNC(rr, iffalsereg); break;
1073
- case LIR_lt: MRGE(rr, iffalsereg); break;
1074
- case LIR_le: MRG(rr, iffalsereg); break;
1075
- case LIR_gt: MRLE(rr, iffalsereg); break;
1076
- case LIR_ge: MRL(rr, iffalsereg); break;
1077
- case LIR_ult: MRAE(rr, iffalsereg); break;
1078
- case LIR_ule: MRA(rr, iffalsereg); break;
1079
- case LIR_ugt: MRBE(rr, iffalsereg); break;
1080
- case LIR_uge: MRB(rr, iffalsereg); break;
1081
- default: debug_only( NanoAssert(0); ) break;
1082
- }
1083
- } else if (op == LIR_qcmov) {
1084
- NanoAssert(0);
1085
- }
1086
- /*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr);
1087
- asm_cmp(condval);
1088
- }
1089
-
1090
- void Assembler::asm_qhi(LInsp ins)
1091
- {
1092
- Register rr = prepResultReg(ins, GpRegs);
1093
- LIns *q = ins->oprnd1();
1094
- int d = findMemFor(q);
1095
- LD(rr, d+4, FP);
1096
- }
1097
-
1098
- void Assembler::asm_param(LInsp ins)
1099
- {
1100
- uint32_t a = ins->imm8();
1101
- uint32_t kind = ins->imm8b();
1102
- if (kind == 0) {
1103
- // ordinary param
1104
- AbiKind abi = _thisfrag->lirbuf->abi;
1105
- uint32_t abi_regcount = max_abi_regs[abi];
1106
- if (a < abi_regcount) {
1107
- // incoming arg in register
1108
- prepResultReg(ins, rmask(argRegs[a]));
1109
- } else {
1110
- // incoming arg is on stack, and EBP points nearby (see genPrologue)
1111
- Register r = prepResultReg(ins, GpRegs);
1112
- int d = (a - abi_regcount) * sizeof(intptr_t) + 8;
1113
- LD(r, d, FP);
1114
- }
1115
- }
1116
- else {
1117
- // saved param
1118
- prepResultReg(ins, rmask(savedRegs[a]));
1119
- }
1120
- }
1121
-
1122
- void Assembler::asm_short(LInsp ins)
1123
- {
1124
- Register rr = prepResultReg(ins, GpRegs);
1125
- int32_t val = ins->imm16();
1126
- if (val == 0)
1127
- XOR(rr,rr);
1128
- else
1129
- LDi(rr, val);
1130
- }
1131
-
1132
- void Assembler::asm_int(LInsp ins)
1133
- {
1134
- Register rr = prepResultReg(ins, GpRegs);
1135
- int32_t val = ins->imm32();
1136
- if (val == 0)
1137
- XOR(rr,rr);
1138
- else
1139
- LDi(rr, val);
1140
- }
1141
-
1142
- void Assembler::asm_quad(LInsp ins)
1143
- {
1144
- Reservation *rR = getresv(ins);
1145
- Register rr = rR->reg;
1146
- if (rr != UnknownReg)
1147
- {
1148
- // @todo -- add special-cases for 0 and 1
1149
- _allocator.retire(rr);
1150
- rR->reg = UnknownReg;
1151
- NanoAssert((rmask(rr) & FpRegs) != 0);
1152
-
1153
- const double d = ins->constvalf();
1154
- const uint64_t q = ins->constvalq();
1155
- if (rmask(rr) & XmmRegs) {
1156
- if (q == 0.0) {
734
+ LInsp rhs = cond->oprnd2();
735
+
736
+ NanoAssert((!lhs->isQuad() && !rhs->isQuad()) || (lhs->isQuad() && rhs->isQuad()));
737
+
738
+ // Not supported yet.
739
+ NanoAssert(!lhs->isQuad() && !rhs->isQuad());
740
+
741
+ // ready to issue the compare
742
+ if (rhs->isconst())
743
+ {
744
+ int c = rhs->imm32();
745
+ if (c == 0 && cond->isop(LIR_eq)) {
746
+ Register r = findRegFor(lhs, GpRegs);
747
+ TEST(r,r);
748
+ } else if (!rhs->isQuad()) {
749
+ Register r = getBaseReg(lhs, c, GpRegs);
750
+ CMPi(r, c);
751
+ }
752
+ }
753
+ else
754
+ {
755
+ Register ra, rb;
756
+ findRegFor2b(GpRegs, lhs, ra, rhs, rb);
757
+ CMP(ra, rb);
758
+ }
759
+ }
760
+
761
+ void Assembler::asm_fcond(LInsp ins)
762
+ {
763
+ // only want certain regs
764
+ Register r = prepResultReg(ins, AllowableFlagRegs);
765
+ asm_setcc(r, ins);
766
+
767
+ // SETcc only sets low 8 bits, so extend
768
+ MOVZX8(r,r);
769
+ SETNP(r);
770
+
771
+ asm_fcmp(ins);
772
+ }
773
+
774
+ void Assembler::asm_cond(LInsp ins)
775
+ {
776
+ // only want certain regs
777
+ LOpcode op = ins->opcode();
778
+ Register r = prepResultReg(ins, AllowableFlagRegs);
779
+ // SETcc only sets low 8 bits, so extend
780
+ MOVZX8(r,r);
781
+ if (op == LIR_eq)
782
+ SETE(r);
783
+ else if (op == LIR_ov)
784
+ SETO(r);
785
+ else if (op == LIR_lt)
786
+ SETL(r);
787
+ else if (op == LIR_le)
788
+ SETLE(r);
789
+ else if (op == LIR_gt)
790
+ SETG(r);
791
+ else if (op == LIR_ge)
792
+ SETGE(r);
793
+ else if (op == LIR_ult)
794
+ SETB(r);
795
+ else if (op == LIR_ule)
796
+ SETBE(r);
797
+ else if (op == LIR_ugt)
798
+ SETA(r);
799
+ else // if (op == LIR_uge)
800
+ SETAE(r);
801
+ asm_cmp(ins);
802
+ }
803
+
804
+ void Assembler::asm_arith(LInsp ins)
805
+ {
806
+ LOpcode op = ins->opcode();
807
+ LInsp lhs = ins->oprnd1();
808
+
809
+ if (op == LIR_mod) {
810
+ asm_div_mod(ins);
811
+ return;
812
+ }
813
+
814
+ LInsp rhs = ins->oprnd2();
815
+
816
+ bool forceReg;
817
+ RegisterMask allow = GpRegs;
818
+ Register rb = UnknownReg;
819
+
820
+ switch (op) {
821
+ case LIR_div:
822
+ // Nb: if the div feeds into a mod it will be handled by
823
+ // asm_div_mod() rather than here.
824
+ forceReg = true;
825
+ rb = findRegFor(rhs, (GpRegs ^ (rmask(EAX)|rmask(EDX))));
826
+ allow = rmask(EAX);
827
+ evictIfActive(EDX);
828
+ break;
829
+ case LIR_mul:
830
+ forceReg = true;
831
+ break;
832
+ case LIR_lsh:
833
+ case LIR_rsh:
834
+ case LIR_ush:
835
+ forceReg = !rhs->isconst();
836
+ if (forceReg) {
837
+ rb = findSpecificRegFor(rhs, ECX);
838
+ allow &= ~rmask(rb);
839
+ }
840
+ break;
841
+ case LIR_add:
842
+ case LIR_addp:
843
+ if (lhs->isop(LIR_alloc) && rhs->isconst()) {
844
+ // add alloc+const, use lea
845
+ Register rr = prepResultReg(ins, allow);
846
+ int d = findMemFor(lhs) + rhs->imm32();
847
+ LEA(rr, d, FP);
848
+ return;
849
+ }
850
+ /* fall through */
851
+ default:
852
+ forceReg = !rhs->isconst();
853
+ break;
854
+ }
855
+
856
+ // if we need a register for the rhs and don't have one yet, get it
857
+ if (forceReg && lhs != rhs && !isKnownReg(rb)) {
858
+ rb = findRegFor(rhs, allow);
859
+ allow &= ~rmask(rb);
860
+ }
861
+
862
+ Register rr = prepResultReg(ins, allow);
863
+ // if this is last use of lhs in reg, we can re-use result reg
864
+ // else, lhs already has a register assigned.
865
+ Register ra = ( lhs->isUnusedOrHasUnknownReg()
866
+ ? findSpecificRegFor(lhs, rr)
867
+ : lhs->getReg() );
868
+
869
+ if (forceReg)
870
+ {
871
+ if (lhs == rhs)
872
+ rb = ra;
873
+
874
+ switch (op) {
875
+ case LIR_add:
876
+ case LIR_addp:
877
+ ADD(rr, rb);
878
+ break;
879
+ case LIR_sub:
880
+ SUB(rr, rb);
881
+ break;
882
+ case LIR_mul:
883
+ MUL(rr, rb);
884
+ break;
885
+ case LIR_and:
886
+ AND(rr, rb);
887
+ break;
888
+ case LIR_or:
889
+ OR(rr, rb);
890
+ break;
891
+ case LIR_xor:
892
+ XOR(rr, rb);
893
+ break;
894
+ case LIR_lsh:
895
+ SHL(rr, rb);
896
+ break;
897
+ case LIR_rsh:
898
+ SAR(rr, rb);
899
+ break;
900
+ case LIR_ush:
901
+ SHR(rr, rb);
902
+ break;
903
+ case LIR_div:
904
+ DIV(rb);
905
+ CDQ();
906
+ break;
907
+ default:
908
+ NanoAssertMsg(0, "Unsupported");
909
+ }
910
+ }
911
+ else
912
+ {
913
+ int c = rhs->imm32();
914
+ switch (op) {
915
+ case LIR_addp:
916
+ // this doesn't set cc's, only use it when cc's not required.
917
+ LEA(rr, c, ra);
918
+ ra = rr; // suppress mov
919
+ break;
920
+ case LIR_add:
921
+ ADDi(rr, c);
922
+ break;
923
+ case LIR_sub:
924
+ SUBi(rr, c);
925
+ break;
926
+ case LIR_and:
927
+ ANDi(rr, c);
928
+ break;
929
+ case LIR_or:
930
+ ORi(rr, c);
931
+ break;
932
+ case LIR_xor:
933
+ XORi(rr, c);
934
+ break;
935
+ case LIR_lsh:
936
+ SHLi(rr, c);
937
+ break;
938
+ case LIR_rsh:
939
+ SARi(rr, c);
940
+ break;
941
+ case LIR_ush:
942
+ SHRi(rr, c);
943
+ break;
944
+ default:
945
+ NanoAssertMsg(0, "Unsupported");
946
+ break;
947
+ }
948
+ }
949
+
950
+ if ( rr != ra )
951
+ MR(rr,ra);
952
+ }
953
+
954
+ // This is called when we have a mod(div(divLhs, divRhs)) sequence.
955
+ void Assembler::asm_div_mod(LInsp mod)
956
+ {
957
+ LInsp div = mod->oprnd1();
958
+
959
+ // LIR_mod expects the LIR_div to be near (no interference from the register allocator)
960
+
961
+ NanoAssert(mod->isop(LIR_mod));
962
+ NanoAssert(div->isop(LIR_div));
963
+
964
+ LInsp divLhs = div->oprnd1();
965
+ LInsp divRhs = div->oprnd2();
966
+
967
+ prepResultReg(mod, rmask(EDX));
968
+ prepResultReg(div, rmask(EAX));
969
+
970
+ Register rDivRhs = findRegFor(divRhs, (GpRegs ^ (rmask(EAX)|rmask(EDX))));
971
+
972
+ Register rDivLhs = ( divLhs->isUnusedOrHasUnknownReg()
973
+ ? findSpecificRegFor(divLhs, EAX)
974
+ : divLhs->getReg() );
975
+
976
+ DIV(rDivRhs);
977
+ CDQ(); // sign-extend EAX into EDX:EAX
978
+
979
+ if ( EAX != rDivLhs )
980
+ MR(EAX, rDivLhs);
981
+ }
982
+
983
+ void Assembler::asm_neg_not(LInsp ins)
984
+ {
985
+ LOpcode op = ins->opcode();
986
+ Register rr = prepResultReg(ins, GpRegs);
987
+
988
+ LIns* lhs = ins->oprnd1();
989
+ // if this is last use of lhs in reg, we can re-use result reg
990
+ // else, lhs already has a register assigned.
991
+ Register ra = ( lhs->isUnusedOrHasUnknownReg()
992
+ ? findSpecificRegFor(lhs, rr)
993
+ : lhs->getReg() );
994
+
995
+ if (op == LIR_not)
996
+ NOT(rr);
997
+ else
998
+ NEG(rr);
999
+
1000
+ if ( rr != ra )
1001
+ MR(rr,ra);
1002
+ }
1003
+
1004
+ void Assembler::asm_ld(LInsp ins)
1005
+ {
1006
+ LOpcode op = ins->opcode();
1007
+ LIns* base = ins->oprnd1();
1008
+ int32_t d = ins->disp();
1009
+ Register rr = prepResultReg(ins, GpRegs);
1010
+
1011
+ if (base->isconst()) {
1012
+ intptr_t addr = base->imm32();
1013
+ addr += d;
1014
+ if (op == LIR_ldcb)
1015
+ LD8Zdm(rr, addr);
1016
+ else if (op == LIR_ldcs)
1017
+ LD16Zdm(rr, addr);
1018
+ else
1019
+ LDdm(rr, addr);
1020
+ return;
1021
+ }
1022
+
1023
+ /* Search for add(X,Y) */
1024
+ if (base->opcode() == LIR_piadd) {
1025
+ int scale = 0;
1026
+ LIns *lhs = base->oprnd1();
1027
+ LIns *rhs = base->oprnd2();
1028
+
1029
+ /* See if we can bypass any SHLs, by searching for
1030
+ * add(X, shl(Y,Z)) -> mov r, [X+Y*Z]
1031
+ */
1032
+ if (rhs->opcode() == LIR_pilsh && rhs->oprnd2()->isconst()) {
1033
+ scale = rhs->oprnd2()->imm32();
1034
+ if (scale >= 1 && scale <= 3)
1035
+ rhs = rhs->oprnd1();
1036
+ else
1037
+ scale = 0;
1038
+ }
1039
+
1040
+ /* Does LHS have a register yet? If not, re-use the result reg.
1041
+ * @todo -- If LHS is const, we could eliminate a register use.
1042
+ */
1043
+ Register rleft = ( lhs->isUnusedOrHasUnknownReg()
1044
+ ? findSpecificRegFor(lhs, rr)
1045
+ : lhs->getReg() );
1046
+
1047
+ /* Does RHS have a register yet? If not, try to re-use the result reg. */
1048
+ Register rright = ( rr != rleft && rhs->isUnusedOrHasUnknownReg()
1049
+ ? findSpecificRegFor(rhs, rr)
1050
+ : findRegFor(rhs, GpRegs & ~(rmask(rleft))) );
1051
+
1052
+ if (op == LIR_ldcb)
1053
+ LD8Zsib(rr, d, rleft, rright, scale);
1054
+ else if (op == LIR_ldcs)
1055
+ LD16Zsib(rr, d, rleft, rright, scale);
1056
+ else
1057
+ LDsib(rr, d, rleft, rright, scale);
1058
+
1059
+ return;
1060
+ }
1061
+
1062
+ Register ra = getBaseReg(base, d, GpRegs);
1063
+ if (op == LIR_ldcb)
1064
+ LD8Z(rr, d, ra);
1065
+ else if (op == LIR_ldcs)
1066
+ LD16Z(rr, d, ra);
1067
+ else
1068
+ LD(rr, d, ra);
1069
+ }
1070
+
1071
+ void Assembler::asm_cmov(LInsp ins)
1072
+ {
1073
+ LOpcode op = ins->opcode();
1074
+ LIns* condval = ins->oprnd1();
1075
+ LIns* iftrue = ins->oprnd2();
1076
+ LIns* iffalse = ins->oprnd3();
1077
+
1078
+ NanoAssert(condval->isCmp());
1079
+ NanoAssert(op == LIR_qcmov || (!iftrue->isQuad() && !iffalse->isQuad()));
1080
+
1081
+ const Register rr = prepResultReg(ins, GpRegs);
1082
+
1083
+ // this code assumes that neither LD nor MR nor MRcc set any of the condition flags.
1084
+ // (This is true on Intel, is it true on all architectures?)
1085
+ const Register iffalsereg = findRegFor(iffalse, GpRegs & ~rmask(rr));
1086
+ if (op == LIR_cmov) {
1087
+ switch (condval->opcode())
1088
+ {
1089
+ // note that these are all opposites...
1090
+ case LIR_eq: MRNE(rr, iffalsereg); break;
1091
+ case LIR_ov: MRNO(rr, iffalsereg); break;
1092
+ case LIR_lt: MRGE(rr, iffalsereg); break;
1093
+ case LIR_le: MRG(rr, iffalsereg); break;
1094
+ case LIR_gt: MRLE(rr, iffalsereg); break;
1095
+ case LIR_ge: MRL(rr, iffalsereg); break;
1096
+ case LIR_ult: MRAE(rr, iffalsereg); break;
1097
+ case LIR_ule: MRA(rr, iffalsereg); break;
1098
+ case LIR_ugt: MRBE(rr, iffalsereg); break;
1099
+ case LIR_uge: MRB(rr, iffalsereg); break;
1100
+ default: NanoAssert(0); break;
1101
+ }
1102
+ } else if (op == LIR_qcmov) {
1103
+ NanoAssert(0);
1104
+ }
1105
+ /*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr);
1106
+ asm_cmp(condval);
1107
+ }
1108
+
1109
+ void Assembler::asm_qhi(LInsp ins)
1110
+ {
1111
+ Register rr = prepResultReg(ins, GpRegs);
1112
+ LIns *q = ins->oprnd1();
1113
+ int d = findMemFor(q);
1114
+ LD(rr, d+4, FP);
1115
+ }
1116
+
1117
+ void Assembler::asm_param(LInsp ins)
1118
+ {
1119
+ uint32_t a = ins->paramArg();
1120
+ uint32_t kind = ins->paramKind();
1121
+ if (kind == 0) {
1122
+ // ordinary param
1123
+ AbiKind abi = _thisfrag->lirbuf->abi;
1124
+ uint32_t abi_regcount = max_abi_regs[abi];
1125
+ if (a < abi_regcount) {
1126
+ // incoming arg in register
1127
+ prepResultReg(ins, rmask(argRegs[a]));
1128
+ } else {
1129
+ // incoming arg is on stack, and EBP points nearby (see genPrologue)
1130
+ Register r = prepResultReg(ins, GpRegs);
1131
+ int d = (a - abi_regcount) * sizeof(intptr_t) + 8;
1132
+ LD(r, d, FP);
1133
+ }
1134
+ }
1135
+ else {
1136
+ // saved param
1137
+ prepResultReg(ins, rmask(savedRegs[a]));
1138
+ }
1139
+ }
1140
+
1141
+ void Assembler::asm_int(LInsp ins)
1142
+ {
1143
+ Register rr = prepResultReg(ins, GpRegs);
1144
+ int32_t val = ins->imm32();
1145
+ if (val == 0)
1146
+ XOR(rr,rr);
1147
+ else
1148
+ LDi(rr, val);
1149
+ }
1150
+
1151
+ void Assembler::asm_quad(LInsp ins)
1152
+ {
1153
+ Register rr = ins->getReg();
1154
+ if (isKnownReg(rr))
1155
+ {
1156
+ // @todo -- add special-cases for 0 and 1
1157
+ _allocator.retire(rr);
1158
+ ins->setReg(UnknownReg);
1159
+ NanoAssert((rmask(rr) & FpRegs) != 0);
1160
+
1161
+ const double d = ins->imm64f();
1162
+ const uint64_t q = ins->imm64();
1163
+ if (rmask(rr) & XmmRegs) {
1164
+ if (q == 0.0) {
1157
1165
  // test (int64)0 since -0.0 == 0.0
1158
- SSE_XORPDr(rr, rr);
1159
- } else if (d == 1.0) {
1160
- // 1.0 is extremely frequent and worth special-casing!
1161
- static const double k_ONE = 1.0;
1162
- LDSDm(rr, &k_ONE);
1163
- } else {
1164
- findMemFor(ins);
1165
- const int d = disp(rR);
1166
- SSE_LDQ(rr, d, FP);
1167
- }
1168
- } else {
1169
- if (q == 0.0) {
1166
+ SSE_XORPDr(rr, rr);
1167
+ } else if (d == 1.0) {
1168
+ // 1.0 is extremely frequent and worth special-casing!
1169
+ static const double k_ONE = 1.0;
1170
+ LDSDm(rr, &k_ONE);
1171
+ } else if (d && d == (int)d) {
1172
+ // can fit in 32bits? then use cvt which is faster
1173
+ Register gr = registerAlloc(GpRegs);
1174
+ SSE_CVTSI2SD(rr, gr);
1175
+ SSE_XORPDr(rr,rr); // zero rr to ensure no dependency stalls
1176
+ LDi(gr, (int)d);
1177
+ _allocator.addFree(gr);
1178
+ } else {
1179
+ findMemFor(ins);
1180
+ const int d = disp(ins);
1181
+ SSE_LDQ(rr, d, FP);
1182
+ }
1183
+ } else {
1184
+ if (q == 0.0) {
1170
1185
  // test (int64)0 since -0.0 == 0.0
1171
- FLDZ();
1172
- } else if (d == 1.0) {
1173
- FLD1();
1174
- } else {
1175
- findMemFor(ins);
1176
- int d = disp(rR);
1177
- FLDQ(d,FP);
1178
- }
1179
- }
1180
- }
1181
-
1182
- // @todo, if we used xor, ldsd, fldz, etc above, we don't need mem here
1183
- int d = disp(rR);
1184
- freeRsrcOf(ins, false);
1185
- if (d)
1186
- {
1187
- const int32_t* p = (const int32_t*) (ins-2);
1188
- STi(FP,d+4,p[1]);
1189
- STi(FP,d,p[0]);
1190
- }
1191
- }
1192
-
1193
- void Assembler::asm_qlo(LInsp ins)
1194
- {
1195
- LIns *q = ins->oprnd1();
1196
-
1197
- if (!config.sse2)
1198
- {
1199
- Register rr = prepResultReg(ins, GpRegs);
1200
- int d = findMemFor(q);
1201
- LD(rr, d, FP);
1202
- }
1203
- else
1204
- {
1205
- Reservation *resv = getresv(ins);
1206
- Register rr = resv->reg;
1207
- if (rr == UnknownReg) {
1208
- // store quad in spill loc
1209
- int d = disp(resv);
1210
- freeRsrcOf(ins, false);
1211
- Register qr = findRegFor(q, XmmRegs);
1212
- SSE_MOVDm(d, FP, qr);
1213
- } else {
1214
- freeRsrcOf(ins, false);
1215
- Register qr = findRegFor(q, XmmRegs);
1216
- SSE_MOVD(rr,qr);
1217
- }
1218
- }
1219
- }
1220
-
1221
- void Assembler::asm_fneg(LInsp ins)
1222
- {
1223
- if (config.sse2)
1224
- {
1225
- LIns *lhs = ins->oprnd1();
1226
-
1227
- Register rr = prepResultReg(ins, XmmRegs);
1228
- Reservation *rA = getresv(lhs);
1229
- Register ra;
1230
-
1231
- // if this is last use of lhs in reg, we can re-use result reg
1232
- if (rA == 0 || (ra = rA->reg) == UnknownReg) {
1233
- ra = findSpecificRegFor(lhs, rr);
1234
- } else if ((rmask(ra) & XmmRegs) == 0) {
1235
- /* We need this case on AMD64, because it's possible that
1236
- * an earlier instruction has done a quadword load and reserved a
1237
- * GPR. If so, ask for a new register.
1238
- */
1239
- ra = findRegFor(lhs, XmmRegs);
1240
- }
1241
- // else, rA already has a register assigned.
1186
+ FLDZ();
1187
+ } else if (d == 1.0) {
1188
+ FLD1();
1189
+ } else {
1190
+ findMemFor(ins);
1191
+ int d = disp(ins);
1192
+ FLDQ(d,FP);
1193
+ }
1194
+ }
1195
+ }
1196
+
1197
+ // @todo, if we used xor, ldsd, fldz, etc above, we don't need mem here
1198
+ int d = disp(ins);
1199
+ freeRsrcOf(ins, false);
1200
+ if (d)
1201
+ {
1202
+ STi(FP,d+4,ins->imm64_1());
1203
+ STi(FP,d, ins->imm64_0());
1204
+ }
1205
+ }
1206
+
1207
+ void Assembler::asm_qlo(LInsp ins)
1208
+ {
1209
+ LIns *q = ins->oprnd1();
1210
+
1211
+ if (!config.sse2)
1212
+ {
1213
+ Register rr = prepResultReg(ins, GpRegs);
1214
+ int d = findMemFor(q);
1215
+ LD(rr, d, FP);
1216
+ }
1217
+ else
1218
+ {
1219
+ Register rr = ins->getReg();
1220
+ if (!isKnownReg(rr)) {
1221
+ // store quad in spill loc
1222
+ int d = disp(ins);
1223
+ freeRsrcOf(ins, false);
1224
+ Register qr = findRegFor(q, XmmRegs);
1225
+ SSE_MOVDm(d, FP, qr);
1226
+ } else {
1227
+ freeRsrcOf(ins, false);
1228
+ Register qr = findRegFor(q, XmmRegs);
1229
+ SSE_MOVD(rr,qr);
1230
+ }
1231
+ }
1232
+ }
1233
+
1234
+ void Assembler::asm_fneg(LInsp ins)
1235
+ {
1236
+ if (config.sse2)
1237
+ {
1238
+ LIns *lhs = ins->oprnd1();
1239
+
1240
+ Register rr = prepResultReg(ins, XmmRegs);
1241
+ Register ra;
1242
+
1243
+ // if this is last use of lhs in reg, we can re-use result reg
1244
+ // else, lhs already has a register assigned.
1245
+ if (lhs->isUnusedOrHasUnknownReg()) {
1246
+ ra = findSpecificRegFor(lhs, rr);
1247
+ } else {
1248
+ ra = lhs->getReg();
1249
+ if ((rmask(ra) & XmmRegs) == 0) {
1250
+ /* We need this case on AMD64, because it's possible that
1251
+ * an earlier instruction has done a quadword load and reserved a
1252
+ * GPR. If so, ask for a new register.
1253
+ */
1254
+ ra = findRegFor(lhs, XmmRegs);
1255
+ }
1256
+ }
1242
1257
 
1243
1258
  #if defined __SUNPRO_CC
1244
- // from Sun Studio C++ Readme: #pragma align inside namespace requires mangled names
1245
- static uint32_t temp[] = {0, 0, 0, 0, 0, 0, 0};
1246
- static uint32_t *negateMask = (uint32_t *)alignUp(temp, 16);
1247
- negateMask[1] = 0x80000000;
1259
+ // from Sun Studio C++ Readme: #pragma align inside namespace requires mangled names
1260
+ static uint32_t temp[] = {0, 0, 0, 0, 0, 0, 0};
1261
+ static uint32_t *negateMask = (uint32_t *)alignUp(temp, 16);
1262
+ negateMask[1] = 0x80000000;
1248
1263
  #else
1249
- static const AVMPLUS_ALIGN16(uint32_t) negateMask[] = {0,0x80000000,0,0};
1264
+ static const AVMPLUS_ALIGN16(uint32_t) negateMask[] = {0,0x80000000,0,0};
1250
1265
  #endif
1251
- SSE_XORPD(rr, negateMask);
1266
+ SSE_XORPD(rr, negateMask);
1252
1267
 
1253
- if (rr != ra)
1254
- SSE_MOVSD(rr, ra);
1255
- }
1256
- else
1257
- {
1258
- Register rr = prepResultReg(ins, FpRegs);
1268
+ if (rr != ra)
1269
+ SSE_MOVSD(rr, ra);
1270
+ }
1271
+ else
1272
+ {
1273
+ Register rr = prepResultReg(ins, FpRegs);
1259
1274
 
1260
- LIns* lhs = ins->oprnd1();
1275
+ LIns* lhs = ins->oprnd1();
1261
1276
 
1262
- // lhs into reg, prefer same reg as result
1263
- Reservation* rA = getresv(lhs);
1264
- // if this is last use of lhs in reg, we can re-use result reg
1265
- if (rA == 0 || rA->reg == UnknownReg)
1266
- findSpecificRegFor(lhs, rr);
1267
- // else, rA already has a different reg assigned
1277
+ // lhs into reg, prefer same reg as result
1268
1278
 
1269
- NanoAssert(getresv(lhs)!=0 && getresv(lhs)->reg==FST0);
1270
- // assume that the lhs is in ST(0) and rhs is on stack
1271
- FCHS();
1279
+ // if this is last use of lhs in reg, we can re-use result reg
1280
+ // else, lhs already has a different reg assigned
1281
+ if (lhs->isUnusedOrHasUnknownReg())
1282
+ findSpecificRegFor(lhs, rr);
1272
1283
 
1273
- // if we had more than one fpu reg, this is where
1274
- // we would move ra into rr if rr != ra.
1275
- }
1276
- }
1284
+ NanoAssert(lhs->getReg()==FST0);
1285
+ // assume that the lhs is in ST(0) and rhs is on stack
1286
+ FCHS();
1287
+
1288
+ // if we had more than one fpu reg, this is where
1289
+ // we would move ra into rr if rr != ra.
1290
+ }
1291
+ }
1277
1292
 
1278
1293
  void Assembler::asm_arg(ArgSize sz, LInsp p, Register r)
1279
1294
  {
1280
- if (sz == ARGSIZE_Q)
1295
+ if (sz == ARGSIZE_Q)
1281
1296
  {
1282
- // ref arg - use lea
1283
- if (r != UnknownReg)
1284
- {
1285
- // arg in specific reg
1286
- int da = findMemFor(p);
1287
- LEA(r, da, FP);
1288
- }
1289
- else
1290
- {
1291
- NanoAssert(0); // not supported
1292
- }
1293
- }
1294
- else if (sz == ARGSIZE_LO)
1295
- {
1296
- if (r != UnknownReg) {
1297
- // arg goes in specific register
1297
+ // ref arg - use lea
1298
+ if (isKnownReg(r))
1299
+ {
1300
+ // arg in specific reg
1301
+ int da = findMemFor(p);
1302
+ LEA(r, da, FP);
1303
+ }
1304
+ else
1305
+ {
1306
+ NanoAssert(0); // not supported
1307
+ }
1308
+ }
1309
+ else if (sz == ARGSIZE_I || sz == ARGSIZE_U)
1310
+ {
1311
+ if (isKnownReg(r)) {
1312
+ // arg goes in specific register
1298
1313
  if (p->isconst()) {
1299
- LDi(r, p->constval());
1314
+ LDi(r, p->imm32());
1300
1315
  } else {
1301
- Reservation* rA = getresv(p);
1302
- if (rA) {
1303
- if (rA->reg == UnknownReg) {
1316
+ if (p->isUsed()) {
1317
+ if (!p->hasKnownReg()) {
1304
1318
  // load it into the arg reg
1305
1319
  int d = findMemFor(p);
1306
1320
  if (p->isop(LIR_alloc)) {
@@ -1310,252 +1324,249 @@ namespace nanojit
1310
1324
  }
1311
1325
  } else {
1312
1326
  // it must be in a saved reg
1313
- MR(r, rA->reg);
1327
+ MR(r, p->getReg());
1314
1328
  }
1315
- }
1329
+ }
1316
1330
  else {
1317
1331
  // this is the last use, so fine to assign it
1318
1332
  // to the scratch reg, it's dead after this point.
1319
- findSpecificRegFor(p, r);
1333
+ findSpecificRegFor(p, r);
1320
1334
  }
1321
1335
  }
1322
- }
1336
+ }
1323
1337
  else {
1324
- asm_pusharg(p);
1325
- }
1326
- }
1338
+ asm_pusharg(p);
1339
+ }
1340
+ }
1327
1341
  else
1328
- {
1342
+ {
1329
1343
  NanoAssert(sz == ARGSIZE_F);
1330
- asm_farg(p);
1331
- }
1344
+ asm_farg(p);
1345
+ }
1332
1346
  }
1333
1347
 
1334
- void Assembler::asm_pusharg(LInsp p)
1335
- {
1336
- // arg goes on stack
1337
- Reservation* rA = getresv(p);
1338
- if (rA == 0 && p->isconst())
1339
- {
1340
- // small const we push directly
1341
- PUSHi(p->constval());
1342
- }
1343
- else if (rA == 0 || p->isop(LIR_alloc))
1344
- {
1345
- Register ra = findRegFor(p, GpRegs);
1346
- PUSHr(ra);
1347
- }
1348
- else if (rA->reg == UnknownReg)
1349
- {
1350
- PUSHm(disp(rA), FP);
1351
- }
1352
- else
1353
- {
1354
- PUSHr(rA->reg);
1355
- }
1356
- }
1357
-
1358
- void Assembler::asm_farg(LInsp p)
1359
- {
1348
+ void Assembler::asm_pusharg(LInsp p)
1349
+ {
1350
+ // arg goes on stack
1351
+ if (!p->isUsed() && p->isconst())
1352
+ {
1353
+ // small const we push directly
1354
+ PUSHi(p->imm32());
1355
+ }
1356
+ else if (!p->isUsed() || p->isop(LIR_alloc))
1357
+ {
1358
+ Register ra = findRegFor(p, GpRegs);
1359
+ PUSHr(ra);
1360
+ }
1361
+ else if (!p->hasKnownReg())
1362
+ {
1363
+ PUSHm(disp(p), FP);
1364
+ }
1365
+ else
1366
+ {
1367
+ PUSHr(p->getReg());
1368
+ }
1369
+ }
1370
+
1371
+ void Assembler::asm_farg(LInsp p)
1372
+ {
1360
1373
  NanoAssert(p->isQuad());
1361
- Register r = findRegFor(p, FpRegs);
1362
- if (rmask(r) & XmmRegs) {
1363
- SSE_STQ(0, SP, r);
1364
- } else {
1365
- FSTPQ(0, SP);
1366
- /* It's possible that the same LIns* with r=FST0 will appear in the argument list more
1367
- * than once. In this case FST0 will not have been evicted and the multiple pop
1368
- * actions will unbalance the FPU stack. A quick fix is to always evict FST0 manually.
1369
- */
1370
- evict(FST0);
1371
- }
1374
+ Register r = findRegFor(p, FpRegs);
1375
+ if (rmask(r) & XmmRegs) {
1376
+ SSE_STQ(0, SP, r);
1377
+ } else {
1378
+ FSTPQ(0, SP);
1379
+ /* It's possible that the same LIns* with r=FST0 will appear in the argument list more
1380
+ * than once. In this case FST0 will not have been evicted and the multiple pop
1381
+ * actions will unbalance the FPU stack. A quick fix is to always evict FST0 manually.
1382
+ */
1383
+ evictIfActive(FST0);
1384
+ }
1372
1385
  SUBi(ESP,8);
1373
- }
1374
-
1375
- void Assembler::asm_fop(LInsp ins)
1376
- {
1377
- LOpcode op = ins->opcode();
1378
- if (config.sse2)
1379
- {
1380
- LIns *lhs = ins->oprnd1();
1381
- LIns *rhs = ins->oprnd2();
1382
-
1383
- RegisterMask allow = XmmRegs;
1384
- Register rb = UnknownReg;
1385
- if (lhs != rhs) {
1386
- rb = findRegFor(rhs,allow);
1387
- allow &= ~rmask(rb);
1388
- }
1389
-
1390
- Register rr = prepResultReg(ins, allow);
1391
- Reservation *rA = getresv(lhs);
1392
- Register ra;
1393
-
1394
- // if this is last use of lhs in reg, we can re-use result reg
1395
- if (rA == 0 || (ra = rA->reg) == UnknownReg) {
1396
- ra = findSpecificRegFor(lhs, rr);
1397
- } else if ((rmask(ra) & XmmRegs) == 0) {
1398
- /* We need this case on AMD64, because it's possible that
1399
- * an earlier instruction has done a quadword load and reserved a
1400
- * GPR. If so, ask for a new register.
1401
- */
1402
- ra = findRegFor(lhs, XmmRegs);
1403
- }
1404
- else {
1405
- // rA already has a register assigned but maybe not from the allow set
1386
+ }
1387
+
1388
+ void Assembler::asm_fop(LInsp ins)
1389
+ {
1390
+ LOpcode op = ins->opcode();
1391
+ if (config.sse2)
1392
+ {
1393
+ LIns *lhs = ins->oprnd1();
1394
+ LIns *rhs = ins->oprnd2();
1395
+
1396
+ RegisterMask allow = XmmRegs;
1397
+ Register rb = UnknownReg;
1398
+ if (lhs != rhs) {
1399
+ rb = findRegFor(rhs,allow);
1400
+ allow &= ~rmask(rb);
1401
+ }
1402
+
1403
+ Register rr = prepResultReg(ins, allow);
1404
+ Register ra;
1405
+
1406
+ // if this is last use of lhs in reg, we can re-use result reg
1407
+ if (lhs->isUnusedOrHasUnknownReg()) {
1408
+ ra = findSpecificRegFor(lhs, rr);
1409
+ } else if ((rmask(lhs->getReg()) & XmmRegs) == 0) {
1410
+ // We need this case on AMD64, because it's possible that
1411
+ // an earlier instruction has done a quadword load and reserved a
1412
+ // GPR. If so, ask for a new register.
1413
+ ra = findRegFor(lhs, XmmRegs);
1414
+ } else {
1415
+ // lhs already has a register assigned but maybe not from the allow set
1406
1416
  ra = findRegFor(lhs, allow);
1407
1417
  }
1408
1418
 
1409
- if (lhs == rhs)
1410
- rb = ra;
1411
-
1412
- if (op == LIR_fadd)
1413
- SSE_ADDSD(rr, rb);
1414
- else if (op == LIR_fsub)
1415
- SSE_SUBSD(rr, rb);
1416
- else if (op == LIR_fmul)
1417
- SSE_MULSD(rr, rb);
1418
- else //if (op == LIR_fdiv)
1419
- SSE_DIVSD(rr, rb);
1420
-
1421
- if (rr != ra)
1422
- SSE_MOVSD(rr, ra);
1423
- }
1424
- else
1425
- {
1426
- // we swap lhs/rhs on purpose here, works out better
1427
- // if you only have one fpu reg. use divr/subr.
1428
- LIns* rhs = ins->oprnd1();
1429
- LIns* lhs = ins->oprnd2();
1430
- Register rr = prepResultReg(ins, rmask(FST0));
1431
-
1432
- // make sure rhs is in memory
1433
- int db = findMemFor(rhs);
1434
-
1435
- // lhs into reg, prefer same reg as result
1436
- Reservation* rA = getresv(lhs);
1437
- // last use of lhs in reg, can reuse rr
1438
- if (rA == 0 || rA->reg == UnknownReg)
1439
- findSpecificRegFor(lhs, rr);
1440
- // else, rA already has a different reg assigned
1441
-
1442
- NanoAssert(getresv(lhs)!=0 && getresv(lhs)->reg==FST0);
1443
- // assume that the lhs is in ST(0) and rhs is on stack
1444
- if (op == LIR_fadd)
1445
- { FADD(db, FP); }
1446
- else if (op == LIR_fsub)
1447
- { FSUBR(db, FP); }
1448
- else if (op == LIR_fmul)
1449
- { FMUL(db, FP); }
1450
- else if (op == LIR_fdiv)
1451
- { FDIVR(db, FP); }
1452
- }
1453
- }
1454
-
1455
- void Assembler::asm_i2f(LInsp ins)
1456
- {
1457
- // where our result goes
1458
- Register rr = prepResultReg(ins, FpRegs);
1459
- if (rmask(rr) & XmmRegs)
1460
- {
1461
- // todo support int value in memory
1462
- Register gr = findRegFor(ins->oprnd1(), GpRegs);
1463
- SSE_CVTSI2SD(rr, gr);
1464
- }
1465
- else
1466
- {
1467
- int d = findMemFor(ins->oprnd1());
1468
- FILD(d, FP);
1469
- }
1470
- }
1471
-
1472
- Register Assembler::asm_prep_fcall(Reservation *rR, LInsp ins)
1473
- {
1474
- if (rR) {
1475
- Register rr;
1476
- if ((rr=rR->reg) != UnknownReg && (rmask(rr) & XmmRegs))
1477
- evict(rr);
1478
- }
1479
- return prepResultReg(ins, rmask(FST0));
1480
- }
1481
-
1482
- void Assembler::asm_u2f(LInsp ins)
1483
- {
1484
- // where our result goes
1485
- Register rr = prepResultReg(ins, FpRegs);
1486
- if (rmask(rr) & XmmRegs)
1487
- {
1488
- // don't call findRegFor, we want a reg we can stomp on for a very short time,
1489
- // not a reg that will continue to be associated with the LIns
1490
- Register gr = registerAlloc(GpRegs);
1491
-
1492
- // technique inspired by gcc disassembly
1493
- // Edwin explains it:
1494
- //
1495
- // gr is 0..2^32-1
1496
- //
1497
- // sub gr,0x80000000
1498
- //
1499
- // now gr is -2^31..2^31-1, i.e. the range of int, but not the same value
1500
- // as before
1501
- //
1502
- // cvtsi2sd rr,gr
1503
- //
1504
- // rr is now a double with the int value range
1505
- //
1506
- // addsd rr, 2147483648.0
1507
- //
1508
- // adding back double(0x80000000) makes the range 0..2^32-1.
1509
-
1510
- static const double k_NEGONE = 2147483648.0;
1511
- SSE_ADDSDm(rr, &k_NEGONE);
1512
-
1513
- SSE_CVTSI2SD(rr, gr);
1514
-
1515
- Reservation* resv = getresv(ins->oprnd1());
1516
- Register xr;
1517
- if (resv && (xr = resv->reg) != UnknownReg && (rmask(xr) & GpRegs))
1518
- {
1519
- LEA(gr, 0x80000000, xr);
1520
- }
1521
- else
1522
- {
1523
- const int d = findMemFor(ins->oprnd1());
1524
- SUBi(gr, 0x80000000);
1525
- LD(gr, d, FP);
1526
- }
1527
-
1528
- // ok, we're done with it
1529
- _allocator.addFree(gr);
1530
- }
1531
- else
1532
- {
1419
+ if (lhs == rhs)
1420
+ rb = ra;
1421
+
1422
+ if (op == LIR_fadd)
1423
+ SSE_ADDSD(rr, rb);
1424
+ else if (op == LIR_fsub)
1425
+ SSE_SUBSD(rr, rb);
1426
+ else if (op == LIR_fmul)
1427
+ SSE_MULSD(rr, rb);
1428
+ else //if (op == LIR_fdiv)
1429
+ SSE_DIVSD(rr, rb);
1430
+
1431
+ if (rr != ra)
1432
+ SSE_MOVSD(rr, ra);
1433
+ }
1434
+ else
1435
+ {
1436
+ // we swap lhs/rhs on purpose here, works out better
1437
+ // if you only have one fpu reg. use divr/subr.
1438
+ LIns* rhs = ins->oprnd1();
1439
+ LIns* lhs = ins->oprnd2();
1440
+ Register rr = prepResultReg(ins, rmask(FST0));
1441
+
1442
+ // make sure rhs is in memory
1443
+ int db = findMemFor(rhs);
1444
+
1445
+ // lhs into reg, prefer same reg as result
1446
+
1447
+ // last use of lhs in reg, can reuse rr
1448
+ // else, lhs already has a different reg assigned
1449
+ if (lhs->isUnusedOrHasUnknownReg())
1450
+ findSpecificRegFor(lhs, rr);
1451
+
1452
+ NanoAssert(lhs->getReg()==FST0);
1453
+ // assume that the lhs is in ST(0) and rhs is on stack
1454
+ if (op == LIR_fadd)
1455
+ { FADD(db, FP); }
1456
+ else if (op == LIR_fsub)
1457
+ { FSUBR(db, FP); }
1458
+ else if (op == LIR_fmul)
1459
+ { FMUL(db, FP); }
1460
+ else if (op == LIR_fdiv)
1461
+ { FDIVR(db, FP); }
1462
+ }
1463
+ }
1464
+
1465
+ void Assembler::asm_i2f(LInsp ins)
1466
+ {
1467
+ // where our result goes
1468
+ Register rr = prepResultReg(ins, FpRegs);
1469
+ if (rmask(rr) & XmmRegs)
1470
+ {
1471
+ // todo support int value in memory
1472
+ Register gr = findRegFor(ins->oprnd1(), GpRegs);
1473
+ SSE_CVTSI2SD(rr, gr);
1474
+ SSE_XORPDr(rr,rr); // zero rr to ensure no dependency stalls
1475
+ }
1476
+ else
1477
+ {
1478
+ int d = findMemFor(ins->oprnd1());
1479
+ FILD(d, FP);
1480
+ }
1481
+ }
1482
+
1483
+ Register Assembler::asm_prep_fcall(Reservation* /*unused*/, LInsp ins)
1484
+ {
1485
+ Register rr;
1486
+ if (ins->isUsed() && (rr = ins->getReg(), isKnownReg(rr)) && (rmask(rr) & XmmRegs)) {
1487
+ evict(rr, ins);
1488
+ }
1489
+ return prepResultReg(ins, rmask(FST0));
1490
+ }
1491
+
1492
+ void Assembler::asm_u2f(LInsp ins)
1493
+ {
1494
+ // where our result goes
1495
+ Register rr = prepResultReg(ins, FpRegs);
1496
+ if (rmask(rr) & XmmRegs)
1497
+ {
1498
+ // don't call findRegFor, we want a reg we can stomp on for a very short time,
1499
+ // not a reg that will continue to be associated with the LIns
1500
+ Register gr = registerAlloc(GpRegs);
1501
+
1502
+ // technique inspired by gcc disassembly
1503
+ // Edwin explains it:
1504
+ //
1505
+ // gr is 0..2^32-1
1506
+ //
1507
+ // sub gr,0x80000000
1508
+ //
1509
+ // now gr is -2^31..2^31-1, i.e. the range of int, but not the same value
1510
+ // as before
1511
+ //
1512
+ // cvtsi2sd rr,gr
1513
+ //
1514
+ // rr is now a double with the int value range
1515
+ //
1516
+ // addsd rr, 2147483648.0
1517
+ //
1518
+ // adding back double(0x80000000) makes the range 0..2^32-1.
1519
+
1520
+ static const double k_NEGONE = 2147483648.0;
1521
+ SSE_ADDSDm(rr, &k_NEGONE);
1522
+
1523
+ SSE_CVTSI2SD(rr, gr);
1524
+ SSE_XORPDr(rr,rr); // zero rr to ensure no dependency stalls
1525
+
1526
+ LIns* op1 = ins->oprnd1();
1527
+ Register xr;
1528
+ if (op1->isUsed() && (xr = op1->getReg(), isKnownReg(xr)) && (rmask(xr) & GpRegs))
1529
+ {
1530
+ LEA(gr, 0x80000000, xr);
1531
+ }
1532
+ else
1533
+ {
1534
+ const int d = findMemFor(ins->oprnd1());
1535
+ SUBi(gr, 0x80000000);
1536
+ LD(gr, d, FP);
1537
+ }
1538
+
1539
+ // ok, we're done with it
1540
+ _allocator.addFree(gr);
1541
+ }
1542
+ else
1543
+ {
1533
1544
  const int disp = -8;
1534
1545
  const Register base = SP;
1535
- Register gr = findRegFor(ins->oprnd1(), GpRegs);
1536
- NanoAssert(rr == FST0);
1537
- FILDQ(disp, base);
1538
- STi(base, disp+4, 0); // high 32 bits = 0
1539
- ST(base, disp, gr); // low 32 bits = unsigned value
1540
- }
1541
- }
1542
-
1543
- void Assembler::asm_nongp_copy(Register r, Register s)
1544
- {
1545
- if ((rmask(r) & XmmRegs) && (rmask(s) & XmmRegs)) {
1546
- SSE_MOVSD(r, s);
1547
- } else if ((rmask(r) & GpRegs) && (rmask(s) & XmmRegs)) {
1548
- SSE_MOVD(r, s);
1549
- } else {
1550
- if (rmask(r) & XmmRegs) {
1551
- // x87 -> xmm
1552
- NanoAssertMsg(false, "Should not move data from GPR to XMM");
1553
- } else {
1554
- // xmm -> x87
1555
- NanoAssertMsg(false, "Should not move data from GPR/XMM to x87 FPU");
1556
- }
1557
- }
1558
- }
1546
+ Register gr = findRegFor(ins->oprnd1(), GpRegs);
1547
+ NanoAssert(rr == FST0);
1548
+ FILDQ(disp, base);
1549
+ STi(base, disp+4, 0); // high 32 bits = 0
1550
+ ST(base, disp, gr); // low 32 bits = unsigned value
1551
+ }
1552
+ }
1553
+
1554
+ void Assembler::asm_nongp_copy(Register r, Register s)
1555
+ {
1556
+ if ((rmask(r) & XmmRegs) && (rmask(s) & XmmRegs)) {
1557
+ SSE_MOVSD(r, s);
1558
+ } else if ((rmask(r) & GpRegs) && (rmask(s) & XmmRegs)) {
1559
+ SSE_MOVD(r, s);
1560
+ } else {
1561
+ if (rmask(r) & XmmRegs) {
1562
+ // x87 -> xmm
1563
+ NanoAssertMsg(false, "Should not move data from GPR to XMM");
1564
+ } else {
1565
+ // xmm -> x87
1566
+ NanoAssertMsg(false, "Should not move data from GPR/XMM to x87 FPU");
1567
+ }
1568
+ }
1569
+ }
1559
1570
 
1560
1571
  NIns * Assembler::asm_jmpcc(bool branchOnFalse, LIns *cond, NIns *targ)
1561
1572
  {
@@ -1573,24 +1584,24 @@ namespace nanojit
1573
1584
  }
1574
1585
 
1575
1586
  if (c == LIR_fgt) {
1576
- if (branchOnFalse) { JNA(targ, false); } else { JA(targ, false); }
1587
+ if (branchOnFalse) { JNA(targ); } else { JA(targ); }
1577
1588
  }
1578
1589
  else { // if (c == LIR_fge)
1579
- if (branchOnFalse) { JNAE(targ, false); } else { JAE(targ, false); }
1590
+ if (branchOnFalse) { JNAE(targ); } else { JAE(targ); }
1580
1591
  }
1581
1592
  NIns *at = _nIns;
1582
- Reservation *rA, *rB;
1583
- findRegFor2(XmmRegs, lhs, rA, rhs, rB);
1584
- SSE_UCOMISD(rA->reg, rB->reg);
1593
+ Register ra, rb;
1594
+ findRegFor2b(XmmRegs, lhs, ra, rhs, rb);
1595
+ SSE_UCOMISD(ra, rb);
1585
1596
  return at;
1586
1597
  }
1587
1598
 
1588
- if (branchOnFalse)
1589
- JP(targ, false);
1590
- else
1591
- JNP(targ, false);
1592
- NIns *at = _nIns;
1593
- asm_fcmp(cond);
1599
+ if (branchOnFalse)
1600
+ JP(targ);
1601
+ else
1602
+ JNP(targ);
1603
+ NIns *at = _nIns;
1604
+ asm_fcmp(cond);
1594
1605
  return at;
1595
1606
  }
1596
1607
 
@@ -1598,7 +1609,7 @@ namespace nanojit
1598
1609
  {
1599
1610
  LOpcode c = cond->opcode();
1600
1611
  if (config.sse2 && c != LIR_feq) {
1601
- MOVZX8(r,r);
1612
+ MOVZX8(r,r);
1602
1613
  LIns *lhs = cond->oprnd1();
1603
1614
  LIns *rhs = cond->oprnd2();
1604
1615
  if (c == LIR_flt) {
@@ -1615,31 +1626,31 @@ namespace nanojit
1615
1626
  else { // if (c == LIR_fge)
1616
1627
  SETAE(r);
1617
1628
  }
1618
- Reservation *rA, *rB;
1619
- findRegFor2(XmmRegs, lhs, rA, rhs, rB);
1620
- SSE_UCOMISD(rA->reg, rB->reg);
1629
+ Register ra, rb;
1630
+ findRegFor2b(XmmRegs, lhs, ra, rhs, rb);
1631
+ SSE_UCOMISD(ra, rb);
1621
1632
  return;
1622
1633
  }
1623
- // SETcc only sets low 8 bits, so extend
1624
- MOVZX8(r,r);
1625
- SETNP(r);
1634
+ // SETcc only sets low 8 bits, so extend
1635
+ MOVZX8(r,r);
1636
+ SETNP(r);
1626
1637
  asm_fcmp(cond);
1627
1638
  }
1628
1639
 
1629
- void Assembler::asm_fcmp(LIns *cond)
1630
- {
1631
- LOpcode condop = cond->opcode();
1632
- NanoAssert(condop >= LIR_feq && condop <= LIR_fge);
1633
- LIns* lhs = cond->oprnd1();
1634
- LIns* rhs = cond->oprnd2();
1640
+ void Assembler::asm_fcmp(LIns *cond)
1641
+ {
1642
+ LOpcode condop = cond->opcode();
1643
+ NanoAssert(condop >= LIR_feq && condop <= LIR_fge);
1644
+ LIns* lhs = cond->oprnd1();
1645
+ LIns* rhs = cond->oprnd2();
1635
1646
 
1636
1647
  int mask;
1637
- if (condop == LIR_feq)
1638
- mask = 0x44;
1639
- else if (condop == LIR_fle)
1640
- mask = 0x41;
1641
- else if (condop == LIR_flt)
1642
- mask = 0x05;
1648
+ if (condop == LIR_feq)
1649
+ mask = 0x44;
1650
+ else if (condop == LIR_fle)
1651
+ mask = 0x41;
1652
+ else if (condop == LIR_flt)
1653
+ mask = 0x05;
1643
1654
  else if (condop == LIR_fge) {
1644
1655
  // swap, use le
1645
1656
  condop = LIR_fle;
@@ -1649,7 +1660,7 @@ namespace nanojit
1649
1660
  // swap, use lt
1650
1661
  condop = LIR_flt;
1651
1662
  LIns* t = lhs; lhs = rhs; rhs = t;
1652
- mask = 0x05;
1663
+ mask = 0x05;
1653
1664
  }
1654
1665
 
1655
1666
  if (config.sse2)
@@ -1663,86 +1674,103 @@ namespace nanojit
1663
1674
  // nan check
1664
1675
  Register r = findRegFor(lhs, XmmRegs);
1665
1676
  SSE_UCOMISD(r, r);
1666
- }
1677
+ }
1667
1678
  else {
1668
- evict(EAX);
1679
+ evictIfActive(EAX);
1669
1680
  TEST_AH(mask);
1670
1681
  LAHF();
1671
-
1672
- Reservation *rA, *rB;
1673
- findRegFor2(XmmRegs, lhs, rA, rhs, rB);
1674
- SSE_UCOMISD(rA->reg, rB->reg);
1682
+ Register ra, rb;
1683
+ findRegFor2b(XmmRegs, lhs, ra, rhs, rb);
1684
+ SSE_UCOMISD(ra, rb);
1675
1685
  }
1676
1686
  }
1677
1687
  else
1678
1688
  {
1679
- evict(EAX);
1689
+ evictIfActive(EAX);
1680
1690
  TEST_AH(mask);
1681
- FNSTSW_AX();
1682
- NanoAssert(lhs->isQuad() && rhs->isQuad());
1683
- Reservation *rA;
1684
- if (lhs != rhs)
1685
- {
1686
- // compare two different numbers
1687
- int d = findMemFor(rhs);
1688
- rA = getresv(lhs);
1689
- int pop = !rA || rA->reg == UnknownReg;
1690
- findSpecificRegFor(lhs, FST0);
1691
- // lhs is in ST(0) and rhs is on stack
1692
- FCOM(pop, d, FP);
1693
- }
1694
- else
1695
- {
1696
- // compare n to itself, this is a NaN test.
1697
- rA = getresv(lhs);
1698
- int pop = !rA || rA->reg == UnknownReg;
1699
- findSpecificRegFor(lhs, FST0);
1700
- // value in ST(0)
1701
- if (pop)
1702
- FCOMPP();
1703
- else
1704
- FCOMP();
1705
- FLDr(FST0); // DUP
1706
- }
1707
- }
1708
- }
1709
-
1710
- void Assembler::nativePageReset()
1711
- {
1712
- }
1713
-
1714
- Register Assembler::asm_binop_rhs_reg(LInsp ins)
1715
- {
1716
- LOpcode op = ins->opcode();
1717
- LIns *rhs = ins->oprnd2();
1718
-
1719
- if (op == LIR_lsh || op == LIR_rsh || op == LIR_ush)
1720
- return findSpecificRegFor(rhs, ECX);
1721
-
1722
- return UnknownReg;
1723
- }
1724
-
1725
- void Assembler::nativePageSetup()
1726
- {
1727
- if (!_nIns) _nIns = pageAlloc();
1728
- if (!_nExitIns) _nExitIns = pageAlloc(true);
1729
- }
1730
-
1731
- // enough room for n bytes
1691
+ FNSTSW_AX();
1692
+ NanoAssert(lhs->isQuad() && rhs->isQuad());
1693
+ if (lhs != rhs)
1694
+ {
1695
+ // compare two different numbers
1696
+ int d = findMemFor(rhs);
1697
+ int pop = lhs->isUnusedOrHasUnknownReg();
1698
+ findSpecificRegFor(lhs, FST0);
1699
+ // lhs is in ST(0) and rhs is on stack
1700
+ FCOM(pop, d, FP);
1701
+ }
1702
+ else
1703
+ {
1704
+ // compare n to itself, this is a NaN test.
1705
+ int pop = lhs->isUnusedOrHasUnknownReg();
1706
+ findSpecificRegFor(lhs, FST0);
1707
+ // value in ST(0)
1708
+ if (pop)
1709
+ FCOMPP();
1710
+ else
1711
+ FCOMP();
1712
+ FLDr(FST0); // DUP
1713
+ }
1714
+ }
1715
+ }
1716
+
1717
+ // Increment the 32-bit profiling counter at pCtr, without
1718
+ // changing any registers.
1719
+ verbose_only(
1720
+ void Assembler::asm_inc_m32(uint32_t* pCtr)
1721
+ {
1722
+ INCLi(pCtr);
1723
+ }
1724
+ )
1725
+
1726
+ void Assembler::nativePageReset()
1727
+ {}
1728
+
1729
+ void Assembler::nativePageSetup()
1730
+ {
1731
+ if (!_nIns)
1732
+ codeAlloc(codeStart, codeEnd, _nIns verbose_only(, codeBytes));
1733
+ if (!_nExitIns)
1734
+ codeAlloc(exitStart, exitEnd, _nExitIns verbose_only(, exitBytes));
1735
+ }
1736
+
1737
+ // enough room for n bytes
1732
1738
  void Assembler::underrunProtect(int n)
1733
1739
  {
1734
- NanoAssertMsg(n<=LARGEST_UNDERRUN_PROT, "constant LARGEST_UNDERRUN_PROT is too small");
1735
- NIns *eip = this->_nIns;
1736
- Page *p = (Page*)pageTop(eip-1);
1737
- NIns *top = (NIns*) &p->code[0];
1738
- if (eip - n < top) {
1740
+ NIns *eip = _nIns;
1741
+ NanoAssertMsg(n<=LARGEST_UNDERRUN_PROT, "constant LARGEST_UNDERRUN_PROT is too small");
1742
+ if (eip - n < (_inExit ? exitStart : codeStart)) {
1739
1743
  // We are done with the current page. Tell Valgrind that new code
1740
1744
  // has been generated.
1741
- VALGRIND_DISCARD_TRANSLATIONS(pageTop(p), NJ_PAGE_SIZE);
1742
- _nIns = pageAlloc(_inExit);
1745
+ if (_inExit)
1746
+ codeAlloc(exitStart, exitEnd, _nIns verbose_only(, exitBytes));
1747
+ else
1748
+ codeAlloc(codeStart, codeEnd, _nIns verbose_only(, codeBytes));
1743
1749
  JMP(eip);
1744
1750
  }
1745
1751
  }
1746
-
1747
- #endif /* FEATURE_NANOJIT */
1752
+
1753
+ void Assembler::asm_ret(LInsp ins)
1754
+ {
1755
+ genEpilogue();
1756
+
1757
+ // Restore ESP from EBP, undoing SUBi(SP,amt) in the prologue
1758
+ MR(SP,FP);
1759
+
1760
+ assignSavedRegs();
1761
+ LIns *val = ins->oprnd1();
1762
+ if (ins->isop(LIR_ret)) {
1763
+ findSpecificRegFor(val, retRegs[0]);
1764
+ } else {
1765
+ findSpecificRegFor(val, FST0);
1766
+ fpu_pop();
1767
+ }
1768
+ }
1769
+
1770
+ void Assembler::asm_promote(LIns *) {
1771
+ // i2q or u2q
1772
+ TODO(asm_promote);
1773
+ }
1774
+
1775
+ #endif /* FEATURE_NANOJIT */
1748
1776
  }