html-to-markdown 2.28.1 → 2.28.2
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/Gemfile.lock +6 -6
- data/README.md +5 -1
- data/ext/html-to-markdown-rb/native/Cargo.lock +1694 -0
- data/ext/html-to-markdown-rb/native/Cargo.toml +1 -1
- data/lib/html_to_markdown/version.rb +1 -1
- data/rust-vendor/html-to-markdown-rs/Cargo.toml +1 -1
- data/rust-vendor/libc/.cargo-checksum.json +1 -1
- data/rust-vendor/libc/.cargo_vcs_info.json +1 -1
- data/rust-vendor/libc/CHANGELOG.md +19 -0
- data/rust-vendor/libc/Cargo.lock +1 -1
- data/rust-vendor/libc/Cargo.toml +1 -1
- data/rust-vendor/libc/Cargo.toml.orig +1 -1
- data/rust-vendor/libc/build.rs +3 -3
- data/rust-vendor/libc/src/fuchsia/mod.rs +2 -0
- data/rust-vendor/libc/src/hermit.rs +1 -0
- data/rust-vendor/libc/src/lib.rs +1 -0
- data/rust-vendor/libc/src/new/linux_uapi/linux/mod.rs +1 -0
- data/rust-vendor/libc/src/new/linux_uapi/linux/pidfd.rs +59 -0
- data/rust-vendor/libc/src/new/mod.rs +3 -0
- data/rust-vendor/libc/src/new/netbsd/sys/file.rs +16 -0
- data/rust-vendor/libc/src/new/netbsd/sys/mod.rs +2 -0
- data/rust-vendor/libc/src/new/netbsd/sys/socket.rs +44 -0
- data/rust-vendor/libc/src/new/qurt/mod.rs +2 -0
- data/rust-vendor/libc/src/solid/mod.rs +1 -0
- data/rust-vendor/libc/src/switch.rs +1 -0
- data/rust-vendor/libc/src/teeos/mod.rs +2 -0
- data/rust-vendor/libc/src/trusty.rs +1 -0
- data/rust-vendor/libc/src/unix/bsd/apple/b64/mod.rs +1 -0
- data/rust-vendor/libc/src/unix/bsd/netbsdlike/netbsd/mod.rs +31 -0
- data/rust-vendor/libc/src/unix/bsd/netbsdlike/openbsd/mod.rs +92 -0
- data/rust-vendor/libc/src/unix/hurd/mod.rs +1 -0
- data/rust-vendor/libc/src/unix/linux_like/linux/gnu/mod.rs +1 -0
- data/rust-vendor/libc/src/unix/linux_like/linux/mod.rs +22 -46
- data/rust-vendor/libc/src/unix/mod.rs +2 -0
- data/rust-vendor/libc/src/unix/newlib/espidf/mod.rs +2 -0
- data/rust-vendor/libc/src/unix/redox/mod.rs +2 -2
- data/rust-vendor/libc/src/vxworks/mod.rs +46 -0
- data/rust-vendor/libc/src/wasi/mod.rs +2 -0
- data/rust-vendor/libc/src/windows/mod.rs +2 -0
- data/rust-vendor/zerocopy/.cargo-checksum.json +1 -1
- data/rust-vendor/zerocopy/.cargo_vcs_info.json +1 -1
- data/rust-vendor/zerocopy/Cargo.lock +3 -3
- data/rust-vendor/zerocopy/Cargo.toml +178 -4
- data/rust-vendor/zerocopy/Cargo.toml.orig +5 -5
- data/rust-vendor/zerocopy/benches/formats/coco_dynamic_padding.rs +24 -0
- data/rust-vendor/zerocopy/benches/formats/coco_dynamic_size.rs +23 -0
- data/rust-vendor/zerocopy/benches/formats/coco_static_size.rs +23 -0
- data/rust-vendor/zerocopy/benches/read_from_bytes.rs +7 -0
- data/rust-vendor/zerocopy/benches/read_from_bytes.x86-64 +15 -0
- data/rust-vendor/zerocopy/benches/read_from_bytes.x86-64.mca +65 -0
- data/rust-vendor/zerocopy/benches/read_from_prefix.rs +10 -0
- data/rust-vendor/zerocopy/benches/read_from_prefix.x86-64 +14 -0
- data/rust-vendor/zerocopy/benches/read_from_prefix.x86-64.mca +63 -0
- data/rust-vendor/zerocopy/benches/read_from_suffix.rs +10 -0
- data/rust-vendor/zerocopy/benches/read_from_suffix.x86-64 +15 -0
- data/rust-vendor/zerocopy/benches/read_from_suffix.x86-64.mca +65 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.rs +7 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.x86-64 +22 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_padding.x86-64.mca +77 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.rs +7 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.x86-64 +20 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_dynamic_size.x86-64.mca +75 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.rs +7 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.x86-64 +8 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_static_size.x86-64.mca +53 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.x86-64 +30 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_padding.x86-64.mca +95 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.x86-64 +16 -0
- data/rust-vendor/zerocopy/benches/ref_from_bytes_with_elems_dynamic_size.x86-64.mca +65 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.x86-64 +22 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_padding.x86-64.mca +77 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.x86-64 +17 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_dynamic_size.x86-64.mca +67 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.x86-64 +8 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_static_size.x86-64.mca +53 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.rs +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.x86-64 +35 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_padding.x86-64.mca +101 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.rs +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.x86-64 +22 -0
- data/rust-vendor/zerocopy/benches/ref_from_prefix_with_elems_dynamic_size.x86-64.mca +77 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.x86-64 +23 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_padding.x86-64.mca +79 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.x86-64 +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_dynamic_size.x86-64.mca +63 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.x86-64 +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_static_size.x86-64.mca +61 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.rs +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.x86-64 +34 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_padding.x86-64.mca +99 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.rs +13 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.x86-64 +23 -0
- data/rust-vendor/zerocopy/benches/ref_from_suffix_with_elems_dynamic_size.x86-64.mca +77 -0
- data/rust-vendor/zerocopy/benches/transmute.rs +16 -0
- data/rust-vendor/zerocopy/benches/transmute.x86-64 +3 -0
- data/rust-vendor/zerocopy/benches/transmute.x86-64.mca +43 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.rs +16 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.x86-64 +4 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_dynamic_size.x86-64.mca +45 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_static_size.rs +15 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_static_size.x86-64 +3 -0
- data/rust-vendor/zerocopy/benches/transmute_ref_static_size.x86-64.mca +43 -0
- data/rust-vendor/zerocopy/benches/try_read_from_bytes.rs +7 -0
- data/rust-vendor/zerocopy/benches/try_read_from_bytes.x86-64 +23 -0
- data/rust-vendor/zerocopy/benches/try_read_from_bytes.x86-64.mca +79 -0
- data/rust-vendor/zerocopy/benches/try_read_from_prefix.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_read_from_prefix.x86-64 +16 -0
- data/rust-vendor/zerocopy/benches/try_read_from_prefix.x86-64.mca +67 -0
- data/rust-vendor/zerocopy/benches/try_read_from_suffix.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_read_from_suffix.x86-64 +18 -0
- data/rust-vendor/zerocopy/benches/try_read_from_suffix.x86-64.mca +71 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.rs +7 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.x86-64 +24 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_padding.x86-64.mca +81 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.rs +7 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.x86-64 +22 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_dynamic_size.x86-64.mca +79 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.rs +7 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.x86-64 +13 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_static_size.x86-64.mca +59 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.x86-64 +36 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_padding.x86-64.mca +105 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.x86-64 +18 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_bytes_with_elems_dynamic_size.x86-64.mca +69 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.x86-64 +29 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_padding.x86-64.mca +91 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.x86-64 +22 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_dynamic_size.x86-64.mca +77 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.x86-64 +15 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_static_size.x86-64.mca +63 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.rs +13 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.x86-64 +35 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_padding.x86-64.mca +101 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.rs +13 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.x86-64 +26 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_prefix_with_elems_dynamic_size.x86-64.mca +83 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.x86-64 +26 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_padding.x86-64.mca +85 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.x86-64 +18 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_dynamic_size.x86-64.mca +71 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.rs +10 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.x86-64 +16 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_static_size.x86-64.mca +67 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.rs +13 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.x86-64 +39 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_padding.x86-64.mca +109 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.rs +13 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.x86-64 +28 -0
- data/rust-vendor/zerocopy/benches/try_ref_from_suffix_with_elems_dynamic_size.x86-64.mca +87 -0
- data/rust-vendor/zerocopy/benches/try_transmute.rs +16 -0
- data/rust-vendor/zerocopy/benches/try_transmute.x86-64 +9 -0
- data/rust-vendor/zerocopy/benches/try_transmute.x86-64.mca +55 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.rs +18 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.x86-64 +6 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_dynamic_size.x86-64.mca +49 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.rs +17 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.x86-64 +5 -0
- data/rust-vendor/zerocopy/benches/try_transmute_ref_static_size.x86-64.mca +47 -0
- data/rust-vendor/zerocopy/rustdoc/style.css +55 -0
- data/rust-vendor/zerocopy/src/lib.rs +331 -0
- data/rust-vendor/zerocopy/src/macros.rs +48 -1
- data/rust-vendor/zerocopy/src/util/macros.rs +199 -0
- data/rust-vendor/zerocopy/tests/codegen.rs +111 -0
- data/rust-vendor/zerocopy-derive/.cargo-checksum.json +1 -1
- data/rust-vendor/zerocopy-derive/.cargo_vcs_info.json +1 -1
- data/rust-vendor/zerocopy-derive/Cargo.lock +1 -1
- data/rust-vendor/zerocopy-derive/Cargo.toml +1 -1
- data/rust-vendor/zerocopy-derive/Cargo.toml.orig +1 -1
- metadata +137 -2
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Iterations: 100
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Instructions: 1500
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Total Cycles: 507
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Total uOps: 1700
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Dispatch Width: 4
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uOps Per Cycle: 3.35
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IPC: 2.96
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Block RThroughput: 4.3
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Instruction Info:
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[1]: #uOps
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[2]: Latency
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[3]: RThroughput
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[4]: MayLoad
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[5]: MayStore
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[6]: HasSideEffects (U)
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[1] [2] [3] [4] [5] [6] Instructions:
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1 1 0.33 movabs rax, 9223372036854775805
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1 1 0.33 cmp rdx, rax
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2 2 1.00 seta cl
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1 1 0.33 mov rax, rdi
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1 1 0.33 or dil, cl
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1 1 0.33 test dil, 1
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1 1 1.00 jne .LBB5_3
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1 1 0.50 lea rcx, [2*rdx + 4]
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1 1 0.33 cmp rsi, rcx
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1 1 1.00 jne .LBB5_3
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2 6 0.50 * cmp word ptr [rax], -16192
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1 1 1.00 je .LBB5_4
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1 0 0.25 xor eax, eax
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1 1 0.33 mov rdx, rsi
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1 1 1.00 U ret
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Resources:
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[0] - SBDivider
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[1] - SBFPDivider
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[2] - SBPort0
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[3] - SBPort1
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[4] - SBPort4
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[5] - SBPort5
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[6.0] - SBPort23
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[6.1] - SBPort23
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Resource pressure per iteration:
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[0] [1] [2] [3] [4] [5] [6.0] [6.1]
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- - 4.98 4.99 - 5.03 0.50 0.50
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Resource pressure by instruction:
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[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
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- - - 0.99 - 0.01 - - movabs rax, 9223372036854775805
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- - 0.50 0.50 - - - - cmp rdx, rax
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- - 1.96 - - 0.04 - - seta cl
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- - 0.01 0.99 - - - - mov rax, rdi
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- - 1.00 - - - - - or dil, cl
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- - 0.99 0.01 - - - - test dil, 1
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- - - - - 1.00 - - jne .LBB5_3
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- - 0.01 0.99 - - - - lea rcx, [2*rdx + 4]
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- - 0.02 0.49 - 0.49 - - cmp rsi, rcx
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- - - - - 1.00 - - jne .LBB5_3
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- - - 0.51 - 0.49 0.50 0.50 cmp word ptr [rax], -16192
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- - - - - 1.00 - - je .LBB5_4
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- - - - - - - - xor eax, eax
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- - 0.49 0.51 - - - - mov rdx, rsi
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- - - - - 1.00 - - ret
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#[path = "formats/coco_dynamic_padding.rs"]
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mod format;
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#[unsafe(no_mangle)]
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fn bench_try_ref_from_prefix_dynamic_padding(source: &[u8]) -> Option<&format::CocoPacket> {
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match zerocopy::TryFromBytes::try_ref_from_prefix(source) {
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Ok((packet, _rest)) => Some(packet),
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_ => None,
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}
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}
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+
bench_try_ref_from_prefix_dynamic_padding:
|
|
2
|
+
xor edx, edx
|
|
3
|
+
mov eax, 0
|
|
4
|
+
test dil, 3
|
|
5
|
+
je .LBB5_1
|
|
6
|
+
ret
|
|
7
|
+
.LBB5_1:
|
|
8
|
+
movabs rax, 9223372036854775804
|
|
9
|
+
and rsi, rax
|
|
10
|
+
cmp rsi, 9
|
|
11
|
+
jae .LBB5_3
|
|
12
|
+
mov edx, 1
|
|
13
|
+
xor eax, eax
|
|
14
|
+
ret
|
|
15
|
+
.LBB5_3:
|
|
16
|
+
add rsi, -9
|
|
17
|
+
movabs rcx, -6148914691236517205
|
|
18
|
+
mov rax, rsi
|
|
19
|
+
mul rcx
|
|
20
|
+
mov rax, rdx
|
|
21
|
+
shr rax
|
|
22
|
+
movzx ecx, word ptr [rdi]
|
|
23
|
+
cmp cx, -16192
|
|
24
|
+
mov edx, 2
|
|
25
|
+
cmove rdx, rax
|
|
26
|
+
xor eax, eax
|
|
27
|
+
cmp ecx, 49344
|
|
28
|
+
cmove rax, rdi
|
|
29
|
+
ret
|
|
@@ -0,0 +1,91 @@
|
|
|
1
|
+
Iterations: 100
|
|
2
|
+
Instructions: 2600
|
|
3
|
+
Total Cycles: 843
|
|
4
|
+
Total uOps: 2900
|
|
5
|
+
|
|
6
|
+
Dispatch Width: 4
|
|
7
|
+
uOps Per Cycle: 3.44
|
|
8
|
+
IPC: 3.08
|
|
9
|
+
Block RThroughput: 7.3
|
|
10
|
+
|
|
11
|
+
|
|
12
|
+
Instruction Info:
|
|
13
|
+
[1]: #uOps
|
|
14
|
+
[2]: Latency
|
|
15
|
+
[3]: RThroughput
|
|
16
|
+
[4]: MayLoad
|
|
17
|
+
[5]: MayStore
|
|
18
|
+
[6]: HasSideEffects (U)
|
|
19
|
+
|
|
20
|
+
[1] [2] [3] [4] [5] [6] Instructions:
|
|
21
|
+
1 0 0.25 xor edx, edx
|
|
22
|
+
1 1 0.33 mov eax, 0
|
|
23
|
+
1 1 0.33 test dil, 3
|
|
24
|
+
1 1 1.00 je .LBB5_1
|
|
25
|
+
1 1 1.00 U ret
|
|
26
|
+
1 1 0.33 movabs rax, 9223372036854775804
|
|
27
|
+
1 1 0.33 and rsi, rax
|
|
28
|
+
1 1 0.33 cmp rsi, 9
|
|
29
|
+
1 1 1.00 jae .LBB5_3
|
|
30
|
+
1 1 0.33 mov edx, 1
|
|
31
|
+
1 0 0.25 xor eax, eax
|
|
32
|
+
1 1 1.00 U ret
|
|
33
|
+
1 1 0.33 add rsi, -9
|
|
34
|
+
1 1 0.33 movabs rcx, -6148914691236517205
|
|
35
|
+
1 1 0.33 mov rax, rsi
|
|
36
|
+
2 4 1.00 mul rcx
|
|
37
|
+
1 1 0.33 mov rax, rdx
|
|
38
|
+
1 1 0.50 shr rax
|
|
39
|
+
1 5 0.50 * movzx ecx, word ptr [rdi]
|
|
40
|
+
1 1 0.33 cmp cx, -16192
|
|
41
|
+
1 1 0.33 mov edx, 2
|
|
42
|
+
2 2 0.67 cmove rdx, rax
|
|
43
|
+
1 0 0.25 xor eax, eax
|
|
44
|
+
1 1 0.33 cmp ecx, 49344
|
|
45
|
+
2 2 0.67 cmove rax, rdi
|
|
46
|
+
1 1 1.00 U ret
|
|
47
|
+
|
|
48
|
+
|
|
49
|
+
Resources:
|
|
50
|
+
[0] - SBDivider
|
|
51
|
+
[1] - SBFPDivider
|
|
52
|
+
[2] - SBPort0
|
|
53
|
+
[3] - SBPort1
|
|
54
|
+
[4] - SBPort4
|
|
55
|
+
[5] - SBPort5
|
|
56
|
+
[6.0] - SBPort23
|
|
57
|
+
[6.1] - SBPort23
|
|
58
|
+
|
|
59
|
+
|
|
60
|
+
Resource pressure per iteration:
|
|
61
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1]
|
|
62
|
+
- - 8.33 8.33 - 8.34 0.50 0.50
|
|
63
|
+
|
|
64
|
+
Resource pressure by instruction:
|
|
65
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
|
|
66
|
+
- - - - - - - - xor edx, edx
|
|
67
|
+
- - 0.32 0.34 - 0.34 - - mov eax, 0
|
|
68
|
+
- - 0.34 0.33 - 0.33 - - test dil, 3
|
|
69
|
+
- - - - - 1.00 - - je .LBB5_1
|
|
70
|
+
- - - - - 1.00 - - ret
|
|
71
|
+
- - 0.35 0.65 - - - - movabs rax, 9223372036854775804
|
|
72
|
+
- - 0.96 0.03 - 0.01 - - and rsi, rax
|
|
73
|
+
- - 0.01 0.97 - 0.02 - - cmp rsi, 9
|
|
74
|
+
- - - - - 1.00 - - jae .LBB5_3
|
|
75
|
+
- - 0.67 0.01 - 0.32 - - mov edx, 1
|
|
76
|
+
- - - - - - - - xor eax, eax
|
|
77
|
+
- - - - - 1.00 - - ret
|
|
78
|
+
- - 0.02 0.34 - 0.64 - - add rsi, -9
|
|
79
|
+
- - 0.33 0.66 - 0.01 - - movabs rcx, -6148914691236517205
|
|
80
|
+
- - 0.66 0.34 - - - - mov rax, rsi
|
|
81
|
+
- - 1.00 1.00 - - - - mul rcx
|
|
82
|
+
- - 0.01 0.99 - - - - mov rax, rdx
|
|
83
|
+
- - 0.99 - - 0.01 - - shr rax
|
|
84
|
+
- - - - - - 0.50 0.50 movzx ecx, word ptr [rdi]
|
|
85
|
+
- - 0.33 0.03 - 0.64 - - cmp cx, -16192
|
|
86
|
+
- - 0.01 0.31 - 0.68 - - mov edx, 2
|
|
87
|
+
- - 1.00 1.00 - - - - cmove rdx, rax
|
|
88
|
+
- - - - - - - - xor eax, eax
|
|
89
|
+
- - 0.33 0.33 - 0.34 - - cmp ecx, 49344
|
|
90
|
+
- - 1.00 1.00 - - - - cmove rax, rdi
|
|
91
|
+
- - - - - 1.00 - - ret
|
|
@@ -0,0 +1,10 @@
|
|
|
1
|
+
#[path = "formats/coco_dynamic_size.rs"]
|
|
2
|
+
mod format;
|
|
3
|
+
|
|
4
|
+
#[unsafe(no_mangle)]
|
|
5
|
+
fn bench_try_ref_from_prefix_dynamic_size(source: &[u8]) -> Option<&format::CocoPacket> {
|
|
6
|
+
match zerocopy::TryFromBytes::try_ref_from_prefix(source) {
|
|
7
|
+
Ok((packet, _rest)) => Some(packet),
|
|
8
|
+
_ => None,
|
|
9
|
+
}
|
|
10
|
+
}
|
|
@@ -0,0 +1,22 @@
|
|
|
1
|
+
bench_try_ref_from_prefix_dynamic_size:
|
|
2
|
+
xor edx, edx
|
|
3
|
+
mov eax, 0
|
|
4
|
+
test dil, 1
|
|
5
|
+
jne .LBB5_4
|
|
6
|
+
cmp rsi, 4
|
|
7
|
+
jae .LBB5_3
|
|
8
|
+
mov edx, 1
|
|
9
|
+
xor eax, eax
|
|
10
|
+
ret
|
|
11
|
+
.LBB5_3:
|
|
12
|
+
add rsi, -4
|
|
13
|
+
shr rsi
|
|
14
|
+
movzx ecx, word ptr [rdi]
|
|
15
|
+
cmp ecx, 49344
|
|
16
|
+
mov edx, 2
|
|
17
|
+
cmove rdx, rsi
|
|
18
|
+
xor eax, eax
|
|
19
|
+
cmp cx, -16192
|
|
20
|
+
cmove rax, rdi
|
|
21
|
+
.LBB5_4:
|
|
22
|
+
ret
|
|
@@ -0,0 +1,77 @@
|
|
|
1
|
+
Iterations: 100
|
|
2
|
+
Instructions: 1900
|
|
3
|
+
Total Cycles: 573
|
|
4
|
+
Total uOps: 2100
|
|
5
|
+
|
|
6
|
+
Dispatch Width: 4
|
|
7
|
+
uOps Per Cycle: 3.66
|
|
8
|
+
IPC: 3.32
|
|
9
|
+
Block RThroughput: 5.3
|
|
10
|
+
|
|
11
|
+
|
|
12
|
+
Instruction Info:
|
|
13
|
+
[1]: #uOps
|
|
14
|
+
[2]: Latency
|
|
15
|
+
[3]: RThroughput
|
|
16
|
+
[4]: MayLoad
|
|
17
|
+
[5]: MayStore
|
|
18
|
+
[6]: HasSideEffects (U)
|
|
19
|
+
|
|
20
|
+
[1] [2] [3] [4] [5] [6] Instructions:
|
|
21
|
+
1 0 0.25 xor edx, edx
|
|
22
|
+
1 1 0.33 mov eax, 0
|
|
23
|
+
1 1 0.33 test dil, 1
|
|
24
|
+
1 1 1.00 jne .LBB5_4
|
|
25
|
+
1 1 0.33 cmp rsi, 4
|
|
26
|
+
1 1 1.00 jae .LBB5_3
|
|
27
|
+
1 1 0.33 mov edx, 1
|
|
28
|
+
1 0 0.25 xor eax, eax
|
|
29
|
+
1 1 1.00 U ret
|
|
30
|
+
1 1 0.33 add rsi, -4
|
|
31
|
+
1 1 0.50 shr rsi
|
|
32
|
+
1 5 0.50 * movzx ecx, word ptr [rdi]
|
|
33
|
+
1 1 0.33 cmp ecx, 49344
|
|
34
|
+
1 1 0.33 mov edx, 2
|
|
35
|
+
2 2 0.67 cmove rdx, rsi
|
|
36
|
+
1 0 0.25 xor eax, eax
|
|
37
|
+
1 1 0.33 cmp cx, -16192
|
|
38
|
+
2 2 0.67 cmove rax, rdi
|
|
39
|
+
1 1 1.00 U ret
|
|
40
|
+
|
|
41
|
+
|
|
42
|
+
Resources:
|
|
43
|
+
[0] - SBDivider
|
|
44
|
+
[1] - SBFPDivider
|
|
45
|
+
[2] - SBPort0
|
|
46
|
+
[3] - SBPort1
|
|
47
|
+
[4] - SBPort4
|
|
48
|
+
[5] - SBPort5
|
|
49
|
+
[6.0] - SBPort23
|
|
50
|
+
[6.1] - SBPort23
|
|
51
|
+
|
|
52
|
+
|
|
53
|
+
Resource pressure per iteration:
|
|
54
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1]
|
|
55
|
+
- - 5.66 5.67 - 5.67 0.50 0.50
|
|
56
|
+
|
|
57
|
+
Resource pressure by instruction:
|
|
58
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
|
|
59
|
+
- - - - - - - - xor edx, edx
|
|
60
|
+
- - 0.30 0.37 - 0.33 - - mov eax, 0
|
|
61
|
+
- - 0.35 0.32 - 0.33 - - test dil, 1
|
|
62
|
+
- - - - - 1.00 - - jne .LBB5_4
|
|
63
|
+
- - 0.32 0.33 - 0.35 - - cmp rsi, 4
|
|
64
|
+
- - - - - 1.00 - - jae .LBB5_3
|
|
65
|
+
- - 0.33 0.35 - 0.32 - - mov edx, 1
|
|
66
|
+
- - - - - - - - xor eax, eax
|
|
67
|
+
- - - - - 1.00 - - ret
|
|
68
|
+
- - 0.34 0.64 - 0.02 - - add rsi, -4
|
|
69
|
+
- - 1.00 - - - - - shr rsi
|
|
70
|
+
- - - - - - 0.50 0.50 movzx ecx, word ptr [rdi]
|
|
71
|
+
- - 0.60 0.40 - - - - cmp ecx, 49344
|
|
72
|
+
- - 0.05 0.95 - - - - mov edx, 2
|
|
73
|
+
- - 1.00 1.00 - - - - cmove rdx, rsi
|
|
74
|
+
- - - - - - - - xor eax, eax
|
|
75
|
+
- - 0.37 0.31 - 0.32 - - cmp cx, -16192
|
|
76
|
+
- - 1.00 1.00 - - - - cmove rax, rdi
|
|
77
|
+
- - - - - 1.00 - - ret
|
|
@@ -0,0 +1,10 @@
|
|
|
1
|
+
#[path = "formats/coco_static_size.rs"]
|
|
2
|
+
mod format;
|
|
3
|
+
|
|
4
|
+
#[unsafe(no_mangle)]
|
|
5
|
+
fn bench_try_ref_from_prefix_static_size(source: &[u8]) -> Option<&format::CocoPacket> {
|
|
6
|
+
match zerocopy::TryFromBytes::try_ref_from_prefix(source) {
|
|
7
|
+
Ok((packet, _rest)) => Some(packet),
|
|
8
|
+
_ => None,
|
|
9
|
+
}
|
|
10
|
+
}
|
|
@@ -0,0 +1,63 @@
|
|
|
1
|
+
Iterations: 100
|
|
2
|
+
Instructions: 1200
|
|
3
|
+
Total Cycles: 374
|
|
4
|
+
Total uOps: 1300
|
|
5
|
+
|
|
6
|
+
Dispatch Width: 4
|
|
7
|
+
uOps Per Cycle: 3.48
|
|
8
|
+
IPC: 3.21
|
|
9
|
+
Block RThroughput: 3.3
|
|
10
|
+
|
|
11
|
+
|
|
12
|
+
Instruction Info:
|
|
13
|
+
[1]: #uOps
|
|
14
|
+
[2]: Latency
|
|
15
|
+
[3]: RThroughput
|
|
16
|
+
[4]: MayLoad
|
|
17
|
+
[5]: MayStore
|
|
18
|
+
[6]: HasSideEffects (U)
|
|
19
|
+
|
|
20
|
+
[1] [2] [3] [4] [5] [6] Instructions:
|
|
21
|
+
1 1 0.33 cmp rsi, 6
|
|
22
|
+
1 1 0.50 setb al
|
|
23
|
+
1 1 0.33 or al, dil
|
|
24
|
+
1 1 0.33 test al, 1
|
|
25
|
+
1 1 1.00 jne .LBB5_2
|
|
26
|
+
1 5 0.50 * movzx eax, word ptr [rdi]
|
|
27
|
+
1 1 0.33 cmp eax, 49344
|
|
28
|
+
1 1 0.33 mov eax, 2
|
|
29
|
+
2 2 0.67 cmove rax, rdi
|
|
30
|
+
1 1 1.00 je .LBB5_3
|
|
31
|
+
1 0 0.25 xor eax, eax
|
|
32
|
+
1 1 1.00 U ret
|
|
33
|
+
|
|
34
|
+
|
|
35
|
+
Resources:
|
|
36
|
+
[0] - SBDivider
|
|
37
|
+
[1] - SBFPDivider
|
|
38
|
+
[2] - SBPort0
|
|
39
|
+
[3] - SBPort1
|
|
40
|
+
[4] - SBPort4
|
|
41
|
+
[5] - SBPort5
|
|
42
|
+
[6.0] - SBPort23
|
|
43
|
+
[6.1] - SBPort23
|
|
44
|
+
|
|
45
|
+
|
|
46
|
+
Resource pressure per iteration:
|
|
47
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1]
|
|
48
|
+
- - 3.66 3.65 - 3.69 0.50 0.50
|
|
49
|
+
|
|
50
|
+
Resource pressure by instruction:
|
|
51
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
|
|
52
|
+
- - 0.35 0.64 - 0.01 - - cmp rsi, 6
|
|
53
|
+
- - 1.00 - - - - - setb al
|
|
54
|
+
- - 0.02 0.66 - 0.32 - - or al, dil
|
|
55
|
+
- - 0.03 0.65 - 0.32 - - test al, 1
|
|
56
|
+
- - - - - 1.00 - - jne .LBB5_2
|
|
57
|
+
- - - - - - 0.50 0.50 movzx eax, word ptr [rdi]
|
|
58
|
+
- - 0.92 0.07 - 0.01 - - cmp eax, 49344
|
|
59
|
+
- - 0.37 0.63 - - - - mov eax, 2
|
|
60
|
+
- - 0.97 1.00 - 0.03 - - cmove rax, rdi
|
|
61
|
+
- - - - - 1.00 - - je .LBB5_3
|
|
62
|
+
- - - - - - - - xor eax, eax
|
|
63
|
+
- - - - - 1.00 - - ret
|
|
@@ -0,0 +1,13 @@
|
|
|
1
|
+
#[path = "formats/coco_dynamic_padding.rs"]
|
|
2
|
+
mod format;
|
|
3
|
+
|
|
4
|
+
#[unsafe(no_mangle)]
|
|
5
|
+
fn bench_try_ref_from_prefix_with_elems_dynamic_padding(
|
|
6
|
+
source: &[u8],
|
|
7
|
+
count: usize,
|
|
8
|
+
) -> Option<&format::CocoPacket> {
|
|
9
|
+
match zerocopy::TryFromBytes::try_ref_from_prefix_with_elems(source, count) {
|
|
10
|
+
Ok((packet, _rest)) => Some(packet),
|
|
11
|
+
_ => None,
|
|
12
|
+
}
|
|
13
|
+
}
|
|
@@ -0,0 +1,35 @@
|
|
|
1
|
+
bench_try_ref_from_prefix_with_elems_dynamic_padding:
|
|
2
|
+
mov rcx, rdx
|
|
3
|
+
mov edx, 3
|
|
4
|
+
mov rax, rcx
|
|
5
|
+
mul rdx
|
|
6
|
+
jo .LBB5_1
|
|
7
|
+
cmp rax, -10
|
|
8
|
+
ja .LBB5_1
|
|
9
|
+
lea rdx, [rax + 9]
|
|
10
|
+
not eax
|
|
11
|
+
and eax, 3
|
|
12
|
+
add rax, rdx
|
|
13
|
+
jae .LBB5_4
|
|
14
|
+
.LBB5_1:
|
|
15
|
+
xor eax, eax
|
|
16
|
+
mov edx, 1
|
|
17
|
+
ret
|
|
18
|
+
.LBB5_4:
|
|
19
|
+
mov r8, rax
|
|
20
|
+
xor edx, edx
|
|
21
|
+
mov eax, 0
|
|
22
|
+
test dil, 3
|
|
23
|
+
je .LBB5_5
|
|
24
|
+
ret
|
|
25
|
+
.LBB5_5:
|
|
26
|
+
cmp r8, rsi
|
|
27
|
+
ja .LBB5_1
|
|
28
|
+
movzx esi, word ptr [rdi]
|
|
29
|
+
cmp si, -16192
|
|
30
|
+
mov edx, 2
|
|
31
|
+
cmove rdx, rcx
|
|
32
|
+
xor eax, eax
|
|
33
|
+
cmp esi, 49344
|
|
34
|
+
cmove rax, rdi
|
|
35
|
+
ret
|
|
@@ -0,0 +1,101 @@
|
|
|
1
|
+
Iterations: 100
|
|
2
|
+
Instructions: 3100
|
|
3
|
+
Total Cycles: 1008
|
|
4
|
+
Total uOps: 3400
|
|
5
|
+
|
|
6
|
+
Dispatch Width: 4
|
|
7
|
+
uOps Per Cycle: 3.37
|
|
8
|
+
IPC: 3.08
|
|
9
|
+
Block RThroughput: 8.5
|
|
10
|
+
|
|
11
|
+
|
|
12
|
+
Instruction Info:
|
|
13
|
+
[1]: #uOps
|
|
14
|
+
[2]: Latency
|
|
15
|
+
[3]: RThroughput
|
|
16
|
+
[4]: MayLoad
|
|
17
|
+
[5]: MayStore
|
|
18
|
+
[6]: HasSideEffects (U)
|
|
19
|
+
|
|
20
|
+
[1] [2] [3] [4] [5] [6] Instructions:
|
|
21
|
+
1 1 0.33 mov rcx, rdx
|
|
22
|
+
1 1 0.33 mov edx, 3
|
|
23
|
+
1 1 0.33 mov rax, rcx
|
|
24
|
+
2 4 1.00 mul rdx
|
|
25
|
+
1 1 1.00 jo .LBB5_1
|
|
26
|
+
1 1 0.33 cmp rax, -10
|
|
27
|
+
1 1 1.00 ja .LBB5_1
|
|
28
|
+
1 1 0.50 lea rdx, [rax + 9]
|
|
29
|
+
1 1 0.33 not eax
|
|
30
|
+
1 1 0.33 and eax, 3
|
|
31
|
+
1 1 0.33 add rax, rdx
|
|
32
|
+
1 1 1.00 jae .LBB5_4
|
|
33
|
+
1 0 0.25 xor eax, eax
|
|
34
|
+
1 1 0.33 mov edx, 1
|
|
35
|
+
1 1 1.00 U ret
|
|
36
|
+
1 1 0.33 mov r8, rax
|
|
37
|
+
1 0 0.25 xor edx, edx
|
|
38
|
+
1 1 0.33 mov eax, 0
|
|
39
|
+
1 1 0.33 test dil, 3
|
|
40
|
+
1 1 1.00 je .LBB5_5
|
|
41
|
+
1 1 1.00 U ret
|
|
42
|
+
1 1 0.33 cmp r8, rsi
|
|
43
|
+
1 1 1.00 ja .LBB5_1
|
|
44
|
+
1 5 0.50 * movzx esi, word ptr [rdi]
|
|
45
|
+
1 1 0.33 cmp si, -16192
|
|
46
|
+
1 1 0.33 mov edx, 2
|
|
47
|
+
2 2 0.67 cmove rdx, rcx
|
|
48
|
+
1 0 0.25 xor eax, eax
|
|
49
|
+
1 1 0.33 cmp esi, 49344
|
|
50
|
+
2 2 0.67 cmove rax, rdi
|
|
51
|
+
1 1 1.00 U ret
|
|
52
|
+
|
|
53
|
+
|
|
54
|
+
Resources:
|
|
55
|
+
[0] - SBDivider
|
|
56
|
+
[1] - SBFPDivider
|
|
57
|
+
[2] - SBPort0
|
|
58
|
+
[3] - SBPort1
|
|
59
|
+
[4] - SBPort4
|
|
60
|
+
[5] - SBPort5
|
|
61
|
+
[6.0] - SBPort23
|
|
62
|
+
[6.1] - SBPort23
|
|
63
|
+
|
|
64
|
+
|
|
65
|
+
Resource pressure per iteration:
|
|
66
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1]
|
|
67
|
+
- - 9.98 9.99 - 10.03 0.50 0.50
|
|
68
|
+
|
|
69
|
+
Resource pressure by instruction:
|
|
70
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
|
|
71
|
+
- - 0.49 0.50 - 0.01 - - mov rcx, rdx
|
|
72
|
+
- - 0.01 0.99 - - - - mov edx, 3
|
|
73
|
+
- - 0.99 0.01 - - - - mov rax, rcx
|
|
74
|
+
- - 1.00 1.00 - - - - mul rdx
|
|
75
|
+
- - - - - 1.00 - - jo .LBB5_1
|
|
76
|
+
- - 1.00 - - - - - cmp rax, -10
|
|
77
|
+
- - - - - 1.00 - - ja .LBB5_1
|
|
78
|
+
- - - 1.00 - - - - lea rdx, [rax + 9]
|
|
79
|
+
- - 1.00 - - - - - not eax
|
|
80
|
+
- - 0.99 0.01 - - - - and eax, 3
|
|
81
|
+
- - 0.99 0.01 - - - - add rax, rdx
|
|
82
|
+
- - - - - 1.00 - - jae .LBB5_4
|
|
83
|
+
- - - - - - - - xor eax, eax
|
|
84
|
+
- - - 0.98 - 0.02 - - mov edx, 1
|
|
85
|
+
- - - - - 1.00 - - ret
|
|
86
|
+
- - 0.50 0.50 - - - - mov r8, rax
|
|
87
|
+
- - - - - - - - xor edx, edx
|
|
88
|
+
- - 0.02 0.49 - 0.49 - - mov eax, 0
|
|
89
|
+
- - - 0.49 - 0.51 - - test dil, 3
|
|
90
|
+
- - - - - 1.00 - - je .LBB5_5
|
|
91
|
+
- - - - - 1.00 - - ret
|
|
92
|
+
- - 0.98 0.02 - - - - cmp r8, rsi
|
|
93
|
+
- - - - - 1.00 - - ja .LBB5_1
|
|
94
|
+
- - - - - - 0.50 0.50 movzx esi, word ptr [rdi]
|
|
95
|
+
- - 0.02 0.98 - - - - cmp si, -16192
|
|
96
|
+
- - 0.98 0.02 - - - - mov edx, 2
|
|
97
|
+
- - 0.50 1.00 - 0.50 - - cmove rdx, rcx
|
|
98
|
+
- - - - - - - - xor eax, eax
|
|
99
|
+
- - 0.01 0.99 - - - - cmp esi, 49344
|
|
100
|
+
- - 0.50 1.00 - 0.50 - - cmove rax, rdi
|
|
101
|
+
- - - - - 1.00 - - ret
|
|
@@ -0,0 +1,13 @@
|
|
|
1
|
+
#[path = "formats/coco_dynamic_size.rs"]
|
|
2
|
+
mod format;
|
|
3
|
+
|
|
4
|
+
#[unsafe(no_mangle)]
|
|
5
|
+
fn bench_try_ref_from_prefix_with_elems_dynamic_size(
|
|
6
|
+
source: &[u8],
|
|
7
|
+
count: usize,
|
|
8
|
+
) -> Option<&format::CocoPacket> {
|
|
9
|
+
match zerocopy::TryFromBytes::try_ref_from_prefix_with_elems(source, count) {
|
|
10
|
+
Ok((packet, _rest)) => Some(packet),
|
|
11
|
+
_ => None,
|
|
12
|
+
}
|
|
13
|
+
}
|
|
@@ -0,0 +1,26 @@
|
|
|
1
|
+
bench_try_ref_from_prefix_with_elems_dynamic_size:
|
|
2
|
+
movabs rax, 9223372036854775805
|
|
3
|
+
cmp rdx, rax
|
|
4
|
+
ja .LBB5_1
|
|
5
|
+
mov rcx, rdx
|
|
6
|
+
xor edx, edx
|
|
7
|
+
mov eax, 0
|
|
8
|
+
test dil, 1
|
|
9
|
+
jne .LBB5_5
|
|
10
|
+
lea rax, [2*rcx + 4]
|
|
11
|
+
cmp rax, rsi
|
|
12
|
+
jbe .LBB5_4
|
|
13
|
+
.LBB5_1:
|
|
14
|
+
xor eax, eax
|
|
15
|
+
mov edx, 1
|
|
16
|
+
ret
|
|
17
|
+
.LBB5_4:
|
|
18
|
+
movzx esi, word ptr [rdi]
|
|
19
|
+
cmp si, -16192
|
|
20
|
+
mov edx, 2
|
|
21
|
+
cmove rdx, rcx
|
|
22
|
+
xor eax, eax
|
|
23
|
+
cmp esi, 49344
|
|
24
|
+
cmove rax, rdi
|
|
25
|
+
.LBB5_5:
|
|
26
|
+
ret
|
|
@@ -0,0 +1,83 @@
|
|
|
1
|
+
Iterations: 100
|
|
2
|
+
Instructions: 2200
|
|
3
|
+
Total Cycles: 674
|
|
4
|
+
Total uOps: 2400
|
|
5
|
+
|
|
6
|
+
Dispatch Width: 4
|
|
7
|
+
uOps Per Cycle: 3.56
|
|
8
|
+
IPC: 3.26
|
|
9
|
+
Block RThroughput: 6.0
|
|
10
|
+
|
|
11
|
+
|
|
12
|
+
Instruction Info:
|
|
13
|
+
[1]: #uOps
|
|
14
|
+
[2]: Latency
|
|
15
|
+
[3]: RThroughput
|
|
16
|
+
[4]: MayLoad
|
|
17
|
+
[5]: MayStore
|
|
18
|
+
[6]: HasSideEffects (U)
|
|
19
|
+
|
|
20
|
+
[1] [2] [3] [4] [5] [6] Instructions:
|
|
21
|
+
1 1 0.33 movabs rax, 9223372036854775805
|
|
22
|
+
1 1 0.33 cmp rdx, rax
|
|
23
|
+
1 1 1.00 ja .LBB5_1
|
|
24
|
+
1 1 0.33 mov rcx, rdx
|
|
25
|
+
1 0 0.25 xor edx, edx
|
|
26
|
+
1 1 0.33 mov eax, 0
|
|
27
|
+
1 1 0.33 test dil, 1
|
|
28
|
+
1 1 1.00 jne .LBB5_5
|
|
29
|
+
1 1 0.50 lea rax, [2*rcx + 4]
|
|
30
|
+
1 1 0.33 cmp rax, rsi
|
|
31
|
+
1 1 1.00 jbe .LBB5_4
|
|
32
|
+
1 0 0.25 xor eax, eax
|
|
33
|
+
1 1 0.33 mov edx, 1
|
|
34
|
+
1 1 1.00 U ret
|
|
35
|
+
1 5 0.50 * movzx esi, word ptr [rdi]
|
|
36
|
+
1 1 0.33 cmp si, -16192
|
|
37
|
+
1 1 0.33 mov edx, 2
|
|
38
|
+
2 2 0.67 cmove rdx, rcx
|
|
39
|
+
1 0 0.25 xor eax, eax
|
|
40
|
+
1 1 0.33 cmp esi, 49344
|
|
41
|
+
2 2 0.67 cmove rax, rdi
|
|
42
|
+
1 1 1.00 U ret
|
|
43
|
+
|
|
44
|
+
|
|
45
|
+
Resources:
|
|
46
|
+
[0] - SBDivider
|
|
47
|
+
[1] - SBFPDivider
|
|
48
|
+
[2] - SBPort0
|
|
49
|
+
[3] - SBPort1
|
|
50
|
+
[4] - SBPort4
|
|
51
|
+
[5] - SBPort5
|
|
52
|
+
[6.0] - SBPort23
|
|
53
|
+
[6.1] - SBPort23
|
|
54
|
+
|
|
55
|
+
|
|
56
|
+
Resource pressure per iteration:
|
|
57
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1]
|
|
58
|
+
- - 6.65 6.66 - 6.69 0.50 0.50
|
|
59
|
+
|
|
60
|
+
Resource pressure by instruction:
|
|
61
|
+
[0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
|
|
62
|
+
- - 0.66 0.33 - 0.01 - - movabs rax, 9223372036854775805
|
|
63
|
+
- - 0.02 0.66 - 0.32 - - cmp rdx, rax
|
|
64
|
+
- - - - - 1.00 - - ja .LBB5_1
|
|
65
|
+
- - 0.66 0.33 - 0.01 - - mov rcx, rdx
|
|
66
|
+
- - - - - - - - xor edx, edx
|
|
67
|
+
- - 0.33 0.01 - 0.66 - - mov eax, 0
|
|
68
|
+
- - 0.34 0.65 - 0.01 - - test dil, 1
|
|
69
|
+
- - - - - 1.00 - - jne .LBB5_5
|
|
70
|
+
- - 0.65 0.35 - - - - lea rax, [2*rcx + 4]
|
|
71
|
+
- - - 1.00 - - - - cmp rax, rsi
|
|
72
|
+
- - - - - 1.00 - - jbe .LBB5_4
|
|
73
|
+
- - - - - - - - xor eax, eax
|
|
74
|
+
- - 0.34 0.01 - 0.65 - - mov edx, 1
|
|
75
|
+
- - - - - 1.00 - - ret
|
|
76
|
+
- - - - - - 0.50 0.50 movzx esi, word ptr [rdi]
|
|
77
|
+
- - 0.65 0.34 - 0.01 - - cmp si, -16192
|
|
78
|
+
- - 0.66 0.34 - - - - mov edx, 2
|
|
79
|
+
- - 1.00 0.99 - 0.01 - - cmove rdx, rcx
|
|
80
|
+
- - - - - - - - xor eax, eax
|
|
81
|
+
- - 0.34 0.66 - - - - cmp esi, 49344
|
|
82
|
+
- - 1.00 0.99 - 0.01 - - cmove rax, rdi
|
|
83
|
+
- - - - - 1.00 - - ret
|