haxor 0.4.0 → 0.5.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
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-  data.tar.gz: 6660137e743eb98ba7c64d3770d0326ea7e84710
+  metadata.gz: 8a4e2b69873a7f50003c2fb9d403f9529a7fc88e
+  data.tar.gz: 1531d3af090791055290d4bfb982fca8e9ae188e
 SHA512:
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+  data.tar.gz: c0220e732f98cff88b1045bcd5418d36983a838197d8e765d49c1e7434f52fcc8cc7bc6eff93c1c33f62fdd0dcf8cc29c4a3b6e4e9d590a0bf62a3eb2a1136e1

data/lib/haxor.rb

@@ -15,8 +15,7 @@ require_relative 'haxor/vm/subsystem'
 require_relative 'haxor/vm/mem'
 require_relative 'haxor/vm/stack'
 require_relative 'haxor/vm/os'
-require_relative 'haxor/vm/registers'
-require_relative 'haxor/vm/cpu/core'
+require_relative 'haxor/vm/cpu'
 
 # compiler
 require_relative 'haxor/compiler/unit'

data/lib/haxor/compiler/core.rb

@@ -2,9 +2,9 @@ module Haxor
   module Compiler
     class Core
       REG_ALIASES = {
-        '$sp'  => Vm::Cpu::Core::REG_STACK,
-        '$ret' => Vm::Cpu::Core::REG_RETURN,
-        '$sc'  => Vm::Cpu::Core::REG_SYSCALL
+        '$sp'  => Vm::Cpu::REG_STACK,
+        '$ret' => Vm::Cpu::REG_RETURN,
+        '$sc'  => Vm::Cpu::REG_SYSCALL
       }
 
       def initialize
@@ -41,37 +41,37 @@ module Haxor
         bind_cmd 'bgtz',    [:reg, :imm],       :cmd_bgtz
         bind_cmd 'beqz',    [:reg, :imm],       :cmd_beqz
 
-        bind_cmd 'nop',     [],                 Vm::Cpu::Core::OP_NOP
-        bind_cmd 'add',     [:reg, :reg, :reg], Vm::Cpu::Core::OP_ADD
-        bind_cmd 'addi',    [:reg, :reg, :imm], Vm::Cpu::Core::OP_ADDI
-        bind_cmd 'sub',     [:reg, :reg, :reg], Vm::Cpu::Core::OP_SUB
-        bind_cmd 'mult',    [:reg, :reg, :reg], Vm::Cpu::Core::OP_MULT
-        bind_cmd 'div',     [:reg, :reg, :reg], Vm::Cpu::Core::OP_DIV
-        bind_cmd 'mod',     [:reg, :reg, :reg], Vm::Cpu::Core::OP_MOD
-        bind_cmd 'lw',      [:reg, :reg, :imm], Vm::Cpu::Core::OP_LW
-        bind_cmd 'sw',      [:reg, :imm, :reg], Vm::Cpu::Core::OP_SW
-        bind_cmd 'lui',     [:reg, :imm],       Vm::Cpu::Core::OP_LUI
-        bind_cmd 'and',     [:reg, :reg, :reg], Vm::Cpu::Core::OP_AND
-        bind_cmd 'andi',    [:reg, :reg, :imm], Vm::Cpu::Core::OP_ANDI
-        bind_cmd 'or',      [:reg, :reg, :reg], Vm::Cpu::Core::OP_OR
-        bind_cmd 'ori',     [:reg, :reg, :imm], Vm::Cpu::Core::OP_ORI
-        bind_cmd 'xor',     [:reg, :reg, :reg], Vm::Cpu::Core::OP_XOR
-        bind_cmd 'nor',     [:reg, :reg, :reg], Vm::Cpu::Core::OP_NOR
-        bind_cmd 'slt',     [:reg, :reg, :reg], Vm::Cpu::Core::OP_SLT
-        bind_cmd 'slti',    [:reg, :reg, :imm], Vm::Cpu::Core::OP_SLTI
-        bind_cmd 'slli',    [:reg, :reg, :imm], Vm::Cpu::Core::OP_SLLI
-        bind_cmd 'srli',    [:reg, :reg, :imm], Vm::Cpu::Core::OP_SRLI
-        bind_cmd 'sll',     [:reg, :reg, :reg], Vm::Cpu::Core::OP_SLL
-        bind_cmd 'srl',     [:reg, :reg, :reg], Vm::Cpu::Core::OP_SRL
-        bind_cmd 'beq',     [:reg, :reg, :imm], Vm::Cpu::Core::OP_BEQ,  [:rel_imm, :x8]
-        bind_cmd 'beql',    [:reg, :reg, :imm], Vm::Cpu::Core::OP_BEQL, [:rel_imm, :x8]
-        bind_cmd 'bne',     [:reg, :reg, :imm], Vm::Cpu::Core::OP_BNE,  [:rel_imm, :x8]
-        bind_cmd 'bnel',    [:reg, :reg, :imm], Vm::Cpu::Core::OP_BNEL, [:rel_imm, :x8]
-        bind_cmd 'j',       [:imm],             Vm::Cpu::Core::OP_J,    [:x8]
-        bind_cmd 'jr',      [:reg],             Vm::Cpu::Core::OP_JR
-        bind_cmd 'jal',     [:imm],             Vm::Cpu::Core::OP_JAL,  [:x8]
-        bind_cmd 'exiti',   [:imm],             Vm::Cpu::Core::OP_EXITI
-        bind_cmd 'syscall', [],                 Vm::Cpu::Core::OP_SYSCALL
+        bind_cmd 'nop',     [],                 Vm::Cpu::OP_NOP
+        bind_cmd 'add',     [:reg, :reg, :reg], Vm::Cpu::OP_ADD
+        bind_cmd 'addi',    [:reg, :reg, :imm], Vm::Cpu::OP_ADDI
+        bind_cmd 'sub',     [:reg, :reg, :reg], Vm::Cpu::OP_SUB
+        bind_cmd 'mult',    [:reg, :reg, :reg], Vm::Cpu::OP_MULT
+        bind_cmd 'div',     [:reg, :reg, :reg], Vm::Cpu::OP_DIV
+        bind_cmd 'mod',     [:reg, :reg, :reg], Vm::Cpu::OP_MOD
+        bind_cmd 'lw',      [:reg, :reg, :imm], Vm::Cpu::OP_LW
+        bind_cmd 'sw',      [:reg, :imm, :reg], Vm::Cpu::OP_SW
+        bind_cmd 'lui',     [:reg, :imm],       Vm::Cpu::OP_LUI
+        bind_cmd 'and',     [:reg, :reg, :reg], Vm::Cpu::OP_AND
+        bind_cmd 'andi',    [:reg, :reg, :imm], Vm::Cpu::OP_ANDI
+        bind_cmd 'or',      [:reg, :reg, :reg], Vm::Cpu::OP_OR
+        bind_cmd 'ori',     [:reg, :reg, :imm], Vm::Cpu::OP_ORI
+        bind_cmd 'xor',     [:reg, :reg, :reg], Vm::Cpu::OP_XOR
+        bind_cmd 'nor',     [:reg, :reg, :reg], Vm::Cpu::OP_NOR
+        bind_cmd 'slt',     [:reg, :reg, :reg], Vm::Cpu::OP_SLT
+        bind_cmd 'slti',    [:reg, :reg, :imm], Vm::Cpu::OP_SLTI
+        bind_cmd 'slli',    [:reg, :reg, :imm], Vm::Cpu::OP_SLLI
+        bind_cmd 'srli',    [:reg, :reg, :imm], Vm::Cpu::OP_SRLI
+        bind_cmd 'sll',     [:reg, :reg, :reg], Vm::Cpu::OP_SLL
+        bind_cmd 'srl',     [:reg, :reg, :reg], Vm::Cpu::OP_SRL
+        bind_cmd 'beq',     [:reg, :reg, :imm], Vm::Cpu::OP_BEQ,  [:rel_imm, :x8]
+        bind_cmd 'beql',    [:reg, :reg, :imm], Vm::Cpu::OP_BEQL, [:rel_imm, :x8]
+        bind_cmd 'bne',     [:reg, :reg, :imm], Vm::Cpu::OP_BNE,  [:rel_imm, :x8]
+        bind_cmd 'bnel',    [:reg, :reg, :imm], Vm::Cpu::OP_BNEL, [:rel_imm, :x8]
+        bind_cmd 'j',       [:imm],             Vm::Cpu::OP_J,    [:x8]
+        bind_cmd 'jr',      [:reg],             Vm::Cpu::OP_JR
+        bind_cmd 'jal',     [:imm],             Vm::Cpu::OP_JAL,  [:x8]
+        bind_cmd 'exiti',   [:imm],             Vm::Cpu::OP_EXITI
+        bind_cmd 'syscall', [],                 Vm::Cpu::OP_SYSCALL
       end
 
       def bind_cmd(cmd, args, opcode, opts = [])
@@ -155,7 +155,7 @@ module Haxor
       end
 
       def cmd_ret(*_args)
-        process_cmd 'jr', ['$' + Vm::Cpu::Core::REG_RETURN.to_s]
+        process_cmd 'jr', ['$' + Vm::Cpu::REG_RETURN.to_s]
       end
 
       def cmd_b(*args)

data/lib/haxor/consts.rb

@@ -1,7 +1,7 @@
 module Haxor
   class Consts
     MAJOR = 0
-    MINOR = 4
+    MINOR = 5
     PATCH = 0
     GEM_VERSION = "#{MAJOR}.#{MINOR}.#{PATCH}"
     VERSION = (MAJOR << 16) | (MINOR << 8) | PATCH

data/lib/haxor/linker.rb

@@ -5,7 +5,7 @@ module Haxor
     SECTIONS = [:text, :data, :bss]
 
     def initialize
-      @cpu = Vm::Cpu::Core.new
+      @cpu = Vm::Cpu.new
       @units = []
       @tokens = []
       @labels = {}

data/lib/haxor/vm/core.rb

@@ -5,7 +5,7 @@ module Haxor
 
       def initialize
         @subsystems = {}
-        register_subsystem :cpu, Cpu::Core.new
+        register_subsystem :cpu, Cpu.new
         register_subsystem :mem, Mem.new(Consts::RESERVED_MEM)
         register_subsystem :stack, Stack.new
         register_subsystem :os, Os.new
@@ -45,7 +45,7 @@ module Haxor
         subsystem(:cpu).ip = @hdr.entry_point # instruction pointer
         subsystem(:mem).enlarge @hdr.bss_size
         subsystem(:mem).enlarge @hdr.stack_size
-        subsystem(:cpu).reg Vm::Cpu::Core::REG_STACK, subsystem(:mem).size
+        subsystem(:cpu).reg Vm::Cpu::REG_STACK, subsystem(:mem).size
       end
     end
   end

data/lib/haxor/vm/cpu.rb

@@ -0,0 +1,258 @@
+module Haxor
+  module Vm
+    class Cpu < Subsystem
+      attr_accessor :ip
+
+      # Misc
+      OP_NOP     = 0x00
+      OP_EXITI   = 0x01
+      OP_SYSCALL = 0x02
+
+      # Arithmetic
+      OP_ADD     = 0x10
+      OP_ADDI    = 0x11
+      OP_SUB     = 0x12
+      OP_MULT    = 0x13
+      OP_DIV     = 0x14
+      OP_MOD     = 0x15
+
+      # Data transfer
+      OP_LW      = 0x20
+      OP_SW      = 0x21
+      OP_LUI     = 0x22
+
+      # Logical
+      OP_AND     = 0x30
+      OP_ANDI    = 0x31
+      OP_OR      = 0x32
+      OP_ORI     = 0x33
+      OP_XOR     = 0x34
+      OP_NOR     = 0x35
+      OP_SLT     = 0x36
+      OP_SLTI    = 0x37
+
+      # Bitwise shift
+      OP_SLLI    = 0x40
+      OP_SRLI    = 0x41
+      OP_SLL     = 0x42
+      OP_SRL     = 0x43
+
+      # Branch/Jumps
+      OP_BEQ     = 0x50
+      OP_BEQL    = 0x51
+      OP_BNE     = 0x52
+      OP_BNEL    = 0x53
+      OP_J       = 0x54
+      OP_JR      = 0x55
+      OP_JAL     = 0x56
+
+      REG_ZERO    = 0
+      REG_STACK   = 61
+      REG_RETURN  = 62
+      REG_SYSCALL = 63
+
+      def initialize
+        @registers = Array.new(64, 0)
+        @units = []
+        @opcodes = {}
+        init_opcodes
+      end
+
+      def init_opcodes
+        bind_opcode OP_NOP, :op_nop
+        bind_opcode OP_ADD, :op_add
+        bind_opcode OP_ADDI, :op_addi
+        bind_opcode OP_SUB, :op_sub
+        bind_opcode OP_MULT, :op_mult
+        bind_opcode OP_DIV, :op_div
+        bind_opcode OP_MOD, :op_mod
+        bind_opcode OP_LW, :op_lw
+        bind_opcode OP_SW, :op_sw
+        bind_opcode OP_LUI, :op_lui
+        bind_opcode OP_AND, :op_and
+        bind_opcode OP_ANDI, :op_andi
+        bind_opcode OP_OR, :op_or
+        bind_opcode OP_ORI, :op_ori
+        bind_opcode OP_XOR, :op_xor
+        bind_opcode OP_NOR, :op_nor
+        bind_opcode OP_SLT, :op_slt
+        bind_opcode OP_SLTI, :op_slti
+        bind_opcode OP_SLLI, :op_slli
+        bind_opcode OP_SRLI, :op_srli
+        bind_opcode OP_SLL, :op_sll
+        bind_opcode OP_SRL, :op_srl
+        bind_opcode OP_BEQ, :op_beq
+        bind_opcode OP_BEQL, :op_beql
+        bind_opcode OP_BNE, :op_bne
+        bind_opcode OP_BNEL, :op_bnel
+        bind_opcode OP_J, :op_j
+        bind_opcode OP_JR, :op_jr
+        bind_opcode OP_JAL, :op_jal
+        bind_opcode OP_EXITI, :op_exiti
+        bind_opcode OP_SYSCALL, :op_syscall
+      end
+
+      def op_nop(info)
+      end
+
+      def op_add(info)
+        reg info.reg1, reg(info.reg2) + reg(info.reg3)
+      end
+
+      def op_addi(info)
+        reg info.reg1, reg(info.reg2) + info.imm
+      end
+
+      def op_sub(info)
+        reg info.reg1, reg(info.reg2) - reg(info.reg3)
+      end
+
+      def op_mult(info)
+        reg info.reg1, reg(info.reg2) * reg(info.reg3)
+      end
+
+      def op_div(info)
+        reg info.reg1, reg(info.reg2) / reg(info.reg3)
+      end
+
+      def op_mod(info)
+        reg info.reg1, reg(info.reg2) % reg(info.reg3)
+      end
+
+      # reg1 = memory[reg2+imm]
+      def op_lw(info)
+        addr = reg(info.reg2) + info.imm
+        reg info.reg1, subsystem(:mem).read(addr)
+      end
+
+      # memory[reg1+imm] = reg2
+      def op_sw(info)
+        addr = reg(info.reg1) + info.imm
+        subsystem(:mem).write addr, reg(info.reg2)
+      end
+
+      def op_lui(info)
+        reg info.reg1, (info.imm << 32)
+      end
+
+      def op_and(info)
+        reg info.reg1, reg(info.reg2) & reg(info.reg3)
+      end
+
+      def op_andi(info)
+        reg info.reg1, reg(info.reg2) & info.imm
+      end
+
+      def op_or(info)
+        reg info.reg1, reg(info.reg2) | reg(info.reg3)
+      end
+
+      def op_ori(info)
+        reg info.reg1, reg(info.reg2) | info.imm
+      end
+
+      def op_xor(info)
+        reg info.reg1, reg(info.reg2) ^ reg(info.reg3)
+      end
+
+      def op_nor(info)
+        reg info.reg1, ~(reg(info.reg2) | reg(info.reg3))
+      end
+
+      def op_slt(info)
+        reg info.reg1, reg(info.reg2) < reg(info.reg3) ? 1 : 0
+      end
+
+      def op_slti(info)
+        reg info.reg1, reg(info.reg2) < info.imm ? 1 : 0
+      end
+
+      def op_slli(info)
+        reg info.reg1, reg(info.reg2) << info.imm
+      end
+
+      def op_srli(info)
+        reg info.reg1, reg(info.reg2) >> info.imm
+      end
+
+      def op_sll(info)
+        reg info.reg1, reg(info.reg2) << reg(info.reg3)
+      end
+
+      def op_srl(info)
+        reg info.reg1, reg(info.reg2) >> reg(info.reg3)
+      end
+
+      def op_beq(info)
+        branch(info.imm) if reg(info.reg1) == reg(info.reg2)
+      end
+
+      def op_beql(info)
+        return if reg(info.reg1) != reg(info.reg2)
+
+        reg REG_RETURN, @ip
+        branch(info.imm)
+      end
+
+      def op_bne(info)
+        branch info.imm if reg(info.reg1) != reg(info.reg2)
+      end
+
+      def op_bnel(info)
+        return if reg(info.reg1) == reg(info.reg2)
+
+        reg REG_RETURN, @ip
+        branch(info.imm)
+      end
+
+      def op_j(info)
+        jmp info.imm
+      end
+
+      def op_jr(info)
+        @ip = reg(info.reg1)
+      end
+
+      def op_jal(info)
+        reg REG_RETURN, @ip
+        jmp info.imm
+      end
+
+      def op_exiti(info)
+        exit info.imm
+      end
+
+      def op_syscall(_info)
+        @vm.subsystem(:os).syscall
+      end
+
+      def reg(id, value = nil)
+        return @registers[id] if value.nil?
+        return if id == REG_ZERO # $0 cannot be overwritten
+        @registers[id] = value
+      end
+
+      def jmp(addr)
+        @ip = addr * Consts::WORD_SIZE
+      end
+
+      def branch(rel_addr)
+        @ip += rel_addr * Consts::WORD_SIZE
+      end
+
+      def bind_opcode(opcode, method)
+        fail "OpCode already defined - #{opcode}." if @opcodes.key? opcode
+        @opcodes[opcode] = {
+          method: method
+        }
+      end
+
+      def iterate
+        opcode = subsystem(:mem).read @ip
+        @ip += Consts::WORD_SIZE
+        info = Utils.decode_opcode opcode
+        send @opcodes[info.cmd][:method], info
+      end
+    end
+  end
+end

data/lib/haxor/vm/os.rb

@@ -8,7 +8,7 @@ module Haxor
       }
 
       def syscall
-        func = subsystem(:cpu).reg(Vm::Cpu::Core::REG_SYSCALL)
+        func = subsystem(:cpu).reg(Vm::Cpu::REG_SYSCALL)
         send(TABLE[func])
       end
 
@@ -78,7 +78,7 @@ module Haxor
         result = file.scanf fmt
 
         if result.size != types.size
-          subsystem(:cpu).reg Vm::Cpu::Core::REG_SYSCALL, -1
+          subsystem(:cpu).reg Vm::Cpu::REG_SYSCALL, -1
           return
         end
 

data/lib/haxor/vm/stack.rb

@@ -7,9 +7,9 @@ module Haxor
       end
 
       def push_value(value)
-        sp = @vm.subsystem(:cpu).reg Vm::Cpu::Core::REG_STACK
+        sp = @vm.subsystem(:cpu).reg Vm::Cpu::REG_STACK
         sp -= Consts::WORD_SIZE
-        @vm.subsystem(:cpu).reg Vm::Cpu::Core::REG_STACK, sp
+        @vm.subsystem(:cpu).reg Vm::Cpu::REG_STACK, sp
         @vm.subsystem(:mem).write sp, value
       end
 
@@ -19,10 +19,10 @@ module Haxor
       end
 
       def pop_value
-        sp = @vm.subsystem(:cpu).reg Vm::Cpu::Core::REG_STACK
+        sp = @vm.subsystem(:cpu).reg Vm::Cpu::REG_STACK
         value = @vm.subsystem(:mem).read sp
         sp += Consts::WORD_SIZE
-        @vm.subsystem(:cpu).reg Vm::Cpu::Core::REG_STACK, sp
+        @vm.subsystem(:cpu).reg Vm::Cpu::REG_STACK, sp
 
         value
       end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: haxor
 version: !ruby/object:Gem::Version
-  version: 0.4.0
+  version: 0.5.0
 platform: ruby
 authors:
 - Krzysztof Magosa
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2016-01-04 00:00:00.000000000 Z
+date: 2016-01-05 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -75,10 +75,9 @@ files:
 - lib/haxor/token/pointer.rb
 - lib/haxor/utils.rb
 - lib/haxor/vm/core.rb
-- lib/haxor/vm/cpu/core.rb
+- lib/haxor/vm/cpu.rb
 - lib/haxor/vm/mem.rb
 - lib/haxor/vm/os.rb
-- lib/haxor/vm/registers.rb
 - lib/haxor/vm/stack.rb
 - lib/haxor/vm/subsystem.rb
 - media/memory.png

data/lib/haxor/vm/cpu/core.rb

@@ -1,260 +0,0 @@
-module Haxor
-  module Vm
-    module Cpu
-      class Core < Subsystem
-        attr_accessor :ip
-
-        # Misc
-        OP_NOP     = 0x00
-        OP_EXITI   = 0x01
-        OP_SYSCALL = 0x02
-
-        # Arithmetic
-        OP_ADD     = 0x10
-        OP_ADDI    = 0x11
-        OP_SUB     = 0x12
-        OP_MULT    = 0x13
-        OP_DIV     = 0x14
-        OP_MOD     = 0x15
-
-        # Data transfer
-        OP_LW      = 0x20
-        OP_SW      = 0x21
-        OP_LUI     = 0x22
-
-        # Logical
-        OP_AND     = 0x30
-        OP_ANDI    = 0x31
-        OP_OR      = 0x32
-        OP_ORI     = 0x33
-        OP_XOR     = 0x34
-        OP_NOR     = 0x35
-        OP_SLT     = 0x36
-        OP_SLTI    = 0x37
-
-        # Bitwise shift
-        OP_SLLI    = 0x40
-        OP_SRLI    = 0x41
-        OP_SLL     = 0x42
-        OP_SRL     = 0x43
-
-        # Branch/Jumps
-        OP_BEQ     = 0x50
-        OP_BEQL    = 0x51
-        OP_BNE     = 0x52
-        OP_BNEL    = 0x53
-        OP_J       = 0x54
-        OP_JR      = 0x55
-        OP_JAL     = 0x56
-
-        REG_ZERO    = 0
-        REG_STACK   = 61
-        REG_RETURN  = 62
-        REG_SYSCALL = 63
-
-        def initialize
-          @registers = Array.new(64, 0)
-          @units = []
-          @opcodes = {}
-          init_opcodes
-        end
-
-        def init_opcodes
-          bind_opcode OP_NOP, :op_nop
-          bind_opcode OP_ADD, :op_add
-          bind_opcode OP_ADDI, :op_addi
-          bind_opcode OP_SUB, :op_sub
-          bind_opcode OP_MULT, :op_mult
-          bind_opcode OP_DIV, :op_div
-          bind_opcode OP_MOD, :op_mod
-          bind_opcode OP_LW, :op_lw
-          bind_opcode OP_SW, :op_sw
-          bind_opcode OP_LUI, :op_lui
-          bind_opcode OP_AND, :op_and
-          bind_opcode OP_ANDI, :op_andi
-          bind_opcode OP_OR, :op_or
-          bind_opcode OP_ORI, :op_ori
-          bind_opcode OP_XOR, :op_xor
-          bind_opcode OP_NOR, :op_nor
-          bind_opcode OP_SLT, :op_slt
-          bind_opcode OP_SLTI, :op_slti
-          bind_opcode OP_SLLI, :op_slli
-          bind_opcode OP_SRLI, :op_srli
-          bind_opcode OP_SLL, :op_sll
-          bind_opcode OP_SRL, :op_srl
-          bind_opcode OP_BEQ, :op_beq
-          bind_opcode OP_BEQL, :op_beql
-          bind_opcode OP_BNE, :op_bne
-          bind_opcode OP_BNEL, :op_bnel
-          bind_opcode OP_J, :op_j
-          bind_opcode OP_JR, :op_jr
-          bind_opcode OP_JAL, :op_jal
-          bind_opcode OP_EXITI, :op_exiti
-          bind_opcode OP_SYSCALL, :op_syscall
-        end
-
-        def op_nop(info)
-        end
-
-        def op_add(info)
-          reg info.reg1, reg(info.reg2) + reg(info.reg3)
-        end
-
-        def op_addi(info)
-          reg info.reg1, reg(info.reg2) + info.imm
-        end
-
-        def op_sub(info)
-          reg info.reg1, reg(info.reg2) - reg(info.reg3)
-        end
-
-        def op_mult(info)
-          reg info.reg1, reg(info.reg2) * reg(info.reg3)
-        end
-
-        def op_div(info)
-          reg info.reg1, reg(info.reg2) / reg(info.reg3)
-        end
-
-        def op_mod(info)
-          reg info.reg1, reg(info.reg2) % reg(info.reg3)
-        end
-
-        # reg1 = memory[reg2+imm]
-        def op_lw(info)
-          addr = reg(info.reg2) + info.imm
-          reg info.reg1, subsystem(:mem).read(addr)
-        end
-
-        # memory[reg1+imm] = reg2
-        def op_sw(info)
-          addr = reg(info.reg1) + info.imm
-          subsystem(:mem).write addr, reg(info.reg2)
-        end
-
-        def op_lui(info)
-          reg info.reg1, (info.imm << 32)
-        end
-
-        def op_and(info)
-          reg info.reg1, reg(info.reg2) & reg(info.reg3)
-        end
-
-        def op_andi(info)
-          reg info.reg1, reg(info.reg2) & info.imm
-        end
-
-        def op_or(info)
-          reg info.reg1, reg(info.reg2) | reg(info.reg3)
-        end
-
-        def op_ori(info)
-          reg info.reg1, reg(info.reg2) | info.imm
-        end
-
-        def op_xor(info)
-          reg info.reg1, reg(info.reg2) ^ reg(info.reg3)
-        end
-
-        def op_nor(info)
-          reg info.reg1, ~(reg(info.reg2) | reg(info.reg3))
-        end
-
-        def op_slt(info)
-          reg info.reg1, reg(info.reg2) < reg(info.reg3) ? 1 : 0
-        end
-
-        def op_slti(info)
-          reg info.reg1, reg(info.reg2) < info.imm ? 1 : 0
-        end
-
-        def op_slli(info)
-          reg info.reg1, reg(info.reg2) << info.imm
-        end
-
-        def op_srli(info)
-          reg info.reg1, reg(info.reg2) >> info.imm
-        end
-
-        def op_sll(info)
-          reg info.reg1, reg(info.reg2) << reg(info.reg3)
-        end
-
-        def op_srl(info)
-          reg info.reg1, reg(info.reg2) >> reg(info.reg3)
-        end
-
-        def op_beq(info)
-          branch(info.imm) if reg(info.reg1) == reg(info.reg2)
-        end
-
-        def op_beql(info)
-          return if reg(info.reg1) != reg(info.reg2)
-
-          reg REG_RETURN, @ip
-          branch(info.imm)
-        end
-
-        def op_bne(info)
-          branch info.imm if reg(info.reg1) != reg(info.reg2)
-        end
-
-        def op_bnel(info)
-          return if reg(info.reg1) == reg(info.reg2)
-
-          reg REG_RETURN, @ip
-          branch(info.imm)
-        end
-
-        def op_j(info)
-          jmp info.imm
-        end
-
-        def op_jr(info)
-          @ip = reg(info.reg1)
-        end
-
-        def op_jal(info)
-          reg REG_RETURN, @ip
-          jmp info.imm
-        end
-
-        def op_exiti(info)
-          exit info.imm
-        end
-
-        def op_syscall(_info)
-          @vm.subsystem(:os).syscall
-        end
-
-        def reg(id, value = nil)
-          return @registers[id] if value.nil?
-          return if id == REG_ZERO # $0 cannot be overwritten
-          @registers[id] = value
-        end
-
-        def jmp(addr)
-          @ip = addr * Consts::WORD_SIZE
-        end
-
-        def branch(rel_addr)
-          @ip += rel_addr * Consts::WORD_SIZE
-        end
-
-        def bind_opcode(opcode, method)
-          fail "OpCode already defined - #{opcode}." if @opcodes.key? opcode
-          @opcodes[opcode] = {
-            method: method
-          }
-        end
-
-        def iterate
-          opcode = subsystem(:mem).read @ip
-          @ip += Consts::WORD_SIZE
-          info = Utils.decode_opcode opcode
-          send @opcodes[info.cmd][:method], info
-        end
-      end
-    end
-  end
-end

data/lib/haxor/vm/registers.rb

@@ -1,42 +0,0 @@
-module Haxor
-  module Vm
-    class Registers < Subsystem
-      def initialize
-        @registers = {}
-      end
-
-      def flag(flag, enabled)
-        flags = read 'fr'
-        if enabled
-          flags |= flag
-        else
-          flags &= ~flag
-        end
-        write 'fr', flags
-      end
-
-      def check_flag(flag)
-        flags = read 'fr'
-        (flags & flag) > 0
-      end
-
-      def read(register)
-        addr = resolve register
-        @vm.subsystem(:mem).read addr
-      end
-
-      def write(register, value)
-        addr = resolve register
-        @vm.subsystem(:mem).write addr, value
-      end
-
-      def resolve(register)
-        @registers[register]
-      end
-
-      def add_register(register, addr)
-        @registers[register] = addr
-      end
-    end
-  end
-end