gupl 0.0.2 → 0.0.3
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- checksums.yaml +4 -4
- data/gupl.gemspec +1 -1
- data/lib/gupl/entity.rb +192 -0
- data/lib/gupl/process.rb +56 -0
- data/lib/gupl/signal.rb +43 -0
- data/lib/gupl/statemachine.rb +136 -0
- data/lib/gupl/upl.rb +216 -0
- data/lib/gupl/version.rb +1 -1
- data/lib/gupl.rb +5 -637
- metadata +9 -3
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA256:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: 683eccdc06e67a71d0436efc49a9aebc0d9bcd26ae56edb7aad2672f4563c05f
|
4
|
+
data.tar.gz: a588c41d5a1a7f03fcced129a7b26b3eda3fcc37b8c2b1e175836e51c86e465e
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: 0f0e9e7eb3781b130229ccae01daf8bb8812a2307886ee267990a615d5d4a71e5b629bb6c892645597978a26dca1f8eb164ab603a7eb4483aa85fbc5dd893674
|
7
|
+
data.tar.gz: e6219cd55a80a810b74ea37adfd223a5a5d01847856657d447c164e5aef28fdddf638c2cb5a99b3c911c9f81cd252481328ca9bed567d227f011fcb869c730bf
|
data/gupl.gemspec
CHANGED
@@ -7,7 +7,7 @@ Gem::Specification.new do |spec|
|
|
7
7
|
spec.version = Gupl::VERSION
|
8
8
|
spec.authors = ["Takefumi MIYOSHI"]
|
9
9
|
spec.email = ["miyo@wasamon.net"]
|
10
|
-
|
10
|
+
spec.license = 'Apache-2.0'
|
11
11
|
spec.summary = "gupl makes UPL module."
|
12
12
|
spec.description = "gupl makes UPL modules, which is a VHDL generator."
|
13
13
|
spec.homepage = "https://github.com/e-trees/gupl"
|
data/lib/gupl/entity.rb
ADDED
@@ -0,0 +1,192 @@
|
|
1
|
+
module Gupl
|
2
|
+
class Entity
|
3
|
+
|
4
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+
def initialize(name)
|
5
|
+
@name = name
|
6
|
+
@send_upls = []
|
7
|
+
@recv_upls = []
|
8
|
+
@ports = []
|
9
|
+
@signals = []
|
10
|
+
@process = MainProcess.new(self)
|
11
|
+
@async = ""
|
12
|
+
end
|
13
|
+
attr_reader :name, :send_upls, :recv_upls, :process
|
14
|
+
|
15
|
+
def get_main_recv_upl()
|
16
|
+
@recv_upls.each{|upl|
|
17
|
+
return upl if upl.id == 0
|
18
|
+
}
|
19
|
+
return nil
|
20
|
+
end
|
21
|
+
|
22
|
+
def add_send_upl(upl)
|
23
|
+
@send_upls << upl
|
24
|
+
end
|
25
|
+
|
26
|
+
def add_recv_upl(upl)
|
27
|
+
@recv_upls << upl
|
28
|
+
end
|
29
|
+
|
30
|
+
def add_port(port)
|
31
|
+
@ports << port
|
32
|
+
end
|
33
|
+
|
34
|
+
def add_signal(signal)
|
35
|
+
@signals << signal
|
36
|
+
end
|
37
|
+
|
38
|
+
def add_reset_stage(str)
|
39
|
+
@process.add_reset_stage(str)
|
40
|
+
end
|
41
|
+
|
42
|
+
def add_idle_stage(str)
|
43
|
+
@process.add_idle_stage(str)
|
44
|
+
end
|
45
|
+
|
46
|
+
def add_new_stage(name)
|
47
|
+
@process.add_new_stage(name)
|
48
|
+
end
|
49
|
+
|
50
|
+
def add_async(str)
|
51
|
+
@async += str
|
52
|
+
end
|
53
|
+
|
54
|
+
def generate_vhdl_header(buf)
|
55
|
+
buf.puts("library ieee;")
|
56
|
+
buf.puts("use ieee.std_logic_1164.all;")
|
57
|
+
buf.puts("use ieee.numeric_std.all;")
|
58
|
+
buf.puts("")
|
59
|
+
end
|
60
|
+
|
61
|
+
def generate_entity_define(buf)
|
62
|
+
buf.puts("entity #{@name} is")
|
63
|
+
buf.puts("port(")
|
64
|
+
|
65
|
+
@recv_upls.each{|upl|
|
66
|
+
upl.generate_ports(buf)
|
67
|
+
}
|
68
|
+
|
69
|
+
@send_upls.each{|upl|
|
70
|
+
upl.generate_ports(buf)
|
71
|
+
}
|
72
|
+
|
73
|
+
buf.puts(" -- user-defiend ports")
|
74
|
+
@ports.each{|port|
|
75
|
+
port.generate_define(buf)
|
76
|
+
}
|
77
|
+
buf.puts("")
|
78
|
+
|
79
|
+
buf.puts(" -- system clock and reset")
|
80
|
+
buf.puts(" clk : in std_logic;")
|
81
|
+
buf.puts(" reset : in std_logic")
|
82
|
+
buf.puts(");")
|
83
|
+
buf.puts("end entity #{@name};")
|
84
|
+
buf.puts("")
|
85
|
+
end
|
86
|
+
|
87
|
+
def generate_architecture_define(buf)
|
88
|
+
buf.puts("architecture RTL of #{@name} is")
|
89
|
+
buf.puts("")
|
90
|
+
|
91
|
+
@process.statemachine.generate_define(buf)
|
92
|
+
|
93
|
+
buf.puts()
|
94
|
+
buf.puts(" -- UPL signals")
|
95
|
+
table = {}
|
96
|
+
@send_upls.each{|upl|
|
97
|
+
upl.variables.each{|var|
|
98
|
+
next if table[var.name] != nil
|
99
|
+
table[var.name] = var
|
100
|
+
var.generate_define(buf)
|
101
|
+
}
|
102
|
+
}
|
103
|
+
@recv_upls.each{|upl|
|
104
|
+
upl.variables.each{|var|
|
105
|
+
next if table[var.name] != nil
|
106
|
+
table[var.name] = var
|
107
|
+
var.generate_define(buf)
|
108
|
+
}
|
109
|
+
}
|
110
|
+
|
111
|
+
buf.puts()
|
112
|
+
buf.puts(" -- user-defiend signals")
|
113
|
+
@signals.each{|signal|
|
114
|
+
signal.generate_define(buf)
|
115
|
+
}
|
116
|
+
buf.puts("")
|
117
|
+
|
118
|
+
buf.puts(" -- ip-cores")
|
119
|
+
simple_dualportram = false
|
120
|
+
table.values.each{|var|
|
121
|
+
if var.storage? and simple_dualportram == false then
|
122
|
+
simple_dualportram = true
|
123
|
+
buf.puts(" component simple_dualportram")
|
124
|
+
buf.puts(" generic (")
|
125
|
+
buf.puts(" DEPTH : integer := 10;")
|
126
|
+
buf.puts(" WIDTH : integer := 32;")
|
127
|
+
buf.puts(" WORDS : integer := 1024")
|
128
|
+
buf.puts(" );")
|
129
|
+
buf.puts(" port (")
|
130
|
+
buf.puts(" clk : in std_logic;")
|
131
|
+
buf.puts(" reset : in std_logic;")
|
132
|
+
buf.puts(" we : in std_logic_vector(0 downto 0);")
|
133
|
+
buf.puts(" raddr : in std_logic_vector(31 downto 0);")
|
134
|
+
buf.puts(" waddr : in std_logic_vector(31 downto 0);")
|
135
|
+
buf.puts(" dout : out std_logic_vector(WIDTH-1 downto 0);")
|
136
|
+
buf.puts(" din : in std_logic_vector(WIDTH-1 downto 0);")
|
137
|
+
buf.puts(" length : out std_logic_vector(31 downto 0)")
|
138
|
+
buf.puts(" );")
|
139
|
+
buf.puts(" end component simple_dualportram;")
|
140
|
+
end
|
141
|
+
}
|
142
|
+
buf.puts("")
|
143
|
+
|
144
|
+
buf.puts("begin")
|
145
|
+
buf.puts("")
|
146
|
+
buf.puts(" -- add async")
|
147
|
+
buf.puts(@async)
|
148
|
+
|
149
|
+
buf.puts("")
|
150
|
+
@process.generate(buf)
|
151
|
+
buf.puts("")
|
152
|
+
|
153
|
+
buf.puts("")
|
154
|
+
table.values.each{|var|
|
155
|
+
if var.storage? then
|
156
|
+
buf.puts(" buf_#{var.name}_i : simple_dualportram")
|
157
|
+
buf.puts(" generic map(")
|
158
|
+
buf.puts(" DEPTH => #{Math.log2((var.bits/var.upl.width).ceil).ceil},")
|
159
|
+
buf.puts(" WIDTH => #{var.upl.width},")
|
160
|
+
buf.puts(" WORDS => #{(var.bits/var.upl.width).ceil}")
|
161
|
+
buf.puts(" )")
|
162
|
+
buf.puts(" port map(")
|
163
|
+
buf.puts(" clk => clk,")
|
164
|
+
buf.puts(" reset => reset,")
|
165
|
+
buf.puts(" we => #{var.name}_we,")
|
166
|
+
buf.puts(" raddr => #{var.name}_raddr,")
|
167
|
+
buf.puts(" waddr => #{var.name}_waddr,")
|
168
|
+
buf.puts(" dout => #{var.name}_dout,")
|
169
|
+
buf.puts(" din => #{var.name}_din,")
|
170
|
+
buf.puts(" length => open")
|
171
|
+
buf.puts(" );")
|
172
|
+
end
|
173
|
+
}
|
174
|
+
|
175
|
+
|
176
|
+
buf.puts("end RTL;")
|
177
|
+
end
|
178
|
+
|
179
|
+
def generate(buf)
|
180
|
+
buf.puts("--")
|
181
|
+
buf.puts("-- generated by gupl ver.#{VERSION}")
|
182
|
+
buf.puts("-- https://github.com/e-trees/gupl")
|
183
|
+
buf.puts("--")
|
184
|
+
buf.puts("")
|
185
|
+
generate_vhdl_header(buf)
|
186
|
+
generate_entity_define(buf)
|
187
|
+
generate_architecture_define(buf)
|
188
|
+
end
|
189
|
+
|
190
|
+
end
|
191
|
+
end
|
192
|
+
|
data/lib/gupl/process.rb
ADDED
@@ -0,0 +1,56 @@
|
|
1
|
+
module Gupl
|
2
|
+
class MainProcess
|
3
|
+
|
4
|
+
def initialize(entity)
|
5
|
+
@entity = entity
|
6
|
+
@reset_stage = nil
|
7
|
+
@statemachine = StateMachine.new(self, "gupl_state")
|
8
|
+
end
|
9
|
+
attr_reader :entity, :statemachine
|
10
|
+
|
11
|
+
def add_reset_stage(str)
|
12
|
+
@reset_stage = str
|
13
|
+
end
|
14
|
+
|
15
|
+
def add_idle_stage(str)
|
16
|
+
@statemachine.add_idle_stage(str)
|
17
|
+
end
|
18
|
+
|
19
|
+
def add_new_stage(name)
|
20
|
+
@statemachine.add_new_stage(name)
|
21
|
+
end
|
22
|
+
|
23
|
+
def generate_reset(buf)
|
24
|
+
@entity.send_upls.each{|upl|
|
25
|
+
buf.puts(" #{upl.enable.name} <= '0';")
|
26
|
+
buf.puts(" #{upl.request.name} <= '0';")
|
27
|
+
buf.puts(" #{upl.data.name} <= (others => '0');")
|
28
|
+
}
|
29
|
+
@entity.recv_upls.each{|upl|
|
30
|
+
buf.puts(" #{upl.ack.name} <= '0';")
|
31
|
+
}
|
32
|
+
buf.puts(" #{@statemachine.name} <= IDLE;")
|
33
|
+
buf.puts(" #{@entity.process.statemachine.name}_next <= IDLE;")
|
34
|
+
if @reset_stage != nil then
|
35
|
+
buf.puts("")
|
36
|
+
buf.puts(" -- user-defiend reset stage")
|
37
|
+
buf.puts(@reset_stage)
|
38
|
+
buf.puts("")
|
39
|
+
end
|
40
|
+
end
|
41
|
+
|
42
|
+
def generate(buf)
|
43
|
+
buf.puts("process(clk)")
|
44
|
+
buf.puts("begin")
|
45
|
+
buf.puts(" if rising_edge(clk) then")
|
46
|
+
buf.puts(" if reset = '1' then")
|
47
|
+
generate_reset(buf)
|
48
|
+
buf.puts(" else")
|
49
|
+
@statemachine.generate(buf)
|
50
|
+
buf.puts(" end if;")
|
51
|
+
buf.puts(" end if;")
|
52
|
+
buf.puts("end process;")
|
53
|
+
end
|
54
|
+
|
55
|
+
end
|
56
|
+
end
|
data/lib/gupl/signal.rb
ADDED
@@ -0,0 +1,43 @@
|
|
1
|
+
module Gupl
|
2
|
+
class LocalSignal
|
3
|
+
|
4
|
+
def initialize(name:, width:)
|
5
|
+
@name = name
|
6
|
+
@width = width.to_i
|
7
|
+
@type = "std_logic_vector"
|
8
|
+
end
|
9
|
+
attr_reader :name, :width
|
10
|
+
|
11
|
+
def generate_define(buf)
|
12
|
+
if @width > 0 then
|
13
|
+
buf.puts(" signal #{@name} : #{@type}(#{@width}-1 downto 0);")
|
14
|
+
else
|
15
|
+
buf.puts(" signal #{@name} : std_logic;")
|
16
|
+
end
|
17
|
+
end
|
18
|
+
|
19
|
+
def set_type(type)
|
20
|
+
@type = type
|
21
|
+
end
|
22
|
+
|
23
|
+
end
|
24
|
+
|
25
|
+
class GenericPort
|
26
|
+
|
27
|
+
def initialize(name:, width:, dir:)
|
28
|
+
@name = name
|
29
|
+
@width = width.to_i
|
30
|
+
@dir = dir
|
31
|
+
end
|
32
|
+
attr_reader :name, :width, :dir
|
33
|
+
|
34
|
+
def generate_define(buf)
|
35
|
+
if @width > 0 then
|
36
|
+
buf.puts(" #{@name} : #{@dir} std_logic_vector(#{@width}-1 downto 0);")
|
37
|
+
else
|
38
|
+
buf.puts(" #{@name} : #{@dir} std_logic;")
|
39
|
+
end
|
40
|
+
end
|
41
|
+
|
42
|
+
end
|
43
|
+
end
|
@@ -0,0 +1,136 @@
|
|
1
|
+
module Gupl
|
2
|
+
class StateMachine
|
3
|
+
|
4
|
+
def initialize(process, name)
|
5
|
+
@process = process
|
6
|
+
@name = name
|
7
|
+
@idle_state = State.new(self, "IDLE")
|
8
|
+
@states = [@idle_state]
|
9
|
+
end
|
10
|
+
attr_reader :name
|
11
|
+
|
12
|
+
def init_storage(buf)
|
13
|
+
table = {}
|
14
|
+
@process.entity.send_upls.each{|upl|
|
15
|
+
upl.variables.each{|var|
|
16
|
+
if var.storage? and table[var.name] == nil then
|
17
|
+
table[var.name] = true
|
18
|
+
buf.puts(" #{var.name}_we <= (others => '0');")
|
19
|
+
buf.puts(" #{var.name}_waddr <= (others => '1');")
|
20
|
+
buf.puts(" #{var.name}_raddr <= (others => '0');")
|
21
|
+
buf.puts(" #{var.name}_recv_words <= (others => '0');")
|
22
|
+
buf.puts(" #{var.name}_send_words <= (others => '0');")
|
23
|
+
end
|
24
|
+
}
|
25
|
+
}
|
26
|
+
@process.entity.recv_upls.each{|upl|
|
27
|
+
upl.variables.each{|var|
|
28
|
+
if var.storage? and table[var.name] == nil then
|
29
|
+
table[var.name] = true
|
30
|
+
buf.puts(" #{var.name}_we <= (others => '0');")
|
31
|
+
buf.puts(" #{var.name}_waddr <= (others => '1');")
|
32
|
+
buf.puts(" #{var.name}_raddr <= (others => '0');")
|
33
|
+
buf.puts(" #{var.name}_recv_words <= (others => '0');")
|
34
|
+
buf.puts(" #{var.name}_send_words <= (others => '0');")
|
35
|
+
end
|
36
|
+
}
|
37
|
+
}
|
38
|
+
end
|
39
|
+
|
40
|
+
def init_idle_state
|
41
|
+
upl = @process.entity.get_main_recv_upl
|
42
|
+
if upl != nil
|
43
|
+
buf = StringIO.new("", "w")
|
44
|
+
buf.puts(" #{name} <= #{upl.name}_recv_0;")
|
45
|
+
buf.puts(" #{name}_next <= #{@process.entity.name};")
|
46
|
+
@process.entity.send_upls.each{|upl|
|
47
|
+
buf.puts(" #{upl.enable.name} <= '0';")
|
48
|
+
buf.puts(" #{upl.request.name} <= '0';")
|
49
|
+
buf.puts(" #{upl.data.name} <= (others => '0');")
|
50
|
+
}
|
51
|
+
@process.entity.recv_upls.each{|upl|
|
52
|
+
buf.puts(" #{upl.ack.name} <= '0';")
|
53
|
+
}
|
54
|
+
init_storage(buf)
|
55
|
+
@idle_state.add_contents(buf.string)
|
56
|
+
end
|
57
|
+
end
|
58
|
+
|
59
|
+
def generate(buf)
|
60
|
+
init_idle_state()
|
61
|
+
buf.puts(" case #{@name} is")
|
62
|
+
@states.each{|state|
|
63
|
+
buf.puts(" when #{state.name} =>")
|
64
|
+
state.generate(buf)
|
65
|
+
}
|
66
|
+
@process.entity.send_upls.each{|upl|
|
67
|
+
upl.generate_stages(buf)
|
68
|
+
}
|
69
|
+
@process.entity.recv_upls.each{|upl|
|
70
|
+
upl.generate_stages(buf)
|
71
|
+
}
|
72
|
+
buf.puts(" when others => #{@name} <= IDLE;")
|
73
|
+
buf.puts(" end case;")
|
74
|
+
end
|
75
|
+
|
76
|
+
def add_idle_stage(str)
|
77
|
+
@idle_state.add_contents(str)
|
78
|
+
end
|
79
|
+
|
80
|
+
def add_new_stage(name)
|
81
|
+
state = State.new(self, name)
|
82
|
+
@states << state
|
83
|
+
return state
|
84
|
+
end
|
85
|
+
|
86
|
+
def generate_define(buf)
|
87
|
+
buf.puts(" -- statemachine type and signal")
|
88
|
+
sep = ""
|
89
|
+
buf.puts(" type StateType is (")
|
90
|
+
@states.each{|state|
|
91
|
+
buf.print("#{sep} #{state.name}")
|
92
|
+
sep = ",\n"
|
93
|
+
}
|
94
|
+
@process.entity.send_upls.each{|upl|
|
95
|
+
(upl.stages.size+2).times{|i|
|
96
|
+
buf.print("#{sep} #{upl.name}_send_#{i}")
|
97
|
+
sep = ",\n"
|
98
|
+
}
|
99
|
+
}
|
100
|
+
@process.entity.recv_upls.each{|upl|
|
101
|
+
(upl.stages.size+1).times{|i|
|
102
|
+
buf.print("#{sep} #{upl.name}_recv_#{i}")
|
103
|
+
sep = ",\n"
|
104
|
+
}
|
105
|
+
}
|
106
|
+
buf.puts("\n );")
|
107
|
+
buf.puts(" signal #{@name} : StateType := IDLE;")
|
108
|
+
buf.puts(" signal #{@name}_next : StateType := IDLE;")
|
109
|
+
end
|
110
|
+
|
111
|
+
end
|
112
|
+
|
113
|
+
class State
|
114
|
+
|
115
|
+
def initialize(statemachine, name)
|
116
|
+
@statemachine = statemachine
|
117
|
+
@name = name
|
118
|
+
@contents = ""
|
119
|
+
end
|
120
|
+
attr_reader :name
|
121
|
+
|
122
|
+
def add_contents(str)
|
123
|
+
@contents += str
|
124
|
+
end
|
125
|
+
|
126
|
+
def generate(buf)
|
127
|
+
if @contents == "" then
|
128
|
+
buf.puts(" pass;")
|
129
|
+
else
|
130
|
+
buf.puts(@contents)
|
131
|
+
end
|
132
|
+
end
|
133
|
+
|
134
|
+
end
|
135
|
+
|
136
|
+
end
|
data/lib/gupl/upl.rb
ADDED
@@ -0,0 +1,216 @@
|
|
1
|
+
module Gupl
|
2
|
+
class UPL
|
3
|
+
def initialize(entity:, name:, width:, id:)
|
4
|
+
@entity = entity
|
5
|
+
@name = name
|
6
|
+
@width = width.to_i
|
7
|
+
@id = id.to_i
|
8
|
+
@variables = []
|
9
|
+
@variable_ptr = 0
|
10
|
+
@stages = []
|
11
|
+
@storage = nil
|
12
|
+
end
|
13
|
+
attr_reader :id, :name, :width
|
14
|
+
attr_reader :data, :enable, :ack, :request
|
15
|
+
attr_reader :variables, :stages
|
16
|
+
|
17
|
+
def add_variable(name, bits)
|
18
|
+
variable = UPLVariable.new(self, name, @variable_ptr, bits)
|
19
|
+
@variables << variable
|
20
|
+
if (@variable_ptr / @width) > (@stages.size - 1) then
|
21
|
+
@stages << [variable]
|
22
|
+
else
|
23
|
+
@stages[-1] << variable
|
24
|
+
end
|
25
|
+
@variable_ptr += variable.bits
|
26
|
+
if variable.storage?
|
27
|
+
@storage = variable
|
28
|
+
end
|
29
|
+
end
|
30
|
+
|
31
|
+
def generate_ports(buf)
|
32
|
+
buf.puts(" -- #{@name}")
|
33
|
+
@data.generate_define(buf)
|
34
|
+
@enable.generate_define(buf)
|
35
|
+
@request.generate_define(buf)
|
36
|
+
@ack.generate_define(buf)
|
37
|
+
buf.puts("")
|
38
|
+
end
|
39
|
+
|
40
|
+
end
|
41
|
+
|
42
|
+
class RecvUPL < UPL
|
43
|
+
|
44
|
+
def initialize(entity:, name:, width:, id:)
|
45
|
+
super(entity: entity, name: name, width: width, id: id)
|
46
|
+
@data = GenericPort.new(name: "UPL_#{@name}_data", width: @width, dir: "in")
|
47
|
+
@enable = GenericPort.new(name: "UPL_#{@name}_en", width: 0, dir: "in")
|
48
|
+
@request = GenericPort.new(name: "UPL_#{@name}_req", width: 0, dir: "in")
|
49
|
+
@ack = GenericPort.new(name: "UPL_#{@name}_ack", width: 0, dir: "out")
|
50
|
+
end
|
51
|
+
|
52
|
+
def generate_stages(buf)
|
53
|
+
t = " " * 8
|
54
|
+
@stages.each_with_index{|stage, i|
|
55
|
+
buf.puts("#{t}when #{name}_recv_#{i} =>")
|
56
|
+
pos = @width
|
57
|
+
if i == 0 then
|
58
|
+
buf.puts("#{t} if #{enable.name} = '1' then")
|
59
|
+
buf.puts("#{t} #{@ack.name} <= '0';")
|
60
|
+
buf.puts("#{t} else")
|
61
|
+
buf.puts("#{t} #{@ack.name} <= '1';")
|
62
|
+
buf.puts("#{t} end if;")
|
63
|
+
else
|
64
|
+
buf.puts("#{t} #{@ack.name} <= '0';")
|
65
|
+
end
|
66
|
+
stage.each_with_index{|variable|
|
67
|
+
if variable.storage? then
|
68
|
+
buf.puts("#{t} if #{enable.name} = '1' then")
|
69
|
+
buf.puts("#{t} #{variable.name}_waddr <= std_logic_vector(unsigned(#{variable.name}_waddr)+1);")
|
70
|
+
buf.puts("#{t} #{variable.name}_we <= \"1\";")
|
71
|
+
buf.puts("#{t} #{variable.name}_din <= #{@data.name};")
|
72
|
+
buf.puts("#{t} #{variable.name}_recv_words <= std_logic_vector(unsigned(#{variable.name}_recv_words)+1);")
|
73
|
+
buf.puts("#{t} else")
|
74
|
+
buf.puts("#{t} #{variable.name}_we <= \"0\";")
|
75
|
+
buf.puts("#{t} end if;")
|
76
|
+
else
|
77
|
+
buf.puts("#{t} #{variable.name} <= #{@data.name}(#{pos-1} downto #{pos-variable.bits});")
|
78
|
+
pos -= variable.bits
|
79
|
+
end
|
80
|
+
}
|
81
|
+
|
82
|
+
if i == 0 then
|
83
|
+
buf.puts("#{t} if #{enable.name} = '1' then")
|
84
|
+
t += " "
|
85
|
+
end
|
86
|
+
|
87
|
+
buf.puts("#{t} #{@entity.process.statemachine.name} <= #{name}_recv_#{i+1};")
|
88
|
+
|
89
|
+
if i == 0 then
|
90
|
+
t = t[2..]
|
91
|
+
buf.puts("#{t} end if;")
|
92
|
+
end
|
93
|
+
}
|
94
|
+
buf.puts("#{t}when #{name}_recv_#{stages.size} =>")
|
95
|
+
buf.puts("#{t} if #{@enable.name} = '0' then")
|
96
|
+
buf.puts("#{t} #{@entity.process.statemachine.name} <= #{@entity.process.statemachine.name}_next;")
|
97
|
+
if @storage != nil then
|
98
|
+
buf.puts("#{t} #{@storage.name}_we <= \"0\";")
|
99
|
+
buf.puts("#{t} else")
|
100
|
+
buf.puts("#{t} #{@storage.name}_waddr <= std_logic_vector(unsigned(#{@storage.name}_waddr)+1);")
|
101
|
+
buf.puts("#{t} #{@storage.name}_we <= \"1\";")
|
102
|
+
buf.puts("#{t} #{@storage.name}_din <= #{@data.name};")
|
103
|
+
buf.puts("#{t} #{@storage.name}_recv_words <= std_logic_vector(unsigned(#{@storage.name}_recv_words)+1);")
|
104
|
+
end
|
105
|
+
buf.puts("#{t} end if;")
|
106
|
+
end
|
107
|
+
|
108
|
+
end
|
109
|
+
|
110
|
+
class SendUPL < UPL
|
111
|
+
|
112
|
+
def initialize(entity:, name:, width:, id:)
|
113
|
+
super(entity: entity, name: name, width: width, id: id)
|
114
|
+
@data = GenericPort.new(name: "UPL_#{@name}_data", width: @width, dir: "out")
|
115
|
+
@enable = GenericPort.new(name: "UPL_#{@name}_en", width: 0, dir: "out")
|
116
|
+
@request = GenericPort.new(name: "UPL_#{@name}_req", width: 0, dir: "out")
|
117
|
+
@ack = GenericPort.new(name: "UPL_#{@name}_ack", width: 0, dir: "in")
|
118
|
+
end
|
119
|
+
|
120
|
+
def generate_stages(buf)
|
121
|
+
buf.puts(" when #{name}_send_0 =>")
|
122
|
+
buf.puts(" #{@request.name} <= '1';")
|
123
|
+
if @storage != nil then
|
124
|
+
buf.puts(" #{@storage.name}_send_words <= (others => '0');")
|
125
|
+
end
|
126
|
+
buf.puts(" if #{@ack.name} = '1' then")
|
127
|
+
if @storage != nil then
|
128
|
+
buf.puts(" #{@storage.name}_raddr <= (others => '0'); -- for next next")
|
129
|
+
end
|
130
|
+
buf.puts(" #{@entity.process.statemachine.name} <= #{name}_send_1;")
|
131
|
+
buf.puts(" end if;")
|
132
|
+
|
133
|
+
buf.puts(" when #{name}_send_1 =>")
|
134
|
+
buf.puts(" #{@entity.process.statemachine.name} <= #{name}_send_2;")
|
135
|
+
if @storage != nil and @stages[0][0] == @storage then
|
136
|
+
buf.puts(" #{@storage.name}_raddr <= std_logic_vector(unsigned(#{@storage.name}_raddr)+1);")
|
137
|
+
end
|
138
|
+
|
139
|
+
@stages.each_with_index{|stage, i|
|
140
|
+
buf.puts(" when #{name}_send_#{i+2} =>")
|
141
|
+
pos = @width
|
142
|
+
state_trans = false
|
143
|
+
buf.puts(" #{@request.name} <= '0';")
|
144
|
+
stage.each{|variable|
|
145
|
+
if variable.storage? then
|
146
|
+
state_trans = true
|
147
|
+
buf.puts(" if #{variable.name}_recv_words = #{variable.name}_send_words then")
|
148
|
+
buf.puts(" #{@entity.process.statemachine.name} <= #{@entity.process.statemachine.name}_next;")
|
149
|
+
buf.puts(" #{@enable.name} <= '0';")
|
150
|
+
buf.puts(" else")
|
151
|
+
buf.puts(" #{variable.name}_raddr <= std_logic_vector(unsigned(#{variable.name}_raddr)+1); -- for next next")
|
152
|
+
buf.puts(" #{@data.name} <= #{variable.name}_dout;")
|
153
|
+
buf.puts(" #{variable.name}_send_words <= std_logic_vector(unsigned(#{variable.name}_send_words)+1);")
|
154
|
+
buf.puts(" #{@enable.name} <= '1';")
|
155
|
+
buf.puts(" end if;")
|
156
|
+
else
|
157
|
+
buf.puts(" #{@data.name}(#{pos-1} downto #{pos-variable.bits}) <= #{variable.name};")
|
158
|
+
pos -= variable.bits
|
159
|
+
end
|
160
|
+
}
|
161
|
+
if @storage != nil and @stages[i+1] != nil and @stages[i+1][0] == @storage then
|
162
|
+
buf.puts(" #{@storage.name}_raddr <= std_logic_vector(unsigned(#{@storage.name}_raddr)+1); -- for next next")
|
163
|
+
end
|
164
|
+
if state_trans == false
|
165
|
+
buf.puts(" #{@enable.name} <= '1';")
|
166
|
+
if i == stages.size - 1 then
|
167
|
+
buf.puts(" #{@entity.process.statemachine.name} <= #{@entity.process.statemachine.name}_next;")
|
168
|
+
else
|
169
|
+
buf.puts(" #{@entity.process.statemachine.name} <= #{name}_send_#{i+2+1};")
|
170
|
+
end
|
171
|
+
end
|
172
|
+
}
|
173
|
+
end
|
174
|
+
|
175
|
+
end
|
176
|
+
|
177
|
+
class UPLVariable
|
178
|
+
def initialize(upl, name, pos, bits)
|
179
|
+
@upl = upl
|
180
|
+
@name = name
|
181
|
+
@pos = pos
|
182
|
+
if bits[0] == '<' then
|
183
|
+
@storage = true
|
184
|
+
@bits = bits[1..].to_i
|
185
|
+
else
|
186
|
+
@storage = false
|
187
|
+
@bits = bits.to_i
|
188
|
+
end
|
189
|
+
@signals = []
|
190
|
+
if @storage then
|
191
|
+
@signals << LocalSignal.new(name: "#{@name}_waddr", width: 32)
|
192
|
+
@signals << LocalSignal.new(name: "#{@name}_we", width: 1)
|
193
|
+
@signals << LocalSignal.new(name: "#{@name}_din", width: @upl.width)
|
194
|
+
@signals << LocalSignal.new(name: "#{@name}_raddr", width: 32)
|
195
|
+
@signals << LocalSignal.new(name: "#{@name}_dout", width: @upl.width)
|
196
|
+
@signals << LocalSignal.new(name: "#{@name}_send_words", width: 32)
|
197
|
+
@signals << LocalSignal.new(name: "#{@name}_recv_words", width: 32)
|
198
|
+
else
|
199
|
+
@signals << LocalSignal.new(name: "#{@name}", width: bits)
|
200
|
+
end
|
201
|
+
end
|
202
|
+
attr_reader :name, :pos, :bits, :upl
|
203
|
+
|
204
|
+
def generate_define(buf)
|
205
|
+
@signals.each{|signal|
|
206
|
+
signal.generate_define(buf)
|
207
|
+
}
|
208
|
+
end
|
209
|
+
|
210
|
+
def storage?()
|
211
|
+
return @storage
|
212
|
+
end
|
213
|
+
|
214
|
+
end
|
215
|
+
|
216
|
+
end
|
data/lib/gupl/version.rb
CHANGED
data/lib/gupl.rb
CHANGED
@@ -1,645 +1,13 @@
|
|
1
1
|
require 'stringio'
|
2
2
|
require "gupl/version"
|
3
|
+
require "gupl/entity"
|
4
|
+
require "gupl/upl"
|
5
|
+
require "gupl/statemachine"
|
6
|
+
require "gupl/process"
|
7
|
+
require "gupl/signal"
|
3
8
|
|
4
9
|
module Gupl
|
5
10
|
|
6
|
-
class LocalSignal
|
7
|
-
|
8
|
-
def initialize(name:, width:)
|
9
|
-
@name = name
|
10
|
-
@width = width.to_i
|
11
|
-
@type = "std_logic_vector"
|
12
|
-
end
|
13
|
-
attr_reader :name, :width
|
14
|
-
|
15
|
-
def generate_define(buf)
|
16
|
-
if @width > 0 then
|
17
|
-
buf.puts(" signal #{@name} : #{@type}(#{@width}-1 downto 0);")
|
18
|
-
else
|
19
|
-
buf.puts(" signal #{@name} : std_logic;")
|
20
|
-
end
|
21
|
-
end
|
22
|
-
|
23
|
-
def set_type(type)
|
24
|
-
@type = type
|
25
|
-
end
|
26
|
-
|
27
|
-
end
|
28
|
-
|
29
|
-
class GenericPort
|
30
|
-
|
31
|
-
def initialize(name:, width:, dir:)
|
32
|
-
@name = name
|
33
|
-
@width = width.to_i
|
34
|
-
@dir = dir
|
35
|
-
end
|
36
|
-
attr_reader :name, :width, :dir
|
37
|
-
|
38
|
-
def generate_define(buf)
|
39
|
-
if @width > 0 then
|
40
|
-
buf.puts(" #{@name} : #{@dir} std_logic_vector(#{@width}-1 downto 0);")
|
41
|
-
else
|
42
|
-
buf.puts(" #{@name} : #{@dir} std_logic;")
|
43
|
-
end
|
44
|
-
end
|
45
|
-
|
46
|
-
end
|
47
|
-
|
48
|
-
class UPLVariable
|
49
|
-
def initialize(upl, name, pos, bits)
|
50
|
-
@upl = upl
|
51
|
-
@name = name
|
52
|
-
@pos = pos
|
53
|
-
if bits[0] == '<' then
|
54
|
-
@storage = true
|
55
|
-
@bits = bits[1..].to_i
|
56
|
-
else
|
57
|
-
@storage = false
|
58
|
-
@bits = bits.to_i
|
59
|
-
end
|
60
|
-
@signals = []
|
61
|
-
if @storage then
|
62
|
-
@signals << LocalSignal.new(name: "#{@name}_waddr", width: 32)
|
63
|
-
@signals << LocalSignal.new(name: "#{@name}_we", width: 1)
|
64
|
-
@signals << LocalSignal.new(name: "#{@name}_din", width: @upl.width)
|
65
|
-
@signals << LocalSignal.new(name: "#{@name}_raddr", width: 32)
|
66
|
-
@signals << LocalSignal.new(name: "#{@name}_dout", width: @upl.width)
|
67
|
-
@signals << LocalSignal.new(name: "#{@name}_send_words", width: 32)
|
68
|
-
@signals << LocalSignal.new(name: "#{@name}_recv_words", width: 32)
|
69
|
-
else
|
70
|
-
@signals << LocalSignal.new(name: "#{@name}", width: bits)
|
71
|
-
end
|
72
|
-
end
|
73
|
-
attr_reader :name, :pos, :bits, :upl
|
74
|
-
|
75
|
-
def generate_define(buf)
|
76
|
-
@signals.each{|signal|
|
77
|
-
signal.generate_define(buf)
|
78
|
-
}
|
79
|
-
end
|
80
|
-
|
81
|
-
def storage?()
|
82
|
-
return @storage
|
83
|
-
end
|
84
|
-
|
85
|
-
end
|
86
|
-
|
87
|
-
class UPL
|
88
|
-
def initialize(entity:, name:, width:, id:)
|
89
|
-
@entity = entity
|
90
|
-
@name = name
|
91
|
-
@width = width.to_i
|
92
|
-
@id = id.to_i
|
93
|
-
@variables = []
|
94
|
-
@variable_ptr = 0
|
95
|
-
@stages = []
|
96
|
-
@storage = nil
|
97
|
-
end
|
98
|
-
attr_reader :id, :name, :width
|
99
|
-
attr_reader :data, :enable, :ack, :request
|
100
|
-
attr_reader :variables, :stages
|
101
|
-
|
102
|
-
def add_variable(name, bits)
|
103
|
-
variable = UPLVariable.new(self, name, @variable_ptr, bits)
|
104
|
-
@variables << variable
|
105
|
-
if (@variable_ptr / @width) > (@stages.size - 1) then
|
106
|
-
@stages << [variable]
|
107
|
-
else
|
108
|
-
@stages[-1] << variable
|
109
|
-
end
|
110
|
-
@variable_ptr += variable.bits
|
111
|
-
if variable.storage?
|
112
|
-
@storage = variable
|
113
|
-
end
|
114
|
-
end
|
115
|
-
|
116
|
-
def generate_ports(buf)
|
117
|
-
buf.puts(" -- #{@name}")
|
118
|
-
@data.generate_define(buf)
|
119
|
-
@enable.generate_define(buf)
|
120
|
-
@request.generate_define(buf)
|
121
|
-
@ack.generate_define(buf)
|
122
|
-
buf.puts("")
|
123
|
-
end
|
124
|
-
|
125
|
-
end
|
126
|
-
|
127
|
-
class RecvUPL < UPL
|
128
|
-
|
129
|
-
def initialize(entity:, name:, width:, id:)
|
130
|
-
super(entity: entity, name: name, width: width, id: id)
|
131
|
-
@data = GenericPort.new(name: "UPL_#{@name}_data", width: @width, dir: "in")
|
132
|
-
@enable = GenericPort.new(name: "UPL_#{@name}_en", width: 0, dir: "in")
|
133
|
-
@request = GenericPort.new(name: "UPL_#{@name}_req", width: 0, dir: "in")
|
134
|
-
@ack = GenericPort.new(name: "UPL_#{@name}_ack", width: 0, dir: "out")
|
135
|
-
end
|
136
|
-
|
137
|
-
def generate_stages(buf)
|
138
|
-
t = " " * 8
|
139
|
-
@stages.each_with_index{|stage, i|
|
140
|
-
buf.puts("#{t}when #{name}_recv_#{i} =>")
|
141
|
-
pos = @width
|
142
|
-
if i == 0 then
|
143
|
-
buf.puts("#{t} if #{enable.name} = '1' then")
|
144
|
-
buf.puts("#{t} #{@ack.name} <= '0';")
|
145
|
-
buf.puts("#{t} else")
|
146
|
-
buf.puts("#{t} #{@ack.name} <= '1';")
|
147
|
-
buf.puts("#{t} end if;")
|
148
|
-
else
|
149
|
-
buf.puts("#{t} #{@ack.name} <= '0';")
|
150
|
-
end
|
151
|
-
stage.each_with_index{|variable|
|
152
|
-
if variable.storage? then
|
153
|
-
buf.puts("#{t} if #{enable.name} = '1' then")
|
154
|
-
buf.puts("#{t} #{variable.name}_waddr <= std_logic_vector(unsigned(#{variable.name}_waddr)+1);")
|
155
|
-
buf.puts("#{t} #{variable.name}_we <= \"1\";")
|
156
|
-
buf.puts("#{t} #{variable.name}_din <= #{@data.name};")
|
157
|
-
buf.puts("#{t} #{variable.name}_recv_words <= std_logic_vector(unsigned(#{variable.name}_recv_words)+1);")
|
158
|
-
buf.puts("#{t} else")
|
159
|
-
buf.puts("#{t} #{variable.name}_we <= \"0\";")
|
160
|
-
buf.puts("#{t} end if;")
|
161
|
-
else
|
162
|
-
buf.puts("#{t} #{variable.name} <= #{@data.name}(#{pos-1} downto #{pos-variable.bits});")
|
163
|
-
pos -= variable.bits
|
164
|
-
end
|
165
|
-
}
|
166
|
-
|
167
|
-
if i == 0 then
|
168
|
-
buf.puts("#{t} if #{enable.name} = '1' then")
|
169
|
-
t += " "
|
170
|
-
end
|
171
|
-
|
172
|
-
buf.puts("#{t} #{@entity.process.statemachine.name} <= #{name}_recv_#{i+1};")
|
173
|
-
|
174
|
-
if i == 0 then
|
175
|
-
t = t[2..]
|
176
|
-
buf.puts("#{t} end if;")
|
177
|
-
end
|
178
|
-
}
|
179
|
-
buf.puts("#{t}when #{name}_recv_#{stages.size} =>")
|
180
|
-
buf.puts("#{t} if #{@enable.name} = '0' then")
|
181
|
-
buf.puts("#{t} #{@entity.process.statemachine.name} <= #{@entity.process.statemachine.name}_next;")
|
182
|
-
if @storage != nil then
|
183
|
-
buf.puts("#{t} #{@storage.name}_we <= \"0\";")
|
184
|
-
buf.puts("#{t} else")
|
185
|
-
buf.puts("#{t} #{@storage.name}_waddr <= std_logic_vector(unsigned(#{@storage.name}_waddr)+1);")
|
186
|
-
buf.puts("#{t} #{@storage.name}_we <= \"1\";")
|
187
|
-
buf.puts("#{t} #{@storage.name}_din <= #{@data.name};")
|
188
|
-
buf.puts("#{t} #{@storage.name}_recv_words <= std_logic_vector(unsigned(#{@storage.name}_recv_words)+1);")
|
189
|
-
end
|
190
|
-
buf.puts("#{t} end if;")
|
191
|
-
end
|
192
|
-
|
193
|
-
end
|
194
|
-
|
195
|
-
class SendUPL < UPL
|
196
|
-
|
197
|
-
def initialize(entity:, name:, width:, id:)
|
198
|
-
super(entity: entity, name: name, width: width, id: id)
|
199
|
-
@data = GenericPort.new(name: "UPL_#{@name}_data", width: @width, dir: "out")
|
200
|
-
@enable = GenericPort.new(name: "UPL_#{@name}_en", width: 0, dir: "out")
|
201
|
-
@request = GenericPort.new(name: "UPL_#{@name}_req", width: 0, dir: "out")
|
202
|
-
@ack = GenericPort.new(name: "UPL_#{@name}_ack", width: 0, dir: "in")
|
203
|
-
end
|
204
|
-
|
205
|
-
def generate_stages(buf)
|
206
|
-
buf.puts(" when #{name}_send_0 =>")
|
207
|
-
buf.puts(" #{@request.name} <= '1';")
|
208
|
-
if @storage != nil then
|
209
|
-
buf.puts(" #{@storage.name}_send_words <= (others => '0');")
|
210
|
-
end
|
211
|
-
buf.puts(" if #{@ack.name} = '1' then")
|
212
|
-
if @storage != nil then
|
213
|
-
buf.puts(" #{@storage.name}_raddr <= (others => '0'); -- for next next")
|
214
|
-
end
|
215
|
-
buf.puts(" #{@entity.process.statemachine.name} <= #{name}_send_1;")
|
216
|
-
buf.puts(" end if;")
|
217
|
-
|
218
|
-
buf.puts(" when #{name}_send_1 =>")
|
219
|
-
buf.puts(" #{@entity.process.statemachine.name} <= #{name}_send_2;")
|
220
|
-
if @storage != nil and @stages[0][0] == @storage then
|
221
|
-
buf.puts(" #{@storage.name}_raddr <= std_logic_vector(unsigned(#{@storage.name}_raddr)+1);")
|
222
|
-
end
|
223
|
-
|
224
|
-
@stages.each_with_index{|stage, i|
|
225
|
-
buf.puts(" when #{name}_send_#{i+2} =>")
|
226
|
-
pos = @width
|
227
|
-
state_trans = false
|
228
|
-
buf.puts(" #{@request.name} <= '0';")
|
229
|
-
stage.each{|variable|
|
230
|
-
if variable.storage? then
|
231
|
-
state_trans = true
|
232
|
-
buf.puts(" if #{variable.name}_recv_words = #{variable.name}_send_words then")
|
233
|
-
buf.puts(" #{@entity.process.statemachine.name} <= #{@entity.process.statemachine.name}_next;")
|
234
|
-
buf.puts(" #{@enable.name} <= '0';")
|
235
|
-
buf.puts(" else")
|
236
|
-
buf.puts(" #{variable.name}_raddr <= std_logic_vector(unsigned(#{variable.name}_raddr)+1); -- for next next")
|
237
|
-
buf.puts(" #{@data.name} <= #{variable.name}_dout;")
|
238
|
-
buf.puts(" #{variable.name}_send_words <= std_logic_vector(unsigned(#{variable.name}_send_words)+1);")
|
239
|
-
buf.puts(" #{@enable.name} <= '1';")
|
240
|
-
buf.puts(" end if;")
|
241
|
-
else
|
242
|
-
buf.puts(" #{@data.name}(#{pos-1} downto #{pos-variable.bits}) <= #{variable.name};")
|
243
|
-
pos -= variable.bits
|
244
|
-
end
|
245
|
-
}
|
246
|
-
if @storage != nil and @stages[i+1] != nil and @stages[i+1][0] == @storage then
|
247
|
-
buf.puts(" #{@storage.name}_raddr <= std_logic_vector(unsigned(#{@storage.name}_raddr)+1); -- for next next")
|
248
|
-
end
|
249
|
-
if state_trans == false
|
250
|
-
buf.puts(" #{@enable.name} <= '1';")
|
251
|
-
if i == stages.size - 1 then
|
252
|
-
buf.puts(" #{@entity.process.statemachine.name} <= #{@entity.process.statemachine.name}_next;")
|
253
|
-
else
|
254
|
-
buf.puts(" #{@entity.process.statemachine.name} <= #{name}_send_#{i+2+1};")
|
255
|
-
end
|
256
|
-
end
|
257
|
-
}
|
258
|
-
end
|
259
|
-
|
260
|
-
end
|
261
|
-
|
262
|
-
class State
|
263
|
-
|
264
|
-
def initialize(statemachine, name)
|
265
|
-
@statemachine = statemachine
|
266
|
-
@name = name
|
267
|
-
@contents = ""
|
268
|
-
end
|
269
|
-
attr_reader :name
|
270
|
-
|
271
|
-
def add_contents(str)
|
272
|
-
@contents += str
|
273
|
-
end
|
274
|
-
|
275
|
-
def generate(buf)
|
276
|
-
if @contents == "" then
|
277
|
-
buf.puts(" pass;")
|
278
|
-
else
|
279
|
-
buf.puts(@contents)
|
280
|
-
end
|
281
|
-
end
|
282
|
-
|
283
|
-
end
|
284
|
-
|
285
|
-
|
286
|
-
class StateMachine
|
287
|
-
|
288
|
-
def initialize(process, name)
|
289
|
-
@process = process
|
290
|
-
@name = name
|
291
|
-
@idle_state = State.new(self, "IDLE")
|
292
|
-
@states = [@idle_state]
|
293
|
-
end
|
294
|
-
attr_reader :name
|
295
|
-
|
296
|
-
def init_storage(buf)
|
297
|
-
table = {}
|
298
|
-
@process.entity.send_upls.each{|upl|
|
299
|
-
upl.variables.each{|var|
|
300
|
-
if var.storage? and table[var.name] == nil then
|
301
|
-
table[var.name] = true
|
302
|
-
buf.puts(" #{var.name}_we <= (others => '0');")
|
303
|
-
buf.puts(" #{var.name}_waddr <= (others => '1');")
|
304
|
-
buf.puts(" #{var.name}_raddr <= (others => '0');")
|
305
|
-
buf.puts(" #{var.name}_recv_words <= (others => '0');")
|
306
|
-
buf.puts(" #{var.name}_send_words <= (others => '0');")
|
307
|
-
end
|
308
|
-
}
|
309
|
-
}
|
310
|
-
@process.entity.recv_upls.each{|upl|
|
311
|
-
upl.variables.each{|var|
|
312
|
-
if var.storage? and table[var.name] == nil then
|
313
|
-
table[var.name] = true
|
314
|
-
buf.puts(" #{var.name}_we <= (others => '0');")
|
315
|
-
buf.puts(" #{var.name}_waddr <= (others => '1');")
|
316
|
-
buf.puts(" #{var.name}_raddr <= (others => '0');")
|
317
|
-
buf.puts(" #{var.name}_recv_words <= (others => '0');")
|
318
|
-
buf.puts(" #{var.name}_send_words <= (others => '0');")
|
319
|
-
end
|
320
|
-
}
|
321
|
-
}
|
322
|
-
end
|
323
|
-
|
324
|
-
def init_idle_state
|
325
|
-
upl = @process.entity.get_main_recv_upl
|
326
|
-
if upl != nil
|
327
|
-
buf = StringIO.new("", "w")
|
328
|
-
buf.puts(" #{name} <= #{upl.name}_recv_0;")
|
329
|
-
buf.puts(" #{name}_next <= #{@process.entity.name};")
|
330
|
-
@process.entity.send_upls.each{|upl|
|
331
|
-
buf.puts(" #{upl.enable.name} <= '0';")
|
332
|
-
buf.puts(" #{upl.request.name} <= '0';")
|
333
|
-
buf.puts(" #{upl.data.name} <= (others => '0');")
|
334
|
-
}
|
335
|
-
@process.entity.recv_upls.each{|upl|
|
336
|
-
buf.puts(" #{upl.ack.name} <= '0';")
|
337
|
-
}
|
338
|
-
init_storage(buf)
|
339
|
-
@idle_state.add_contents(buf.string)
|
340
|
-
end
|
341
|
-
end
|
342
|
-
|
343
|
-
def generate(buf)
|
344
|
-
init_idle_state()
|
345
|
-
buf.puts(" case #{@name} is")
|
346
|
-
@states.each{|state|
|
347
|
-
buf.puts(" when #{state.name} =>")
|
348
|
-
state.generate(buf)
|
349
|
-
}
|
350
|
-
@process.entity.send_upls.each{|upl|
|
351
|
-
upl.generate_stages(buf)
|
352
|
-
}
|
353
|
-
@process.entity.recv_upls.each{|upl|
|
354
|
-
upl.generate_stages(buf)
|
355
|
-
}
|
356
|
-
buf.puts(" when others => #{@name} <= IDLE;")
|
357
|
-
buf.puts(" end case;")
|
358
|
-
end
|
359
|
-
|
360
|
-
def add_idle_stage(str)
|
361
|
-
@idle_state.add_contents(str)
|
362
|
-
end
|
363
|
-
|
364
|
-
def add_new_stage(name)
|
365
|
-
state = State.new(self, name)
|
366
|
-
@states << state
|
367
|
-
return state
|
368
|
-
end
|
369
|
-
|
370
|
-
def generate_define(buf)
|
371
|
-
buf.puts(" -- statemachine type and signal")
|
372
|
-
sep = ""
|
373
|
-
buf.puts(" type StateType is (")
|
374
|
-
@states.each{|state|
|
375
|
-
buf.print("#{sep} #{state.name}")
|
376
|
-
sep = ",\n"
|
377
|
-
}
|
378
|
-
@process.entity.send_upls.each{|upl|
|
379
|
-
(upl.stages.size+2).times{|i|
|
380
|
-
buf.print("#{sep} #{upl.name}_send_#{i}")
|
381
|
-
sep = ",\n"
|
382
|
-
}
|
383
|
-
}
|
384
|
-
@process.entity.recv_upls.each{|upl|
|
385
|
-
(upl.stages.size+1).times{|i|
|
386
|
-
buf.print("#{sep} #{upl.name}_recv_#{i}")
|
387
|
-
sep = ",\n"
|
388
|
-
}
|
389
|
-
}
|
390
|
-
buf.puts("\n );")
|
391
|
-
buf.puts(" signal #{@name} : StateType := IDLE;")
|
392
|
-
buf.puts(" signal #{@name}_next : StateType := IDLE;")
|
393
|
-
end
|
394
|
-
|
395
|
-
end
|
396
|
-
|
397
|
-
|
398
|
-
class MainProcess
|
399
|
-
|
400
|
-
def initialize(entity)
|
401
|
-
@entity = entity
|
402
|
-
@reset_stage = nil
|
403
|
-
@statemachine = StateMachine.new(self, "gupl_state")
|
404
|
-
end
|
405
|
-
attr_reader :entity, :statemachine
|
406
|
-
|
407
|
-
def add_reset_stage(str)
|
408
|
-
@reset_stage = str
|
409
|
-
end
|
410
|
-
|
411
|
-
def add_idle_stage(str)
|
412
|
-
@statemachine.add_idle_stage(str)
|
413
|
-
end
|
414
|
-
|
415
|
-
def add_new_stage(name)
|
416
|
-
@statemachine.add_new_stage(name)
|
417
|
-
end
|
418
|
-
|
419
|
-
def generate_reset(buf)
|
420
|
-
@entity.send_upls.each{|upl|
|
421
|
-
buf.puts(" #{upl.enable.name} <= '0';")
|
422
|
-
buf.puts(" #{upl.request.name} <= '0';")
|
423
|
-
buf.puts(" #{upl.data.name} <= (others => '0');")
|
424
|
-
}
|
425
|
-
@entity.recv_upls.each{|upl|
|
426
|
-
buf.puts(" #{upl.ack.name} <= '0';")
|
427
|
-
}
|
428
|
-
buf.puts(" #{@statemachine.name} <= IDLE;")
|
429
|
-
buf.puts(" #{@entity.process.statemachine.name}_next <= IDLE;")
|
430
|
-
if @reset_stage != nil then
|
431
|
-
buf.puts("")
|
432
|
-
buf.puts(" -- user-defiend reset stage")
|
433
|
-
buf.puts(@reset_stage)
|
434
|
-
buf.puts("")
|
435
|
-
end
|
436
|
-
end
|
437
|
-
|
438
|
-
def generate(buf)
|
439
|
-
buf.puts("process(clk)")
|
440
|
-
buf.puts("begin")
|
441
|
-
buf.puts(" if rising_edge(clk) then")
|
442
|
-
buf.puts(" if reset = '1' then")
|
443
|
-
generate_reset(buf)
|
444
|
-
buf.puts(" else")
|
445
|
-
@statemachine.generate(buf)
|
446
|
-
buf.puts(" end if;")
|
447
|
-
buf.puts(" end if;")
|
448
|
-
buf.puts("end process;")
|
449
|
-
end
|
450
|
-
|
451
|
-
end
|
452
|
-
|
453
|
-
class Entity
|
454
|
-
|
455
|
-
def initialize(name)
|
456
|
-
@name = name
|
457
|
-
@send_upls = []
|
458
|
-
@recv_upls = []
|
459
|
-
@ports = []
|
460
|
-
@signals = []
|
461
|
-
@process = MainProcess.new(self)
|
462
|
-
@async = ""
|
463
|
-
end
|
464
|
-
attr_reader :name, :send_upls, :recv_upls, :process
|
465
|
-
|
466
|
-
def get_main_recv_upl()
|
467
|
-
@recv_upls.each{|upl|
|
468
|
-
return upl if upl.id == 0
|
469
|
-
}
|
470
|
-
return nil
|
471
|
-
end
|
472
|
-
|
473
|
-
def add_send_upl(upl)
|
474
|
-
@send_upls << upl
|
475
|
-
end
|
476
|
-
|
477
|
-
def add_recv_upl(upl)
|
478
|
-
@recv_upls << upl
|
479
|
-
end
|
480
|
-
|
481
|
-
def add_port(port)
|
482
|
-
@ports << port
|
483
|
-
end
|
484
|
-
|
485
|
-
def add_signal(signal)
|
486
|
-
@signals << signal
|
487
|
-
end
|
488
|
-
|
489
|
-
def add_reset_stage(str)
|
490
|
-
@process.add_reset_stage(str)
|
491
|
-
end
|
492
|
-
|
493
|
-
def add_idle_stage(str)
|
494
|
-
@process.add_idle_stage(str)
|
495
|
-
end
|
496
|
-
|
497
|
-
def add_new_stage(name)
|
498
|
-
@process.add_new_stage(name)
|
499
|
-
end
|
500
|
-
|
501
|
-
def add_async(str)
|
502
|
-
@async += str
|
503
|
-
end
|
504
|
-
|
505
|
-
def generate_vhdl_header(buf)
|
506
|
-
buf.puts("library ieee;")
|
507
|
-
buf.puts("use ieee.std_logic_1164.all;")
|
508
|
-
buf.puts("use ieee.numeric_std.all;")
|
509
|
-
buf.puts("")
|
510
|
-
end
|
511
|
-
|
512
|
-
def generate_entity_define(buf)
|
513
|
-
buf.puts("entity #{@name} is")
|
514
|
-
buf.puts("port(")
|
515
|
-
|
516
|
-
@recv_upls.each{|upl|
|
517
|
-
upl.generate_ports(buf)
|
518
|
-
}
|
519
|
-
|
520
|
-
@send_upls.each{|upl|
|
521
|
-
upl.generate_ports(buf)
|
522
|
-
}
|
523
|
-
|
524
|
-
buf.puts(" -- user-defiend ports")
|
525
|
-
@ports.each{|port|
|
526
|
-
port.generate_define(buf)
|
527
|
-
}
|
528
|
-
buf.puts("")
|
529
|
-
|
530
|
-
buf.puts(" -- system clock and reset")
|
531
|
-
buf.puts(" clk : in std_logic;")
|
532
|
-
buf.puts(" reset : in std_logic")
|
533
|
-
buf.puts(");")
|
534
|
-
buf.puts("end entity #{@name};")
|
535
|
-
buf.puts("")
|
536
|
-
end
|
537
|
-
|
538
|
-
def generate_architecture_define(buf)
|
539
|
-
buf.puts("architecture RTL of #{@name} is")
|
540
|
-
buf.puts("")
|
541
|
-
|
542
|
-
@process.statemachine.generate_define(buf)
|
543
|
-
|
544
|
-
buf.puts()
|
545
|
-
buf.puts(" -- UPL signals")
|
546
|
-
table = {}
|
547
|
-
@send_upls.each{|upl|
|
548
|
-
upl.variables.each{|var|
|
549
|
-
next if table[var.name] != nil
|
550
|
-
table[var.name] = var
|
551
|
-
var.generate_define(buf)
|
552
|
-
}
|
553
|
-
}
|
554
|
-
@recv_upls.each{|upl|
|
555
|
-
upl.variables.each{|var|
|
556
|
-
next if table[var.name] != nil
|
557
|
-
table[var.name] = var
|
558
|
-
var.generate_define(buf)
|
559
|
-
}
|
560
|
-
}
|
561
|
-
|
562
|
-
buf.puts()
|
563
|
-
buf.puts(" -- user-defiend signals")
|
564
|
-
@signals.each{|signal|
|
565
|
-
signal.generate_define(buf)
|
566
|
-
}
|
567
|
-
buf.puts("")
|
568
|
-
|
569
|
-
buf.puts(" -- ip-cores")
|
570
|
-
simple_dualportram = false
|
571
|
-
table.values.each{|var|
|
572
|
-
if var.storage? and simple_dualportram == false then
|
573
|
-
simple_dualportram = true
|
574
|
-
buf.puts(" component simple_dualportram")
|
575
|
-
buf.puts(" generic (")
|
576
|
-
buf.puts(" DEPTH : integer := 10;")
|
577
|
-
buf.puts(" WIDTH : integer := 32;")
|
578
|
-
buf.puts(" WORDS : integer := 1024")
|
579
|
-
buf.puts(" );")
|
580
|
-
buf.puts(" port (")
|
581
|
-
buf.puts(" clk : in std_logic;")
|
582
|
-
buf.puts(" reset : in std_logic;")
|
583
|
-
buf.puts(" we : in std_logic_vector(0 downto 0);")
|
584
|
-
buf.puts(" raddr : in std_logic_vector(31 downto 0);")
|
585
|
-
buf.puts(" waddr : in std_logic_vector(31 downto 0);")
|
586
|
-
buf.puts(" dout : out std_logic_vector(WIDTH-1 downto 0);")
|
587
|
-
buf.puts(" din : in std_logic_vector(WIDTH-1 downto 0);")
|
588
|
-
buf.puts(" length : out std_logic_vector(31 downto 0)")
|
589
|
-
buf.puts(" );")
|
590
|
-
buf.puts(" end component simple_dualportram;")
|
591
|
-
end
|
592
|
-
}
|
593
|
-
buf.puts("")
|
594
|
-
|
595
|
-
buf.puts("begin")
|
596
|
-
buf.puts("")
|
597
|
-
buf.puts(" -- add async")
|
598
|
-
buf.puts(@async)
|
599
|
-
|
600
|
-
buf.puts("")
|
601
|
-
@process.generate(buf)
|
602
|
-
buf.puts("")
|
603
|
-
|
604
|
-
buf.puts("")
|
605
|
-
table.values.each{|var|
|
606
|
-
if var.storage? then
|
607
|
-
buf.puts(" buf_#{var.name}_i : simple_dualportram")
|
608
|
-
buf.puts(" generic map(")
|
609
|
-
buf.puts(" DEPTH => #{Math.log2((var.bits/var.upl.width).ceil).ceil},")
|
610
|
-
buf.puts(" WIDTH => #{var.upl.width},")
|
611
|
-
buf.puts(" WORDS => #{(var.bits/var.upl.width).ceil}")
|
612
|
-
buf.puts(" )")
|
613
|
-
buf.puts(" port map(")
|
614
|
-
buf.puts(" clk => clk,")
|
615
|
-
buf.puts(" reset => reset,")
|
616
|
-
buf.puts(" we => #{var.name}_we,")
|
617
|
-
buf.puts(" raddr => #{var.name}_raddr,")
|
618
|
-
buf.puts(" waddr => #{var.name}_waddr,")
|
619
|
-
buf.puts(" dout => #{var.name}_dout,")
|
620
|
-
buf.puts(" din => #{var.name}_din,")
|
621
|
-
buf.puts(" length => open")
|
622
|
-
buf.puts(" );")
|
623
|
-
end
|
624
|
-
}
|
625
|
-
|
626
|
-
|
627
|
-
buf.puts("end RTL;")
|
628
|
-
end
|
629
|
-
|
630
|
-
def generate(buf)
|
631
|
-
buf.puts("--")
|
632
|
-
buf.puts("-- generated by gupl ver.#{VERSION}")
|
633
|
-
buf.puts("-- https://github.com/e-trees/gupl")
|
634
|
-
buf.puts("--")
|
635
|
-
buf.puts("")
|
636
|
-
generate_vhdl_header(buf)
|
637
|
-
generate_entity_define(buf)
|
638
|
-
generate_architecture_define(buf)
|
639
|
-
end
|
640
|
-
|
641
|
-
end
|
642
|
-
|
643
11
|
def self.parse_ports(reader, entity)
|
644
12
|
|
645
13
|
while line = reader.gets
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: gupl
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.0.
|
4
|
+
version: 0.0.3
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Takefumi MIYOSHI
|
8
8
|
autorequire:
|
9
9
|
bindir: exe
|
10
10
|
cert_chain: []
|
11
|
-
date: 2022-06-
|
11
|
+
date: 2022-06-06 00:00:00.000000000 Z
|
12
12
|
dependencies: []
|
13
13
|
description: gupl makes UPL modules, which is a VHDL generator.
|
14
14
|
email:
|
@@ -32,11 +32,17 @@ files:
|
|
32
32
|
- exe/gupl
|
33
33
|
- gupl.gemspec
|
34
34
|
- lib/gupl.rb
|
35
|
+
- lib/gupl/entity.rb
|
36
|
+
- lib/gupl/process.rb
|
37
|
+
- lib/gupl/signal.rb
|
38
|
+
- lib/gupl/statemachine.rb
|
39
|
+
- lib/gupl/upl.rb
|
35
40
|
- lib/gupl/version.rb
|
36
41
|
- sig/gupl.rbs
|
37
42
|
- vhdl_lib/simple_dualportram.vhd
|
38
43
|
homepage: https://github.com/e-trees/gupl
|
39
|
-
licenses:
|
44
|
+
licenses:
|
45
|
+
- Apache-2.0
|
40
46
|
metadata:
|
41
47
|
allowed_push_host: https://rubygems.org
|
42
48
|
homepage_uri: https://github.com/e-trees/gupl
|