github-linguist 5.3.3 → 6.0.0

data/grammars/source.systemverilog.json

@@ -1,29 +1,10 @@
 {
-  "fileTypes": [
-    "sv",
-    "SV",
-    "v",
-    "V",
-    "svh",
-    "SVH",
-    "vh",
-    "VH"
-  ],
-  "hidden": true,
-  "foldingStartMarker": "(begin)\\s*(//.*)?$",
-  "foldingStopMarker": "^\\s*(begin)$",
   "name": "SystemVerilog",
+  "scopeName": "source.systemverilog",
   "patterns": [
     {
+      "name": "meta.function.systemverilog",
       "begin": "\\s*\\b(function|task)\\b(\\s+automatic)?",
-      "beginCaptures": {
-        "1": {
-          "name": "keyword.control.systemverilog"
-        },
-        "2": {
-          "name": "keyword.control.systemverilog"
-        }
-      },
       "end": ";",
       "patterns": [
         {
@@ -44,9 +25,17 @@
           "include": "#base-grammar"
         }
       ],
-      "name": "meta.function.systemverilog"
+      "beginCaptures": {
+        "1": {
+          "name": "keyword.control.systemverilog"
+        },
+        "2": {
+          "name": "keyword.control.systemverilog"
+        }
+      }
     },
     {
+      "name": "meta.task.simple.systemverilog",
       "match": "\\s*\\b(task)\\s+(automatic)?\\s*(\\w+)\\s*;",
       "captures": {
         "1": {
@@ -58,11 +47,20 @@
         "3": {
           "name": "entity.name.function.systemverilog"
         }
-      },
-      "name": "meta.task.simple.systemverilog"
+      }
     },
     {
+      "name": "meta.typedef.struct.systemverilog",
       "begin": "\\s*\\b(typedef\\s+(struct|enum|union)\\b)\\s*(packed)?\\s*([a-zA-Z_][a-zA-Z0-9_]*)?",
+      "end": "(})\\s*([a-zA-Z_][a-zA-Z0-9_]*)\\s*;",
+      "patterns": [
+        {
+          "include": "#struct-anonymous"
+        },
+        {
+          "include": "#base-grammar"
+        }
+      ],
       "beginCaptures": {
         "1": {
           "name": "keyword.control.systemverilog"
@@ -77,7 +75,6 @@
           "name": "storage.type.systemverilog"
         }
       },
-      "end": "(})\\s*([a-zA-Z_][a-zA-Z0-9_]*)\\s*;",
       "endCaptures": {
         "1": {
           "name": "keyword.operator.other.systemverilog"
@@ -85,18 +82,10 @@
         "2": {
           "name": "entity.name.function.systemverilog"
         }
-      },
-      "patterns": [
-        {
-          "include": "#struct-anonymous"
-        },
-        {
-          "include": "#base-grammar"
-        }
-      ],
-      "name": "meta.typedef.struct.systemverilog"
+      }
     },
     {
+      "name": "meta.typedef.class.systemverilog",
       "match": "\\s*\\b(typedef\\s+class)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\s*;",
       "captures": {
         "1": {
@@ -105,24 +94,15 @@
         "2": {
           "name": "entity.name.declaration.systemverilog"
         }
-      },
-      "name": "meta.typedef.class.systemverilog"
+      }
     },
     {
+      "name": "meta.typedef.simple.systemverilog",
       "begin": "\\s*\\b(typedef)\\b",
-      "beginCaptures": {
-        "1": {
-          "name": "keyword.control.systemverilog"
-        }
-      },
       "end": "([a-zA-Z_][a-zA-Z0-9_]*)\\s*(?=(\\[[a-zA-Z0-9_:\\$\\-\\+]*\\])?;)",
-      "endCaptures": {
-        "1": {
-          "name": "entity.name.function.systemverilog"
-        }
-      },
       "patterns": [
         {
+          "name": "meta.typedef.class.systemverilog",
           "match": "\\b([a-zA-Z_]\\w*)\\s*(#)\\(",
           "captures": {
             "1": {
@@ -131,8 +111,7 @@
             "2": {
               "name": "keyword.operator.param.systemverilog"
             }
-          },
-          "name": "meta.typedef.class.systemverilog"
+          }
         },
         {
           "include": "#base-grammar"
@@ -141,31 +120,28 @@
           "include": "#module-binding"
         }
       ],
-      "name": "meta.typedef.simple.systemverilog"
-    },
-    {
-      "begin": "\\s*(module)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
       "beginCaptures": {
         "1": {
           "name": "keyword.control.systemverilog"
-        },
-        "2": {
-          "name": "entity.name.type.module.systemverilog"
         }
       },
-      "end": ";",
       "endCaptures": {
         "1": {
           "name": "entity.name.function.systemverilog"
         }
-      },
+      }
+    },
+    {
+      "name": "meta.module.systemverilog",
+      "begin": "\\s*(module)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
+      "end": ";",
       "patterns": [
         {
           "include": "#port-dir"
         },
         {
-          "match": "\\s*(parameter)",
-          "name": "keyword.other.systemverilog"
+          "name": "keyword.other.systemverilog",
+          "match": "\\s*(parameter)"
         },
         {
           "include": "#base-grammar"
@@ -174,9 +150,23 @@
           "include": "#ifmodport"
         }
       ],
-      "name": "meta.module.systemverilog"
+      "beginCaptures": {
+        "1": {
+          "name": "keyword.control.systemverilog"
+        },
+        "2": {
+          "name": "entity.name.type.module.systemverilog"
+        }
+      },
+      "endCaptures": {
+        "1": {
+          "name": "entity.name.function.systemverilog"
+        }
+      }
     },
     {
+      "name": "meta.sequence.systemverilog",
+      "match": "\\b(sequence)\\s+([a-zA-Z_][a-zA-Z0-9_]*)",
       "captures": {
         "1": {
           "name": "keyword.control.systemverilog"
@@ -184,9 +174,7 @@
         "2": {
           "name": "entity.name.function.systemverilog"
         }
-      },
-      "match": "\\b(sequence)\\s+([a-zA-Z_][a-zA-Z0-9_]*)",
-      "name": "meta.sequence.systemverilog"
+      }
     },
     {
       "match": "\\b(bind)\\s+([a-zA-Z_][a-zA-Z0-9_\\.]*)\\b",
@@ -197,6 +185,8 @@
       }
     },
     {
+      "name": "meta.definition.systemverilog",
+      "match": "\\s*(begin|fork)\\s*((:)\\s*([a-zA-Z_][a-zA-Z0-9_]*))\\b",
       "captures": {
         "0": {
           "name": "meta.section.begin.systemverilog"
@@ -210,9 +200,7 @@
         "4": {
           "name": "entity.name.section.systemverilog"
         }
-      },
-      "match": "\\s*(begin|fork)\\s*((:)\\s*([a-zA-Z_][a-zA-Z0-9_]*))\\b",
-      "name": "meta.definition.systemverilog"
+      }
     },
     {
       "match": "\\b(property)\\s+(\\w+)",
@@ -240,32 +228,13 @@
       }
     },
     {
+      "name": "meta.psl.systemverilog",
       "begin": "\\s*(//)\\s*(psl)\\s+((\\w+)\\s*(:))?\\s*(default|assert|assume)",
-      "beginCaptures": {
-        "0": {
-          "name": "meta.psl.systemverilog"
-        },
-        "1": {
-          "name": "comment.line.double-slash.systemverilog"
-        },
-        "2": {
-          "name": "keyword.psl.systemverilog"
-        },
-        "4": {
-          "name": "entity.psl.name.systemverilog"
-        },
-        "5": {
-          "name": "keyword.operator.systemverilog"
-        },
-        "6": {
-          "name": "keyword.psl.systemverilog"
-        }
-      },
       "end": ";",
       "patterns": [
         {
-          "match": "\\b(never|always|default|clock|within|rose|fell|stable|until|before|next|eventually|abort|posedge)\\b",
-          "name": "keyword.psl.systemverilog"
+          "name": "keyword.psl.systemverilog",
+          "match": "\\b(never|always|default|clock|within|rose|fell|stable|until|before|next|eventually|abort|posedge)\\b"
         },
         {
           "include": "#operators"
@@ -277,27 +246,31 @@
           "include": "#constants"
         }
       ],
-      "name": "meta.psl.systemverilog"
-    },
-    {
-      "begin": "\\s*(/\\*)\\s*(psl)",
       "beginCaptures": {
         "0": {
           "name": "meta.psl.systemverilog"
         },
         "1": {
-          "name": "comment.block.systemverilog"
+          "name": "comment.line.double-slash.systemverilog"
         },
         "2": {
           "name": "keyword.psl.systemverilog"
+        },
+        "4": {
+          "name": "entity.psl.name.systemverilog"
+        },
+        "5": {
+          "name": "keyword.operator.systemverilog"
+        },
+        "6": {
+          "name": "keyword.psl.systemverilog"
         }
-      },
+      }
+    },
+    {
+      "name": "meta.psl.systemverilog",
+      "begin": "\\s*(/\\*)\\s*(psl)",
       "end": "(\\*/)",
-      "endCaptures": {
-        "1": {
-          "name": "comment.block.systemverilog"
-        }
-      },
       "patterns": [
         {
           "match": "^\\s*((\\w+)\\s*(:))?\\s*(default|assert|assume)",
@@ -328,8 +301,8 @@
           }
         },
         {
-          "match": "\\b(never|always|default|clock|within|rose|fell|stable|until|before|next|eventually|abort|posedge|negedge)\\b",
-          "name": "keyword.psl.systemverilog"
+          "name": "keyword.psl.systemverilog",
+          "match": "\\b(never|always|default|clock|within|rose|fell|stable|until|before|next|eventually|abort|posedge|negedge)\\b"
         },
         {
           "include": "#operators"
@@ -341,7 +314,22 @@
           "include": "#constants"
         }
       ],
-      "name": "meta.psl.systemverilog"
+      "beginCaptures": {
+        "0": {
+          "name": "meta.psl.systemverilog"
+        },
+        "1": {
+          "name": "comment.block.systemverilog"
+        },
+        "2": {
+          "name": "keyword.psl.systemverilog"
+        }
+      },
+      "endCaptures": {
+        "1": {
+          "name": "comment.block.systemverilog"
+        }
+      }
     },
     {
       "match": "\\s*\\b(automatic|cell|config|deassign|defparam|design|disable|edge|endconfig|endgenerate|endspecify|endtable|event|generate|genvar|ifnone|incdir|instance|liblist|library|macromodule|negedge|noshowcancelled|posedge|pulsestyle_onevent|pulsestyle_ondetect|scalared|showcancelled|specify|specparam|table|use|vectored)\\b",
@@ -360,6 +348,7 @@
       }
     },
     {
+      "name": "meta.object.end.systemverilog",
       "match": "\\s*\\b(end|endtask|endmodule|endfunction|endprimitive|endclass|endpackage|endsequence|endprogram|endclocking|endproperty|endgroup|endinterface|join|join_any|join_none)\\b(\\s*(:)\\s*(\\w+))?",
       "captures": {
         "1": {
@@ -371,14 +360,15 @@
         "4": {
           "name": "entity.label.systemverilog"
         }
-      },
-      "name": "meta.object.end.systemverilog"
+      }
     },
     {
-      "match": "\\b(std)\\b::",
-      "name": "support.class.systemverilog"
+      "name": "support.class.systemverilog",
+      "match": "\\b(std)\\b::"
     },
     {
+      "name": "meta.define.systemverilog",
+      "match": "^\\s*(`define)\\s+([a-zA-Z_][a-zA-Z0-9_]*)",
       "captures": {
         "1": {
           "name": "constant.other.define.systemverilog"
@@ -386,14 +376,14 @@
         "2": {
           "name": "entity.name.type.define.systemverilog"
         }
-      },
-      "match": "^\\s*(`define)\\s+([a-zA-Z_][a-zA-Z0-9_]*)",
-      "name": "meta.define.systemverilog"
+      }
     },
     {
       "include": "#comments"
     },
     {
+      "name": "meta.definition.systemverilog",
+      "match": "\\s*(primitive|package|constraint|interface|covergroup|program)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
       "captures": {
         "1": {
           "name": "keyword.control.systemverilog"
@@ -401,11 +391,11 @@
         "2": {
           "name": "entity.name.type.class.systemverilog"
         }
-      },
-      "match": "\\s*(primitive|package|constraint|interface|covergroup|program)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
-      "name": "meta.definition.systemverilog"
+      }
     },
     {
+      "name": "meta.definition.systemverilog",
+      "match": "(([a-zA-Z_][a-zA-Z0-9_]*)\\s*(:))?\\s*(coverpoint|cross)\\s+([a-zA-Z_][a-zA-Z0-9_]*)",
       "captures": {
         "2": {
           "name": "entity.name.type.class.systemverilog"
@@ -416,11 +406,11 @@
         "4": {
           "name": "keyword.control.systemverilog"
         }
-      },
-      "match": "(([a-zA-Z_][a-zA-Z0-9_]*)\\s*(:))?\\s*(coverpoint|cross)\\s+([a-zA-Z_][a-zA-Z0-9_]*)",
-      "name": "meta.definition.systemverilog"
+      }
     },
     {
+      "name": "meta.definition.class.systemverilog",
+      "match": "\\b(virtual\\s+)?(class)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
       "captures": {
         "1": {
           "name": "keyword.control.systemverilog"
@@ -431,11 +421,11 @@
         "3": {
           "name": "entity.name.type.class.systemverilog"
         }
-      },
-      "match": "\\b(virtual\\s+)?(class)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
-      "name": "meta.definition.class.systemverilog"
+      }
     },
     {
+      "name": "meta.definition.systemverilog",
+      "match": "\\b(extends)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\b",
       "captures": {
         "1": {
           "name": "keyword.control.systemverilog"
@@ -443,9 +433,7 @@
         "2": {
           "name": "entity.other.inherited-class.systemverilog"
         }
-      },
-      "match": "\\b(extends)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\b",
-      "name": "meta.definition.systemverilog"
+      }
     },
     {
       "include": "#all-types"
@@ -457,19 +445,19 @@
       "include": "#port-dir"
     },
     {
-      "match": "\\b(and|nand|nor|or|xor|xnor|buf|not|bufif[01]|notif[01]|r?[npc]mos|tran|r?tranif[01]|pullup|pulldown)\\b",
-      "name": "support.type.systemverilog"
+      "name": "support.type.systemverilog",
+      "match": "\\b(and|nand|nor|or|xor|xnor|buf|not|bufif[01]|notif[01]|r?[npc]mos|tran|r?tranif[01]|pullup|pulldown)\\b"
     },
     {
       "include": "#strings"
     },
     {
-      "match": "\\$\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
-      "name": "support.function.systemverilog"
+      "name": "support.function.systemverilog",
+      "match": "\\$\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b"
     },
     {
-      "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*)(')(?=\\()",
       "name": "meta.cast.systemverilog",
+      "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*)(')(?=\\()",
       "captures": {
         "1": {
           "name": "storage.type.systemverilog"
@@ -480,8 +468,8 @@
       }
     },
     {
-      "match": "^\\s*(localparam|parameter)\\s+([A-Z_][A-Z0-9_]*)\\b\\s*(?=(=))",
       "name": "meta.param.systemverilog",
+      "match": "^\\s*(localparam|parameter)\\s+([A-Z_][A-Z0-9_]*)\\b\\s*(?=(=))",
       "captures": {
         "1": {
           "name": "keyword.other.systemverilog"
@@ -492,8 +480,8 @@
       }
     },
     {
-      "match": "^\\s*(localparam|parameter)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\b\\s*(?=(=))",
       "name": "meta.param.systemverilog",
+      "match": "^\\s*(localparam|parameter)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\b\\s*(?=(=))",
       "captures": {
         "1": {
           "name": "keyword.other.systemverilog"
@@ -501,8 +489,8 @@
       }
     },
     {
-      "match": "^\\s*(local\\s+|protected\\s+|localparam\\s+|parameter\\s+)?(const\\s+|virtual\\s+)?(rand\\s+|randc\\s+)?(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)\\b\\s*(?=(#\\s*\\([\\w,]+\\)\\s*)?([a-zA-Z][a-zA-Z0-9_\\s\\[\\]']*)(;|,|=|'\\{))",
       "name": "meta.userdefined.systemverilog",
+      "match": "^\\s*(local\\s+|protected\\s+|localparam\\s+|parameter\\s+)?(const\\s+|virtual\\s+)?(rand\\s+|randc\\s+)?(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)\\b\\s*(?=(#\\s*\\([\\w,]+\\)\\s*)?([a-zA-Z][a-zA-Z0-9_\\s\\[\\]']*)(;|,|=|'\\{))",
       "captures": {
         "1": {
           "name": "keyword.other.systemverilog"
@@ -541,19 +529,12 @@
       }
     },
     {
-      "match": "\\s*\\b(rand|randc)\\b",
-      "name": "storage.type.rand.systemverilog"
+      "name": "storage.type.rand.systemverilog",
+      "match": "\\s*\\b(rand|randc)\\b"
     },
     {
+      "name": "meta.module.inst.param.systemverilog",
       "begin": "^(\\s*(bind)\\s+([a-zA-Z_][\\w\\.]*))?\\s*([a-zA-Z_][a-zA-Z0-9_]*)\\s*(?=#[^#])",
-      "beginCaptures": {
-        "2": {
-          "name": "keyword.control.systemverilog"
-        },
-        "4": {
-          "name": "storage.module.systemverilog"
-        }
-      },
       "end": "(?=;|=|:)",
       "patterns": [
         {
@@ -575,28 +556,22 @@
           "include": "#strings"
         },
         {
-          "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b(?=\\s*(\\(|$))",
-          "name": "entity.name.type.module.systemverilog"
+          "name": "entity.name.type.module.systemverilog",
+          "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b(?=\\s*(\\(|$))"
         }
       ],
-      "name": "meta.module.inst.param.systemverilog"
-    },
-    {
-      "begin": "\\b([a-zA-Z_][a-zA-Z0-9_]*)\\s+(?!intersect|and|or|throughout|within)([a-zA-Z_][a-zA-Z0-9_]*)\\s*(\\[(\\d+)(\\:(\\d+))?\\])?\\s*(\\(|$)",
       "beginCaptures": {
-        "1": {
-          "name": "storage.module.systemverilog"
-        },
         "2": {
-          "name": "entity.name.type.module.systemverilog"
+          "name": "keyword.control.systemverilog"
         },
         "4": {
-          "name": "constant.numeric.systemverilog"
-        },
-        "6": {
-          "name": "constant.numeric.systemverilog"
+          "name": "storage.module.systemverilog"
         }
-      },
+      }
+    },
+    {
+      "name": "meta.module.inst.systemverilog",
+      "begin": "\\b([a-zA-Z_][a-zA-Z0-9_]*)\\s+(?!intersect|and|or|throughout|within)([a-zA-Z_][a-zA-Z0-9_]*)\\s*(\\[(\\d+)(\\:(\\d+))?\\])?\\s*(\\(|$)",
       "end": ";",
       "patterns": [
         {
@@ -615,22 +590,24 @@
           "include": "#constants"
         }
       ],
-      "name": "meta.module.inst.systemverilog"
-    },
-    {
-      "name": "meta.struct.assign.systemverilog",
-      "begin": "\\b\\s+(<?=)\\s*(\\'{)",
       "beginCaptures": {
         "1": {
-          "name": "keyword.operator.other.systemverilog"
+          "name": "storage.module.systemverilog"
         },
         "2": {
-          "name": "keyword.operator.other.systemverilog"
+          "name": "entity.name.type.module.systemverilog"
         },
-        "3": {
-          "name": "keyword.operator.other.systemverilog"
+        "4": {
+          "name": "constant.numeric.systemverilog"
+        },
+        "6": {
+          "name": "constant.numeric.systemverilog"
         }
-      },
+      }
+    },
+    {
+      "name": "meta.struct.assign.systemverilog",
+      "begin": "\\b\\s+(\u003c?=)\\s*(\\'{)",
       "end": ";",
       "patterns": [
         {
@@ -659,7 +636,18 @@
         {
           "include": "#storage-scope-systemverilog"
         }
-      ]
+      ],
+      "beginCaptures": {
+        "1": {
+          "name": "keyword.operator.other.systemverilog"
+        },
+        "2": {
+          "name": "keyword.operator.other.systemverilog"
+        },
+        "3": {
+          "name": "keyword.operator.other.systemverilog"
+        }
+      }
     },
     {
       "include": "#storage-scope-systemverilog"
@@ -672,10 +660,6 @@
     }
   ],
   "repository": {
-    "functions": {
-      "match": "\\b(\\w+)(?=\\s*\\()",
-      "name": "support.function.generic.systemverilog"
-    },
     "all-types": {
       "patterns": [
         {
@@ -686,203 +670,113 @@
         }
       ]
     },
-    "constants": {
+    "base-grammar": {
       "patterns": [
         {
-          "match": "(\\b\\d+)?'(s?[bB]\\s*[0-1xXzZ?][0-1_xXzZ?]*|s?[oO]\\s*[0-7xXzZ?][0-7_xXzZ?]*|s?[dD]\\s*[0-9xXzZ?][0-9_xXzZ?]*|s?[hH]\\s*[0-9a-fA-FxXzZ?][0-9a-fA-F_xXzZ?]*)((e|E)(\\+|-)?[0-9]+)?(?!'|\\w)",
-          "name": "constant.numeric.systemverilog"
-        },
-        {
-          "match": "'[01xXzZ]",
-          "name": "constant.numeric.bit.systemverilog"
+          "include": "#all-types"
         },
         {
-          "match": "\\b((\\d[\\d_]*)(e|E)(\\+|-)?[0-9]+)\\b",
-          "name": "constant.numeric.exp.systemverilog"
+          "include": "#comments"
         },
         {
-          "match": "\\b(\\d[\\d_]*)\\b",
-          "name": "constant.numeric.decimal.systemverilog"
+          "include": "#operators"
         },
         {
-          "match": "\\b(\\d+(fs|ps|ns|us|ms|s)?)\\b",
-          "name": "constant.numeric.time.systemverilog"
+          "include": "#constants"
         },
         {
-          "match": "\\b([A-Z][A-Z0-9_]*)\\b",
-          "name": "constant.other.net.systemverilog"
+          "include": "#strings"
         },
         {
-          "match": "(`ifdef|`ifndef|`default_nettype)\\s+(\\w+)",
+          "match": "^\\s*([a-zA-Z_][a-zA-Z0-9_]*)\\s+[a-zA-Z_][a-zA-Z0-9_,=\\s]*",
           "captures": {
             "1": {
-              "name": "constant.other.preprocessor.systemverilog"
-            },
-            "2": {
-              "name": "support.variable.systemverilog"
+              "name": "storage.type.interface.systemverilog"
             }
           }
         },
         {
-          "match": "`(celldefine|else|elsif|endcelldefine|endif|include|line|nounconnected_drive|resetall|timescale|unconnected_drive|undef|begin_\\w+|end_\\w+|remove_\\w+|restore_\\w+)\\b",
-          "name": "constant.other.preprocessor.systemverilog"
-        },
-        {
-          "match": "`\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
-          "name": "constant.other.define.systemverilog"
-        },
-        {
-          "match": "\\b(null)\\b",
-          "name": "support.constant.systemverilog"
-        }
-      ]
-    },
-    "operators": {
-      "patterns": [
-        {
-          "match": "(=|==|===|!=|!==|<=|>=|<|>)",
-          "name": "keyword.operator.comparison.systemverilog"
-        },
-        {
-          "match": "(\\-|\\+|\\*|\\/|%)",
-          "name": "keyword.operator.arithmetic.systemverilog"
-        },
-        {
-          "match": "(!|&&|\\|\\||\\bor\\b)",
-          "name": "keyword.operator.logical.systemverilog"
-        },
-        {
-          "match": "(&|\\||\\^|~|{|'{|}|<<|>>|\\?|:)",
-          "name": "keyword.operator.bitwise.systemverilog"
-        },
-        {
-          "match": "(#|@)",
-          "name": "keyword.operator.other.systemverilog"
+          "include": "#storage-scope-systemverilog"
         }
       ]
     },
     "comments": {
       "patterns": [
         {
+          "name": "comment.block.systemverilog",
           "begin": "/\\*",
+          "end": "\\*/",
           "captures": {
             "0": {
               "name": "punctuation.definition.comment.systemverilog"
             }
-          },
-          "end": "\\*/",
-          "name": "comment.block.systemverilog"
+          }
         },
         {
+          "name": "comment.line.double-slash.systemverilog",
+          "match": "(//).*$\\n?",
           "captures": {
             "1": {
               "name": "punctuation.definition.comment.systemverilog"
             }
-          },
-          "match": "(//).*$\\n?",
-          "name": "comment.line.double-slash.systemverilog"
+          }
         }
       ]
     },
-    "port-dir": {
+    "constants": {
       "patterns": [
         {
-          "match": "\\s*\\b(output|input|inout|ref)\\s+(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)?\\s+(?=\\[[a-zA-Z0-9_\\-\\+]*:[a-zA-Z0-9_\\-\\+]*\\]\\s+[a-zA-Z_][a-zA-Z0-9_\\s]*)",
-          "captures": {
-            "1": {
-              "name": "support.type.systemverilog"
-            },
-            "3": {
-              "name": "support.type.scope.systemverilog"
-            },
-            "4": {
-              "name": "keyword.operator.scope.systemverilog"
-            },
-            "5": {
-              "name": "storage.type.interface.systemverilog"
-            }
-          }
+          "name": "constant.numeric.systemverilog",
+          "match": "(\\b\\d+)?'(s?[bB]\\s*[0-1xXzZ?][0-1_xXzZ?]*|s?[oO]\\s*[0-7xXzZ?][0-7_xXzZ?]*|s?[dD]\\s*[0-9xXzZ?][0-9_xXzZ?]*|s?[hH]\\s*[0-9a-fA-FxXzZ?][0-9a-fA-F_xXzZ?]*)((e|E)(\\+|-)?[0-9]+)?(?!'|\\w)"
         },
         {
-          "match": "\\s*\\b(output|input|inout|ref)\\s+(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)?\\s+(?=[a-zA-Z_][a-zA-Z0-9_\\s]*)",
-          "captures": {
-            "1": {
-              "name": "support.type.systemverilog"
-            },
-            "3": {
-              "name": "support.type.scope.systemverilog"
-            },
-            "4": {
-              "name": "keyword.operator.scope.systemverilog"
-            },
-            "5": {
-              "name": "storage.type.interface.systemverilog"
-            }
-          }
+          "name": "constant.numeric.bit.systemverilog",
+          "match": "'[01xXzZ]"
         },
         {
-          "match": "\\s*\\b(output|input|inout|ref)\\b",
-          "name": "support.type.systemverilog"
-        }
-      ]
-    },
-    "base-grammar": {
-      "patterns": [
-        {
-          "include": "#all-types"
+          "name": "constant.numeric.exp.systemverilog",
+          "match": "\\b((\\d[\\d_]*)(e|E)(\\+|-)?[0-9]+)\\b"
         },
         {
-          "include": "#comments"
+          "name": "constant.numeric.decimal.systemverilog",
+          "match": "\\b(\\d[\\d_]*)\\b"
         },
         {
-          "include": "#operators"
+          "name": "constant.numeric.time.systemverilog",
+          "match": "\\b(\\d+(fs|ps|ns|us|ms|s)?)\\b"
         },
         {
-          "include": "#constants"
+          "name": "constant.other.net.systemverilog",
+          "match": "\\b([A-Z][A-Z0-9_]*)\\b"
         },
         {
-          "include": "#strings"
-        },
-        {
-          "match": "^\\s*([a-zA-Z_][a-zA-Z0-9_]*)\\s+[a-zA-Z_][a-zA-Z0-9_,=\\s]*",
+          "match": "(`ifdef|`ifndef|`default_nettype)\\s+(\\w+)",
           "captures": {
             "1": {
-              "name": "storage.type.interface.systemverilog"
+              "name": "constant.other.preprocessor.systemverilog"
+            },
+            "2": {
+              "name": "support.variable.systemverilog"
             }
           }
         },
         {
-          "include": "#storage-scope-systemverilog"
-        }
-      ]
-    },
-    "storage-type-systemverilog": {
-      "patterns": [
+          "name": "constant.other.preprocessor.systemverilog",
+          "match": "`(celldefine|else|elsif|endcelldefine|endif|include|line|nounconnected_drive|resetall|timescale|unconnected_drive|undef|begin_\\w+|end_\\w+|remove_\\w+|restore_\\w+)\\b"
+        },
         {
-          "match": "\\s*\\b(var|wire|tri|tri[01]|supply[01]|wand|triand|wor|trior|trireg|reg|integer|int|longint|shortint|logic|bit|byte|shortreal|string|time|realtime|real|process|void)\\b",
-          "name": "storage.type.systemverilog"
+          "name": "constant.other.define.systemverilog",
+          "match": "`\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b"
         },
         {
-          "match": "\\s*\\b(uvm_transaction|uvm_component|uvm_monitor|uvm_driver|uvm_test|uvm_env|uvm_object|uvm_agent|uvm_sequence_base|uvm_sequence|uvm_sequence_item|uvm_sequence_state|uvm_sequencer|uvm_sequencer_base|uvm_component_registry|uvm_analysis_imp|uvm_analysis_port|uvm_analysis_export|uvm_config_db|uvm_active_passive_enum|uvm_phase|uvm_verbosity|uvm_tlm_analysis_fifo|uvm_tlm_fifo|uvm_report_server|uvm_objection|uvm_recorder|uvm_domain|uvm_reg_field|uvm_reg|uvm_reg_block|uvm_bitstream_t|uvm_radix_enum|uvm_printer|uvm_packer|uvm_comparer|uvm_scope_stack)\\b",
-          "name": "storage.type.uvm.systemverilog"
+          "name": "support.constant.systemverilog",
+          "match": "\\b(null)\\b"
         }
       ]
     },
-    "storage-scope-systemverilog": {
-      "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*)(::)",
-      "captures": {
-        "1": {
-          "name": "support.type.systemverilog"
-        },
-        "2": {
-          "name": "keyword.operator.scope.systemverilog"
-        }
-      },
-      "name": "meta.scope.systemverilog"
-    },
-    "storage-modifier-systemverilog": {
-      "match": "\\b(signed|unsigned|small|medium|large|supply[01]|strong[01]|pull[01]|weak[01]|highz[01])\\b",
-      "name": "storage.modifier.systemverilog"
+    "functions": {
+      "name": "support.function.generic.systemverilog",
+      "match": "\\b(\\w+)(?=\\s*\\()"
     },
     "ifmodport": {
       "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*)\\.([a-zA-Z_][a-zA-Z0-9_]*)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\b",
@@ -895,46 +789,9 @@
         }
       }
     },
-    "strings": {
-      "patterns": [
-        {
-          "begin": "\"",
-          "beginCaptures": {
-            "0": {
-              "name": "punctuation.definition.string.begin.systemverilog"
-            }
-          },
-          "end": "\"",
-          "endCaptures": {
-            "0": {
-              "name": "punctuation.definition.string.end.systemverilog"
-            }
-          },
-          "name": "string.quoted.double.systemverilog",
-          "patterns": [
-            {
-              "match": "\\\\.",
-              "name": "constant.character.escape.systemverilog"
-            },
-            {
-              "match": "(?x)%\r\n\t\t\t\t\t\t\t\t\t\t(\\d+\\$)?                             # field (argument #)\r\n\t\t\t\t\t\t\t\t\t\t[#0\\- +']*                           # flags\r\n\t\t\t\t\t\t\t\t\t\t[,;:_]?                              # separator character (AltiVec)\r\n\t\t\t\t\t\t\t\t\t\t((-?\\d+)|\\*(-?\\d+\\$)?)?              # minimum field width\r\n\t\t\t\t\t\t\t\t\t\t(\\.((-?\\d+)|\\*(-?\\d+\\$)?)?)?         # precision\r\n\t\t\t\t\t\t\t\t\t\t(hh|h|ll|l|j|t|z|q|L|vh|vl|v|hv|hl)? # length modifier\r\n\t\t\t\t\t\t\t\t\t\t[bdiouxXhHDOUeEfFgGaACcSspnmt%]      # conversion type\r\n\t\t\t\t\t\t\t\t\t",
-              "name": "constant.other.placeholder.systemverilog"
-            },
-            {
-              "match": "%",
-              "name": "invalid.illegal.placeholder.systemverilog"
-            }
-          ]
-        }
-      ]
-    },
     "module-binding": {
+      "match": "\\.([a-zA-Z_][a-zA-Z0-9_]*)\\s*",
       "begin": "\\.([a-zA-Z_][a-zA-Z0-9_]*)\\s*\\(",
-      "beginCaptures": {
-        "1": {
-          "name": "support.function.port.systemverilog"
-        }
-      },
       "end": "\\)",
       "patterns": [
         {
@@ -975,29 +832,28 @@
           }
         },
         {
-          "match": "\\$\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
-          "name": "support.function.systemverilog"
+          "name": "support.function.systemverilog",
+          "match": "\\$\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b"
         },
         {
-          "match": "\\b(virtual)\\b",
-          "name": "keyword.control.systemverilog"
+          "name": "keyword.control.systemverilog",
+          "match": "\\b(virtual)\\b"
         }
       ],
-      "match": "\\.([a-zA-Z_][a-zA-Z0-9_]*)\\s*",
       "captures": {
         "1": {
           "name": "support.function.port.implicit.systemverilog"
         }
+      },
+      "beginCaptures": {
+        "1": {
+          "name": "support.function.port.systemverilog"
+        }
       }
     },
     "module-param": {
       "name": "meta.module-param.systemverilog",
       "begin": "(#)\\s*\\(",
-      "beginCaptures": {
-        "1": {
-          "name": "keyword.operator.param.systemverilog"
-        }
-      },
       "end": "\\)",
       "patterns": [
         {
@@ -1016,13 +872,152 @@
           "include": "#module-binding"
         },
         {
-          "match": "\\b(virtual)\\b",
-          "name": "keyword.control.systemverilog"
+          "name": "keyword.control.systemverilog",
+          "match": "\\b(virtual)\\b"
+        }
+      ],
+      "beginCaptures": {
+        "1": {
+          "name": "keyword.operator.param.systemverilog"
+        }
+      }
+    },
+    "operators": {
+      "patterns": [
+        {
+          "name": "keyword.operator.comparison.systemverilog",
+          "match": "(=|==|===|!=|!==|\u003c=|\u003e=|\u003c|\u003e)"
+        },
+        {
+          "name": "keyword.operator.arithmetic.systemverilog",
+          "match": "(\\-|\\+|\\*|\\/|%)"
+        },
+        {
+          "name": "keyword.operator.logical.systemverilog",
+          "match": "(!|\u0026\u0026|\\|\\||\\bor\\b)"
+        },
+        {
+          "name": "keyword.operator.bitwise.systemverilog",
+          "match": "(\u0026|\\||\\^|~|{|'{|}|\u003c\u003c|\u003e\u003e|\\?|:)"
+        },
+        {
+          "name": "keyword.operator.other.systemverilog",
+          "match": "(#|@)"
+        }
+      ]
+    },
+    "port-dir": {
+      "patterns": [
+        {
+          "match": "\\s*\\b(output|input|inout|ref)\\s+(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)?\\s+(?=\\[[a-zA-Z0-9_\\-\\+]*:[a-zA-Z0-9_\\-\\+]*\\]\\s+[a-zA-Z_][a-zA-Z0-9_\\s]*)",
+          "captures": {
+            "1": {
+              "name": "support.type.systemverilog"
+            },
+            "3": {
+              "name": "support.type.scope.systemverilog"
+            },
+            "4": {
+              "name": "keyword.operator.scope.systemverilog"
+            },
+            "5": {
+              "name": "storage.type.interface.systemverilog"
+            }
+          }
+        },
+        {
+          "match": "\\s*\\b(output|input|inout|ref)\\s+(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)?\\s+(?=[a-zA-Z_][a-zA-Z0-9_\\s]*)",
+          "captures": {
+            "1": {
+              "name": "support.type.systemverilog"
+            },
+            "3": {
+              "name": "support.type.scope.systemverilog"
+            },
+            "4": {
+              "name": "keyword.operator.scope.systemverilog"
+            },
+            "5": {
+              "name": "storage.type.interface.systemverilog"
+            }
+          }
+        },
+        {
+          "name": "support.type.systemverilog",
+          "match": "\\s*\\b(output|input|inout|ref)\\b"
+        }
+      ]
+    },
+    "storage-modifier-systemverilog": {
+      "name": "storage.modifier.systemverilog",
+      "match": "\\b(signed|unsigned|small|medium|large|supply[01]|strong[01]|pull[01]|weak[01]|highz[01])\\b"
+    },
+    "storage-scope-systemverilog": {
+      "name": "meta.scope.systemverilog",
+      "match": "\\b([a-zA-Z_][a-zA-Z0-9_]*)(::)",
+      "captures": {
+        "1": {
+          "name": "support.type.systemverilog"
+        },
+        "2": {
+          "name": "keyword.operator.scope.systemverilog"
+        }
+      }
+    },
+    "storage-type-systemverilog": {
+      "patterns": [
+        {
+          "name": "storage.type.systemverilog",
+          "match": "\\s*\\b(var|wire|tri|tri[01]|supply[01]|wand|triand|wor|trior|trireg|reg|integer|int|longint|shortint|logic|bit|byte|shortreal|string|time|realtime|real|process|void)\\b"
+        },
+        {
+          "name": "storage.type.uvm.systemverilog",
+          "match": "\\s*\\b(uvm_transaction|uvm_component|uvm_monitor|uvm_driver|uvm_test|uvm_env|uvm_object|uvm_agent|uvm_sequence_base|uvm_sequence|uvm_sequence_item|uvm_sequence_state|uvm_sequencer|uvm_sequencer_base|uvm_component_registry|uvm_analysis_imp|uvm_analysis_port|uvm_analysis_export|uvm_config_db|uvm_active_passive_enum|uvm_phase|uvm_verbosity|uvm_tlm_analysis_fifo|uvm_tlm_fifo|uvm_report_server|uvm_objection|uvm_recorder|uvm_domain|uvm_reg_field|uvm_reg|uvm_reg_block|uvm_bitstream_t|uvm_radix_enum|uvm_printer|uvm_packer|uvm_comparer|uvm_scope_stack)\\b"
+        }
+      ]
+    },
+    "strings": {
+      "patterns": [
+        {
+          "name": "string.quoted.double.systemverilog",
+          "begin": "\"",
+          "end": "\"",
+          "patterns": [
+            {
+              "name": "constant.character.escape.systemverilog",
+              "match": "\\\\."
+            },
+            {
+              "name": "constant.other.placeholder.systemverilog",
+              "match": "(?x)%\n\t\t\t\t\t\t\t\t\t\t(\\d+\\$)?                             # field (argument #)\n\t\t\t\t\t\t\t\t\t\t[#0\\- +']*                           # flags\n\t\t\t\t\t\t\t\t\t\t[,;:_]?                              # separator character (AltiVec)\n\t\t\t\t\t\t\t\t\t\t((-?\\d+)|\\*(-?\\d+\\$)?)?              # minimum field width\n\t\t\t\t\t\t\t\t\t\t(\\.((-?\\d+)|\\*(-?\\d+\\$)?)?)?         # precision\n\t\t\t\t\t\t\t\t\t\t(hh|h|ll|l|j|t|z|q|L|vh|vl|v|hv|hl)? # length modifier\n\t\t\t\t\t\t\t\t\t\t[bdiouxXhHDOUeEfFgGaACcSspnmt%]      # conversion type\n\t\t\t\t\t\t\t\t\t"
+            },
+            {
+              "name": "invalid.illegal.placeholder.systemverilog",
+              "match": "%"
+            }
+          ],
+          "beginCaptures": {
+            "0": {
+              "name": "punctuation.definition.string.begin.systemverilog"
+            }
+          },
+          "endCaptures": {
+            "0": {
+              "name": "punctuation.definition.string.end.systemverilog"
+            }
+          }
         }
       ]
     },
     "struct-anonymous": {
+      "name": "meta.struct.anonymous.systemverilog",
       "begin": "\\s*\\b(struct|union)\\s*(packed)?\\s*",
+      "end": "(})\\s*([a-zA-Z_]\\w*)\\s*;",
+      "patterns": [
+        {
+          "include": "#base-grammar"
+        }
+      ],
       "beginCaptures": {
         "1": {
           "name": "keyword.control.systemverilog"
@@ -1031,20 +1026,11 @@
           "name": "keyword.control.systemverilog"
         }
       },
-      "end": "(})\\s*([a-zA-Z_]\\w*)\\s*;",
       "endCaptures": {
         "1": {
           "name": "keyword.operator.other.systemverilog"
         }
-      },
-      "patterns": [
-        {
-          "include": "#base-grammar"
-        }
-      ],
-      "name": "meta.struct.anonymous.systemverilog"
+      }
     }
-  },
-  "scopeName": "source.systemverilog",
-  "uuid": "789be04c-8b74-352e-8f37-63d336001277"
-}
+  }
+}