faiss 0.6.1 → 0.6.3

data/vendor/faiss/faiss/impl/scalar_quantizer/sq-neon.cpp

@@ -9,6 +9,7 @@
 
 #include <faiss/impl/simdlib/simdlib_neon.h>
 
+#include <algorithm>
 #include <cstring>
 
 #include <faiss/impl/scalar_quantizer/codecs.h>
@@ -180,6 +181,12 @@ struct QuantizerTemplate<
                                 xi.data.val[1],
                                 this->vdiff)});
     }
+
+    /// Raw codec decode without denormalization (for pre-decode opt)
+    FAISS_ALWAYS_INLINE simd8float32
+    decode_8_raw(const uint8_t* code, int i) const {
+        return Codec::decode_8_components(code, i);
+    }
 };
 
 template <class Codec>
@@ -216,41 +223,52 @@ struct QuantizerTemplate<
 };
 
 /**********************************************************
- * TurboQuant MSE quantizer
+ * Lloyd-Max scalar quantizer
  **********************************************************/
 
-#define DEFINE_TQMSE_NEON_SPECIALIZATION(NBITS, UNPACK_FN)                  \
-    template <>                                                             \
-    struct QuantizerTurboQuantMSE<NBITS, SIMDLevel::ARM_NEON>               \
-            : QuantizerTurboQuantMSE<NBITS, SIMDLevel::NONE> {              \
-        using Base = QuantizerTurboQuantMSE<NBITS, SIMDLevel::NONE>;        \
-                                                                            \
-        QuantizerTurboQuantMSE(size_t d, const std::vector<float>& trained) \
-                : Base(d, trained) {                                        \
-            assert(d % 8 == 0);                                             \
-        }                                                                   \
-                                                                            \
-        FAISS_ALWAYS_INLINE simd8float32                                    \
-        reconstruct_8_components(const uint8_t* code, int i) const {        \
-            uint8_t indices[8];                                             \
-            UNPACK_FN(code, i, indices);                                    \
-            return gather_8_components(this->centroids, indices);           \
-        }                                                                   \
-    }
-
-DEFINE_TQMSE_NEON_SPECIALIZATION(1, unpack_8x1bit_to_u8);
-DEFINE_TQMSE_NEON_SPECIALIZATION(2, unpack_8x2bit_to_u8);
-DEFINE_TQMSE_NEON_SPECIALIZATION(3, unpack_8x3bit_to_u8);
-DEFINE_TQMSE_NEON_SPECIALIZATION(4, unpack_8x4bit_to_u8);
-
-#undef DEFINE_TQMSE_NEON_SPECIALIZATION
+// NEON Lloyd-Max: decode via gather, encode stays scalar.
+// NEON doesn't have movemask so 1-bit encode is also scalar.
+#define DEFINE_LLOYD_MAX_NEON_SPECIALIZATION(NBITS, UNPACK_FN)               \
+    template <>                                                              \
+    struct QuantizerLloydMax<NBITS, SIMDLevel::ARM_NEON>                     \
+            : QuantizerLloydMax<NBITS, SIMDLevel::NONE> {                    \
+        using Base = QuantizerLloydMax<NBITS, SIMDLevel::NONE>;              \
+                                                                             \
+        QuantizerLloydMax(size_t d, const std::vector<float>& trained)       \
+                : Base(d, trained) {                                         \
+            assert(d % 8 == 0);                                              \
+        }                                                                    \
+                                                                             \
+        FAISS_ALWAYS_INLINE simd8float32                                     \
+        reconstruct_8_components(const uint8_t* code, int i) const {         \
+            uint8_t indices[8];                                              \
+            UNPACK_FN(code, i, indices);                                     \
+            return gather_8_components(this->centroids, indices);            \
+        }                                                                    \
+                                                                             \
+        void decode_vector(const uint8_t* code, float* x) const final {      \
+            for (size_t i = 0; i < this->d; i += 8) {                        \
+                simd8float32 xi =                                            \
+                        reconstruct_8_components(code, static_cast<int>(i)); \
+                vst1q_f32(x + i, xi.data.val[0]);                            \
+                vst1q_f32(x + i + 4, xi.data.val[1]);                        \
+            }                                                                \
+        }                                                                    \
+    }
+
+DEFINE_LLOYD_MAX_NEON_SPECIALIZATION(1, unpack_8x1bit_to_u8);
+DEFINE_LLOYD_MAX_NEON_SPECIALIZATION(2, unpack_8x2bit_to_u8);
+DEFINE_LLOYD_MAX_NEON_SPECIALIZATION(3, unpack_8x3bit_to_u8);
+DEFINE_LLOYD_MAX_NEON_SPECIALIZATION(4, unpack_8x4bit_to_u8);
+
+#undef DEFINE_LLOYD_MAX_NEON_SPECIALIZATION
 
 template <>
-struct QuantizerTurboQuantMSE<8, SIMDLevel::ARM_NEON>
-        : QuantizerTurboQuantMSE<8, SIMDLevel::NONE> {
-    using Base = QuantizerTurboQuantMSE<8, SIMDLevel::NONE>;
+struct QuantizerLloydMax<8, SIMDLevel::ARM_NEON>
+        : QuantizerLloydMax<8, SIMDLevel::NONE> {
+    using Base = QuantizerLloydMax<8, SIMDLevel::NONE>;
 
-    QuantizerTurboQuantMSE(size_t d, const std::vector<float>& trained)
+    QuantizerLloydMax(size_t d, const std::vector<float>& trained)
             : Base(d, trained) {
         assert(d % 8 == 0);
     }
@@ -261,6 +279,15 @@ struct QuantizerTurboQuantMSE<8, SIMDLevel::ARM_NEON>
         std::memcpy(indices, code + static_cast<size_t>(i), sizeof(indices));
         return gather_8_components(this->centroids, indices);
     }
+
+    void decode_vector(const uint8_t* code, float* x) const final {
+        for (size_t i = 0; i < this->d; i += 8) {
+            simd8float32 xi =
+                    reconstruct_8_components(code, static_cast<int>(i));
+            vst1q_f32(x + i, xi.data.val[0]);
+            vst1q_f32(x + i + 4, xi.data.val[1]);
+        }
+    }
 };
 
 /**********************************************************
@@ -397,6 +424,22 @@ struct SimilarityL2<SIMDLevel::ARM_NEON> {
     FAISS_ALWAYS_INLINE float result_8() {
         return horizontal_add(accu8);
     }
+
+    static void adjust_query_for_raw_decode(
+            const float* x,
+            float* q_adj,
+            size_t d,
+            float vmin,
+            float vdiff,
+            float& scale_factor,
+            float& bias) {
+        float inv_vdiff = (vdiff != 0) ? 1.0f / vdiff : 0.0f;
+        for (size_t i = 0; i < d; i++) {
+            q_adj[i] = (x[i] - vmin) * inv_vdiff;
+        }
+        scale_factor = vdiff * vdiff;
+        bias = 0;
+    }
 };
 
 template <>
@@ -431,6 +474,23 @@ struct SimilarityIP<SIMDLevel::ARM_NEON> {
     FAISS_ALWAYS_INLINE float result_8() {
         return horizontal_add(accu8);
     }
+
+    static void adjust_query_for_raw_decode(
+            const float* x,
+            float* q_adj,
+            size_t d,
+            float vmin,
+            float vdiff,
+            float& scale_factor,
+            float& bias) {
+        float sum_q = 0;
+        for (size_t i = 0; i < d; i++) {
+            q_adj[i] = x[i];
+            sum_q += x[i];
+        }
+        scale_factor = vdiff;
+        bias = vmin * sum_q;
+    }
 };
 
 /**********************************************************
@@ -444,8 +504,23 @@ struct DCTemplate<Quantizer, Similarity, SIMDLevel::ARM_NEON>
 
     Quantizer quant;
 
+    // Pre-adjusted query buffer for uniform quantizers
+    std::vector<float> q_adj;
+    float scale_factor = 0;
+    float bias = 0;
+
+    static constexpr bool has_decode_raw() {
+        return requires(const Quantizer& q, const uint8_t* c, int i) {
+            { q.decode_8_raw(c, i) };
+        };
+    }
+
     DCTemplate(size_t d, const std::vector<float>& trained)
-            : quant(d, trained) {}
+            : quant(d, trained) {
+        if constexpr (has_decode_raw()) {
+            q_adj.resize(d);
+        }
+    }
 
     float compute_distance(const float* x, const uint8_t* code) const {
         Similarity sim(x);
@@ -471,6 +546,26 @@ struct DCTemplate<Quantizer, Similarity, SIMDLevel::ARM_NEON>
 
     void set_query(const float* x) final {
         q = x;
+        if constexpr (has_decode_raw()) {
+            Sim::adjust_query_for_raw_decode(
+                    x,
+                    q_adj.data(),
+                    quant.d,
+                    quant.vmin,
+                    quant.vdiff,
+                    scale_factor,
+                    bias);
+        }
+    }
+
+    float query_to_code_predecoded(const uint8_t* code) const {
+        Similarity sim(q_adj.data());
+        sim.begin_8();
+        for (size_t i = 0; i < quant.d; i += 8) {
+            simd8float32 xi = quant.decode_8_raw(code, i);
+            sim.add_8_components(xi);
+        }
+        return bias + scale_factor * sim.result_8();
     }
 
     float symmetric_dis(idx_t i, idx_t j) override {
@@ -479,7 +574,11 @@ struct DCTemplate<Quantizer, Similarity, SIMDLevel::ARM_NEON>
     }
 
     float query_to_code(const uint8_t* code) const final {
-        return compute_distance(q, code);
+        if constexpr (has_decode_raw()) {
+            return query_to_code_predecoded(code);
+        } else {
+            return compute_distance(q, code);
+        }
     }
 
     void query_to_codes_batch_4(
@@ -564,6 +663,32 @@ struct DistanceComputerByte<Similarity, SIMDLevel::ARM_NEON>
     }
 };
 
+/**********************************************************
+ * TurboQuant masked_sum NEON specialization (scalar fallback)
+ **********************************************************/
+
+template <SIMDLevel SL0>
+float turboq_masked_sum(const float* arr, const uint8_t* bits, size_t d);
+
+template <>
+float turboq_masked_sum<SIMDLevel::ARM_NEON>(
+        const float* arr,
+        const uint8_t* bits,
+        size_t d) {
+    float result = 0;
+    for (size_t byte_idx = 0; byte_idx < (d + 7) / 8; byte_idx++) {
+        uint8_t b = bits[byte_idx];
+        size_t base = byte_idx * 8;
+        size_t end = std::min(base + 8, d);
+        for (size_t j = base; j < end; j++) {
+            if (b & (1 << (j - base))) {
+                result += arr[j];
+            }
+        }
+    }
+    return result;
+}
+
 } // namespace scalar_quantizer
 } // namespace faiss
 

data/vendor/faiss/faiss/impl/scalar_quantizer/sq-rvv.cpp

@@ -302,6 +302,32 @@ struct DCTemplate<
     }
 };
 
+/**********************************************************
+ * TurboQuant masked_sum RVV specialization (scalar fallback)
+ **********************************************************/
+
+template <SIMDLevel SL0>
+float turboq_masked_sum(const float* arr, const uint8_t* bits, size_t d);
+
+template <>
+float turboq_masked_sum<SIMDLevel::RISCV_RVV>(
+        const float* arr,
+        const uint8_t* bits,
+        size_t d) {
+    float result = 0;
+    for (size_t byte_idx = 0; byte_idx < (d + 7) / 8; byte_idx++) {
+        uint8_t b = bits[byte_idx];
+        size_t base = byte_idx * 8;
+        size_t end = std::min(base + 8, d);
+        for (size_t j = base; j < end; j++) {
+            if (b & (1 << (j - base))) {
+                result += arr[j];
+            }
+        }
+    }
+    return result;
+}
+
 } // namespace scalar_quantizer
 } // namespace faiss
 

data/vendor/faiss/faiss/impl/simd_dispatch.h

@@ -36,6 +36,12 @@ constexpr int AVAILABLE_SIMD_LEVELS_AVX2_NEON = AVAILABLE_SIMD_LEVELS_NONE |
 constexpr int AVAILABLE_SIMD_LEVELS_A0 = AVAILABLE_SIMD_LEVELS_AVX2_NEON |
         (1 << int(SIMDLevel::AVX512)) | (1 << int(SIMDLevel::RISCV_RVV));
 
+// A0_SPR: same as A0 + AVX512_SPR (for functions with a dedicated SPR
+// specialization on top of an AVX512 fallback). Currently used by the
+// RaBitQ popcount kernels, which use VPOPCNTDQ on SPR+.
+constexpr int AVAILABLE_SIMD_LEVELS_A0_SPR =
+        AVAILABLE_SIMD_LEVELS_A0 | (1 << int(SIMDLevel::AVX512_SPR));
+
 // A1: same + ARM_SVE (for functions with dedicated SVE implementations)
 constexpr int AVAILABLE_SIMD_LEVELS_A1 =
         AVAILABLE_SIMD_LEVELS_A0 | (1 << int(SIMDLevel::ARM_SVE));
@@ -47,6 +53,55 @@ constexpr int AVAILABLE_SIMD_LEVELS_A2 = AVAILABLE_SIMD_LEVELS_NONE |
 
 constexpr int AVAILABLE_SIMD_LEVELS_ALL = -1;
 
+constexpr SIMDLevel get_simd_fallback(SIMDLevel level) {
+    switch (level) {
+        case SIMDLevel::AVX512_SPR:
+            return SIMDLevel::AVX512;
+        case SIMDLevel::AVX512:
+            return SIMDLevel::AVX2;
+        case SIMDLevel::ARM_SVE:
+            return SIMDLevel::ARM_NEON;
+        case SIMDLevel::AVX2:
+        case SIMDLevel::ARM_NEON:
+        case SIMDLevel::RISCV_RVV:
+            return SIMDLevel::NONE;
+        default:
+            return SIMDLevel::NONE;
+    }
+}
+
+template <int available_levels, SIMDLevel current_level, typename LambdaType>
+inline auto dispatch_with_fallback(LambdaType&& action) {
+    if constexpr (available_levels & (1 << int(current_level))) {
+        return action.template operator()<current_level>();
+    } else if constexpr (current_level != SIMDLevel::NONE) {
+        return dispatch_with_fallback<
+                available_levels,
+                get_simd_fallback(current_level)>(
+                std::forward<LambdaType>(action));
+    } else {
+        return action.template operator()<SIMDLevel::NONE>();
+    }
+}
+
+/** Run action at current_level; on a null result, retry the next-lower level,
+ * down to NONE (terminal). action is called per level tried, so never moved. */
+template <int available_levels, SIMDLevel current_level, typename LambdaType>
+inline auto dispatch_simd_level_or_lower(LambdaType& action) {
+    if constexpr (current_level == SIMDLevel::NONE) {
+        return action.template operator()<SIMDLevel::NONE>();
+    } else {
+        if constexpr (available_levels & (1 << int(current_level))) {
+            if (auto result = action.template operator()<current_level>()) {
+                return result;
+            }
+        }
+        return dispatch_simd_level_or_lower<
+                available_levels,
+                get_simd_fallback(current_level)>(action);
+    }
+}
+
 /** The complete dispatching function. It takes into account:
  * - the currently selected SIMD level
  * - the compiled in SIMD levels (given by COMPILE_SIMD_XXX)
@@ -114,17 +169,30 @@ inline auto with_selected_simd_levels(LambdaType&& action) {
     }
 #else // static dispatch
     // In static mode, SINGLE_SIMD_LEVEL is a constexpr resolved at compile
-    // time. If the compiled level is not in the available set, fall through
-    // to NONE (mirroring the DD fallthrough behavior). Only SINGLE_SIMD_LEVEL
-    // and NONE have compiled specializations.
-    if constexpr (available_levels & (1 << int(SINGLE_SIMD_LEVEL))) {
-        return action.template operator()<SINGLE_SIMD_LEVEL>();
-    } else {
-        return action.template operator()<SIMDLevel::NONE>();
-    }
+    // time. We mirror the DD fallthrough behavior at compile time via
+    // dispatch_with_fallback, which recursively walks get_simd_fallback:
+    //   x86:   AVX512_SPR -> AVX512 -> AVX2 -> NONE
+    //   ARM:   ARM_SVE -> ARM_NEON -> NONE
+    //   RISCV: RISCV_RVV -> NONE
+    // The first level in the chain that appears in available_levels is
+    // selected; if none match, NONE is used unconditionally.
+    return dispatch_with_fallback<available_levels, SINGLE_SIMD_LEVEL>(
+            std::forward<LambdaType>(action));
 #endif
 }
 
+/** Like with_selected_simd_levels, but for factory actions that return null to
+ * decline a level (e.g. AVX-512 needing d % 16 == 0). Falls back to the next
+ * lower level, down to NONE. */
+template <int available_levels, typename LambdaType>
+inline auto with_simd_level_fallback(const LambdaType& action) {
+    return with_selected_simd_levels<available_levels>(
+            [&action]<SIMDLevel SL>() {
+                return dispatch_simd_level_or_lower<available_levels, SL>(
+                        action);
+            });
+}
+
 /**
  * Dispatch to a lambda with SIMDLevel as a compile-time constant.
  *
@@ -170,4 +238,14 @@ inline auto with_simd_level_256bit(LambdaType&& action) {
             std::forward<LambdaType>(action));
 }
 
+/**
+ * Use for functions that have A0-level implementations plus an AVX512_SPR
+ * specialization (e.g. using VPOPCNTDQ).
+ */
+template <typename LambdaType>
+inline auto with_simd_level_a0_spr(LambdaType&& action) {
+    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_A0_SPR>(
+            std::forward<LambdaType>(action));
+}
+
 } // namespace faiss

data/vendor/faiss/faiss/index_factory.cpp

@@ -21,11 +21,13 @@
 #include <faiss/Index2Layer.h>
 #include <faiss/IndexAdditiveQuantizer.h>
 #include <faiss/IndexAdditiveQuantizerFastScan.h>
+#include <faiss/IndexEDEN.h>
 #include <faiss/IndexFlat.h>
 #include <faiss/IndexHNSW.h>
 #include <faiss/IndexIVF.h>
 #include <faiss/IndexIVFAdditiveQuantizer.h>
 #include <faiss/IndexIVFAdditiveQuantizerFastScan.h>
+#include <faiss/IndexIVFEDEN.h>
 #include <faiss/IndexIVFFlat.h>
 #include <faiss/IndexIVFFlatPanorama.h>
 #include <faiss/IndexIVFPQ.h>
@@ -168,9 +170,13 @@ std::map<std::string, ScalarQuantizer::QuantizerType> sq_types = {
         {"SQtqmse3", ScalarQuantizer::QT_3bit_tqmse},
         {"SQtqmse4", ScalarQuantizer::QT_4bit_tqmse},
         {"SQtqmse8", ScalarQuantizer::QT_8bit_tqmse},
+        {"SQtq2", ScalarQuantizer::QT_2bit_tq},
+        {"SQtq3", ScalarQuantizer::QT_3bit_tq},
+        {"SQtq4", ScalarQuantizer::QT_4bit_tq},
+        {"SQtq5", ScalarQuantizer::QT_5bit_tq},
 };
 const std::string sq_pattern =
-        "(SQ0|SQ4|SQ8|SQ6|SQfp16|SQbf16|SQ8_direct_signed|SQ8_direct|SQtqmse1|SQtqmse2|SQtqmse3|SQtqmse4|SQtqmse8)";
+        "(SQ0|SQ4|SQ8|SQ6|SQfp16|SQbf16|SQ8_direct_signed|SQ8_direct|SQtqmse1|SQtqmse2|SQtqmse3|SQtqmse4|SQtqmse8|SQtq2|SQtq3|SQtq4|SQtq5)";
 
 std::map<std::string, AdditiveQuantizer::Search_type_t> aq_search_type = {
         {"_Nfloat", AdditiveQuantizer::ST_norm_float},
@@ -311,8 +317,8 @@ Index* parse_coarse_quantizer(
         SVSStorageKind storage = SVSStorageKind::SVS_FP32;
         if (sm[3].matched) {
             std::string s = sm[3].str().substr(1);
-            if (s == "SQI8") {
-                storage = SVSStorageKind::SVS_SQI8;
+            if (s == "SQ8") {
+                storage = SVSStorageKind::SVS_SQ8;
             } else if (s == "FP16") {
                 storage = SVSStorageKind::SVS_FP16;
             } else if (s == "FP32") {
@@ -510,6 +516,18 @@ IndexIVF* parse_IndexIVF(
         uint8_t nb_bits = sm[1].length() > 0 ? std::stoi(sm[1].str()) : 1;
         return new IndexIVFRaBitQ(get_q(), d, nlist, mt, own_il, nb_bits);
     }
+    // IndexIVFEDEN with optional nb_bits (1-8) and scale type.
+    // Accepts: "EDEN" (default 1-bit), "EDEN{nb_bits}" (e.g., "EDEN4"),
+    //          or "EDEN{nb_bits}BIASED" for the MSE-minimizing scale.
+    if (match("EDEN([1-8])?(BIASED|BIAS)?")) {
+        uint8_t nb_bits = sm[1].length() > 0 ? std::stoi(sm[1].str()) : 1;
+        EDENScaleType scale_type =
+                sm[2].str() == "BIASED" || sm[2].str() == "BIAS"
+                ? EDENScaleType_BIASED
+                : EDENScaleType_UNBIASED;
+        return new IndexIVFEDEN(
+                get_q(), d, nlist, mt, own_il, nb_bits, scale_type);
+    }
     // Accepts: "RaBitQfs" (default 1-bit, batch size 32)
     //          "RaBitQfs{nb_bits}" (e.g., "RaBitQfs4")
     //          "RaBitQfs_64" (1-bit, batch size 64)
@@ -677,16 +695,16 @@ Index* parse_svs_datatype(
         }
         FAISS_ASSERT(false && "Unsupported SVS index type for Float16");
     }
-    if (re_match(datatype_string, "SQI8", sm)) {
+    if (re_match(datatype_string, "SQ8", sm)) {
         if (index_type == "Vamana") {
             return new IndexSVSVamana(
-                    d, std::stoul(arg_string), mt, SVSStorageKind::SVS_SQI8);
+                    d, std::stoul(arg_string), mt, SVSStorageKind::SVS_SQ8);
         }
         if (index_type == "IVF") {
             return new IndexSVSIVF(
-                    d, std::stoul(arg_string), mt, SVSStorageKind::SVS_SQI8);
+                    d, std::stoul(arg_string), mt, SVSStorageKind::SVS_SQ8);
         }
-        FAISS_ASSERT(false && "Unsupported SVS index type for SQI8");
+        FAISS_ASSERT(false && "Unsupported SVS index type for SQ8");
     }
     if (re_match(datatype_string, "(LVQ[0-9]+x[0-9]+)", sm)) {
         if (index_type == "Vamana") {
@@ -913,6 +931,18 @@ Index* parse_other_indexes(
         return new IndexRaBitQ(d, metric, nb_bits);
     }
 
+    // IndexEDEN with optional nb_bits (1-8) and scale type.
+    // Accepts: "EDEN" (default 1-bit), "EDEN{nb_bits}" (e.g., "EDEN4"),
+    //          or "EDEN{nb_bits}BIASED" for the MSE-minimizing scale.
+    if (match("EDEN([1-8])?(BIASED|BIAS)?")) {
+        uint8_t nb_bits = sm[1].length() > 0 ? std::stoi(sm[1].str()) : 1;
+        EDENScaleType scale_type =
+                sm[2].str() == "BIASED" || sm[2].str() == "BIAS"
+                ? EDENScaleType_BIASED
+                : EDENScaleType_UNBIASED;
+        return new IndexEDEN(d, metric, nb_bits, scale_type);
+    }
+
     if (match("RaBitQfs([1-9])?(_[0-9]+)?")) {
         uint8_t nb_bits = sm[1].length() > 0 ? std::stoi(sm[1].str()) : 1;
         int bbs = mres_to_int(sm[2], 32, 1);

data/vendor/faiss/faiss/index_io.h

@@ -137,6 +137,22 @@ size_t get_deserialization_vector_byte_limit();
 // and do not modify while deserialization is in progress on other threads.
 void set_deserialization_vector_byte_limit(size_t value);
 
+// Returns the current IndexLattice r2 limit for deserialization.
+// When nonzero, deserialization rejects IndexLattice payloads whose
+// r2 (squared lattice radius) exceeds this value.  The
+// ZnSphereCodecRec constructor that runs at IndexLattice deserialize
+// time builds a decode cache whose population cost scales
+// polynomially in r2 and dim, and can exceed real-world workload time
+// budgets even for r2 values that do not trip the existing
+// decode-cache memory cap.
+// Default: 0 (no limit).
+size_t get_deserialization_lattice_r2_limit();
+
+// Sets the IndexLattice r2 deserialization limit.
+// NOT thread-safe: set before any concurrent deserialization calls
+// and do not modify while deserialization is in progress on other threads.
+void set_deserialization_lattice_r2_limit(size_t value);
+
 } // namespace faiss
 
 #endif

data/vendor/faiss/faiss/invlists/DirectMap.cpp

@@ -80,7 +80,7 @@ idx_t DirectMap::get(idx_t key) const {
         return lo;
     } else if (type == Hashtable) {
         auto res = hashtable.find(key);
-        FAISS_THROW_IF_NOT_MSG(res != hashtable.end(), "key not found");
+        FAISS_THROW_IF_MSG(res == hashtable.end(), "key not found");
         return res->second;
     } else {
         FAISS_THROW_MSG("direct map not initialized");
@@ -254,7 +254,10 @@ void DirectMap::update_codes(
                 int64_t id2 = invlists->get_single_id(il, l - 1);
                 array[id2] = lo_build(il, ofs);
                 invlists->update_entry(
-                        il, ofs, id2, invlists->get_single_code(il, l - 1));
+                        il,
+                        ofs,
+                        id2,
+                        InvertedLists::ScopedCodes(invlists, il, l - 1).get());
             }
             invlists->resize(il, l - 1);
         }

data/vendor/faiss/faiss/invlists/InvertedLists.cpp

@@ -371,8 +371,8 @@ ArrayInvertedListsPanorama::ArrayInvertedListsPanorama(
           pano(code_size_in, n_levels_in, batch_size) {
     FAISS_THROW_IF_NOT(n_levels_in > 0);
     FAISS_THROW_IF_NOT(code_size_in % sizeof(float) == 0);
-    FAISS_THROW_IF_NOT_MSG(
-            !use_iterator,
+    FAISS_THROW_IF_MSG(
+            use_iterator,
             "IndexIVFFlatPanorama does not support iterators, use vanilla IndexIVFFlat instead");
     FAISS_ASSERT(level_width % sizeof(float) == 0);
 
@@ -498,12 +498,12 @@ void ReadOnlyInvertedLists::resize(size_t, size_t) {
  * HStackInvertedLists implementation
  ******************************************/
 
-HStackInvertedLists::HStackInvertedLists(int nil, const InvertedLists** ils_in)
+HStackInvertedLists::HStackInvertedLists(int n_il, const InvertedLists** ils_in)
         : ReadOnlyInvertedLists(
-                  nil > 0 ? ils_in[0]->nlist : 0,
-                  nil > 0 ? ils_in[0]->code_size : 0) {
-    FAISS_THROW_IF_NOT(nil > 0);
-    for (int i = 0; i < nil; i++) {
+                  n_il > 0 ? ils_in[0]->nlist : 0,
+                  n_il > 0 ? ils_in[0]->code_size : 0) {
+    FAISS_THROW_IF_NOT(n_il > 0);
+    for (int i = 0; i < n_il; i++) {
         ils.push_back(ils_in[i]);
         FAISS_THROW_IF_NOT(
                 ils_in[i]->code_size == code_size && ils_in[i]->nlist == nlist);
@@ -683,9 +683,9 @@ int translate_list_no(const VStackInvertedLists* vil, idx_t list_no) {
     return i0;
 }
 
-idx_t sum_il_sizes(int nil, const InvertedLists** ils_in) {
+idx_t sum_il_sizes(int n_il, const InvertedLists** ils_in) {
     idx_t tot = 0;
-    for (int i = 0; i < nil; i++) {
+    for (int i = 0; i < n_il; i++) {
         tot += ils_in[i]->nlist;
     }
     return tot;
@@ -693,13 +693,13 @@ idx_t sum_il_sizes(int nil, const InvertedLists** ils_in) {
 
 } // namespace
 
-VStackInvertedLists::VStackInvertedLists(int nil, const InvertedLists** ils_in)
+VStackInvertedLists::VStackInvertedLists(int n_il, const InvertedLists** ils_in)
         : ReadOnlyInvertedLists(
-                  sum_il_sizes(nil, ils_in),
-                  nil > 0 ? ils_in[0]->code_size : 0) {
-    FAISS_THROW_IF_NOT(nil > 0);
-    cumsz.resize(nil + 1);
-    for (int i = 0; i < nil; i++) {
+                  sum_il_sizes(n_il, ils_in),
+                  n_il > 0 ? ils_in[0]->code_size : 0) {
+    FAISS_THROW_IF_NOT(n_il > 0);
+    cumsz.resize(n_il + 1);
+    for (int i = 0; i < n_il; i++) {
         ils.push_back(ils_in[i]);
         FAISS_THROW_IF_NOT(ils_in[i]->code_size == code_size);
         cumsz[i + 1] = cumsz[i] + ils_in[i]->nlist;

data/vendor/faiss/faiss/invlists/InvertedLists.h

@@ -376,7 +376,7 @@ struct HStackInvertedLists : ReadOnlyInvertedLists {
     std::vector<const InvertedLists*> ils;
 
     /// build InvertedLists by concatenating nil of them
-    HStackInvertedLists(int nil, const InvertedLists** ils);
+    HStackInvertedLists(int n_il, const InvertedLists** ils);
 
     size_t list_size(size_t list_no) const override;
     const uint8_t* get_codes(size_t list_no) const override;
@@ -422,7 +422,7 @@ struct VStackInvertedLists : ReadOnlyInvertedLists {
     std::vector<idx_t> cumsz;
 
     /// build InvertedLists by concatenating nil of them
-    VStackInvertedLists(int nil, const InvertedLists** ils);
+    VStackInvertedLists(int n_il, const InvertedLists** ils);
 
     size_t list_size(size_t list_no) const override;
     const uint8_t* get_codes(size_t list_no) const override;