faiss 0.5.3 → 0.6.1

data/vendor/faiss/faiss/utils/simd_impl/super_kmeans_kernels_avx2.cpp

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+#ifdef COMPILE_SIMD_AVX2
+
+#include <faiss/utils/simd_impl/super_kmeans_kernels.h>
+
+#include <immintrin.h>
+
+namespace faiss {
+namespace detail {
+
+namespace {
+
+// Reduce 8 float lanes of an AVX2 register to a scalar sum.
+// Uses a shuffle+add tree instead of two _mm_hadd_ps. On Skylake-class
+// cores, hadd is 3-cycle latency / 2-uop, while movehdup/movehl/add_ss
+// are single-uop, single-cycle ops.
+inline float horizontal_sum_avx2(__m256 v) {
+    __m128 lo = _mm256_castps256_ps128(v);
+    __m128 hi = _mm256_extractf128_ps(v, 1);
+    __m128 sum128 = _mm_add_ps(lo, hi);     // 4 lanes
+    __m128 shuf = _mm_movehdup_ps(sum128);  // [s1, s1, s3, s3]
+    __m128 sums = _mm_add_ps(sum128, shuf); // [s0+s1, _, s2+s3, _]
+    shuf = _mm_movehl_ps(shuf, sums);       // [s2+s3, s3, _, _]
+    sums = _mm_add_ss(sums, shuf);          // (s0+s1) + (s2+s3)
+    return _mm_cvtss_f32(sums);
+}
+
+} // namespace
+
+template <>
+float block_l2<SIMDLevel::AVX2>(const float* x, const float* y, int n) {
+    __m256 acc = _mm256_setzero_ps();
+    int m = 0;
+    for (; m + 8 <= n; m += 8) {
+        __m256 xv = _mm256_loadu_ps(x + m);
+        __m256 yv = _mm256_loadu_ps(y + m);
+        __m256 diff = _mm256_sub_ps(xv, yv);
+        acc = _mm256_fmadd_ps(diff, diff, acc);
+    }
+    float result = horizontal_sum_avx2(acc);
+    for (; m < n; ++m) {
+        const float d = x[m] - y[m];
+        result += d * d;
+    }
+    return result;
+}
+
+} // namespace detail
+} // namespace faiss
+
+#endif // COMPILE_SIMD_AVX2

data/vendor/faiss/faiss/utils/simd_impl/super_kmeans_kernels_avx512.cpp

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+#ifdef COMPILE_SIMD_AVX512
+
+#include <faiss/utils/simd_impl/super_kmeans_kernels.h>
+
+#include <immintrin.h>
+
+namespace faiss {
+namespace detail {
+
+template <>
+float block_l2<SIMDLevel::AVX512>(const float* x, const float* y, int n) {
+    __m512 acc = _mm512_setzero_ps();
+    int m = 0;
+    for (; m + 16 <= n; m += 16) {
+        __m512 xv = _mm512_loadu_ps(x + m);
+        __m512 yv = _mm512_loadu_ps(y + m);
+        __m512 diff = _mm512_sub_ps(xv, yv);
+        acc = _mm512_fmadd_ps(diff, diff, acc);
+    }
+    // _mm512_reduce_add_ps: on modern AVX-512 SKUs (Cascade Lake+, Sapphire
+    // Rapids) GCC/Clang lower this to a shuffle+add tree, ~5-cycle latency.
+    // On older AVX-512 SKUs (Skylake-X, Ice Lake) the cross-lane reduction
+    // can be ~20 cycles. Acceptable here because n ~ pdx_block_size = 64
+    // (4 iterations of 16-wide accumulation), so per-block work dominates
+    // the reduction cost. AVX2 uses a manual shuffle+add tree explicitly
+    // to avoid `_mm_hadd_ps` overhead, where the ratio is reversed.
+    float result = _mm512_reduce_add_ps(acc);
+    for (; m < n; ++m) {
+        const float d = x[m] - y[m];
+        result += d * d;
+    }
+    return result;
+}
+
+} // namespace detail
+} // namespace faiss
+
+#endif // COMPILE_SIMD_AVX512

data/vendor/faiss/faiss/utils/simd_levels.cpp

@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+#include <faiss/utils/simd_levels.h>
+
+#include <cstdlib>
+
+#include <faiss/impl/FaissAssert.h>
+#include <faiss/impl/simd_dispatch.h>
+
+namespace faiss {
+
+// Static member definitions - used in both DD and static modes
+SIMDLevel SIMDConfig::level = SIMDLevel::NONE;
+
+// Bitmask of supported SIMD levels (1 << SIMDLevel)
+uint64_t SIMDConfig::supported_simd_levels = 0;
+
+// ARM SVE runtime detection
+#if defined(__aarch64__) || defined(_M_ARM64)
+
+#if defined(__linux__)
+#include <sys/auxv.h>
+#ifndef HWCAP_SVE
+#define HWCAP_SVE (1 << 22)
+#endif
+
+static bool has_sve() {
+    return (getauxval(AT_HWCAP) & HWCAP_SVE) != 0;
+}
+
+#elif defined(__APPLE__)
+// Apple Silicon does NOT support SVE
+static bool has_sve() {
+    return false;
+}
+
+#else
+// Other aarch64 platforms: conservatively report no SVE
+static bool has_sve() {
+    return false;
+}
+
+#endif // __linux__ / __APPLE__ / other
+
+#else // Not ARM64
+[[maybe_unused]] static bool has_sve() {
+    return false;
+}
+#endif
+
+#ifdef FAISS_ENABLE_DD
+
+// =============================================================================
+// Dynamic Dispatch (DD) mode implementation
+// =============================================================================
+
+// Static initializer to run constructor at load time
+// NOLINTNEXTLINE(facebook-avoid-non-const-global-variables)
+static SIMDConfig simd_config_initializer;
+
+SIMDConfig::SIMDConfig(const char** faiss_simd_level_env) {
+    // Support dependency injection for testing
+    const char* env_var = faiss_simd_level_env ? *faiss_simd_level_env
+                                               : getenv("FAISS_SIMD_LEVEL");
+
+    if (!env_var) {
+        level = auto_detect_simd_level();
+    } else {
+        level = to_simd_level(env_var);
+        supported_simd_levels = (1 << static_cast<int>(level));
+    }
+    supported_simd_levels |= (1 << static_cast<int>(SIMDLevel::NONE));
+}
+
+void SIMDConfig::set_level(SIMDLevel l) {
+    if (!is_simd_level_available(l)) {
+        FAISS_THROW_FMT(
+                "SIMDConfig::set_level: level %s is not available",
+                to_string(l).c_str());
+    }
+    level = l;
+}
+
+SIMDLevel SIMDConfig::get_level() {
+    return level;
+}
+
+std::string SIMDConfig::get_level_name() {
+    return to_string(level);
+}
+
+bool SIMDConfig::is_simd_level_available(SIMDLevel l) {
+    return (supported_simd_levels & (1 << static_cast<int>(l))) != 0;
+}
+
+SIMDLevel SIMDConfig::auto_detect_simd_level() {
+    SIMDLevel detected_level = SIMDLevel::NONE;
+
+#if defined(__x86_64__) && \
+        (defined(COMPILE_SIMD_AVX2) || defined(COMPILE_SIMD_AVX512))
+    unsigned int eax, ebx, ecx, edx;
+
+    eax = 1;
+    ecx = 0;
+    asm volatile("cpuid"
+                 : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
+                 : "a"(eax), "c"(ecx));
+
+    bool has_avx = (ecx & (1 << 28)) != 0;
+
+    bool has_xsave_osxsave =
+            (ecx & ((1 << 26) | (1 << 27))) == ((1 << 26) | (1 << 27));
+
+    bool avx_supported = false;
+    if (has_avx && has_xsave_osxsave) {
+        unsigned int xcr0;
+        asm volatile("xgetbv" : "=a"(xcr0), "=d"(edx) : "c"(0));
+        avx_supported = (xcr0 & 6) == 6;
+    }
+
+    if (avx_supported) {
+        eax = 7;
+        ecx = 0;
+        asm volatile("cpuid"
+                     : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
+                     : "a"(eax), "c"(ecx));
+
+        unsigned int xcr0;
+        asm volatile("xgetbv" : "=a"(xcr0), "=d"(edx) : "c"(0));
+
+#if defined(COMPILE_SIMD_AVX2) || defined(COMPILE_SIMD_AVX512)
+        bool has_avx2 = (ebx & (1 << 5)) != 0;
+        if (has_avx2) {
+            supported_simd_levels |= (1 << static_cast<int>(SIMDLevel::AVX2));
+            detected_level = SIMDLevel::AVX2;
+        }
+
+#if defined(COMPILE_SIMD_AVX512)
+        bool cpu_has_avx512f = (ebx & (1 << 16)) != 0;
+        bool os_supports_avx512 = (xcr0 & 0xE0) == 0xE0;
+        bool has_avx512f = cpu_has_avx512f && os_supports_avx512;
+        if (has_avx512f) {
+            bool has_avx512cd = (ebx & (1 << 28)) != 0;
+            bool has_avx512vl = (ebx & (1 << 31)) != 0;
+            bool has_avx512dq = (ebx & (1 << 17)) != 0;
+            bool has_avx512bw = (ebx & (1 << 30)) != 0;
+            if (has_avx512bw && has_avx512cd && has_avx512vl && has_avx512dq) {
+                detected_level = SIMDLevel::AVX512;
+                supported_simd_levels |=
+                        (1 << static_cast<int>(SIMDLevel::AVX512));
+
+#if defined(COMPILE_SIMD_AVX512_SPR)
+                // Check for Sapphire Rapids features (AVX512_BF16)
+                // CPUID EAX=7, ECX=1: EAX bit 5 = AVX512_BF16
+                unsigned int eax1, ebx1, ecx1, edx1;
+                eax1 = 7;
+                ecx1 = 1;
+                asm volatile("cpuid"
+                             : "=a"(eax1), "=b"(ebx1), "=c"(ecx1), "=d"(edx1)
+                             : "a"(eax1), "c"(ecx1));
+                bool has_avx512_bf16 = (eax1 & (1 << 5)) != 0;
+                if (has_avx512_bf16) {
+                    detected_level = SIMDLevel::AVX512_SPR;
+                    supported_simd_levels |=
+                            (1 << static_cast<int>(SIMDLevel::AVX512_SPR));
+                }
+#endif // defined(COMPILE_SIMD_AVX512_SPR)
+            }
+        }
+#endif // defined(COMPILE_SIMD_AVX512)
+#endif // defined(COMPILE_SIMD_AVX2) || defined(COMPILE_SIMD_AVX512)
+    }
+#endif // defined(__x86_64__) && ...
+
+#ifdef COMPILE_SIMD_ARM_NEON
+    // ARM NEON is standard on aarch64
+    supported_simd_levels |= (1 << static_cast<int>(SIMDLevel::ARM_NEON));
+    detected_level = SIMDLevel::ARM_NEON;
+#endif
+
+#ifdef COMPILE_SIMD_ARM_SVE
+    if (has_sve()) {
+        supported_simd_levels |= (1 << static_cast<int>(SIMDLevel::ARM_SVE));
+        detected_level = SIMDLevel::ARM_SVE;
+    }
+#endif
+
+#if defined(__riscv) && defined(COMPILE_SIMD_RISCV_RVV)
+    // RVV is always available on RISC-V builds compiled with rv64gcv.
+    supported_simd_levels |= (1 << static_cast<int>(SIMDLevel::RISCV_RVV));
+    detected_level = SIMDLevel::RISCV_RVV;
+#endif
+
+    return detected_level;
+}
+
+namespace {
+
+template <SIMDLevel Level>
+SIMDLevel get_dispatched_level_impl() {
+    return Level;
+}
+
+} // namespace
+
+SIMDLevel SIMDConfig::get_dispatched_level() {
+    return with_selected_simd_levels<AVAILABLE_SIMD_LEVELS_ALL>(
+            [&]<SIMDLevel SL>() { return get_dispatched_level_impl<SL>(); });
+}
+
+#else // Static mode
+
+// =============================================================================
+// Static mode implementation
+// =============================================================================
+
+// Static initializer to set up the single supported level
+// NOLINTNEXTLINE(facebook-avoid-non-const-global-variables)
+static SIMDConfig simd_config_initializer;
+
+SIMDConfig::SIMDConfig(const char** /* faiss_simd_level_env */) {
+    // In static mode, the level is fixed at compile time
+    level = auto_detect_simd_level();
+    supported_simd_levels = (1 << static_cast<int>(level));
+}
+
+void SIMDConfig::set_level(SIMDLevel l) {
+    if (!is_simd_level_available(l)) {
+        FAISS_THROW_FMT(
+                "SIMDConfig::set_level: level %s is not available "
+                "(static build only supports %s)",
+                to_string(l).c_str(),
+                to_string(level).c_str());
+    }
+    // In static mode, setting to the same level is a no-op
+    level = l;
+}
+
+SIMDLevel SIMDConfig::get_level() {
+    return level;
+}
+
+std::string SIMDConfig::get_level_name() {
+    return to_string(level);
+}
+
+bool SIMDConfig::is_simd_level_available(SIMDLevel l) {
+    return (supported_simd_levels & (1 << static_cast<int>(l))) != 0;
+}
+
+SIMDLevel SIMDConfig::auto_detect_simd_level() {
+    // In static mode, return the compiled-in level
+#if defined(COMPILE_SIMD_AVX512_SPR)
+    return SIMDLevel::AVX512_SPR;
+#elif defined(COMPILE_SIMD_AVX512)
+    return SIMDLevel::AVX512;
+#elif defined(COMPILE_SIMD_AVX2)
+    return SIMDLevel::AVX2;
+#elif defined(COMPILE_SIMD_ARM_SVE)
+    return SIMDLevel::ARM_SVE;
+#elif defined(COMPILE_SIMD_ARM_NEON)
+    return SIMDLevel::ARM_NEON;
+#elif defined(COMPILE_SIMD_RISCV_RVV)
+    return SIMDLevel::RISCV_RVV;
+#else
+    return SIMDLevel::NONE;
+#endif
+}
+
+SIMDLevel SIMDConfig::get_dispatched_level() {
+    // In static mode, just return the current level (no dispatch)
+    return get_level();
+}
+
+#endif // FAISS_ENABLE_DD
+
+// =============================================================================
+// Common functions (both modes)
+// =============================================================================
+
+std::string to_string(SIMDLevel level) {
+    switch (level) {
+        case SIMDLevel::NONE:
+            return "NONE";
+        case SIMDLevel::AVX2:
+            return "AVX2";
+        case SIMDLevel::AVX512:
+            return "AVX512";
+        case SIMDLevel::AVX512_SPR:
+            return "AVX512_SPR";
+        case SIMDLevel::ARM_NEON:
+            return "ARM_NEON";
+        case SIMDLevel::ARM_SVE:
+            return "ARM_SVE";
+        case SIMDLevel::RISCV_RVV:
+            return "RISCV_RVV";
+        case SIMDLevel::COUNT:
+        default:
+            throw FaissException("Invalid SIMDLevel");
+    }
+}
+
+SIMDLevel to_simd_level(const std::string& level_str) {
+    if (level_str == "NONE") {
+        return SIMDLevel::NONE;
+    }
+    if (level_str == "AVX2") {
+        return SIMDLevel::AVX2;
+    }
+    if (level_str == "AVX512") {
+        return SIMDLevel::AVX512;
+    }
+    if (level_str == "AVX512_SPR") {
+        return SIMDLevel::AVX512_SPR;
+    }
+    if (level_str == "ARM_NEON") {
+        return SIMDLevel::ARM_NEON;
+    }
+    if (level_str == "ARM_SVE") {
+        return SIMDLevel::ARM_SVE;
+    }
+    if (level_str == "RISCV_RVV") {
+        return SIMDLevel::RISCV_RVV;
+    }
+
+    throw FaissException("Invalid SIMD level string: " + level_str);
+}
+
+} // namespace faiss

data/vendor/faiss/faiss/utils/simd_levels.h

@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * This source code is licensed under the MIT license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+#pragma once
+
+#include <cstdint>
+#include <string>
+
+#include <faiss/impl/platform_macros.h>
+
+namespace faiss {
+
+#define COMPILE_SIMD_NONE
+
+enum class SIMDLevel {
+    NONE,
+    // x86
+    AVX2,
+    AVX512,
+    AVX512_SPR, // Sapphire Rapids: AVX512 + BF16 + FP16 + VNNI
+    // arm & aarch64
+    ARM_NEON,
+    ARM_SVE, // Scalable Vector Extension (ARMv8.2+)
+    // riscv
+    RISCV_RVV, // RISC-V Vector Extension (rv64gcv)
+
+    COUNT
+};
+
+/***************************************************************
+ * SINGLE_SIMD_LEVEL: the SIMD level for code without explicit SL context.
+ *
+ * In static mode: resolves to the compiled-in level (zero overhead).
+ * In DD mode: resolves to NONE (emulated scalar). Code using
+ * SINGLE_SIMD_LEVEL is meant to be incrementally migrated to use
+ * proper SL dispatch — SINGLE_SIMD_LEVEL is migration scaffolding,
+ * not permanent API.
+ ***************************************************************/
+#ifdef FAISS_ENABLE_DD
+// DD dispatches to the highest optional SIMD level at runtime.
+// On ARM64, NEON is mandatory (always available via COMPILE_SIMD_ARM_NEON),
+// so the baseline is ARM_NEON. On x86, the baseline is NONE.
+#if defined(COMPILE_SIMD_ARM_NEON)
+inline constexpr SIMDLevel SINGLE_SIMD_LEVEL = SIMDLevel::ARM_NEON;
+#else
+inline constexpr SIMDLevel SINGLE_SIMD_LEVEL = SIMDLevel::NONE;
+#endif
+#else
+#if defined(COMPILE_SIMD_AVX512_SPR)
+inline constexpr SIMDLevel SINGLE_SIMD_LEVEL = SIMDLevel::AVX512_SPR;
+#elif defined(COMPILE_SIMD_AVX512)
+inline constexpr SIMDLevel SINGLE_SIMD_LEVEL = SIMDLevel::AVX512;
+#elif defined(COMPILE_SIMD_AVX2)
+inline constexpr SIMDLevel SINGLE_SIMD_LEVEL = SIMDLevel::AVX2;
+#elif defined(COMPILE_SIMD_ARM_SVE)
+inline constexpr SIMDLevel SINGLE_SIMD_LEVEL = SIMDLevel::ARM_SVE;
+#elif defined(COMPILE_SIMD_ARM_NEON)
+inline constexpr SIMDLevel SINGLE_SIMD_LEVEL = SIMDLevel::ARM_NEON;
+#elif defined(COMPILE_SIMD_RISCV_RVV)
+inline constexpr SIMDLevel SINGLE_SIMD_LEVEL = SIMDLevel::RISCV_RVV;
+#else
+inline constexpr SIMDLevel SINGLE_SIMD_LEVEL = SIMDLevel::NONE;
+#endif
+#endif
+
+/***************************************************************
+ * Helper to select the appropriate 256-bit SIMD level.
+ *
+ * For 256-bit SIMD types (simd16uint16, simd32uint8, etc.), maps:
+ *   AVX512/AVX512_SPR → AVX2 (256-bit ops use AVX2 instructions)
+ *   AVX2 → AVX2
+ *   ARM_NEON/ARM_SVE → ARM_NEON
+ *   NONE → NONE
+ ***************************************************************/
+template <SIMDLevel SL>
+struct simd256_level_selector {
+    static constexpr SIMDLevel value =
+            (SL == SIMDLevel::AVX512 || SL == SIMDLevel::AVX512_SPR)
+            ? SIMDLevel::AVX2
+            : (SL == SIMDLevel::ARM_SVE             ? SIMDLevel::ARM_NEON
+                       : SL == SIMDLevel::RISCV_RVV ? SIMDLevel::NONE
+                                                    : SL);
+};
+
+/// SINGLE_SIMD_LEVEL mapped to 256-bit: use this for 256-bit simd types
+/// (simd16uint16, simd32uint8, etc.) which don't have AVX512/SVE
+/// specializations.
+inline constexpr SIMDLevel SINGLE_SIMD_LEVEL_256 =
+        simd256_level_selector<SINGLE_SIMD_LEVEL>::value;
+
+/***************************************************************
+ * Helper to select the appropriate 512-bit SIMD level.
+ *
+ * For 512-bit SIMD types (simd32uint16, simd64uint8, etc.), maps:
+ *   AVX512_SPR → AVX512 (512-bit ops share the same instructions)
+ *   AVX512 → AVX512
+ *   NONE → NONE
+ ***************************************************************/
+template <SIMDLevel SL>
+struct simd512_level_selector {
+    static constexpr SIMDLevel value = (SL == SIMDLevel::AVX512_SPR)
+            ? SIMDLevel::AVX512
+            : (SL == SIMDLevel::RISCV_RVV) ? SIMDLevel::NONE
+                                           : SL;
+};
+
+/// SINGLE_SIMD_LEVEL mapped to 512-bit: use this for 512-bit simd types
+/// (simd32uint16, simd64uint8, etc.) which don't have AVX512_SPR
+/// specializations (AVX512_SPR uses the same 512-bit integer ops as AVX512).
+inline constexpr SIMDLevel SINGLE_SIMD_LEVEL_512 =
+        simd512_level_selector<SINGLE_SIMD_LEVEL>::value;
+
+/// Number of float32 lanes for a given SIMD level.
+/// ARM_SVE is variable-width (128–2048 bits); no single constant is correct.
+template <SIMDLevel SL>
+constexpr int simd_width() {
+    static_assert(
+            SL != SIMDLevel::ARM_SVE,
+            "simd_width<ARM_SVE> is not supported: SVE is variable-width");
+    static_assert(
+            SL != SIMDLevel::RISCV_RVV,
+            "simd_width<RISCV_RVV> is not supported: RVV is variable-width");
+    if constexpr (SL == SIMDLevel::AVX512 || SL == SIMDLevel::AVX512_SPR)
+        return 16;
+    else if constexpr (SL == SIMDLevel::AVX2 || SL == SIMDLevel::ARM_NEON)
+        return 8;
+    else
+        return 1;
+}
+
+/// Convert SIMDLevel to string. Throws FaissException for invalid level.
+std::string to_string(SIMDLevel level);
+
+/// Parse string to SIMDLevel. Throws FaissException for invalid strings.
+SIMDLevel to_simd_level(const std::string& level_str);
+
+/**
+ * Current SIMD configuration.
+ *
+ * This class provides a uniform API for querying and setting the SIMD level,
+ * regardless of whether faiss was built with Dynamic Dispatch (DD) or static
+ * SIMD selection.
+ *
+ * In DD mode:
+ *   - get_level() returns the runtime-detected or user-set level
+ *   - set_level() changes the runtime level (if level is supported)
+ *   - supported_simd_levels() returns bitmask of all compiled-in levels
+ *
+ * In static mode:
+ *   - get_level() returns the compiled-in level
+ *   - set_level() succeeds only if level matches compiled-in level
+ *   - supported_simd_levels() returns bitmask with single level
+ */
+struct FAISS_API SIMDConfig {
+    static SIMDLevel level;
+
+    /// Returns bitmask of supported SIMD levels (1 << SIMDLevel).
+    static uint64_t supported_simd_levels;
+
+    static SIMDLevel auto_detect_simd_level();
+
+    SIMDConfig(const char** faiss_simd_level_env = nullptr);
+
+    /// Set the SIMD level. Throws FaissException if level is not supported.
+    static void set_level(SIMDLevel level);
+    static SIMDLevel get_level();
+    static std::string get_level_name();
+
+    /// Check if a SIMD level is available (compiled in).
+    static bool is_simd_level_available(SIMDLevel level);
+
+    /// Returns the SIMD level via the dispatch mechanism.
+    /// In DD mode, uses with_simd_level internally.
+    /// In static mode, returns the compiled-in level.
+    /// Useful for verification: get_level() == get_dispatched_level()
+    static SIMDLevel get_dispatched_level();
+};
+
+} // namespace faiss