ecic 0.3.0 → 0.4.0
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- checksums.yaml +4 -4
- data/Gemfile.lock +1 -1
- data/README.md +18 -14
- data/config/locales/help.en.yaml +17 -3
- data/lib/ecic.rb +1 -0
- data/lib/ecic/cli.rb +6 -4
- data/lib/ecic/design_generator.rb +32 -0
- data/lib/ecic/generate.rb +44 -4
- data/lib/ecic/library.rb +2 -0
- data/lib/ecic/project.rb +9 -7
- data/lib/ecic/version.rb +1 -1
- data/templates/project/src/design/lib/arc_rtl.vhd.tt +0 -0
- data/templates/project/src/design/lib/ent.vhd.tt +0 -0
- data/templates/project/src/design/lib/pkg_comp.vhd.tt +0 -0
- data/templates/project/src/design/lib/pkg_types.vhd.tt +0 -0
- metadata +7 -2
checksums.yaml
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data/Gemfile.lock
CHANGED
data/README.md
CHANGED
@@ -64,9 +64,9 @@ To see the full list of options for the `ecic generate library` command, run `ec
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### Create new RTL file
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-
Creating a **new** RTL design can be done with the `ecic generate design` command. For VHDL designs, this command will generate both the component, entity and architecture and for SystemVerilog it will create a module. If you already have existing RTL design files you wish to add to the project, you should use the `ecic add design` command instead, see the
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Creating a **new** RTL design can be done with the `ecic generate design` command. For VHDL designs, this command will generate both the component, entity and architecture and for SystemVerilog it will create a module. If you already have existing RTL design files you wish to add to the project, you should use the `ecic add design` command instead, see the `Add existing RTL files` section.
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-
The type of RTL design (VHDL or Verilog) to create is controlled by a `--type=vhdl|
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The type of RTL design (VHDL or Verilog) to create is controlled by a `--type=vhdl|sv` option and defaults to the value defined by the `config.generator.library.type.default` setting in the `./src/config/ecic.rb` configuratinon file.
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The `ecic generate design` command can be called from any directory within your project. To see the full list of options for the `ecic generate design` command, run `ecic generate help design`.
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@@ -82,17 +82,19 @@ When creating a new VHDL design, you will be given the option to also create and
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The following VHDL files will be created (relative to the project root folder):
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./src/design/my_lib/my_design1-
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./src/design/my_lib/my_design1-pkg_types.vhd # Types and constants definition package (optional)
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./src/design/my_lib/my_design1-pkg_comp.vhd # Component definition
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./src/design/my_lib/my_design1-ent.vhd # Entity definition
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./src/design/my_lib/my_design1-
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./src/design/my_lib/my_design1-pkg-types.vhd # Types and constants definition package (optional)
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./src/design/my_lib/my_design1-arc_rtl.vhd # RTL architecture
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Placing each component, entity and architecture in separate files allows a projects to be recompiled very fast when only a few files have been modified, since eg. an update that is isolated to a single RTL architecture only requires that one file to be recompiled. Splitting the entity and architecture into separate files also allows you to have multiple architectures for the save entity and choose between the architecture files at compile time without having to use `VHDL configuration` constructs.
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Should you still wish to combine eg. the entity and architecture files into one file, you can configure `ECIC` to do this by default by setting `config.generator.design.vhdl.combine` option in `./src/config/ecic.rb
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Should you still wish to combine eg. the entity and architecture files into one file, you can configure `ECIC` to do this by default by setting the `config.generator.design.vhdl.combine` option in `./src/config/ecic.rb`, eg.:
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config.generator.design.vhdl.combine = 'entity + architecture'
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This would result in a file with a `-ent-arc_rtl.vhd` extention for the file containing both the entity and architecture.
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##### Create multiple VHDL design for the same library
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You can create multiple designs at the same time, and designs can be placed in subfolders within a library. For example, to create a new VHDL design called `my_design2` at the root of a library called `my_lib` and create another VHDL design called `my_design3` in a subfolder called `my_subblock`, run:
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This will create the following VHDL files (relative to the project root folder):
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./src/design/my_lib/my_design2-
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./src/design/my_lib/my_design2-pkg_types.vhd # Types and constants definition package (optional)
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./src/design/my_lib/my_design2-pkg_comp.vhd # Component definition
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./src/design/my_lib/my_design2-ent.vhd # Entity definition
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./src/design/my_lib/my_design2-
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./src/design/my_lib/
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./src/design/my_lib/my_subblock/my_design3-
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./src/design/my_lib/my_design2-arc_rtl.vhd # RTL architecture
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./src/design/my_lib/my_subblock/my_design3-pkg_types.vhd # Types and constants definition package (optional)
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./src/design/my_lib/my_subblock/my_design3-pkg_comp.vhd # Component definition
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./src/design/my_lib/my_subblock/my_design3-ent.vhd # Entity definition
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./src/design/my_lib/my_subblock/my_design3-
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./src/design/my_lib/my_subblock/my_design3-pkg-types.vhd # Types and constants definition package (optional)
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./src/design/my_lib/my_subblock/my_design3-arc_rtl.vhd # RTL architecture
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In this example the `--types-package` option is used to automatically include the `*-pkg-types.vhd` files without prompting the user with the option.
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@@ -131,7 +133,7 @@ All generated SystemVerilog files will be added to the `sources.rb` file in the
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#### Omitting the --lib option
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If the `ecic generate design` command is called from within a library folder (or subfolder)
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If the `ecic generate design` command is called from within a library folder (or subfolder) and the `--lib` option is omitted, the new designs will be created for the library in that folder.
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Example:
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@@ -140,7 +142,9 @@ Example:
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That will generate the files as:
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-
./src/design/queue_system/
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./src/design/queue_system/statemachine-*.vhd #Path is relative to the project root folder
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Note that even though the current working directory in this example is `arbitor`, the generated files will be placed in the `queue_system` folder, since no hierarchy is included in the design name.
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## Migrating an existing project to use ECIC
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data/config/locales/help.en.yaml
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@@ -35,11 +35,11 @@ help:
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script:
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short: Generate script that can be eval to setup auto-completion
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long:
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long: |
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To use, add the following to your ~/.bashrc or ~/.profile
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eval $(ecic completion script)
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-
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generate:
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short: Generate new testbenches, RTL modules, tests etc.!
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testbench:
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@@ -60,4 +60,18 @@ help:
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Example: ecic generate library lib1 lib2 lib3...
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This creates the given libraries in the ./src/design/ directory of
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your project and adds the libraries to ./src/config/libraries.rb
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your project and adds the libraries to ./src/config/libraries.rb
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design:
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short: Create a new RTL design
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long: |
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Create a new VHDL/SystemVerilog design.
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Example: ecic generate design --type=vhdl --library=some_lib design1 sub_block/design2
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This creates the component, entity and architecture files for two designs called 'design1' and 'design2'.
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An optional types and constants definition file may also be created for each design.
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The files for 'design1' will be placed under 'src/design/some_lib' whereas the files for 'design2'
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will be placed in 'src/design/some_lib/sub_block'.
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The RTL files are automatically added to the project and the given library will be created and added as well if needed.
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data/lib/ecic.rb
CHANGED
@@ -23,6 +23,7 @@ module Ecic
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autoload :Generate, "ecic/generate"
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autoload :Completion, "ecic/completion"
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autoload :Completer, "ecic/completer"
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autoload :DesignGenerator, "ecic/design_generator"
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autoload :ProjectGenerator, "ecic/project_generator"
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autoload :LibraryGenerator, "ecic/library_generator"
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autoload :Library, "ecic/library"
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data/lib/ecic/cli.rb
CHANGED
@@ -83,10 +83,12 @@ module Ecic
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desc 'libraries', 'Display list of libraries in your project'
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def libraries
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root_dir = Project::root
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-
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-
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-
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-
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if root_dir.nil?
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shell.error "You must be within an ECIC project before calling this command"
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exit(3)
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end
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project = Project.new(root_dir)
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project.load_libraries
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say project.libraries { |lib| "#{lib.to_s}" }.join("\n")
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end
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@@ -0,0 +1,32 @@
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module Ecic
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class DesignGenerator < Thor::Group
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include Thor::Actions
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desc 'Generate a new RTL design'
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attr_writer :library_name, :design_name
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def self.source_root
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File.dirname(__FILE__) + '/../../templates/project'
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end
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# def initialize(project_root_path, lib_name)
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# @destination_root = project_root_path
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# @library_name = lib_name
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# end
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# def create_design_directory
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# empty_directory "src/design/#{@library_name}/#{File.dirname(@design_name)}"
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# end
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def update_src_list
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template("src/design/lib/pkg_types.vhd.tt", "src/design/#{@library_name}/#{@design_name}-pkg_types.vhd")
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template("src/design/lib/pkg_comp.vhd.tt", "src/design/#{@library_name}/#{@design_name}-pkg_comp.vhd")
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template("src/design/lib/ent.vhd.tt", "src/design/#{@library_name}/#{@design_name}-ent.vhd")
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template("src/design/lib/arc_rtl.vhd.tt", "src/design/#{@library_name}/#{@design_name}-arc_rtl.vhd")
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end
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end
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end
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data/lib/ecic/generate.rb
CHANGED
@@ -32,13 +32,53 @@ module Ecic
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names.each { |lib_name|
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generator = LibraryGenerator.new
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generator.destination_root = project_root_path
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-
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-
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generator.invoke_all
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# end
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generator.library_name = lib_name
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generator.invoke_all
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}
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end
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end
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#--------------------------------------------------------------------------
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# design generator:
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#--------------------------------------------------------------------------
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desc "design NAME...", Help.text('generate')['design']['short']
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long_desc Help.text('generate')['design']['long']
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option :just_print, :type => :boolean, :aliases => '-n', :desc => "Don't actually run any commands; just print them."
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option :type, :type => :string, :banner => 'vhdl|sv', :required => true, :desc => 'Speficy the RTL type (VHDL or Verilog/SystemVerilog)'
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option :lib, :type => :string, :banner => 'LIBRARY_NAME', :required => true, :desc => 'Speficy the RTL type (VHDL or Verilog/SystemVerilog)'
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def design(*names)
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lib_name = options[:lib]
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type = options[:type]
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root_dir = Project::root
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if root_dir.nil?
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shell.error "You must be within an ECIC project before calling this command"
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exit(1)
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end
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project = Project.new(root_dir)
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project.load_libraries
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# p project.libraries
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unless project.libraries.any? {|l| l.name == lib_name }
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if yes?("Library '#{lib_name}' does not exist. Create it?")
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generator = LibraryGenerator.new
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generator.destination_root = root_dir
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generator.library_name = lib_name
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generator.invoke_all
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else
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shell.error "Operation aborted!"
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exit(2)
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end
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end
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names.each { |design_name|
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# shell.say "Generating '#{design_name}' design in #{lib_name} ..."
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generator = DesignGenerator.new
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# shell.error "DesignGenerator could not be created" if generator.nil?
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generator.destination_root = root_dir
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generator.library_name = lib_name
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generator.design_name = design_name
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generator.invoke_all
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}
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end
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end
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end
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data/lib/ecic/library.rb
CHANGED
data/lib/ecic/project.rb
CHANGED
@@ -6,17 +6,14 @@ module Ecic
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require 'pathname'
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-
def initialize
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def initialize(root = Project::root)
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@libraries = []
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@root = root
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end
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SCRIPT_ECIC = File.join('src', 'config', 'ecic.rb')
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LIBRARIES_CFG_SCRIPT = File.join('src', 'config', 'libraries.rb')
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-
def self.library_cfg_file(root = Project::root)
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File.join(root, LIBRARIES_CFG_SCRIPT)
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-
end
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-
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#Function that returns the root directory of a ECIC project
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def self.root(path = Pathname.new(Dir.pwd))
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if File.exists?(File.join(path, SCRIPT_ECIC))
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@@ -26,10 +23,15 @@ module Ecic
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end
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return root(path.parent)
|
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end
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+
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def default_library_cfg_file
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File.join(@root, LIBRARIES_CFG_SCRIPT)
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end
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30
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-
def load_libraries(lib_file)
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def load_libraries(lib_file = default_library_cfg_file)
|
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if File.exists?(lib_file)
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-
puts "Reading #{lib_file}"
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# puts "Reading #{lib_file}"
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eval File.read(lib_file)
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else
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raise "Could not read library definitions from #{lib_file}"
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data/lib/ecic/version.rb
CHANGED
File without changes
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File without changes
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File without changes
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File without changes
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metadata
CHANGED
@@ -1,14 +1,14 @@
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1
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--- !ruby/object:Gem::Specification
|
2
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name: ecic
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version: !ruby/object:Gem::Version
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-
version: 0.
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+
version: 0.4.0
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platform: ruby
|
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authors:
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- Torben Fox Jacobsen
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autorequire:
|
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bindir: exe
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cert_chain: []
|
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-
date: 2018-10-
|
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+
date: 2018-10-11 00:00:00.000000000 Z
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dependencies:
|
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- !ruby/object:Gem::Dependency
|
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name: thor
|
@@ -140,6 +140,7 @@ files:
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- lib/ecic/completer/script.rb
|
141
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- lib/ecic/completer/script.sh
|
142
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- lib/ecic/completion.rb
|
143
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+
- lib/ecic/design_generator.rb
|
143
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- lib/ecic/generate.rb
|
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- lib/ecic/help.rb
|
145
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- lib/ecic/library.rb
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@@ -155,6 +156,10 @@ files:
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156
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- templates/project/config/libraries.rb
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- templates/project/config/project.rb
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157
158
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- templates/project/gitignore
|
159
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+
- templates/project/src/design/lib/arc_rtl.vhd.tt
|
160
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+
- templates/project/src/design/lib/ent.vhd.tt
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161
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+
- templates/project/src/design/lib/pkg_comp.vhd.tt
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162
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+
- templates/project/src/design/lib/pkg_types.vhd.tt
|
158
163
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- templates/project/src/design/lib/sources.rb
|
159
164
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homepage: https://github.com/ic-factory/ecic
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160
165
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licenses:
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