ceedling 0.29.0 → 0.30.0

data/vendor/cmock/test/iar/iar_v4/srcIAR/Cstartup_SAM7.c

@@ -1,98 +1,98 @@
-// ----------------------------------------------------------------------------
-//         ATMEL Microcontroller Software Support  -  ROUSSET  -
-// ----------------------------------------------------------------------------
-// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ----------------------------------------------------------------------------
-// File Name           : Cstartup_SAM7.c
-// Object              : Low level initialisations written in C for IAR Tools
-// Creation            : FBr   01-Sep-2005
-// 1.0 08-Sep-2005 JPP : Suppress Reset
-// ----------------------------------------------------------------------------
-
-#include "AT91SAM7X256.h"
-
-// The following functions must be write in ARM mode this function called directly by exception vector
-extern void AT91F_Spurious_handler(void);
-extern void AT91F_Default_IRQ_handler(void);
-extern void AT91F_Default_FIQ_handler(void);
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_LowLevelInit
-//* \brief This function performs very low level HW initialization
-//*        this function can use a Stack, depending the compilation
-//*        optimization mode
-//*----------------------------------------------------------------------------
-void AT91F_LowLevelInit(void)
-{
-    unsigned char i;
-    /////////////////////////////////////////////////////////////////////////////////////////////////////
-    // EFC Init
-    /////////////////////////////////////////////////////////////////////////////////////////////////////
-    AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS;      // 1 Wait State necessary to work at 48MHz
-
-    /////////////////////////////////////////////////////////////////////////////////////////////////////
-    // Init PMC Step 1. Enable Main Oscillator
-    // Main Oscillator startup time is board specific:
-    // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms (0x40 for AT91C_CKGR_OSCOUNT field)
-    /////////////////////////////////////////////////////////////////////////////////////////////////////
-    AT91C_BASE_PMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
-#ifndef SIMULATE
-    // Wait Main Oscillator stabilization
-    while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
-#endif
-
-    /////////////////////////////////////////////////////////////////////////////////////////////////////
-    // Init PMC Step 2.
-    // Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz
-    // PLL Startup time depends on PLL RC filter: worst case is choosen
-    // UDP Clock (48,058MHz) is compliant with the Universal Serial Bus Specification (+/- 0.25% for full speed)
-    /////////////////////////////////////////////////////////////////////////////////////////////////////
-    AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1 | AT91C_CKGR_OUT_0 | AT91C_CKGR_PLLCOUNT |
-      (AT91C_CKGR_MUL & (72 << 16)) | (AT91C_CKGR_DIV & 14);
-#ifndef SIMULATE
-    // Wait for PLL stabilization
-    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
-    // Wait until the master clock is established for the case we already turn on the PLL
-    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
-#endif
-
-    /////////////////////////////////////////////////////////////////////////////////////////////////////
-    // Init PMC Step 3.
-    // Selection of Master Clock MCK (equal to Processor Clock PCK) equal to PLL/2 = 48MHz
-    // The PMC_MCKR register must not be programmed in a single write operation (see. Product Errata Sheet)
-    /////////////////////////////////////////////////////////////////////////////////////////////////////
-    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
-#ifndef SIMULATE
-    // Wait until the master clock is established
-    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
-#endif
-
-    AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
-#ifndef SIMULATE
-    // Wait until the master clock is established
-    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
-#endif
-
-    /////////////////////////////////////////////////////////////////////////////////////////////////////
-    //  Disable Watchdog (write once register)
-    /////////////////////////////////////////////////////////////////////////////////////////////////////
-    AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
-
-    ////////////////////////////////////////////////////////////////////////////////////////////////////
-    //  Init AIC: assign corresponding handler for each interrupt source
-    /////////////////////////////////////////////////////////////////////////////////////////////////////
-    AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
-    for (i = 1; i < 31; i++) {
-        AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
-    }
-    AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler;
-}
+// ----------------------------------------------------------------------------
+//         ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : Cstartup_SAM7.c
+// Object              : Low level initialisations written in C for IAR Tools
+// Creation            : FBr   01-Sep-2005
+// 1.0 08-Sep-2005 JPP : Suppress Reset
+// ----------------------------------------------------------------------------
+
+#include "AT91SAM7X256.h"
+
+// The following functions must be write in ARM mode this function called directly by exception vector
+extern void AT91F_Spurious_handler(void);
+extern void AT91F_Default_IRQ_handler(void);
+extern void AT91F_Default_FIQ_handler(void);
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_LowLevelInit
+//* \brief This function performs very low level HW initialization
+//*        this function can use a Stack, depending the compilation
+//*        optimization mode
+//*----------------------------------------------------------------------------
+void AT91F_LowLevelInit(void)
+{
+    unsigned char i;
+    /////////////////////////////////////////////////////////////////////////////////////////////////////
+    // EFC Init
+    /////////////////////////////////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS;      // 1 Wait State necessary to work at 48MHz
+
+    /////////////////////////////////////////////////////////////////////////////////////////////////////
+    // Init PMC Step 1. Enable Main Oscillator
+    // Main Oscillator startup time is board specific:
+    // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms (0x40 for AT91C_CKGR_OSCOUNT field)
+    /////////////////////////////////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_PMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
+#ifndef SIMULATE
+    // Wait Main Oscillator stabilization
+    while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
+#endif
+
+    /////////////////////////////////////////////////////////////////////////////////////////////////////
+    // Init PMC Step 2.
+    // Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz
+    // PLL Startup time depends on PLL RC filter: worst case is choosen
+    // UDP Clock (48,058MHz) is compliant with the Universal Serial Bus Specification (+/- 0.25% for full speed)
+    /////////////////////////////////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1 | AT91C_CKGR_OUT_0 | AT91C_CKGR_PLLCOUNT |
+      (AT91C_CKGR_MUL & (72 << 16)) | (AT91C_CKGR_DIV & 14);
+#ifndef SIMULATE
+    // Wait for PLL stabilization
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
+    // Wait until the master clock is established for the case we already turn on the PLL
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
+#endif
+
+    /////////////////////////////////////////////////////////////////////////////////////////////////////
+    // Init PMC Step 3.
+    // Selection of Master Clock MCK (equal to Processor Clock PCK) equal to PLL/2 = 48MHz
+    // The PMC_MCKR register must not be programmed in a single write operation (see. Product Errata Sheet)
+    /////////////////////////////////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
+#ifndef SIMULATE
+    // Wait until the master clock is established
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
+#endif
+
+    AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
+#ifndef SIMULATE
+    // Wait until the master clock is established
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
+#endif
+
+    /////////////////////////////////////////////////////////////////////////////////////////////////////
+    //  Disable Watchdog (write once register)
+    /////////////////////////////////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+
+    ////////////////////////////////////////////////////////////////////////////////////////////////////
+    //  Init AIC: assign corresponding handler for each interrupt source
+    /////////////////////////////////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
+    for (i = 1; i < 31; i++) {
+        AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
+    }
+    AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler;
+}

data/vendor/cmock/test/iar/iar_v5/Resource/at91SAM7X256_FLASH.icf

@@ -1,43 +1,43 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__      = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__  = 0x00000100;
-define symbol __ICFEDIT_region_ROM_end__    = 0x0003FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x00200000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x0020FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_svcstack__ = 0x100;
-define symbol __ICFEDIT_size_irqstack__ = 0x100;
-define symbol __ICFEDIT_size_fiqstack__ = 0x40;
-define symbol __ICFEDIT_size_undstack__ = 0x40;
-define symbol __ICFEDIT_size_abtstack__ = 0x40;
-define symbol __ICFEDIT_size_heap__     = 0x400;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
-define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
-define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
-define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
-define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__    { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
-                        block UND_STACK, block ABT_STACK, block HEAP };
-
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__      = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__  = 0x00000100;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0003FFFF;
+define symbol __ICFEDIT_region_RAM_start__  = 0x00200000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x0020FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;
+define symbol __ICFEDIT_size_undstack__ = 0x40;
+define symbol __ICFEDIT_size_abtstack__ = 0x40;
+define symbol __ICFEDIT_size_heap__     = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__    { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+                        block UND_STACK, block ABT_STACK, block HEAP };
+

data/vendor/cmock/test/iar/iar_v5/Resource/at91SAM7X256_RAM.icf

@@ -1,42 +1,42 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__      = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__  = 0x00;
-define symbol __ICFEDIT_region_ROM_end__    = 0x00;
-define symbol __ICFEDIT_region_RAM_start__  = 0x00000100;
-define symbol __ICFEDIT_region_RAM_end__    = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_svcstack__ = 0x100;
-define symbol __ICFEDIT_size_irqstack__ = 0x100;
-define symbol __ICFEDIT_size_fiqstack__ = 0x40;
-define symbol __ICFEDIT_size_undstack__ = 0x40;
-define symbol __ICFEDIT_size_abtstack__ = 0x40;
-define symbol __ICFEDIT_size_heap__     = 0x800;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
-define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
-define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
-define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
-define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__    { readonly section .intvec };
-
-place in RAM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
-                        block UND_STACK, block ABT_STACK, block HEAP };
-
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__      = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__  = 0x00;
+define symbol __ICFEDIT_region_ROM_end__    = 0x00;
+define symbol __ICFEDIT_region_RAM_start__  = 0x00000100;
+define symbol __ICFEDIT_region_RAM_end__    = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;
+define symbol __ICFEDIT_size_undstack__ = 0x40;
+define symbol __ICFEDIT_size_abtstack__ = 0x40;
+define symbol __ICFEDIT_size_heap__     = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__    { readonly section .intvec };
+
+place in RAM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+                        block UND_STACK, block ABT_STACK, block HEAP };
+