breadkit 0.1.0

checksums.yaml

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+---
+SHA256:
+  metadata.gz: 233212f063c6709cfaa93b8243125e71a80fd0bfb75b1904e4b989b40cd68c0a
+  data.tar.gz: e665337ec30e9f01baca29c27d66ab819d4c398533cb97d3d04d4c5a7edbeae6
+SHA512:
+  metadata.gz: 0d0bb60ddd1caba719db069e196aee4babb237b534451276763ca04c5f3c40534ebb17b8727bc7b95b0bdabcbaad44c462d8b20d8331e8f835c65b65e5650518
+  data.tar.gz: 313859b4d73d837d2b734ca2bbc613c263d38efb40ac5b4ec8e6c058863aff52e3a86b1d6f7bbda37062d5452b308ec55783896fbfa6e9561687060733510145

data/LICENSE.txt

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+The MIT License (MIT)
+
+Copyright (c) 2026 Yudai Takada
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.

data/README.md

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+# breadkit
+
+`breadkit` provides the Ruby DSL, board and part definitions, connectivity analysis, and JSON IR used by [`breadkit-render`](https://github.com/breadkit/breadkit-render) and [`breadkit-lint`](https://github.com/breadkit/breadkit-lint).
+
+Project site: https://breadkit.github.io/breadkit/
+
+```sh
+gem install breadkit
+breadkit nets circuit.bk.rb
+breadkit ir circuit.bk.rb > circuit.json
+breadkit parts
+```
+
+Ruby DSL files execute as code. Load only trusted files; use IR JSON for data-only input.
+
+See the [user guide](https://breadkit.github.io/breadkit/guide/), [component catalog](https://breadkit.github.io/breadkit/guide/components/), [DSL reference](https://breadkit.github.io/breadkit/guide/dsl/), and [project design](docs/DESIGN.md).

data/SECURITY.md

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+# Security policy
+
+DSL files are executable Ruby. Do not process files from untrusted sources; use IR JSON for data-only input.
+
+Please report suspected vulnerabilities privately through GitHub's Security Advisories feature. Do not include exploit details in a public issue.

data/data/boards/full.yml

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+id: full
+name: Full-size breadboard (830 tie points)
+terminal:
+  columns: 63
+  rows: [a, b, c, d, e, f, g, h, i, j]
+  groups: [[a, b, c, d, e], [f, g, h, i, j]]
+  ravine_between: [e, f]
+rails:
+  - {id: "T+", side: top, order: 0}
+  - {id: "T-", side: top, order: 1}
+  - {id: "B+", side: bottom, order: 1}
+  - {id: "B-", side: bottom, order: 0}
+rail_layout:
+  holes: 50
+  group_size: 5
+  start_column: 3
+  segments: [[1, 50]]
+  split_segments: [[1, 25], [26, 50]]

data/data/boards/half.yml

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+id: half
+name: Half-size breadboard (400 tie points)
+terminal:
+  columns: 30
+  rows: [a, b, c, d, e, f, g, h, i, j]
+  groups: [[a, b, c, d, e], [f, g, h, i, j]]
+  ravine_between: [e, f]
+rails:
+  - {id: "T+", side: top, order: 0}
+  - {id: "T-", side: top, order: 1}
+  - {id: "B+", side: bottom, order: 1}
+  - {id: "B-", side: bottom, order: 0}
+rail_layout:
+  holes: 25
+  group_size: 5
+  start_column: 2
+  segments: [[1, 25]]

data/data/boards/mini.yml

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+id: mini
+name: Mini breadboard (170 tie points)
+terminal:
+  columns: 17
+  rows: [a, b, c, d, e, f, g, h, i, j]
+  groups: [[a, b, c, d, e], [f, g, h, i, j]]
+  ravine_between: [e, f]
+rails: []

data/data/parts/2n3906.yml

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+# Pin order: https://www.onsemi.com/pdf/datasheet/2n3906-d.pdf
+id: 2n3906
+category: transistor
+transistor_polarity: PNP
+placement: leads
+pins:
+  - {num: 1, name: emitter, aliases: [e]}
+  - {num: 2, name: base, aliases: [b]}
+  - {num: 3, name: collector, aliases: [c]}
+render: {shape: generic}

data/data/parts/arduino_uno.yml

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+id: arduino_uno
+category: offboard
+placement: offboard
+pins:
+  - {num: 1, name: D0}
+  - {num: 2, name: D1}
+  - {num: 3, name: D2}
+  - {num: 4, name: D3}
+  - {num: 5, name: D4}
+  - {num: 6, name: D5}
+  - {num: 7, name: D6}
+  - {num: 8, name: D7}
+  - {num: 9, name: D8}
+  - {num: 10, name: D9}
+  - {num: 11, name: D10}
+  - {num: 12, name: D11}
+  - {num: 13, name: D12}
+  - {num: 14, name: D13}
+  - {num: 15, name: GND, role: ground}
+  - {num: 16, name: 5V, role: power}
+  - {num: 17, name: A0}
+  - {num: 18, name: A1}
+  - {num: 19, name: A2}
+  - {num: 20, name: A3}
+  - {num: 21, name: A4}
+  - {num: 22, name: A5}
+  - {num: 23, name: 3V3, role: power}
+  - {num: 24, name: VIN, role: power}
+  - {num: 25, name: GND2, role: ground}
+  - {num: 26, name: GND3, role: ground}
+  - {num: 27, name: RESET}
+  - {num: 28, name: AREF}
+internal: [[15, 25], [15, 26]]
+render: {shape: offboard, label: Arduino Uno}

data/data/parts/bc547.yml

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+# Pin order: https://www.onsemi.com/pdf/datasheet/bc546-d.pdf
+id: bc547
+category: transistor
+transistor_polarity: NPN
+placement: leads
+pins:
+  - {num: 1, name: collector, aliases: [c]}
+  - {num: 2, name: base, aliases: [b]}
+  - {num: 3, name: emitter, aliases: [e]}
+render: {shape: generic}

data/data/parts/bc557.yml

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+# Pin order: https://www.onsemi.com/download/data-sheet/pdf/bc556b-d.pdf
+id: bc557
+category: transistor
+transistor_polarity: PNP
+placement: leads
+pins:
+  - {num: 1, name: collector, aliases: [c]}
+  - {num: 2, name: base, aliases: [b]}
+  - {num: 3, name: emitter, aliases: [e]}
+render: {shape: generic}

data/data/parts/capacitor.yml

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+id: capacitor
+category: passive
+placement: leads
+pins:
+  - {num: 1, name: "1"}
+  - {num: 2, name: "2"}
+render: {shape: capacitor}

data/data/parts/diode.yml

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+id: diode
+category: diode
+placement: leads
+pins:
+  - {num: 1, name: anode, aliases: [a]}
+  - {num: 2, name: cathode, aliases: [k]}
+polarity: {positive: anode, negative: cathode}
+render: {shape: diode}

data/data/parts/electrolytic.yml

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+id: electrolytic
+category: passive
+placement: leads
+pins:
+  - {num: 1, name: plus, aliases: ["+"]}
+  - {num: 2, name: minus, aliases: ["-"]}
+polarity: {positive: plus, negative: minus}
+render: {shape: electrolytic}

data/data/parts/led.yml

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+id: led
+category: diode
+placement: leads
+pins:
+  - {num: 1, name: anode, aliases: [a, "+"]}
+  - {num: 2, name: cathode, aliases: [k, "-"]}
+polarity: {positive: anode, negative: cathode}
+flags: [needs_series_resistor]
+render: {shape: led_5mm}

data/data/parts/ne555.yml

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+id: ne555
+aliases: [NE555, "555"]
+category: ic
+placement: dip
+package: {pins: 8}
+pins:
+  - {num: 1, name: GND, role: ground}
+  - {num: 2, name: TRIG}
+  - {num: 3, name: OUT}
+  - {num: 4, name: RESET}
+  - {num: 5, name: CTRL}
+  - {num: 6, name: THR}
+  - {num: 7, name: DIS}
+  - {num: 8, name: VCC, role: power}
+supply_range: [4.5, 16.0]
+render: {shape: dip, label: NE555}

data/data/parts/pot.yml

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+id: pot
+category: passive
+placement: footprint
+pins:
+  - {num: 1, name: left}
+  - {num: 2, name: wiper}
+  - {num: 3, name: right}
+footprint:
+  "1": [0, 0]
+  "2": [1, 0]
+  "3": [2, 0]
+render: {shape: generic}

data/data/parts/resistor.yml

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+id: resistor
+category: passive
+placement: leads
+pins:
+  - {num: 1, name: "1"}
+  - {num: 2, name: "2"}
+render: {shape: resistor}

data/data/parts/tact_switch_6mm.yml

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+id: tact_switch_6mm
+aliases: [button]
+category: switch
+placement: footprint
+straddle: true
+pins:
+  - {num: 1, name: "1"}
+  - {num: 2, name: "2"}
+  - {num: 3, name: "3"}
+  - {num: 4, name: "4"}
+footprint:
+  "1": [0, 0]
+  "2": [0, 3]
+  "3": [2, 0]
+  "4": [2, 3]
+internal: [[1, 2], [3, 4]]
+switch: [[1, 3]]
+same_strip_ok: [[1, 2], [3, 4]]
+render: {shape: tact_switch}

data/data/parts/transistor.yml

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+id: transistor
+aliases: [2N3904]
+category: transistor
+transistor_polarity: NPN
+placement: leads
+pins:
+  - {num: 1, name: emitter, aliases: [e]}
+  - {num: 2, name: base, aliases: [b]}
+  - {num: 3, name: collector, aliases: [c]}
+render: {shape: generic}

data/docs/assets/01_led_button.svg

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+<?xml version="1.0" encoding="UTF-8"?>
+<svg xmlns="http://www.w3.org/2000/svg" width="330.00" height="185.00" viewBox="-15.00 -30.00 330.00 185.00" font-family="Helvetica, Arial, 'Noto Sans JP', sans-serif" fill="#222" role="img">
+<title>押しボタンで LED を点灯</title>
+<desc>Breadboard wiring diagram generated by Breadkit.</desc>
+<g id="board"><rect x="-8.00" y="-36.00" width="450.00" height="170.00" rx="12" fill="#dce9ce" stroke="#84917f"/><rect x="-5.00" y="46.00" width="390.00" height="8.00" fill="#b8c6b4"/><line x1="10.00" y1="-20.00" x2="290.00" y2="-20.00" stroke="#d34c49" stroke-width="2.40"/><line x1="10.00" y1="-30.00" x2="290.00" y2="-30.00" stroke="#477fb5" stroke-width="2.40"/><line x1="10.00" y1="120.00" x2="290.00" y2="120.00" stroke="#d34c49" stroke-width="2.40"/><line x1="10.00" y1="110.00" x2="290.00" y2="110.00" stroke="#477fb5" stroke-width="2.40"/></g>
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data/docs/dsl.md

@@ -0,0 +1,62 @@
+# Breadkit DSL
+
+Breadkit evaluates a Ruby file into a breadboard circuit, resolves pin and wire locations, and exposes the result as nets and JSON IR. DSL files are executable Ruby; only load files you trust. Use IR JSON when the input must remain data-only.
+
+## A small circuit
+
+```ruby
+title "Button controlled LED"
+board :half
+supply :USB, voltage: 5, plus: "B+1", minus: "B-1"
+net :VCC, at: "B+1"
+net :GND, at: "B-1"
+
+button :SW1, at: "e10"
+resistor :R1, "330", pins: %w[a12 a16]
+led :D1, color: :red, anode: "b16", cathode: "b17"
+wire "a10", "B+", color: :red
+wire "a17", "B-", color: :black
+
+expect do
+  connected "SW1.1", :VCC
+  isolated :VCC, :GND
+end
+```
+
+## Declarations
+
+| Method | Purpose |
+| --- | --- |
+| `title(text)` | Diagram title. |
+| `board(id, split_rails: false)` | Select `:full`, `:half`, `:mini`, or a custom board ID. |
+| `use_parts(path)` / `use_boards(path)` | Load additional YAML definitions relative to the DSL file. Paths may use globs. |
+| `supply(name, voltage:, plus:, minus:)` | Add a DC source. Both terminals occupy board holes. |
+| `net(name, at:)` | Label a hole or component pin. |
+| `part(ref, type, value = nil, pins: ..., at: ..., **attrs)` | Place a defined part. `pins:` accepts pin order arrays or pin-name hashes. |
+| `wire(from, to, color: nil, id: nil, route: :straight, layer: nil, electrical: true, dashed: false)` | Connect two holes or pin references. `route: :arc` curves the wire; `route: :edge` routes around an outer board edge or from an external module along its terminal row. `layer:` groups wires in interactive SVG output; `electrical: false` draws a visual alternative without changing circuit connectivity. |
+| `offboard(name, type, side: :left, at: nil, unused: [], **attrs)` | Place a module beside the board; `at:` aligns its first pin to a board position, and attrs such as `address:` are shown on the module. |
+| `expect { ... }` | Declare `connected`, `isolated`, or named `net` expectations. `strict: true` also rejects unlisted pins on declared nets. |
+| `lint_disable(rule, on: nil, reason: nil)` | Suppress a lint rule, optionally for one target. |
+
+Short forms are available for `resistor`, `capacitor`, `electrolytic`, `diode`, `led`, `transistor`, `pot`, `button`, and `ic`.
+
+## Hole and pin references
+
+- Terminal holes use rows `a` through `j` and 1-based columns, such as `a10` or `J30`.
+- Rail holes use `T+`, `T-`, `B+`, and `B-`, optionally followed by a 1-based index. A rail without an index selects the nearest free hole.
+- A custom board may define other row and rail IDs in its YAML. For example, rows `u` and `v` use `u1` and `v1`; a rail with `id: PWR` uses `PWR1` or the unindexed `PWR`. Set each rail's `polarity:` to `+` or `-` for polarity-aware rendering.
+- Component pins use `R1.1`, `D1.anode`, `U1.8`, or `U1.VCC`. A wire endpoint naming a placed pin selects a free hole in that pin's conductive strip.
+- The built-in `ne555` and generic `dip` definitions must straddle the center gap. For a generic package, set `pin_count`, for example `part :U2, :dip, pin_count: 14, at: "e20"`.
+- A generic pin header can be sized with `part :J1, :pin_header, pin_count: 4, pins: %w[a1 a2 a3 a4]`.
+
+Values accept SI suffixes and RKM notation such as `4.7k`, `4k7`, `1M`, `100n`, `10uF`, and `4.7kΩ`.
+
+## Switch states and IR
+
+`circuit.states("none")`, `circuit.states("single")`, and `circuit.states("all")` control switch contact simulation. `Breadkit.load(path)` reads `.bk.rb` DSL or `.json` IR. `circuit.to_ir` returns the resolved circuit representation; automatically selected holes are fixed in IR and are not selected again when loaded.
+
+The core CLI provides `breadkit nets`, `breadkit parts`, and `breadkit ir`.
+
+Custom module pins can declare their kind with `type:` in the part YAML, for example `power`, `ground`, `clock`, `data`, `address`, or `interrupt`. The renderer colors typed pin markers and dims pins without a wire connection.
+
+Assign the same `layer:` to wires and components to make them appear together in the interactive SVG layer controls. A layer may be a string or a list of strings when an item belongs to multiple views. Components without a layer remain visible in every view. Use `electrical: false, dashed: true` for an alternate connection that must not affect connectivity analysis.

data/exe/breadkit

@@ -0,0 +1,5 @@
+#!/usr/bin/env ruby
+# frozen_string_literal: true
+
+require "breadkit"
+exit Breadkit::CLI.new.run(ARGV)