badline 0.8.0 → 0.10.0

data/lib/badline/roms/README

@@ -17,6 +17,16 @@ character.rom
 -------------
 The character generator ROM.
 
+kernal-sx64.rom
+---------------
+The SX-64's KERNAL, 251104-04. It boots with the SX-64's banner and
+colours, and loads from device 8 rather than tape. Computer.new(kernal:
+:sx64) fits it, as --model sx64 does.
+
+Downloaded from
+https://www.zimmers.net/anonftp/pub/cbm/firmware/computers/c64/kernal.sx.251104-04.bin
+SHA-1 aa136e91ecf3c5ac64f696b3dbcbfc5ba0871c98.
+
 dos1541.rom
 -----------
 The 1541 disk drive's DOS 2.6, 16 KB for $C000-$FFFF: 325302-01
@@ -26,3 +36,30 @@ Both halves downloaded from
 https://www.zimmers.net/anonftp/pub/cbm/firmware/drives/new/1541/
 (1541-c000.325302-01.bin and 1541-e000.901229-05.bin) and concatenated.
 SHA-1 ab16f56989b27d89babe5f89c5a8cb3da71a82f0.
+
+Commodore VIC-20 ROMs
+=====================
+
+Downloaded from
+https://www.zimmers.net/anonftp/pub/cbm/firmware/computers/vic20/
+Vic20::Bus maps them.
+
+vic20/basic.rom
+---------------
+VIC-20 BASIC V2, 901486-01, for $C000-$DFFF.
+SHA-1 587d1e90950675ab6b12d91248a3f0d640d02e8d.
+
+vic20/kernal-pal.rom
+--------------------
+The PAL KERNAL, 901486-07, for $E000-$FFFF.
+SHA-1 ce0137ed69f003a299f43538fa9eee27898e621e.
+
+vic20/kernal-ntsc.rom
+---------------------
+The NTSC KERNAL, 901486-06, for $E000-$FFFF.
+SHA-1 06de7ec017a5e78bd6746d89c2ecebb646efeb19.
+
+vic20/character.rom
+-------------------
+The character generator ROM, 901460-03, for $8000-$8FFF.
+SHA-1 4fd85ab6647ee2ac7ba40f729323f2472d35b9b4.

data/lib/badline/sid/decimator.rb

@@ -22,6 +22,19 @@ module Badline
       # Cycles until the current window closes, counting the next one as 1.
       attr_reader :cycles_to_close
 
+      # How far the current window has got. The clock and the rate are the
+      # host's.
+      def save_state(out)
+        out.int(@phase).int(@sum).int(@count).int(@cycles_to_close)
+      end
+
+      def load_state(input)
+        @phase = input.int
+        @sum = input.int
+        @count = input.int
+        @cycles_to_close = input.int
+      end
+
       # Returns the averaged sample when these cycles close a window, and
       # nil otherwise. They must not run past the window's end.
       def push(sample, cycles = 1)

data/lib/badline/sid/filter.rb

@@ -101,10 +101,13 @@ module Badline
         end
 
         # Takes the input in 1/2^Filter::FRACTION units, and reads the
-        # output out in whole ones.
+        # output out in whole ones. A step of several cycles moves each pole
+        # at most onto its input.
         def cycle!(input, cycles = 1)
-          delta_lowpass = ((W0_LOWPASS >> 8) * cycles * ((input << INPUT_SHIFT) - @lowpass)) >> 12
-          delta_highpass = (W0_HIGHPASS * cycles * (@lowpass - @highpass)) >> 20
+          w0_lowpass = [(W0_LOWPASS >> 8) * cycles, 1 << 12].min
+          w0_highpass = [W0_HIGHPASS * cycles, 1 << 20].min
+          delta_lowpass = (w0_lowpass * ((input << INPUT_SHIFT) - @lowpass)) >> 12
+          delta_highpass = (w0_highpass * (@lowpass - @highpass)) >> 20
           @output = (@lowpass - @highpass) >> FRACTION
           @lowpass += delta_lowpass
           @highpass += delta_highpass

data/lib/badline/sid.rb

@@ -127,6 +127,25 @@ module Badline
       @samples = []
     end
 
+    # How far the recording has got into the sample it is averaging, for
+    # a host that carries on recording from a saved state: it calls
+    # #record, then #load_recording.
+    def save_recording(out)
+      decimator = @decimator
+      raise ArgumentError, "the SID isn't recording" if decimator.nil?
+
+      out.marker("RECORDING")
+      decimator.save_state(out)
+    end
+
+    def load_recording(input)
+      decimator = @decimator
+      raise ArgumentError, "the SID isn't recording" if decimator.nil?
+
+      input.marker("RECORDING")
+      decimator.load_state(input)
+    end
+
     # Also keeps each voice's own output, before the filter and the volume,
     # as each recorded sample closes, for #drain_voice_samples.
     def record_voices!

data/lib/badline/snapshot/container.rb

@@ -26,6 +26,8 @@ module Badline
       FORMAT_MINOR = 0
       # x64sc names its machine C64SC, and refuses a snapshot naming another.
       MACHINE = "C64SC"
+      # xvic names its machine VIC20.
+      VIC20 = "VIC20"
       GZIP_MAGIC = "\x1f\x8b".b
 
       # The VICE version block, when VICE wrote the file: four version

data/lib/badline/snapshot/fields.rb

@@ -38,6 +38,7 @@ module Badline
       def qword = take(8).unpack1("Q<").to_i
       def flag? = !byte.zero?
       def bytes(count) = take(count).bytes
+      def string(count) = take(count)
       def skip(count) = tap { take(count) }
 
       private

data/lib/badline/snapshot/image.rb

@@ -28,11 +28,16 @@ module Badline
       # modules badline reads. Yields a line for each thing left out, or
       # warns it without a block.
       def load(&)
+        return load_vic20(&) if vic20?
+
         computer = badline? ? opening { Computer.restored(state) } : Vice.setup(@container).build
         tell(badline? ? state_report(computer) : Vice::Restore.apply(@container, computer), &)
         computer
       end
 
+      # Whether the machine is a VIC-20, as the container names it.
+      def vic20? = @container.machine == Container::VIC20
+
       # Restores `computer` from the snapshot, and returns the Report. A
       # snapshot that fails leaves the machine as it was.
       def restore(computer, &)
@@ -45,6 +50,16 @@ module Badline
 
       def section = @container[MachineState::NAME]
 
+      # A VIC-20 restores from its BADLINE module alone. xvic's own modules
+      # aren't read.
+      def load_vic20(&)
+        raise FormatError, "badline reads only its own VIC-20 snapshots, not xvic's" unless badline?
+
+        machine = Vic20.restored(state)
+        tell(state_report(machine), &)
+        machine
+      end
+
       def tell(report)
         report.ignored.each { |line| block_given? ? yield(line) : warn("badline: #{line}") }
       end

data/lib/badline/snapshot/setup.rb

@@ -3,27 +3,32 @@
 module Badline
   module Snapshot
     # How a machine was built: its VIC, CIA and SID models, its region, its
-    # RAM expansion and the size of its REU, the arguments Computer.new
-    # takes. A State starts with them, so a machine to restore it into can
+    # RAM expansion, the size of its REU, its KERNAL and whether it has a
+    # datasette, the arguments Computer.new takes. A State starts with them, so a machine to restore it into can
     # be built first.
-    Setup = Data.define(:vic_model, :cia_model, :sid_model, :region, :ram_expansion, :reu)
+    Setup = Data.define(:vic_model, :cia_model, :sid_model, :region, :ram_expansion, :reu, :kernal, :datasette)
 
     class Setup
       SID_MODELS = %i[mos6581 mos8580].freeze
-      REGIONS = [Region::PAL, Region::NTSC].freeze
+      REGIONS = [Region::PAL, Region::NTSC, Region::NTSC_OLD, Region::DREAN].freeze
       RAM_EXPANSIONS = [:none, *RAMExpansion::TYPES.keys].freeze
+      KERNALS = AddressBus::ROMs::KERNALS.keys.freeze
 
       def self.of(address_bus)
         new(vic_model: address_bus.vic.model, cia_model: address_bus.cia1.model, sid_model: address_bus.sid.model,
-            region: address_bus.region, ram_expansion: address_bus.ram_expansion.type, reu: address_bus.reu&.size_kb)
+            region: address_bus.region, ram_expansion: address_bus.ram_expansion.type, reu: address_bus.reu&.size_kb,
+            kernal: address_bus.kernal, datasette: address_bus.datasette.connected?)
       end
 
+      # Layout 3 has no KERNAL or datasette, and stands for the C64's.
       def self.read(input)
         new(vic_model: VIC::MODELS.fetch(input.int), cia_model: CIA::MODELS.fetch(input.int),
             sid_model: SID_MODELS.fetch(input.int), region: REGIONS.fetch(input.int),
-            ram_expansion: ram_expansion(RAM_EXPANSIONS.fetch(input.int)), reu: reu(input.int))
+            ram_expansion: ram_expansion(RAM_EXPANSIONS.fetch(input.int)), reu: reu(input.int),
+            kernal: input.schema > 3 ? KERNALS.fetch(input.int) : :c64,
+            datasette: input.schema > 3 ? input.boolean? : true)
       rescue IndexError
-        raise FormatError, "the state names a chip model, region or RAM expansion badline doesn't know"
+        raise FormatError, "the state names a chip model, region, RAM expansion or KERNAL badline doesn't know"
       end
 
       def self.ram_expansion(name) = name == :none ? nil : name
@@ -40,17 +45,24 @@ module Badline
         out.int(VIC::MODELS.index(vic_model)).int(CIA::MODELS.index(cia_model))
         out.int(SID_MODELS.index(sid_model)).int(REGIONS.index(region))
         out.int(RAM_EXPANSIONS.index(ram_expansion || :none)).int(reu || 0)
+        out.int(KERNALS.index(kernal)).boolean(datasette)
       end
 
       # A machine built this way, at power-on.
       def build
-        Computer.new(vic_model:, cia_model:, sid_model:, region:, ram_expansion:, reu:)
+        Computer.new(vic_model:, cia_model:, sid_model:, region:, ram_expansion:, reu:, kernal:, datasette:)
       end
 
+      # The chips, led by the model's name when they make one of
+      # Badline::Model's.
       def to_s
+        model = Model.of(self)
         parts = [vic_model, cia_model, sid_model, region.name]
+        parts.unshift(model.name) if model
         parts << ram_expansion if ram_expansion
         parts << "a #{reu}K REU" if reu
+        parts << "the #{kernal} KERNAL" unless kernal == :c64
+        parts << "no datasette" unless datasette
         parts.join(", ")
       end
     end

data/lib/badline/snapshot/state.rb

@@ -13,8 +13,11 @@ module Badline
     class State
       # The layout the chips write their fields in. It goes up whenever a
       # save_state writes something else, so a State in another layout
-      # fails before anything is read into a machine.
-      SCHEMA = 2
+      # fails before anything is read into a machine. Layout 3, without the
+      # KERNAL and datasette in the setup, and layout 4, without the VIA
+      # shift register's clock delay, still read.
+      SCHEMA = 5
+      READABLE = [3, 4, SCHEMA].freeze
 
       attr_reader :values, :strings
 
@@ -101,15 +104,19 @@ module Badline
     # A detached reader restores a machine that opens no host file and
     # writes none, for a copy the machine runs on its own: a disk image
     # comes from the bytes the state holds, write-protected, a directory
-    # or .t64 archive device 8 serves and a tape are left out, and a true
-    # drive's disk keeps the state's tracks without its image file.
+    # device 8 serves is left out, and a true drive's disk keeps the
+    # state's tracks without its image file.
     class StateReader
+      # The layout check_stamp found.
+      attr_reader :schema
+
       def initialize(state, detached: false)
         @values = state.values
         @strings = state.strings
         @value = 0
         @string = 0
         @detached = detached
+        @schema = State::SCHEMA
       end
 
       def detached? = @detached
@@ -160,12 +167,13 @@ module Badline
         raise FormatError, "expected #{name} in the state, found #{found[0, 20].inspect}" unless found == name
       end
 
-      # Fails unless the State was written in this layout by this badline
-      # version.
+      # Fails unless the State was written in a layout this badline reads
+      # (State::READABLE) by this badline version.
       def check_stamp
         schema = int
         version = string
-        return if schema == State::SCHEMA && version == VERSION
+        @schema = schema
+        return if State::READABLE.include?(schema) && version == VERSION
 
         raise FormatError, "the state was written by badline #{version.inspect} in layout #{schema}, " \
                            "and this is badline #{VERSION}, layout #{State::SCHEMA}"

data/lib/badline/snapshot/vice/main_cpu.rb

@@ -45,7 +45,7 @@ module Badline
         end
 
         def interrupts(computer, fields)
-          irqs = [computer.vic.interrupted?, computer.cia1.interrupted?].count(true)
+          irqs = [computer.vic.interrupted?, computer.cia1.interrupted?, computer.reu&.irq? || false].count(true)
           nmis = computer.cia2.interrupted? ? 1 : 0
           pending = (irqs.positive? ? IK_IRQ : 0) | (computer.cpu.nmi ? IK_NMI : 0)
           fields.dword(irqs).dword(nmis).dword(pending)

data/lib/badline/snapshot/vice/peripherals.rb

@@ -9,7 +9,8 @@ module Badline
       # control ports and the user port. Each is written as a machine with
       # nothing attached leaves it, with the joysticks released and the
       # glue logic's VIC bank taken from CIA 2. A cartridge or tape badline
-      # has attached is carried by the BADLINE module only.
+      # has attached is carried by the BADLINE module only, and an REU by
+      # REU1764 as well.
       module Peripherals
         # The glue logic's VIC bank, and its pending bank change.
         GLUE = "GLUE"
@@ -29,7 +30,16 @@ module Badline
 
         module_function
 
-        def cartridge_port = section(*FIXED[0])
+        # C64CART 0.1 lists the REU as the one cartridge in the port when
+        # there is one, which REU1764 follows: no main slot cartridge, the
+        # lines inactive, no freeze or NMI pending, then the REU's id.
+        def cartridge_port(computer)
+          return section(*FIXED[0]) unless computer.reu
+
+          fields = FieldWriter.new.byte(1).dword(-1).byte(0).byte(0).dword(0).dword(0).byte(0).byte(0).byte(0)
+          fields.qword(-1).qword(-1).zeros(12 + 16).dword(REU1764::CARTRIDGE_ID)
+          fields.section("C64CART", 0, 1)
+        end
 
         def drives = section(*FIXED[1])
 

data/lib/badline/snapshot/vice/restore.rb

@@ -11,7 +11,7 @@ module Badline
         # MAINCPU and C64MEM hold the machine itself, so a version badline
         # doesn't read fails the restore; the others are left out and
         # reported.
-        READ = [MainCPU::NAME, C64Mem::NAME, "CIA1", "CIA2", SIDRegisters::NAME, SIDExtended::NAME,
+        READ = [MainCPU::NAME, C64Mem::NAME, REU1764::NAME, "CIA1", "CIA2", SIDRegisters::NAME, SIDExtended::NAME,
                 VICII::NAME].freeze
         REQUIRED = [MainCPU::NAME, C64Mem::NAME].freeze
 
@@ -83,6 +83,7 @@ module Badline
           case name
           when MainCPU::NAME then MainCPU.reads?(section)
           when C64Mem::NAME then C64Mem.reads?(section)
+          when REU1764::NAME then REU1764.reads?(section)
           when SIDRegisters::NAME then SIDRegisters.reads?(section)
           when SIDExtended::NAME then SIDExtended.reads?(section)
           when VICII::NAME then VICII.reads?(section)
@@ -94,6 +95,7 @@ module Badline
           case name
           when MainCPU::NAME then MainCPU.import(section, computer)
           when C64Mem::NAME then C64Mem.import(section, computer)
+          when REU1764::NAME then REU1764.import(section, computer)
           when SIDRegisters::NAME then SIDRegisters.import(section, computer)
           when SIDExtended::NAME then SIDExtended.import(section, computer)
           when VICII::NAME then VICII.import(section, computer)

data/lib/badline/snapshot/vice/reu1764.rb

@@ -0,0 +1,55 @@
+# frozen_string_literal: true
+
+module Badline
+  module Snapshot
+    module Vice
+      # REU1764 0.0, VICE's module for an REU of any size, which x64sc
+      # writes straight after C64CART when the cartridge port lists the
+      # REU: the size in K, the sixteen bytes the REC's registers read
+      # from $DF00, and the RAM.
+      #
+      # Written: the registers and the RAM. VICE saves between transfers,
+      # so badline's copy of the machine runs a transfer in flight to its
+      # end first (Vice.settled).
+      #
+      # Read: the registers, as the values the counters run from and
+      # start from, and the RAM. The status register's interrupt, end of
+      # block and fault bits come back with the IRQ line, and a command
+      # waiting for a write to $FF00 stays armed.
+      module REU1764
+        NAME = "REU1764"
+        MAJOR = 0
+        MINOR = 0
+        # C64CART's id for the REU, VICE's CARTRIDGE_REU.
+        CARTRIDGE_ID = -105
+
+        module_function
+
+        def export(computer)
+          reu = computer.reu
+          FieldWriter.new.dword(reu.size_kb).bytes(reu.register_file).bytes(reu.ram_contents)
+                     .section(NAME, MAJOR, MINOR)
+        end
+
+        def reads?(section) = section.major == MAJOR && section.minor == MINOR
+
+        # The REU's size in K, which builds the machine.
+        def size_kb(section)
+          size = FieldReader.new(section).dword
+          return size if REU::SIZES_KB.include?(size)
+
+          raise FormatError, "#{section}: a #{size}K REU, which badline doesn't build"
+        end
+
+        def import(section, computer)
+          reu = computer.reu
+          fields = FieldReader.new(section)
+          fields.skip(4)
+          registers = fields.bytes(16)
+          reu.restore_ram(fields.string(reu.size_kb * 1024))
+          reu.restore_registers(registers)
+        end
+      end
+    end
+  end
+end

data/lib/badline/snapshot/vice/vicii.rb

@@ -25,9 +25,13 @@ module Badline
         MAJOR = 1
         MINOR = 3
         VERSIONS = ["VIC-II 1.3", "VIC-IISC 1.4"].freeze
-        MODELS = %i[mos6569 mos8565].freeze
+        # The VIC model and region each of VICE's model numbers builds: the
+        # 6569, the 8565 and the 6569R1 on PAL, the 6567 and the 8562 on
+        # NTSC, the 6567R56A on old NTSC and the 6572 on PAL-N.
+        VIC_MODELS = %i[mos6569 mos8565 mos6569 mos6569 mos8565 mos6569 mos6569].freeze
+        REGIONS = [Region::PAL, Region::PAL, Region::PAL, Region::NTSC, Region::NTSC, Region::NTSC_OLD,
+                   Region::DREAN].freeze
         FRAME_WIDTH = 384
-        FRAME_HEIGHT = 312
         # The pixel pipeline x64sc keeps between cycles, in bytes.
         PIPELINE = 16 + 32 + 6 + 32 + 8 + 3 + 24 + 0x2f + 2 + 4
 
@@ -35,21 +39,61 @@ module Badline
 
         def export(computer)
           vic = computer.vic
-          fields = FieldWriter.new.byte(MODELS.index(vic.model)).bytes(vic.register_file)
+          fields = FieldWriter.new.byte(number(vic)).bytes(vic.register_file)
           beam(vic, fields)
           counters(vic, fields)
           borders(vic, fields)
           fields.bytes(Array.new(0x400) { |offset| computer.address_bus.color_ram.nibble(0xd800 + offset) })
           8.times { |n| sprite(vic, n, fields) }
           pipeline(vic, fields)
-          fields.dword(vic.rasterline).dword(FRAME_WIDTH).dword(FRAME_HEIGHT).dword(FRAME_WIDTH)
-          fields.zeros(FRAME_WIDTH * (FRAME_HEIGHT + 4))
+          height = frame_height(vic.region)
+          fields.dword(drawn_line(vic)).dword(FRAME_WIDTH).dword(height).dword(FRAME_WIDTH)
+          fields.zeros(FRAME_WIDTH * (height + 4))
           fields.section(NAME, MAJOR, MINOR)
         end
 
+        # VICE has no HMOS chip for old NTSC or PAL-N, so an 8565 there is
+        # written as the NMOS one.
+        def number(vic)
+          hmos = vic.model == :mos8565
+          case vic.region.name
+          when :ntsc then hmos ? 4 : 3
+          when :ntscold then 5
+          when :drean then 6
+          else hmos ? 1 : 0
+          end
+        end
+
+        # x64sc's frame buffer, in lines, which it reads back at the height
+        # the module gives: 312 on PAL and PAL-N, 275 on either NTSC.
+        def frame_height(region) = region.lines_per_frame == 312 ? 312 : 275
+
+        # VICE's cycle in the line is badline's column plus one, so
+        # badline's last column is VICE's cycle 0 of the next line. VICE
+        # moves its line on in cycle 0, but line 0 a cycle later, holding
+        # the last line's number in cycle 0 with the start of frame flag
+        # set.
+        def last_column?(vic) = vic.column + 1 == vic.region.cycles_per_line
+
+        def vice_cycle(vic) = last_column?(vic) ? 0 : vic.column + 1
+
+        def frame_start?(vic) = last_column?(vic) && vic.rasterline + 1 == vic.region.lines_per_frame
+
+        def vice_line(vic)
+          line = vic.rasterline
+          last_column?(vic) && !frame_start?(vic) ? line + 1 : line
+        end
+
+        # The line VICE's frame buffer is drawing, its line but for the
+        # last, where it starts the next frame.
+        def drawn_line(vic)
+          line = vice_line(vic)
+          line >= vic.region.lines_per_frame - 1 ? 0 : line
+        end
+
         def beam(vic, fields)
           registers = vic.registers
-          fields.dword(vic.column).dword(0).dword(vic.rasterline).byte(0)
+          fields.dword(vice_cycle(vic)).dword(0).dword(vice_line(vic)).flag(frame_start?(vic))
           fields.byte((registers[0x19] & 0x0f) | (vic.interrupted? ? 0x80 : 0))
           fields.dword(registers.raster_target).flag(vic.latch_bits.anybits?(1))
           [vic.character_buffer, vic.color_buffer].each { |buffer| fields.bytes(buffer.map { |value| value || 0 }) }
@@ -98,17 +142,19 @@ module Badline
 
         def reads?(section) = VERSIONS.include?(section.to_s)
 
-        # VICE's model numbers: the 6569, the 8565 and the 6569R1 run PAL;
-        # the 6567, 8562 and 6567R56A NTSC, and the 6572 PAL-N, which badline
-        # doesn't run yet.
-        def model(section)
+        # VICE's model number, which a snapshot of a model badline doesn't
+        # build fails on.
+        def model_number(section)
           number = FieldReader.new(section).byte
-          return :mos8565 if number == 1
-          return :mos6569 if [0, 2].include?(number)
+          return number if number < VIC_MODELS.length
 
-          raise FormatError, "#{section}: an NTSC or PAL-N VIC-II (VICE model #{number}), which badline doesn't run"
+          raise FormatError, "#{section}: VICE's VIC-II model #{number}, which badline doesn't build"
         end
 
+        def model(section) = VIC_MODELS[model_number(section)]
+
+        def region(section) = REGIONS[model_number(section)]
+
         def import(section, computer)
           snapshot = Import.new(FieldReader.new(section))
           snapshot.apply(computer)

data/lib/badline/snapshot/vice/vicii_import.rb

@@ -34,7 +34,7 @@ module Badline
             @cycle = f.dword
             f.skip(4)
             @line = f.dword
-            f.skip(1)
+            @frame_start = f.flag?
             @irq_status = f.byte
             f.skip(4)
             @raster_match = f.flag?
@@ -95,15 +95,26 @@ module Badline
           # Clocks the VIC alone from the start of the line to the cycle,
           # so the line's fetches and sprite checks have run.
           def position(vic)
-            vic.restore_line(@line)
+            region = vic.region
+            vic.restore_line(line(region.lines_per_frame))
             load_display_state(vic)
-            @cycle.times { vic.cycle! }
+            column(region.cycles_per_line).times { vic.cycle! }
             registers = vic.registers
             registers.bytes[0x19] = @irq_status & 0x0f
             registers.bytes[0x1e], registers.bytes[0x1f] = @collisions
             registers.update_irq_line
           end
 
+          # badline's column, VICE's cycle less one, with VICE's cycle 0
+          # the last column of the line before (VICII.vice_cycle).
+          def column(cycles_per_line) = @cycle.zero? ? cycles_per_line - 1 : @cycle - 1
+
+          def line(lines)
+            return @line unless @cycle.zero? && !@frame_start
+
+            @line.zero? ? lines - 1 : @line - 1
+          end
+
           def load_display_state(vic)
             vic.display_state.restore_counters([@vc_base, @vc, @rc, @vmli], @display, @bad_lines_enabled)
           end

data/lib/badline/snapshot/vice.rb

@@ -6,6 +6,7 @@ require "badline/snapshot/vice/cias"
 require "badline/snapshot/vice/cias_import"
 require "badline/snapshot/vice/sid_registers"
 require "badline/snapshot/vice/sid_extended"
+require "badline/snapshot/vice/reu1764"
 require "badline/snapshot/vice/peripherals"
 require "badline/snapshot/vice/vicii"
 require "badline/snapshot/vice/vicii_import"
@@ -23,36 +24,32 @@ module Badline
       # boundary: the longest instruction, stretched by the VIC's longest
       # hold on the bus.
       BOUNDARY_CYCLES = 100
+      # Cycles more it may run for an REU transfer in flight to end: a
+      # swap of 64K, two cycles a byte, stretched by the VIC's holds on
+      # the bus.
+      TRANSFER_CYCLES = 0x40000
 
       # The modules a badline snapshot carries for VICE, in x64sc's order.
       # They describe a copy of the machine restored from `state`, so saving
       # leaves the machine itself alone. VICE saves between instructions,
       # and resumes by fetching an opcode at the program counter, so when
-      # badline's CPU is inside an instruction the copy runs on to its end.
-      # The copy's SID catches up, so its registers and voices stand as of
-      # that cycle. badline writes no VICE module for an REU or an NTSC
-      # VIC-II yet, and fails for a machine with either.
+      # badline's CPU is inside an instruction, or an REU transfer holds
+      # the bus, the copy runs on to the end of both. The copy's SID
+      # catches up, so its registers and voices stand as of that cycle.
       def self.export(state)
-        check_exportable(Computer.setup(state))
         machine = settled(state)
-        [MainCPU.export(machine), C64Mem.export(machine), Peripherals.cartridge_port, *CIAs.export(machine),
-         SIDRegisters.export(machine), SIDExtended.export(machine), Peripherals.drives, VICII.export(machine),
-         Peripherals.glue(machine), *Peripherals.rest]
-      end
-
-      def self.check_exportable(setup)
-        raise FormatError, "badline can't save an REU in VICE's terms yet, so can't save this machine" if setup.reu
-        return if setup.region == Region::PAL
-
-        raise FormatError, "badline can't save an NTSC VIC-II in VICE's terms yet, so can't save this machine"
+        sections = [MainCPU.export(machine), C64Mem.export(machine), Peripherals.cartridge_port(machine)]
+        sections << REU1764.export(machine) if machine.reu
+        sections + [*CIAs.export(machine), SIDRegisters.export(machine), SIDExtended.export(machine),
+                    Peripherals.drives, VICII.export(machine), Peripherals.glue(machine), *Peripherals.rest]
       end
 
       # The copy is detached from the host's files (Snapshot::StateReader),
       # so it reads none and its traps write none.
       def self.settled(state)
         copy = Computer.restored(state, detached: true)
-        BOUNDARY_CYCLES.times do
-          break if copy.cpu.boundary?
+        (BOUNDARY_CYCLES + TRANSFER_CYCLES).times do
+          break if copy.cpu.boundary? && !copy.reu&.dma?
 
           copy.cycle!
         end
@@ -60,14 +57,19 @@ module Badline
         copy
       end
 
-      # How the machine the snapshot was saved from was built. VICE doesn't
-      # save the CIA model; the C64C's 8565 VIC-II goes with the 6526A. An
-      # NTSC or PAL-N VIC-II fails, as badline runs PAL only.
+      # How the machine the snapshot was saved from was built: the VIC
+      # model and the region from the VIC-II's model, and an REU from
+      # REU1764. VICE doesn't save the CIA model; the 8565 and 8562 go
+      # with the 6526A.
       def self.setup(container)
-        vic = VICII.find(container) ? VICII.model(VICII.find(container)) : :mos6569
+        vic = VICII.find(container)
+        model = vic ? VICII.model(vic) : :mos6569
         sid = container[SIDRegisters::NAME] ? SIDRegisters.model(container[SIDRegisters::NAME]) : :mos6581
-        Setup.new(vic_model: vic, cia_model: vic == :mos8565 ? :mos6526a : :mos6526, sid_model: sid,
-                  region: Region::PAL, ram_expansion: nil, reu: nil)
+        reu = container[REU1764::NAME]
+        reu = nil unless reu && REU1764.reads?(reu)
+        Setup.new(vic_model: model, cia_model: model == :mos8565 ? :mos6526a : :mos6526, sid_model: sid,
+                  region: vic ? VICII.region(vic) : Region::PAL, ram_expansion: nil,
+                  reu: reu ? REU1764.size_kb(reu) : nil, kernal: :c64, datasette: true)
       end
     end
   end