badline 0.5.1 → 0.6.0

data/lib/badline/kernal_trap/channel.rb

@@ -80,6 +80,33 @@ module Badline
         data ? new(data) : new([], error: [Drive::ILLEGAL_TRACK_OR_SECTOR, track, sector])
       end
 
+      # Reads what save_state wrote after the flag that marks a file open
+      # for writing (Drive::Channels.channel_from_state). A buffer channel
+      # takes its block in `ram`, the drive's RAM, again.
+      def self.from_state(input, ram)
+        new.tap { |channel| channel.load_state(input, ram) }
+      end
+
+      # A buffer channel's bytes are the drive's RAM, which the drive
+      # writes itself.
+      def save_state(out)
+        out.boolean(false).boolean(@writable).int(@base).int(@length).int(@pointer)
+        out.optional_int(@lead).optional_int(@buffer).boolean(!@error.nil?)
+        out.ints(@error) if @error
+        out.blob(@bytes) unless @writable
+      end
+
+      def load_state(input, ram)
+        @writable = input.boolean?
+        @base = input.int
+        @length = input.int
+        @pointer = input.int
+        @lead = input.optional_int
+        @buffer = input.optional_int
+        @error = input.boolean? ? input.ints : nil
+        @bytes = @writable ? ram : input.blob
+      end
+
       def replace(bytes, length = bytes.length)
         @bytes = bytes
         rewind(length)

data/lib/badline/kernal_trap/drive/channels.rb

@@ -22,6 +22,31 @@ module Badline
 
         def clear = @channels.clear
 
+        # Each open channel with its secondary address, in the order they
+        # opened.
+        def save_state(out)
+          out.int(@channels.length)
+          @channels.each do |secondary, channel|
+            out.int(secondary)
+            channel.save_state(out)
+          end
+        end
+
+        # Buffer channels take their block in the drive's RAM again.
+        def load_state(input, memory)
+          @channels.clear
+          input.int.times do
+            secondary = input.int
+            @channels[secondary] = Channels.channel_from_state(input, memory.ram)
+          end
+        end
+
+        # A channel save_state wrote: a file open for writing, or a Channel
+        # whose buffer, if it has one, is in `ram`.
+        def self.channel_from_state(input, ram)
+          input.boolean? ? WriteFile.from_state(input) : Channel.from_state(input, ram)
+        end
+
         # Opens a buffer channel on the buffer a "#n" name asks for, or on
         # the highest free one. Returns nil when that buffer isn't free,
         # which leaves a channel asking again for its own buffer open.

data/lib/badline/kernal_trap/drive/memory.rb

@@ -62,6 +62,15 @@ module Badline
           load_buffer(Channels::BAM_BUFFER, block) if block
         end
 
+        def save_state(out)
+          out.blob(@ram).boolean(@bam)
+        end
+
+        def load_state(input)
+          input.blob_into(@ram)
+          @bam = input.boolean?
+        end
+
         # Whether the BAM has been read since the last reset.
         def bam? = @bam
 

data/lib/badline/kernal_trap/drive/status.rb

@@ -37,6 +37,14 @@ module Badline
           nil
         end
 
+        def save_state(out)
+          @channel.save_state(out)
+        end
+
+        def load_state(input)
+          @channel = Channels.channel_from_state(input, [])
+        end
+
         def replace(bytes)
           @channel.replace(bytes)
         end

data/lib/badline/kernal_trap/drive/write_file.rb

@@ -11,6 +11,17 @@ module Badline
         attr_accessor :buffer
         attr_reader :name, :type, :mode
 
+        TYPES = %i[del seq prg usr rel].freeze
+        MODES = %i[write replace append].freeze
+
+        # Reads what save_state wrote after the flag that marks a file
+        # open for writing.
+        def self.from_state(input)
+          name = input.string
+          type = TYPES.fetch(input.int).to_sym
+          new(name, type, mode: MODES.fetch(input.int).to_sym).tap { |file| file.load_state(input) }
+        end
+
         def initialize(name, type, mode: :write)
           @name = name
           @type = type
@@ -18,6 +29,16 @@ module Badline
           @bytes = []
         end
 
+        def save_state(out)
+          out.boolean(true).string(@name).int(TYPES.index(@type)).int(MODES.index(@mode))
+          out.blob(@bytes).optional_int(@buffer)
+        end
+
+        def load_state(input)
+          @bytes = input.blob
+          @buffer = input.optional_int
+        end
+
         def write(bytes) = @bytes.concat(bytes)
 
         def writable? = true

data/lib/badline/kernal_trap/drive.rb

@@ -143,6 +143,25 @@ module Badline
       # vector, as U: does.
       def reset! = reset(cold: true)
 
+      # The mounted storage's setup, for Storage.reopen, then the drive's
+      # RAM, its status and its open channels.
+      def save_state(out)
+        @storage.save_setup(out)
+        out.marker("TRAP DRIVE")
+        @memory.save_state(out)
+        @status.save_state(out)
+        @channels.save_state(out)
+      end
+
+      # Takes the state after the storage's setup, into a drive mounted on
+      # the reopened storage.
+      def load_state(input)
+        input.marker("TRAP DRIVE")
+        @memory.load_state(input)
+        @status.load_state(input)
+        @channels.load_state(input, @memory)
+      end
+
       # Returns the next byte and whether it is the channel's last, or nil
       # when there is nothing left to send.
       def read(secondary)

data/lib/badline/kernal_trap/save.rb

@@ -37,6 +37,14 @@ module Badline
         @saving = false
       end
 
+      def save_state(out)
+        out.boolean(@saving)
+      end
+
+      def load_state(input)
+        @saving = input.boolean?
+      end
+
       def call
         return unless active?
         return finish if @saving

data/lib/badline/kernal_trap/serial.rb

@@ -46,6 +46,22 @@ module Badline
         @buffer = []
       end
 
+      # The frame under way, with the channels and the bytes it gathered.
+      # The device it answers is the machine's to set.
+      def save_state(out)
+        out.boolean(@listening).boolean(@talking).optional_int(@listen_channel).optional_int(@talk_channel)
+        out.int(@frame).blob(@buffer)
+      end
+
+      def load_state(input)
+        @listening = input.boolean?
+        @talking = input.boolean?
+        @listen_channel = input.optional_int
+        @talk_channel = input.optional_int
+        @frame = input.int
+        @buffer = input.blob
+      end
+
       def install
         ROUTINES.each do |address, routine|
           @cpu.install_trap(address) { call_routine(routine) if kernal? }

data/lib/badline/memory.rb

@@ -29,6 +29,14 @@ module Badline
       Array(bytes).each_with_index { |b, i| poke(addr + i, b) }
     end
 
+    def save_state(out)
+      out.blob(@storage)
+    end
+
+    def load_state(input)
+      input.blob_into(@storage)
+    end
+
     # Refills the whole memory as if newly built with `initial`
     def clear!(initial = [])
       @storage.replace(zero_fill(initial))

data/lib/badline/options.rb

@@ -23,8 +23,9 @@ module Badline
 
       Media can be a .prg/.p00 program, a .d64/.d71/.d81 disk image, a
       .g64 disk image for the true 1541, a .t64 tape archive, a .tap
-      tape, a .crt cartridge, a .sid tune, or a directory to mount as
-      device 8. It opens in the emulator window. Device 8 answers through
+      tape, a .crt cartridge, a .sid tune, a .vsf snapshot, or a directory
+      to mount as device 8. It opens in the emulator window, where F11
+      saves a snapshot and F12 restores it. Device 8 answers through
       traps on the KERNAL's disk routines, unless --true-drive puts an
       emulated 1541 there, which runs its own DOS and reads .d64 and .g64
       images only.

data/lib/badline/ram_expansion/plus256k.rb

@@ -30,6 +30,22 @@ module Badline
         @locked = false
       end
 
+      def type = :plus256k
+
+      def save_state(out)
+        [@low_ram, @video_ram, @high_ram].each { |bank| out.int(@banks.index(bank)) }
+        out.boolean(@locked)
+        @banks.drop(1).each { |bank| bank.save_state(out) }
+      end
+
+      def load_state(input)
+        @low_ram = @banks.fetch(input.int)
+        @video_ram = @banks.fetch(input.int)
+        @high_ram = @banks.fetch(input.int)
+        @locked = input.boolean?
+        @banks.drop(1).each { |bank| bank.load_state(input) }
+      end
+
       def power_on!
         @banks.drop(1).each(&:clear!)
       end

data/lib/badline/ram_expansion/plus60k.rb

@@ -23,6 +23,18 @@ module Badline
         @high_ram = @banks[0]
       end
 
+      def type = :plus60k
+
+      def save_state(out)
+        out.int(@banks.index(@high_ram))
+        @banks[1].save_state(out)
+      end
+
+      def load_state(input)
+        @high_ram = @banks.fetch(input.int)
+        @banks[1].load_state(input)
+      end
+
       def power_on!
         @banks[1].clear!
       end

data/lib/badline/ram_expansion/unexpanded.rb

@@ -12,8 +12,14 @@ module Badline
         @on_change = nil
       end
 
+      def type = nil
+
       def map_io(_read_pages, _write_pages); end
 
+      def save_state(_out); end
+
+      def load_state(_input); end
+
       def reset!; end
 
       def power_on!; end

data/lib/badline/reu/dma.rb

@@ -69,8 +69,44 @@ module Badline
         @moved_all ? wind_down : move(ba_low)
       end
 
+      # Everything a transfer holds between cycles. Before the first
+      # transfer, the fields it sets on starting are empty.
+      def save_state(out)
+        out.int(@c64).int(@expansion).int(@length).int(@events)
+        [@type, @c64_step, @expansion_step, @last, @ba_low_after_writes, @swap_byte, @held_read].each do |value|
+          out.optional_int(value)
+        end
+        [@holding, @waiting, @stopped_after_write, @swap_write_due, @moved_all, @extra_cycle].each do |flag|
+          out.boolean(flag)
+        end
+      end
+
+      def load_state(input)
+        @c64 = input.int
+        @expansion = input.int
+        @length = input.int
+        @events = input.int
+        load_steps(input)
+        @holding = input.boolean?
+        @waiting = input.boolean?
+        @stopped_after_write = input.boolean?
+        @swap_write_due = input.boolean?
+        @moved_all = input.boolean?
+        @extra_cycle = input.boolean?
+      end
+
       private
 
+      def load_steps(input)
+        @type = input.optional_int
+        @c64_step = input.optional_int
+        @expansion_step = input.optional_int
+        @last = input.optional_int
+        @ba_low_after_writes = input.optional_int
+        @swap_byte = input.optional_int
+        @held_read = input.optional_int
+      end
+
       # The second BA-low cycle in a row after writes stops the REC, and so
       # does any BA-low cycle after a read. It then waits for BA to rise.
       def note_ba(ba_low)

data/lib/badline/reu/ram.rb

@@ -37,6 +37,21 @@ module Badline
         bank(addr >> 16)[addr & 0xffff] = value if addr < @size
       end
 
+      # The latch, and each 64K bank the REC has touched. A bank it hasn't
+      # keeps its power-on contents until it does.
+      def save_state(out)
+        out.int(@latch)
+        @banks.each do |bank|
+          out.boolean(!bank.empty?)
+          out.blob(bank) unless bank.empty?
+        end
+      end
+
+      def load_state(input)
+        @latch = input.int
+        @banks.each_index { |number| @banks[number] = input.boolean? ? input.blob : [] }
+      end
+
       private
 
       # A bank takes its power-on contents the first time it is touched,

data/lib/badline/reu/saved_state.rb

@@ -0,0 +1,52 @@
+# frozen_string_literal: true
+
+module Badline
+  class REU
+    # The REU's state for a snapshot: the REC's registers and the values
+    # its counters start from, an armed or running transfer, the IRQ line,
+    # the transfer's own state and the RAM. The size is the machine's
+    # setup (Snapshot::Setup), so a restore finds an REU of the same size.
+    module SavedState
+      def size_kb = @size_kb
+
+      def save_state(out)
+        out.marker("REU")
+        [@status, @command, @c64, @c64_start, @expansion, @expansion_start, @bank, @bank_start, @length,
+         @length_start, @interrupt_mask, @address_control].each { |value| out.int(value) }
+        out.boolean(@armed).boolean(@requested).boolean(@running).boolean(@irq)
+        @dma.save_state(out)
+        @ram.save_state(out)
+      end
+
+      # The IRQ line comes back as it was without calling back into the
+      # machine, which reads it again afterwards.
+      def load_state(input)
+        input.marker("REU")
+        load_registers(input)
+        @armed = input.boolean?
+        @requested = input.boolean?
+        @running = input.boolean?
+        @irq = input.boolean?
+        @dma.load_state(input)
+        @ram.load_state(input)
+      end
+
+      private
+
+      def load_registers(input)
+        @status = input.int
+        @command = input.int
+        @c64 = input.int
+        @c64_start = input.int
+        @expansion = input.int
+        @expansion_start = input.int
+        @bank = input.int
+        @bank_start = input.int
+        @length = input.int
+        @length_start = input.int
+        @interrupt_mask = input.int
+        @address_control = input.int
+      end
+    end
+  end
+end

data/lib/badline/reu.rb

@@ -3,6 +3,7 @@
 require "badline/reu/ram"
 require "badline/reu/dma"
 require "badline/reu/trigger"
+require "badline/reu/saved_state"
 
 module Badline
   # A RAM Expansion Unit: the Commodore 1700 (128K), 1764 (256K) and 1750
@@ -18,6 +19,8 @@ module Badline
   # waits for the CPU's next read cycle with BA high, and Computer then
   # clocks it through #dma_cycle! until it hands the bus back.
   class REU
+    include SavedState
+
     SIZES_KB = [128, 256, 512, 1024, 2048, 4096, 8192, 16_384].freeze
 
     # The registers, by offset.
@@ -74,6 +77,7 @@ module Badline
 
       # The 1700's REC counts 17 address bits, the others' 19.
       span = size_kb == 128 ? 0x20000 : 0x80000
+      @size_kb = size_kb
       size = size_kb * 1024
       @address_mask = [size, span].max - 1
       @bank_bits = size > span ? 0xff : 0x07

data/lib/badline/sdl/events.rb

@@ -4,6 +4,8 @@ module Badline
   module SDL
     KEY_TAB = 0x09
     KEY_F10 = 0x4000_0043
+    KEY_F11 = 0x4000_0044
+    KEY_F12 = 0x4000_0045
     KMOD_SHIFT = 0x0003
 
     # The events the front end handles. SDL_Event is a 56-byte union, read

data/lib/badline/sid/envelope/state.rb

@@ -0,0 +1,68 @@
+# frozen_string_literal: true
+
+module Badline
+  class SID
+    class Envelope
+      # A snapshot of an envelope: its rates, the gate, the state and the
+      # counters and pipelines between them, and the same fields as reSID
+      # keeps them, for VICE's SIDEXTENDED module.
+      module State
+        # The fields reSID keeps for an envelope between cycles: the rate and
+        # exponential counters, the level, the state as an index into STATES,
+        # whether it holds at zero, the two periods and the pipeline.
+        def resid_fields
+          [@rate_counter, @exponential_counter, @counter, STATES.index(@state).to_i, @hold_zero ? 1 : 0,
+           @rate_period, @exponential_period, @envelope_pipeline]
+        end
+
+        # Takes the fields resid_fields gives from `fields`, from `at` on.
+        def restore_resid_fields(fields, at)
+          @rate_counter = fields[at]
+          @exponential_counter = fields[at + 1]
+          @counter = @env3 = fields[at + 2]
+          state = fields[at + 3]
+          @state = @next_state = STATES.fetch(state.clamp(0, STATES.length - 1)).to_sym
+          @hold_zero = fields[at + 4] != 0
+          @rate_period = fields[at + 5]
+          @exponential_period = fields[at + 6]
+          @envelope_pipeline = fields[at + 7]
+        end
+
+        def save_state(out)
+          [@attack, @decay, @sustain, @release].each { |rate| out.int(rate) }
+          out.boolean(@gate).int(STATES.index(@state)).int(STATES.index(@next_state))
+          out.int(@counter).int(@env3).int(@rate_counter).int(@rate_period).boolean(@reset_rate_counter)
+          out.int(@exponential_counter).int(@exponential_period)
+          out.int(@state_pipeline).int(@envelope_pipeline).int(@exponential_pipeline).boolean(@hold_zero)
+        end
+
+        def load_state(input)
+          @attack = input.int
+          @decay = input.int
+          @sustain = input.int
+          @release = input.int
+          @gate = input.boolean?
+          @state = STATES.fetch(input.int).to_sym
+          @next_state = STATES.fetch(input.int).to_sym
+          load_counters(input)
+        end
+
+        private
+
+        def load_counters(input)
+          @counter = input.int
+          @env3 = input.int
+          @rate_counter = input.int
+          @rate_period = input.int
+          @reset_rate_counter = input.boolean?
+          @exponential_counter = input.int
+          @exponential_period = input.int
+          @state_pipeline = input.int
+          @envelope_pipeline = input.int
+          @exponential_pipeline = input.int
+          @hold_zero = input.boolean?
+        end
+      end
+    end
+  end
+end

data/lib/badline/sid/envelope.rb

@@ -1,5 +1,7 @@
 # frozen_string_literal: true
 
+require "badline/sid/envelope/state"
+
 module Badline
   class SID
     # ADSR envelope generator.
@@ -25,6 +27,11 @@ module Badline
       EXPONENTIAL_PERIODS = { 0xff => 1, 0x5d => 2, 0x36 => 4, 0x1a => 8,
                               0x0e => 16, 0x06 => 30, 0x00 => 1 }.freeze
 
+      # The states a snapshot names by index.
+      STATES = %i[attack decay_sustain release].freeze
+
+      include State
+
       attr_reader :state, :counter, :env3
 
       def initialize

data/lib/badline/sid/filter.rb

@@ -90,6 +90,16 @@ module Badline
           @output = 0
         end
 
+        def save_state(out)
+          out.int(@lowpass).int(@highpass).int(@output)
+        end
+
+        def load_state(input)
+          @lowpass = input.int
+          @highpass = input.int
+          @output = input.int
+        end
+
         # Takes the input in 1/2^Filter::FRACTION units, and reads the
         # output out in whole ones.
         def cycle!(input, cycles = 1)
@@ -124,6 +134,25 @@ module Badline
         @input = @unfiltered = 0
       end
 
+      # The registers as the filter decoded them and its integrators. The
+      # W0 table is the model's.
+      def save_state(out)
+        out.int(@cutoff).int(@routing).int(@mode).int(@volume).boolean(@voice3_off).int(@w0).int(@resonance)
+        [@highpass, @bandpass, @lowpass, @unfiltered, @input].each { |value| out.int(value) }
+        @external.save_state(out)
+      end
+
+      def load_state(input)
+        @cutoff = input.int
+        @routing = input.int
+        @mode = input.int
+        @volume = input.int
+        @voice3_off = input.boolean?
+        @w0 = input.int
+        @resonance = input.int
+        load_integrators(input)
+      end
+
       def write(reg, value)
         case reg
         when 0x15 then self.cutoff = (@cutoff & 0x7f8) | (value & 0x07)
@@ -163,6 +192,15 @@ module Badline
 
       private
 
+      def load_integrators(input)
+        @highpass = input.int
+        @bandpass = input.int
+        @lowpass = input.int
+        @unfiltered = input.int
+        @input = input.int
+        @external.load_state(input)
+      end
+
       def write_resonance(value)
         @routing = value & 0x0f
         @resonance = RESONANCE[(value >> 4) & 0x0f]

data/lib/badline/sid/voice.rb

@@ -38,6 +38,16 @@ module Badline
         @envelope = Envelope.new
       end
 
+      def save_state(out)
+        @waveform.save_state(out)
+        @envelope.save_state(out)
+      end
+
+      def load_state(input)
+        @waveform.load_state(input)
+        @envelope.load_state(input)
+      end
+
       def control=(value)
         @waveform.control = value
         @envelope.control = value

data/lib/badline/sid/waveform/state.rb

@@ -0,0 +1,66 @@
+# frozen_string_literal: true
+
+module Badline
+  class SID
+    class Waveform
+      # A snapshot of an oscillator: its phase, the noise register and the
+      # output latch, and the same fields as reSID keeps them, for VICE's
+      # SIDEXTENDED module. The model's tables and the voices it syncs with
+      # are the SID's wiring.
+      module State
+        # The fields reSID keeps for an oscillator between cycles: the phase,
+        # the noise register, its shift pipeline and reset countdown, the
+        # floating output's countdown and the pulse level.
+        def resid_fields
+          [@accumulator, @shift_register, @shift_pipeline, @shift_register_reset, @floating_ttl, @pulse]
+        end
+
+        # Takes the fields resid_fields gives from `fields`, from `at` on.
+        def restore_resid_fields(fields, at)
+          @accumulator = fields[at]
+          @shift_register = fields[at + 1]
+          @shift_pipeline = fields[at + 2]
+          @shift_register_reset = fields[at + 3]
+          @floating_ttl = fields[at + 4]
+          @pulse = fields[at + 5]
+          @stale = true
+        end
+
+        def save_state(out)
+          out.int(@accumulator).int(@delayed_triangle).int(@delayed_sawtooth)
+          out.int(@shift_register).int(@shift_register_reset).int(@shift_pipeline)
+          out.int(@frequency).int(@pulse_width).int(@selected)
+          [@test, @ring, @sync, @msb_rising].each { |flag| out.boolean(flag) }
+          out.int(@floating).int(@floating_ttl).int(@pulse).int(@output).boolean(@stale)
+        end
+
+        def load_state(input)
+          @accumulator = input.int
+          @delayed_triangle = input.int
+          @delayed_sawtooth = input.int
+          @shift_register = input.int
+          @shift_register_reset = input.int
+          @shift_pipeline = input.int
+          @frequency = input.int
+          @pulse_width = input.int
+          @selected = input.int
+          load_latches(input)
+        end
+
+        private
+
+        def load_latches(input)
+          @test = input.boolean?
+          @ring = input.boolean?
+          @sync = input.boolean?
+          @msb_rising = input.boolean?
+          @floating = input.int
+          @floating_ttl = input.int
+          @pulse = input.int
+          @output = input.int
+          @stale = input.boolean?
+        end
+      end
+    end
+  end
+end