badline 0.4.2 → 0.5.0

data/lib/badline/region.rb

@@ -6,8 +6,9 @@ module Badline
   # The timing and geometry a video standard gives the machine.
   module Region
     # The CPU clock, the VIC's raster, where the beam is blanked, the display
-    # window's edges, the part of the raster a front end shows, and the
-    # mains frequency that feeds the CIAs' TOD pins.
+    # window's edges, the part of the raster a front end shows, the mains
+    # frequency that feeds the CIAs' TOD pins, and where the VIC's sprite
+    # fetches and X counter sit in the line.
     #
     # Columns are the VIC's cycles within a line, counted from 0, and a
     # column draws 8 pixels, so the raster is `cycles_per_line * 8` pixels
@@ -16,8 +17,15 @@ module Badline
     # is the larger. `display_x_bounds` holds the display window's
     # [left, right] pixels per CSEL state, 38 columns then 40, and `crop`
     # the [left, top, width, height] a front end shows.
+    #
+    # `sprite_cycle` is Bauer's cycle for sprite 0's p-access, and each
+    # sprite after it takes two more. `sprite_display_cycle` is the cycle
+    # that turns a sprite's display on or off. `x_hold` is how many pixels
+    # the X counter spends past its run, repeating $184-$187, and a raster
+    # of more than 512 pixels needs them.
     Profile = Data.define(:name, :clock_hz, :cycles_per_line, :lines_per_frame, :hblank, :vblank,
-                          :display_x_bounds, :crop, :mains_hz)
+                          :display_x_bounds, :crop, :mains_hz, :sprite_cycle, :sprite_display_cycle,
+                          :x_hold)
 
     # The 6569 of a PAL C64: 63 cycles by 312 lines at 985,248 Hz, with
     # 50 Hz mains.
@@ -25,19 +33,36 @@ module Badline
       name: :pal, clock_hz: 985_248, cycles_per_line: 63, lines_per_frame: 312,
       hblank: [61, 9].freeze, vblank: [300, 15].freeze,
       display_x_bounds: [[135, 438].freeze, [128, 447].freeze].freeze,
-      crop: [96, 20, 384, 272].freeze, mains_hz: 50
+      crop: [96, 20, 384, 272].freeze, mains_hz: 50,
+      sprite_cycle: 58, sprite_display_cycle: 58, x_hold: 0
     )
 
     # The 6567R8 of an NTSC C64: 65 cycles by 263 lines at 1,022,727 Hz,
-    # with 60 Hz mains, and lines 13-40 blanked (Bauer). The machine does
-    # not run it yet: the blanked columns and the display window are PAL's
-    # stand-ins, and the crop leaves out lines 0-12, which show below the
-    # last line.
+    # with 60 Hz mains. The sprite fetches and the compares ahead of them
+    # run a cycle later than on the 6569 (the spritesteal, spritex and
+    # phi1timing testprogs), and the X counter pauses near $184, as Bauer's
+    # 6567R8 diagram shows, reading $184-$187 for 8 pixels more. The
+    # blanked lines are the ones VICE's NTSC view leaves out, 12-27. It shows lines 0-11 below
+    # line 262, and the crop leaves those out.
     NTSC = Profile.new(
       name: :ntsc, clock_hz: 1_022_727, cycles_per_line: 65, lines_per_frame: 263,
-      hblank: [61, 9].freeze, vblank: [13, 40].freeze,
+      hblank: [63, 9].freeze, vblank: [12, 27].freeze,
+      display_x_bounds: [[135, 438].freeze, [128, 447].freeze].freeze,
+      crop: [96, 28, 384, 235].freeze, mains_hz: 60,
+      sprite_cycle: 59, sprite_display_cycle: 59, x_hold: 8
+    )
+
+    # The 6567R56A of the first NTSC C64s: 64 cycles by 262 lines at
+    # 1,022,727 Hz. Its sprite fetches run a cycle later than the 6569's,
+    # as on the 6567R8, but it turns the display on in the same cycle as
+    # the 6569, and its X counter runs straight through 512 pixels, one
+    # coordinate for each.
+    NTSC_OLD = Profile.new(
+      name: :ntscold, clock_hz: 1_022_727, cycles_per_line: 64, lines_per_frame: 262,
+      hblank: [62, 9].freeze, vblank: [13, 27].freeze,
       display_x_bounds: [[135, 438].freeze, [128, 447].freeze].freeze,
-      crop: [96, 41, 384, 222].freeze, mains_hz: 60
+      crop: [96, 28, 384, 234].freeze, mains_hz: 60,
+      sprite_cycle: 59, sprite_display_cycle: 58, x_hold: 0
     )
 
     # Whether a column or line lies in a [first, last] blanking span.

data/lib/badline/reu/dma.rb

@@ -0,0 +1,228 @@
+# frozen_string_literal: true
+
+module Badline
+  class REU
+    # One transfer between the C64 and the REU's RAM, clocked a cycle at a
+    # time while the REC holds the bus. The REC only reads the C64's bus
+    # while BA is high, so a read followed by BA low waits for BA to rise.
+    # After a write it goes on through the first BA-low cycle and stops at
+    # the second. See doc/pinned-behaviour.md, REU DMA.
+    class DMA
+      # Transfer types, as the command register's bottom two bits give
+      # them.
+      STASH = 0
+      FETCH = 1
+      SWAP = 2
+      VERIFY = 3
+
+      # What the REC did on the cycle before.
+      IDLE = 0
+      READ = 1
+      WRITE = 2
+
+      # Where the transfer stopped, what it left for the length register,
+      # and the status bits it ended with.
+      attr_reader :c64, :expansion, :length, :events
+
+      def initialize(ram, span, bus)
+        @ram = ram
+        @span = span
+        @bus = bus
+        @c64 = @expansion = @length = @events = 0
+        @holding = false
+      end
+
+      # Whether the REC held the bus on the last cycle clocked, which it
+      # does while it waits for BA too, since the CPU stays halted.
+      def holds_bus? = @holding
+
+      # A length of 0 moves 64K. control is the address control register,
+      # which can hold either address where it is.
+      def start(type, c64, expansion, length, control)
+        @type = type
+        @c64 = c64
+        @expansion = expansion
+        @length = length.zero? ? 0x10000 : length
+        @c64_step = control.anybits?(FIX_C64) ? 0 : 1
+        @expansion_step = control.anybits?(FIX_EXPANSION) ? 0 : 1
+        @events = 0
+        @holding = true
+        @last = IDLE
+        @waiting = false
+        @ba_low_after_writes = 0
+        @stopped_after_write = false
+        @swap_write_due = false
+        @swap_byte = 0
+        @held_read = 0
+        @moved_all = false
+        @extra_cycle = false
+      end
+
+      # One cycle of the transfer. The cycle the REC lets go of the bus on
+      # is the CPU's.
+      def cycle!(ba_low)
+        note_ba(ba_low)
+        settle_held_read(ba_low) if @held_read.positive?
+        return if @waiting && ba_low
+
+        @waiting = false
+        @moved_all ? wind_down : move(ba_low)
+      end
+
+      private
+
+      # The second BA-low cycle in a row after writes stops the REC, and so
+      # does any BA-low cycle after a read. It then waits for BA to rise.
+      def note_ba(ba_low)
+        if @last == READ
+          @waiting = ba_low
+        elsif @last == WRITE
+          @ba_low_after_writes = ba_low ? @ba_low_after_writes + 1 : 0
+          @stopped_after_write = @ba_low_after_writes == 2
+          if @stopped_after_write
+            @waiting = true
+            @ba_low_after_writes = 0
+          end
+        end
+        @last = IDLE
+      end
+
+      # A fetch or a swap whose last write ran into BA, or a verify that
+      # found a difference before its last byte, takes one more cycle before
+      # the REC lets go of the bus.
+      def wind_down
+        if @extra_cycle || (@stopped_after_write && (@type == FETCH || @type == SWAP))
+          @extra_cycle = @stopped_after_write = false
+          @last = READ
+          return
+        end
+
+        @holding = false
+        settle
+      end
+
+      def move(ba_low)
+        case @type
+        when STASH then stash
+        when FETCH then fetch
+        when SWAP then swap(ba_low)
+        else verify
+        end
+      end
+
+      # The REU's data bus latch keeps the last byte the REC stored.
+      def stash
+        byte = read_c64
+        @ram.poke(@expansion, byte)
+        @ram.latch = byte
+        step
+        @last = READ
+      end
+
+      def fetch
+        byte = @ram.peek(@expansion)
+        @ram.latch = byte
+        write_c64(byte)
+        step
+        @last = WRITE
+      end
+
+      # Two cycles a byte: the C64's byte is read and stored while the
+      # REU's is fetched, and the REU's is written to the C64 on the next.
+      def swap(ba_low)
+        if @swap_write_due
+          @swap_write_due = false
+          write_c64(@swap_byte)
+          step
+          @last = WRITE
+          return
+        end
+
+        @swap_byte = @ram.peek(@expansion)
+        @swap_write_due = true
+        @last = READ
+        return swap_read_on_ba if ba_low
+
+        @ram.poke(@expansion, read_c64)
+      end
+
+      # A swap's read on the first BA-low cycle after a write, while AEC is
+      # still high. On the last byte the read is made there, the write
+      # follows on the next cycle whatever BA does, and the REC lets go.
+      # Otherwise the read stays open and takes what is on the bus two
+      # cycles later, or on the cycle BA rises if that comes first. Pinned
+      # by REU/reutiming2/e5-m2, f3-m2 and f4-m2.
+      def swap_read_on_ba
+        return @held_read = 2 unless @length == 1
+
+        @ram.poke(@expansion, read_c64)
+        @last = IDLE
+        @ba_low_after_writes = 0
+      end
+
+      def settle_held_read(ba_low)
+        @held_read -= 1
+        return if @held_read.positive? && ba_low
+
+        @held_read = 0
+        @ram.poke(@expansion, read_c64)
+      end
+
+      # A difference ends the transfer, with one cycle more if bytes were
+      # left to compare.
+      def verify
+        same = @ram.peek(@expansion) == read_c64
+        step
+        @last = READ
+        return if same
+
+        @events |= FAULT
+        @extra_cycle = @length.positive?
+        @moved_all = true
+      end
+
+      # The REC reaches C64 memory as the CPU sees it, but at $00 and $01
+      # it reaches the RAM under the CPU's port.
+      def read_c64
+        @c64 < 0x02 ? @bus.ram.peek(@c64) : @bus.peek(@c64)
+      end
+
+      def write_c64(byte)
+        @c64 < 0x02 ? @bus.ram.poke(@c64, byte) : @bus.poke(@c64, byte)
+      end
+
+      # The REC counts the expansion address in its 19 low bits, from the
+      # top of its span back to 0, and leaves the bank bits above them as
+      # they were.
+      def step
+        @c64 = (@c64 + @c64_step) & 0xffff
+        low = (@expansion & 0x7ffff) + @expansion_step
+        @expansion = (@expansion & 0xf80000) | (low == @span ? 0 : low)
+        @length -= 1
+        @moved_all = true if @length.zero?
+      end
+
+      # The length register is left at 1 after a whole block. A fetch has
+      # already fetched the byte after its last into the latch.
+      def settle
+        return settle_verify if @type == VERIFY
+
+        @length += 1
+        @events |= END_OF_BLOCK
+        @ram.latch = @ram.peek(@expansion) if @type == FETCH
+      end
+
+      # A verify that compared every byte ends the block. One that found a
+      # difference on the byte before the last compares the last too, and
+      # ends the block if that one is the same.
+      def settle_verify
+        if @length.zero?
+          @length = 1
+          @events |= END_OF_BLOCK
+        elsif @length == 1 && @ram.peek(@expansion) == read_c64
+          @events |= END_OF_BLOCK
+        end
+      end
+    end
+  end
+end

data/lib/badline/reu/ram.rb

@@ -0,0 +1,65 @@
+# frozen_string_literal: true
+
+module Badline
+  class REU
+    # The REU's DRAM, as the REC addresses it. The REC counts 19 address
+    # bits, 17 on the 1700, and the 1764 fills only the first 256K of
+    # them: past that a read finds the latch on the REU's data bus, which
+    # holds the last byte the REC moved. A unit past 512K takes its upper
+    # address lines from the bank register.
+    class RAM
+      BANK_SIZE = 0x10000
+
+      # Where a bank of a 1764 that has just been switched on reads
+      # inverted, over the first 128K of each 256K. Over the second 128K
+      # it is the rest of the bank that reads inverted. Measured from
+      # REU/raminitpattern/dumpfile-256k-x1541.bin, a real 1764's dump.
+      INVERTED = [0x2a00...0x5400, 0x8000...0xac00, 0xd600...0x10000].freeze
+
+      attr_reader :size
+      attr_accessor :latch
+
+      def initialize(size, span)
+        @size = size
+        @mask = (size > 0x80000 ? size : span) - 1
+        @banks = Array.new(size / BANK_SIZE) { [] }
+        @power_on = [[], []]
+        @latch = 0xff
+      end
+
+      def peek(addr)
+        addr &= @mask
+        addr < @size ? bank(addr >> 16)[addr & 0xffff] : @latch
+      end
+
+      def poke(addr, value)
+        addr &= @mask
+        bank(addr >> 16)[addr & 0xffff] = value if addr < @size
+      end
+
+      private
+
+      # A bank takes its power-on contents the first time it is touched,
+      # so an REU costs only the memory a program uses.
+      def bank(number)
+        bank = @banks[number]
+        return bank unless bank.empty?
+
+        half = (number >> 1) & 1
+        @power_on[half] = power_on_bank(half == 1) if @power_on[half].empty?
+        @banks[number] = @power_on[half].dup
+      end
+
+      # Pairs of $FF and $00 bytes, starting with a single $FF, and each
+      # odd page the inverse of the even one before it.
+      def power_on_bank(upper)
+        Array.new(BANK_SIZE) do |offset|
+          byte = (offset + 1).anybits?(2) ? 0x00 : 0xff
+          byte ^= 0xff if offset.anybits?(0x100)
+          inverted = INVERTED.any? { |range| range.cover?(offset) }
+          inverted == upper ? byte : byte ^ 0xff
+        end
+      end
+    end
+  end
+end

data/lib/badline/reu/trigger.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+module Badline
+  class REU
+    # Stands in for the page at $FF00 in the write table, passing each
+    # write on to what is mapped there and telling the REC when $FF00 is
+    # written, which starts an armed transfer.
+    class Trigger
+      ADDRESS = 0xff00
+
+      def initialize(reu)
+        @reu = reu
+        @target = nil
+      end
+
+      # Puts the trigger in front of target and returns it.
+      def wrap(target)
+        @target = target
+        self
+      end
+
+      def peek(addr)
+        @target.peek(addr)
+      end
+
+      def poke(addr, value)
+        @target.poke(addr, value)
+        @reu.ff00_written if addr == ADDRESS
+      end
+    end
+  end
+end

data/lib/badline/reu.rb

@@ -0,0 +1,276 @@
+# frozen_string_literal: true
+
+require "badline/reu/ram"
+require "badline/reu/dma"
+require "badline/reu/trigger"
+
+module Badline
+  # A RAM Expansion Unit: the Commodore 1700 (128K), 1764 (256K) and 1750
+  # (512K), and the bigger units built around the same 8726 RAM Expansion
+  # Controller (REC), such as the CMD 1750XL, up to 16M.
+  #
+  # The REC's eleven registers sit in I/O 2 from $DF00, repeated every 32
+  # bytes up to $DFFF, as the 1764 and 1750 manuals map them. It moves
+  # bytes between the C64 and its RAM by DMA, one bus cycle each, with the
+  # CPU held off the bus. A command with the execute bit set starts a
+  # transfer, or with bit 4 clear arms the REC to start one on the next
+  # write to $FF00, so a program can bank the ROMs out first. A transfer
+  # waits for the CPU's next read cycle with BA high, and Computer then
+  # clocks it through #dma_cycle! until it hands the bus back.
+  class REU
+    SIZES_KB = [128, 256, 512, 1024, 2048, 4096, 8192, 16_384].freeze
+
+    # The registers, by offset.
+    STATUS = 0x00
+    COMMAND = 0x01
+    C64_LOW = 0x02
+    C64_HIGH = 0x03
+    EXPANSION_LOW = 0x04
+    EXPANSION_HIGH = 0x05
+    EXPANSION_BANK = 0x06
+    LENGTH_LOW = 0x07
+    LENGTH_HIGH = 0x08
+    INTERRUPT_MASK = 0x09
+    ADDRESS_CONTROL = 0x0a
+
+    # Status: an interrupt is pending, the block ended, a verify found a
+    # difference (the manual's fault bit), and the unit is built from 256K
+    # chips, which only the 1700 isn't. Reading the status clears the top
+    # three.
+    INTERRUPT_PENDING = 0x80
+    END_OF_BLOCK = 0x40
+    FAULT = 0x20
+    CHIPS_256K = 0x10
+
+    # Command: execute, reload the registers after the transfer, don't wait
+    # for $FF00, and the transfer type in the bottom two bits.
+    EXECUTE = 0x80
+    AUTOLOAD = 0x20
+    NO_FF00_TRIGGER = 0x10
+    TRANSFER_TYPE = 0x03
+
+    # Interrupt mask: interrupts on at all, then on the end of a block and
+    # on a fault. The low five bits aren't there and read as 1.
+    INTERRUPTS_ON = 0x80
+    INTERRUPT_ON_END = 0x40
+    INTERRUPT_ON_FAULT = 0x20
+
+    # Address control: hold the C64 address or the expansion address where
+    # it is. The low six bits aren't there and read as 1.
+    FIX_C64 = 0x80
+    FIX_EXPANSION = 0x40
+
+    # The REC's bank register has three bits, and the other five read as
+    # 1. A unit past 512K latches all eight onto its own address lines.
+    BANK_STUCK = 0xf8
+
+    attr_reader :trigger
+
+    # bus is the bus the REC reaches C64 memory through, and vic the VIC,
+    # whose phi1 fetch is what a register read finds on the bus during a
+    # transfer.
+    def initialize(size_kb, bus:, vic:)
+      raise ArgumentError, "No #{size_kb}K REU. Pick one of #{SIZES_KB.join(', ')}." unless SIZES_KB.include?(size_kb)
+
+      # The 1700's REC counts 17 address bits, the others' 19.
+      span = size_kb == 128 ? 0x20000 : 0x80000
+      size = size_kb * 1024
+      @address_mask = [size, span].max - 1
+      @bank_bits = size > span ? 0xff : 0x07
+      @chips = size_kb == 128 ? 0 : CHIPS_256K
+      @ram = RAM.new(size, span)
+      @dma = DMA.new(@ram, span, bus)
+      @trigger = Trigger.new(self)
+      @vic = vic
+      @on_irq_change = nil
+      @on_dma = nil
+      @irq = false
+      reset!
+    end
+
+    def on_irq_change(&block)
+      @on_irq_change = block
+    end
+
+    # Called when the REC asks for the bus.
+    def on_dma(&block)
+      @on_dma = block
+    end
+
+    def irq? = @irq
+
+    # From the moment the REC asks for the bus until it hands it back.
+    def dma? = @requested || @running
+
+    # Whether the REC held the bus on the last cycle clocked. The CPU keeps
+    # it while the REC waits to start, and has it back from the cycle the
+    # REC lets go.
+    def holds_bus? = @running
+
+    def reset!
+      @status = @chips
+      @command = NO_FF00_TRIGGER
+      @c64 = @c64_start = 0
+      @expansion = @expansion_start = 0
+      @bank = @bank_start = 0
+      @length = @length_start = 0xffff
+      @interrupt_mask = 0x1f
+      @address_control = 0x3f
+      @armed = @requested = @running = false
+      interrupt(false)
+    end
+
+    def peek(addr)
+      return @vic.phi1_data if @running
+
+      register = addr & 0x1f
+      value = register_value(register)
+      read_status if register == STATUS
+      value
+    end
+
+    def poke(addr, value)
+      return if @running
+
+      register = addr & 0x1f
+      case register
+      when COMMAND then write_command(value)
+      when C64_LOW, C64_HIGH then @c64 = @c64_start = with_byte(@c64_start, value, register == C64_HIGH)
+      when EXPANSION_LOW, EXPANSION_HIGH
+        @expansion = @expansion_start = with_byte(@expansion_start, value, register == EXPANSION_HIGH)
+      when EXPANSION_BANK then @bank = @bank_start = value & @bank_bits
+      when LENGTH_LOW, LENGTH_HIGH
+        @length = @length_start = with_byte(@length_start, value, register == LENGTH_HIGH)
+      when INTERRUPT_MASK then write_interrupt_mask(value)
+      when ADDRESS_CONTROL then @address_control = value | 0x3f
+      end
+    end
+
+    # A write to $FF00 starts the transfer the command register armed.
+    def ff00_written
+      return unless @armed
+
+      @armed = false
+      request_bus
+    end
+
+    # Clocks the REC for a cycle, given the VIC's BA line and whether the
+    # CPU writes on it. A requested transfer starts on the first cycle the
+    # CPU reads with BA high.
+    def dma_cycle!(ba_low, cpu_writing)
+      if @requested
+        return if cpu_writing || ba_low
+
+        start_transfer
+      end
+      @dma.cycle!(ba_low)
+      end_transfer unless @dma.holds_bus?
+    end
+
+    # The REU's RAM, at an address as the REC's registers give it.
+    def ram_peek(addr) = @ram.peek(addr)
+
+    def ram_poke(addr, value) = @ram.poke(addr, value)
+
+    private
+
+    def register_value(register)
+      case register
+      when STATUS then @status
+      when COMMAND then @command
+      when C64_LOW then @c64 & 0xff
+      when C64_HIGH then @c64 >> 8
+      when EXPANSION_LOW then @expansion & 0xff
+      when EXPANSION_HIGH then @expansion >> 8
+      when EXPANSION_BANK then @bank | BANK_STUCK
+      when LENGTH_LOW then @length & 0xff
+      when LENGTH_HIGH then @length >> 8
+      when INTERRUPT_MASK then @interrupt_mask
+      when ADDRESS_CONTROL then @address_control
+      else 0xff
+      end
+    end
+
+    def read_status
+      @status &= CHIPS_256K
+      interrupt(false)
+    end
+
+    # Writing either byte of an address or the length sets the value the
+    # transfer starts from, and puts the counter back to it.
+    def with_byte(word, value, high)
+      high ? (word & 0x00ff) | (value << 8) : (word & 0xff00) | value
+    end
+
+    def write_command(value)
+      @command = value
+      return if value.nobits?(EXECUTE)
+
+      @armed = value.nobits?(NO_FF00_TRIGGER)
+      request_bus unless @armed
+    end
+
+    # An interrupt enabled over a block that already ended, or a fault
+    # already found, fires at once.
+    def write_interrupt_mask(value)
+      @interrupt_mask = value | 0x1f
+      interrupt_on(@status)
+    end
+
+    def interrupt_on(events)
+      return unless @interrupt_mask.anybits?(INTERRUPTS_ON)
+      return unless (events.anybits?(END_OF_BLOCK) && @interrupt_mask.anybits?(INTERRUPT_ON_END)) ||
+                    (events.anybits?(FAULT) && @interrupt_mask.anybits?(INTERRUPT_ON_FAULT))
+
+      @status |= INTERRUPT_PENDING
+      interrupt(true)
+    end
+
+    def interrupt(level)
+      return if @irq == level
+
+      @irq = level
+      @on_irq_change&.call(level)
+    end
+
+    def request_bus
+      @requested = true
+      @on_dma&.call
+    end
+
+    def start_transfer
+      @requested = false
+      @running = true
+      @dma.start(@command & TRANSFER_TYPE, @c64, @expansion | (@bank << 16), @length, @address_control)
+    end
+
+    # The execute bit drops and the $FF00 trigger turns off. With autoload
+    # the addresses and the length go back to where the transfer started,
+    # and otherwise they stay where it stopped.
+    def end_transfer
+      @running = false
+      @command = (@command & ~EXECUTE & 0xff) | NO_FF00_TRIGGER
+      events = @dma.events
+      @status |= events
+      @command.anybits?(AUTOLOAD) ? reload : keep_counters
+      interrupt_on(events)
+    end
+
+    def reload
+      @c64 = @c64_start
+      @expansion = @expansion_start
+      @bank = @bank_start
+      @length = @length_start
+    end
+
+    def keep_counters
+      @c64 = @dma.c64 if @address_control.nobits?(FIX_C64)
+      @length = @dma.length & 0xffff
+      return if @address_control.anybits?(FIX_EXPANSION)
+
+      address = @dma.expansion & @address_mask
+      @expansion = address & 0xffff
+      @bank = (address >> 16) & 0xff
+    end
+  end
+end

data/lib/badline/roms/README

@@ -16,3 +16,13 @@ the C128's C64 mode.
 character.rom
 -------------
 The character generator ROM.
+
+dos1541.rom
+-----------
+The 1541 disk drive's DOS 2.6, 16 KB for $C000-$FFFF: 325302-01
+($C000-$DFFF) followed by 901229-05 ($E000-$FFFF). Drive1541 loads it.
+
+Both halves downloaded from
+https://www.zimmers.net/anonftp/pub/cbm/firmware/drives/new/1541/
+(1541-c000.325302-01.bin and 1541-e000.901229-05.bin) and concatenated.
+SHA-1 ab16f56989b27d89babe5f89c5a8cb3da71a82f0.

data/lib/badline/sdl/functions.rb

@@ -42,6 +42,7 @@ module Badline
     RenderSetLogicalSize = function("SDL_RenderSetLogicalSize", [POINTER, INT, INT], INT)
     SetRenderDrawColor = function("SDL_SetRenderDrawColor", [POINTER, UINT8, UINT8, UINT8, UINT8], INT)
     RenderClear = function("SDL_RenderClear", [POINTER], INT)
+    RenderFillRect = function("SDL_RenderFillRect", [POINTER, POINTER], INT)
     RenderCopy = function("SDL_RenderCopy", [POINTER, POINTER, POINTER, POINTER], INT)
     RenderPresent = function("SDL_RenderPresent", [POINTER], VOID)
     CreateRGBSurfaceFrom = function("SDL_CreateRGBSurfaceFrom",