badline 0.3.0 → 0.4.1

data/lib/badline/via/shift_register.rb

@@ -0,0 +1,135 @@
+# frozen_string_literal: true
+
+module Badline
+  class VIA
+    # The 6522's shift register, with the CB1 clock and CB2 data lines it
+    # takes over in every mode but the first.
+    #
+    # ACR bits 4-2 pick the mode. Modes 1 to 3 shift in, left, with the new
+    # bit taken from CB2 into bit 0 on each rising CB1 edge. Modes 4 to 7
+    # shift out: each falling CB1 edge puts bit 7 on CB2 and rotates it back
+    # round into bit 0, so after eight bits the byte is back where it
+    # started. Modes 1, 4 and 5 clock off timer 2, modes 2 and 6 off φ2, and
+    # modes 3 and 7 off whatever drives CB1 from outside.
+    #
+    # Under its own clock the register drives CB1, idling high. Reading or
+    # writing the data register starts a byte: CB1 falls on the first clock
+    # tick after the access and rises on the second, and so on, so a byte is
+    # eight pulses over sixteen ticks. The interrupt flag is set on the tick
+    # that raises CB1 over the eighth bit, and CB1 then stays high until the
+    # next access. A tick is a φ2 cycle in modes 2 and 6, which makes a byte
+    # sixteen cycles, and a timer 2 low byte underflow in modes 1, 4 and 5,
+    # which makes it sixteen underflows. Mode 4 never stops and never
+    # interrupts: its counter is disabled, and the byte goes round and round.
+    #
+    # Under an external clock the register shifts on every CB1 edge, access
+    # or not. The access only arms the counter: the flag is set on the eighth
+    # rising edge after it, and the counter then waits for the next access.
+    class ShiftRegister
+      DISABLED = 0
+      IN_T2 = 1
+      IN_PHI2 = 2
+      IN_EXTERNAL = 3
+      OUT_FREE_RUNNING = 4
+      OUT_T2 = 5
+      OUT_PHI2 = 6
+      OUT_EXTERNAL = 7
+
+      BITS = 8
+
+      attr_reader :mode, :data
+      attr_accessor :cb2_input
+
+      def initialize
+        @mode = DISABLED
+        @data = 0x00
+        # Bits still to count before the flag, zero when the counter is idle.
+        @bits = 0
+        @clock = true
+        @cb2 = true
+        # Nothing drives CB2 from outside, so it floats high.
+        @cb2_input = true
+      end
+
+      def mode=(value)
+        @mode = value & 0x07
+      end
+
+      def data=(value)
+        @data = value & 0xff
+      end
+
+      # Every read or write of the data register (re)starts the count of
+      # eight bits.
+      def access!
+        @bits = BITS
+      end
+
+      # The CB1 level the register drives, or nil when CB1 is an input.
+      def cb1_output
+        internal_clock? ? @clock : nil
+      end
+
+      # The CB2 level the register drives, or nil when it doesn't.
+      def cb2_output
+        @mode >= OUT_FREE_RUNNING ? @cb2 : nil
+      end
+
+      # Clocked once per φ2 cycle, with whether timer 2's low byte underflowed
+      # on it. Returns true on the cycle that sets the interrupt flag.
+      def cycle!(t2_low_underflow)
+        return false if @bits.zero?
+
+        case @mode
+        when IN_PHI2, OUT_PHI2 then tick
+        when IN_T2, OUT_T2, OUT_FREE_RUNNING then t2_low_underflow && tick
+        else false
+        end
+      end
+
+      # A level change on CB1 from outside. Only the external clock modes
+      # listen: shifting in samples CB2 as CB1 rises, and shifting out puts
+      # the next bit on CB2 as it falls. Returns true when the edge sets the
+      # interrupt flag.
+      def cb1_edge!(rising)
+        return false unless @mode == IN_EXTERNAL || @mode == OUT_EXTERNAL
+
+        shift_in if rising && @mode == IN_EXTERNAL
+        shift_out if !rising && @mode == OUT_EXTERNAL
+        rising && eighth_bit?
+      end
+
+      private
+
+      def internal_clock?
+        @mode != DISABLED && @mode != IN_EXTERNAL && @mode != OUT_EXTERNAL
+      end
+
+      # One half period of the register's own clock: a falling edge puts a
+      # bit out, and a rising one takes a bit in and counts it.
+      def tick
+        @clock = !@clock
+        shift_out if !@clock && @mode >= OUT_FREE_RUNNING
+        shift_in if @clock && @mode < IN_EXTERNAL
+        @clock && @mode != OUT_FREE_RUNNING && eighth_bit?
+      end
+
+      # Counts a bit, and says whether it was the eighth since the access.
+      def eighth_bit?
+        return false if @bits.zero?
+
+        @bits -= 1
+        @bits.zero?
+      end
+
+      def shift_in
+        @data = ((@data << 1) | (@cb2_input ? 1 : 0)) & 0xff
+      end
+
+      def shift_out
+        @cb2 = @data.anybits?(0x80)
+        @data = ((@data << 1) | (@cb2 ? 1 : 0)) & 0xff
+      end
+    end
+  end
+end

data/lib/badline/via/timer1.rb

@@ -0,0 +1,82 @@
+# frozen_string_literal: true
+
+module Badline
+  class VIA
+    # Timer 1: a 16-bit counter that decrements on every φ2 cycle, with a
+    # latch it reloads from on every timeout and the PB7 output.
+    #
+    # Writing the high counter byte loads the counter on the cycle after,
+    # so a timer loaded with N reads N, N-1, ... 0 and then $FFFF, which is
+    # the cycle its interrupt flag sets: N + 1.5 cycles after the write in
+    # the datasheet's terms. The counter then reloads from the latch on the
+    # next cycle, which makes the period N + 2 cycles. It does so in one-shot
+    # mode too, unlike timer 2.
+    #
+    # Only a write of the high counter byte arms the timer. An armed timeout
+    # sets the flag and inverts PB7, and in one-shot mode disarms it, so the
+    # first timeout after the load alone does. Free-running keeps it armed,
+    # but switching to free-running doesn't arm it: an unarmed timer counts
+    # and reloads without touching the flag or PB7. The load pulls PB7 low,
+    # and ACR bit 7 turning on drives it high, so a timer loaded before its
+    # PB7 output is enabled reads high until the timeout pulls it low.
+    class Timer1
+      attr_accessor :counter, :latch
+
+      # The level the timer drives on PB7 when ACR bit 7 hands it the pin.
+      attr_reader :pb7
+
+      # ACR bit 7 turning on hands PB7 to the timer high.
+      def pb7_enabled!
+        @pb7 = true
+      end
+
+      def initialize
+        @counter = @latch = 0xffff
+        @reload = @hold = false
+        @armed = false
+        @pb7 = true
+      end
+
+      def write_latch_low(value)
+        @latch = (@latch & 0xff00) | value
+      end
+
+      def write_latch_high(value)
+        @latch = (value << 8) | (@latch & 0xff)
+      end
+
+      # The high counter byte write: load from the latch, hold the count
+      # for a cycle, arm the interrupt and pull PB7 low.
+      def start!
+        @counter = @latch
+        @hold = true
+        @reload = false
+        @armed = true
+        @pb7 = false
+      end
+
+      # One φ2 cycle. Returns true on the cycle that sets the interrupt flag.
+      def cycle!(free_run)
+        if @hold || @reload
+          @counter = @latch if @reload
+          @hold = @reload = false
+          return false
+        end
+        @counter = (@counter - 1) & 0xffff
+        @counter == 0xffff && timeout(free_run)
+      end
+
+      private
+
+      # The counter reloads either way. Armed, PB7 inverts and the flag
+      # sets, and one-shot mode disarms. Returns whether the flag sets.
+      def timeout(free_run)
+        interrupt = @armed
+        @reload = true
+        @pb7 = !@pb7 if @armed
+        @armed &&= free_run
+        interrupt
+      end
+    end
+  end
+end

data/lib/badline/via/timer2.rb

@@ -0,0 +1,84 @@
+# frozen_string_literal: true
+
+module Badline
+  class VIA
+    # Timer 2: a one-shot 16-bit counter that decrements on every φ2 cycle,
+    # or on every falling edge of PB6 when ACR bit 5 sets it counting pulses.
+    # Only its low byte has a latch.
+    #
+    # Timed, it follows timer 1's one-shot timing: loaded with N it reads N
+    # on the cycle after the write, and sets its flag on the cycle it rolls
+    # from 0 to $FFFF. Where timer 1 would reload, it rolls on down without
+    # further interrupts until the next load. Counting pulses, the flag sets
+    # on the pulse that takes it past zero, the N + 1st: the datasheet's
+    # "reaches zero" is the same underflow it means in timed mode.
+    #
+    # While the shift register clocks off it, the low byte also counts as
+    # an 8-bit timer of its own: on each low byte underflow it reloads from
+    # the latch on the next cycle, which makes the shift clock's half period
+    # N + 2 cycles. The borrow still reaches the high byte.
+    #
+    # ACR bit 5 reaches the count input a cycle after the write, so the
+    # counter takes one more step in the mode it leaves.
+    class Timer2
+      attr_accessor :counter, :latch_low
+
+      # ACR bit 5, which picks PB6 pulses over φ2.
+      attr_writer :count_pulses
+
+      # Whether the low byte underflowed on the last cycle.
+      attr_reader :low_underflowed
+
+      def initialize
+        @counter = 0xffff
+        @latch_low = 0xff
+        @hold = false
+        @low_reload = false
+        @armed = false
+        @low_underflowed = false
+        @count_pulses = @counting_pulses = false
+      end
+
+      # The high counter byte write: load the counter with it and the low
+      # latch, arm the interrupt and hold the count for a cycle.
+      def load(high)
+        @counter = (high << 8) | @latch_low
+        @hold = true
+        @low_reload = false
+        @armed = true
+      end
+
+      # One φ2 cycle, with whether the shift register clocks off the low
+      # byte. Returns true on the cycle that sets the flag.
+      def cycle!(sr_service)
+        pulses = @counting_pulses
+        @counting_pulses = @count_pulses
+        return idle! if pulses || @hold
+
+        @low_underflowed = @counter.nobits?(0xff)
+        @hold = @low_reload = sr_service && @low_underflowed
+        decrement
+      end
+
+      # A falling edge on PB6. Returns true when it sets the flag.
+      def pulse! = @counting_pulses && decrement
+
+      private
+
+      # A cycle while counting pulses, or held after a load or a low byte
+      # underflow: the counter stands still, but the hold still ends, so
+      # none carries over into timed mode.
+      def idle!
+        @counter = (@counter & 0xff00) | @latch_low if @low_reload
+        @hold = @low_reload = @low_underflowed = false
+      end
+
+      def decrement
+        @counter = (@counter - 1) & 0xffff
+        interrupt = @armed && @counter == 0xffff
+        @armed = false if interrupt
+        interrupt
+      end
+    end
+  end
+end

data/lib/badline/via.rb

@@ -0,0 +1,262 @@
+# frozen_string_literal: true
+
+require "badline/via/control_lines"
+require "badline/via/interrupt_register"
+require "badline/via/shift_register"
+require "badline/via/timer1"
+require "badline/via/timer2"
+
+module Badline
+  # VIA (Versatile Interface Adapter): the MOS 6522, two ports with
+  # handshake lines, two timers and a shift register. The 1541 has two.
+  #
+  # Sixteen registers repeat across a 1 KB window. The control pins take
+  # levels from outside through ca1= and friends, and PB6 takes its pulses
+  # for timer 2 through pb6= alone: the peripheral's port B input doesn't
+  # feed the counter.
+  class VIA
+    include Addressable
+
+    attr_reader :start, :peripheral, :shift_register, :acr, :pcr
+
+    def timer1 = @t1.counter
+
+    def timer1_latch = @t1.latch
+
+    def timer2 = @t2.counter
+
+    def interrupt_flags = @ifr.read
+
+    def interrupt_enable = @ifr.read_enable
+
+    def initialize(start: 0, peripheral: nil)
+      addressable_at(start, length: 2**10)
+
+      @peripheral = peripheral
+      @t1 = Timer1.new
+      @t2 = Timer2.new
+      @shift_register = ShiftRegister.new
+      @ifr = InterruptRegister.new
+      @ca = ControlLines.new(@ifr, c1_flag: InterruptRegister::CA1, c2_flag: InterruptRegister::CA2,
+                                   handshake_on_read: true)
+      @cb = ControlLines.new(@ifr, c1_flag: InterruptRegister::CB1, c2_flag: InterruptRegister::CB2,
+                                   handshake_on_read: false)
+      @pb6_high = true
+      @acr = 0x00
+      reset!
+    end
+
+    # The RES line clears every register but the timers and the shift
+    # register, which carry on counting, and so releases IRQ.
+    def reset!
+      @ora = @orb = @ddra = @ddrb = 0x00
+      @latch_a = @latch_b = 0xff
+      @ifr.reset!
+      @ca.reset!
+      @cb.reset!
+      write_acr(0x00)
+      @pcr = 0x00
+    end
+
+    def irq? = @ifr.irq?
+
+    def cycle!
+      @ca.cycle! if @ca.pulsing?
+      @cb.cycle! if @cb.pulsing?
+      @ifr.set(InterruptRegister::TIMER1) if @t1.cycle!(@acr.anybits?(0x40))
+      @ifr.set(InterruptRegister::TIMER2) if @t2.cycle!(@sr_uses_t2)
+      @ifr.set(InterruptRegister::SR) if @shift_register.cycle!(@t2.low_underflowed)
+    end
+
+    # Port A as driven by ORA and DDRA, input lines floating high.
+    def port_a_output = driven_lines(@ora, @ddra)
+
+    # Port B as driven by ORB and DDRB, with PB7 handed to timer 1 by ACR
+    # bit 7.
+    def port_b_output
+      lines = driven_lines(@orb, @ddrb)
+      return lines unless @acr.anybits?(0x80)
+
+      @t1.pb7 ? lines | 0x80 : lines & 0x7f
+    end
+
+    # An active CA1 edge latches port A while ACR bit 0 is set.
+    def ca1=(high)
+      return if high == @ca.c1_high
+
+      @latch_a = pins_a if @acr.anybits?(0x01) && @ca.active_c1_edge?(high)
+      @ca.c1 = high
+    end
+
+    def ca2=(high)
+      @ca.c2 = high
+    end
+
+    # An active CB1 edge latches port B while ACR bit 1 is set. CB1 also
+    # clocks the shift register in its external clock modes.
+    def cb1=(high)
+      return if high == @cb.c1_high
+
+      @ifr.set(InterruptRegister::SR) if @shift_register.cb1_edge!(high)
+      @latch_b = pins_b if @acr.anybits?(0x02) && @cb.active_c1_edge?(high)
+      @cb.c1 = high
+    end
+
+    def cb2=(high)
+      @shift_register.cb2_input = high
+      @cb.c2 = high
+    end
+
+    # A falling edge counts a pulse while timer 2 counts them.
+    def pb6=(high)
+      fell = @pb6_high && !high
+      @pb6_high = high
+      @ifr.set(InterruptRegister::TIMER2) if fell && @t2.pulse!
+    end
+
+    def ca2_output = @ca.c2_output
+
+    # The shift register's clock on CB1, or nil when CB1 is an input.
+    def cb1_output = @shift_register.cb1_output
+
+    # The shift register takes CB2 over in its shift-out modes.
+    def cb2_output
+      level = @shift_register.cb2_output
+      level.nil? ? @cb.c2_output : level
+    end
+
+    def peek(addr)
+      case offset_of(addr) & 0x0f
+      when 0x00 then read_port_b
+      when 0x01 then read_port_a(handshake: true)
+      when 0x02 then @ddrb
+      when 0x03 then @ddra
+      when 0x04 then read_timer_low(@t1.counter, InterruptRegister::TIMER1)
+      when 0x05 then high_byte(@t1.counter)
+      when 0x06 then low_byte(@t1.latch)
+      when 0x07 then high_byte(@t1.latch)
+      when 0x08 then read_timer_low(@t2.counter, InterruptRegister::TIMER2)
+      when 0x09 then high_byte(@t2.counter)
+      when 0x0a then read_shift_register
+      when 0x0b then @acr
+      when 0x0c then @pcr
+      when 0x0d then @ifr.read
+      when 0x0e then @ifr.read_enable
+      else read_port_a(handshake: false)
+      end
+    end
+
+    def poke(addr, value)
+      case offset_of(addr) & 0x0f
+      when 0x00 then write_port_b(value)
+      when 0x01 then write_port_a(value, handshake: true)
+      when 0x02 then @ddrb = value
+      when 0x03 then @ddra = value
+      when 0x04, 0x06 then @t1.write_latch_low(value)
+      when 0x05 then write_timer1_high(value, start: true)
+      when 0x07 then write_timer1_high(value, start: false)
+      when 0x08 then @t2.latch_low = value
+      when 0x09 then write_timer2_high(value)
+      when 0x0a then write_shift_register(value)
+      when 0x0b then write_acr(value)
+      when 0x0c then write_pcr(value)
+      when 0x0d then @ifr.write(value)
+      when 0x0e then @ifr.write_enable(value)
+      else write_port_a(value, handshake: false)
+      end
+    end
+
+    private
+
+    # Output bits are driven from the data register; input bits float high.
+    # External peripherals can still pull any line low (wired-AND).
+    def driven_lines(register, direction)
+      (register & direction) | (~direction & 0xff)
+    end
+
+    def pins_a
+      lines = port_a_output
+      peripheral ? lines & peripheral.read_a(lines) : lines
+    end
+
+    def pins_b
+      lines = port_b_output
+      peripheral ? lines & peripheral.read_b(lines) : lines
+    end
+
+    # Port A reads the pins, or what CA1 latched off them.
+    def read_port_a(handshake:)
+      value = @acr.anybits?(0x01) ? @latch_a : pins_a
+      @ca.access!(false) if handshake
+      value
+    end
+
+    def write_port_a(value, handshake:)
+      @ora = value
+      @ca.access!(true) if handshake
+    end
+
+    # Port B reads its output bits from ORB, or from timer 1 for PB7, and
+    # its input bits from the pins, or from what CB1 latched off them.
+    def read_port_b
+      outputs = @acr.anybits?(0x80) ? @ddrb | 0x80 : @ddrb
+      inputs = @acr.anybits?(0x02) ? @latch_b : pins_b
+      @cb.access!(false)
+      (port_b_output & outputs) | (inputs & ~outputs & 0xff)
+    end
+
+    def write_port_b(value)
+      @orb = value
+      @cb.access!(true)
+    end
+
+    # A read of either timer's low counter byte acknowledges its interrupt.
+    def read_timer_low(counter, flag)
+      @ifr.clear(flag)
+      low_byte(counter)
+    end
+
+    # $5 loads and starts the counter; $7 only writes the latch. Both
+    # acknowledge the interrupt.
+    def write_timer1_high(value, start:)
+      @t1.write_latch_high(value)
+      @t1.start! if start
+      @ifr.clear(InterruptRegister::TIMER1)
+    end
+
+    def write_timer2_high(value)
+      @t2.load(value)
+      @ifr.clear(InterruptRegister::TIMER2)
+    end
+
+    def read_shift_register
+      value = @shift_register.data
+      @shift_register.access!
+      @ifr.clear(InterruptRegister::SR)
+      value
+    end
+
+    def write_shift_register(value)
+      @shift_register.data = value
+      @shift_register.access!
+      @ifr.clear(InterruptRegister::SR)
+    end
+
+    # Bits 4-2 pick the shift register's mode. Modes 1, 4 and 5 clock off
+    # timer 2's low byte. Bit 7 turning on hands PB7 to timer 1 high.
+    def write_acr(value)
+      @t1.pb7_enabled! if value.anybits?(0x80) && @acr.nobits?(0x80)
+      @acr = value
+      @t2.count_pulses = value.anybits?(0x20)
+      mode = (value >> 2) & 0x07
+      @shift_register.mode = mode
+      @sr_uses_t2 = [1, 4, 5].include?(mode)
+    end
+
+    def write_pcr(value)
+      @pcr = value
+      @ca.control = value & 0x0f
+      @cb.control = value >> 4
+    end
+  end
+end

data/lib/badline/vic/bank.rb

@@ -2,7 +2,8 @@
 
 module Badline
   class VIC < Cycleable
-    # The 16K window the VIC sees into RAM, selected by CIA2 $DD00. Character
+    # The 16K window the VIC sees into RAM, selected by CIA2 $DD00, in the
+    # bank a +256K picks for it. Character
     # ROM shadows $1000-$1FFF in banks 0 and 2.
     class Bank
       include Addressable
@@ -24,7 +25,7 @@ module Badline
         if bits.allbits?(0b01) && (offset & 0xf000) == 0x1000
           @address_bus.character_rom.peek(0xc000 + offset)
         else
-          @address_bus.ram.peek(BANK_STARTS[bits] + offset)
+          @address_bus.video_ram.peek(BANK_STARTS[bits] + offset)
         end
       end
 
@@ -61,7 +62,7 @@ module Badline
         if romh && offset.allbits?(0x3000)
           romh.peek(0xe000 + (offset & 0x1fff))
         else
-          @address_bus.ram.peek(BANK_STARTS[bank_switch_register] + offset)
+          @address_bus.video_ram.peek(BANK_STARTS[bank_switch_register] + offset)
         end
       end
 

data/lib/badline/vic/color_patches.rb

@@ -5,17 +5,20 @@ module Badline
     # A mid-line color register write becomes visible one pixel into the
     # column emitted the cycle after the write. That emit paints the whole
     # column with the new color, so the boundary pixel is patched back to
-    # the old one before the line is finished.
+    # the old one before the line is finished. On the 8565 the boundary
+    # pixel shows light grey instead, the grey dot, whatever the old and new
+    # colors are.
     class ColorPatches
-      def initialize(sequencer)
+      def initialize(sequencer, grey_dots: false)
         @sequencer = sequencer
+        @grey_dots = grey_dots
         @patches = []
       end
 
       def clear = @patches.clear
 
       def log(reg, old, value, boundary_x)
-        @patches << [boundary_x, reg, old & 0x0f, value & 0x0f]
+        @patches << [boundary_x, reg, @grey_dots ? GREY_DOT : old & 0x0f, value & 0x0f]
       end
 
       def apply(colors, fg_mask)

data/lib/badline/vic/display_state.rb

@@ -75,15 +75,19 @@ module Badline
         @in_window = line.between?(FIRST_LINE, LAST_LINE)
       end
 
+      # Returns true when this compare opened display state.
       def cycle(rasterline, column)
         match = column == WRAP_COLUMN ? wrap_match(rasterline + 1) : line_match
         @matched = match
+        opened = false
         if match
+          opened = !@display
           @display = true
           @ba = column if @ba.nil? && column >= DMA_FIRST && column <= DMA_LAST
         end
         load_counters(match) if column == LOAD_COLUMN
         check_row_counter(match) if column == RC_COLUMN
+        opened
       end
 
       # A g-access in display state consumes one buffer cell and one video