badline 0.15.0 → 0.15.1

data/lib/badline/plus4/bus.rb

@@ -10,9 +10,14 @@ module Badline
     # $C000-$FCFF - the high ROM bank, or RAM; $FC00-$FCFF is always the
     #               KERNAL's while ROM is selected
     # $FD00-$FD0F - the 6551 ACIA (Plus/4 only)
-    # $FD10-$FD1F - the user port's 6529 (Plus/4 only)
+    # $FD10-$FD1F - the user port's 6529 (Plus/4 only), or with a RAM
+    #               expansion, the 6529 at $FD10 and the expansion's
+    #               registers at $FD15 and $FD16
     # $FD30-$FD3F - the keyboard's 6529 (KeyboardPort)
+    # $FD40-$FD5F - a SID card's SID, where one is fitted there
     # $FDD0-$FDDF - the ROM bank latch
+    # $FE80-$FE9F - a SID card's SID, where one is fitted there
+    # $FEC0-$FEFF - a 1551's TCBM interface, where one is plugged in
     # $FF00-$FF1F - the TED
     # $FF3E/$FF3F - a write selects ROM or RAM at $8000-$FFFF
     # $FF40-$FFFF - the high ROM bank, or RAM
@@ -27,7 +32,8 @@ module Badline
     #
     # RAM smaller than 64K repeats through the 64K, as the C16's 16K does
     # without A14 and A15. Where nothing answers, a read finds the last byte
-    # on the bus.
+    # on the bus. A RAM expansion (RAMExpansion) picks the RAM each page
+    # reads and writes, the CPU's and the TED's.
     #
     # The TED fetches through the same banks: the video matrix and the
     # attributes from ROM or RAM at $8000-$FFFF as the CPU sees it, with no
@@ -40,17 +46,18 @@ module Badline
 
       RAM_POWER_ON = 0x00
 
-      # RAM through a size it repeats at.
+      # RAM through a size it repeats at, from +offset+ on in +ram+.
       class MirroredRAM
-        def initialize(ram, mask)
+        def initialize(ram, mask, offset = 0)
           @ram = ram
           @mask = mask
+          @offset = offset
         end
 
-        def peek(addr) = @ram.peek(addr & @mask)
+        def peek(addr) = @ram.peek((addr & @mask) + @offset)
 
         def poke(addr, value)
-          @ram.poke(addr & @mask, value)
+          @ram.poke((addr & @mask) + @offset, value)
         end
       end
 
@@ -80,14 +87,20 @@ module Badline
         end
       end
 
-      # Page $FD: the ACIA, the user port, the keyboard port and the ROM
-      # bank latch, by the address's bits 4-7. +acia+ and +user_port+ are
-      # nil where the machine has none, and +cassette_sense+ answers in the
-      # user port's place on a machine without one (CassetteSense).
+      # Page $FD: the ACIA, the user port, the keyboard port, a SID card and
+      # the ROM bank latch, by the address's bits 4-7. +acia+, +user_port+
+      # and +sid_card+ are nil where the machine has none, and
+      # +cassette_sense+ answers in the user port's place on a machine
+      # without one (CassetteSense). The SID card decodes its 32 bytes
+      # alone, with no mirrors, as xplus4's does. A RAM expansion
+      # (RAMExpansion) leaves the user port only $FD10 of $FD10-$FD1F, and
+      # has its register at $FD16.
       class IOPage
-        def initialize(keyboard_port:, acia: nil, user_port: nil, cassette_sense: nil)
+        def initialize(keyboard_port:, acia: nil, user_port: nil, cassette_sense: nil, sid_card: nil)
           @bus = nil
+          @ram_expansion = nil
           @acia = acia
+          @sid_card = sid_card
           @user_port = user_port
           @cassette_sense = cassette_sense
           @keyboard_port = keyboard_port
@@ -97,13 +110,15 @@ module Badline
         # a write to $FDD0-$FDDF sets.
         def connect(bus)
           @bus = bus
+          @ram_expansion = bus.ram_expansion
         end
 
         def peek(addr)
           case addr & 0xf0
           when 0x00 then @acia ? @acia.peek(addr) : @bus.data
-          when 0x10 then user_port_peek(addr)
+          when 0x10 then @ram_expansion ? expansion_peek(addr) : user_port_peek(addr)
           when 0x30 then @keyboard_port.peek(addr)
+          when 0x40, 0x50 then @sid_card ? @sid_card.peek(addr) : @bus.data
           else @bus.data
           end
         end
@@ -111,14 +126,31 @@ module Badline
         def poke(addr, value)
           case addr & 0xf0
           when 0x00 then @acia&.poke(addr, value)
-          when 0x10 then @user_port&.poke(addr, value)
+          when 0x10 then @ram_expansion ? expansion_poke(addr, value) : @user_port&.poke(addr, value)
           when 0x30 then @keyboard_port.poke(addr, value)
+          when 0x40, 0x50 then @sid_card&.poke(addr, value)
           when 0xd0 then @bus.select_banks(addr)
           end
         end
 
         private
 
+        def expansion_peek(addr)
+          case addr & 0x0f
+          when 0x00 then user_port_peek(addr)
+          when RAMExpansion::CONTROL then @ram_expansion.control
+          else @bus.data
+          end
+        end
+
+        def expansion_poke(addr, value)
+          if addr.nobits?(0x0f)
+            @user_port&.poke(addr, value)
+          else
+            @bus.ram_expansion_written(addr, value)
+          end
+        end
+
         def user_port_peek(addr)
           return @user_port.peek(addr) if @user_port
           return @cassette_sense.read(@bus.data) if @cassette_sense
@@ -148,26 +180,50 @@ module Badline
         end
       end
 
-      # Page $FE with a 1551's TCBM interface plugged in: the 6523 TIA
-      # that talks to drive 9 at $FEC0-$FEDF and drive 8's at $FEE0-$FEFF.
-      # The rest of the page is open.
+      # Page $FE, where a 1551's TCBM interface puts its 6523 TIA: the one
+      # that talks to drive 9 at $FEC0-$FEDF and drive 8's at $FEE0-$FEFF,
+      # and where a SID card can put its SID, at $FE80-$FE9F, decoding its
+      # 32 bytes alone as xplus4's does. The rest of the page, and a place
+      # with nothing in it, is open.
       class TCBMPage
-        def initialize(bus, drive8:, drive9:)
+        # The TIA at $FEE0-$FEFF and the one at $FEC0-$FEDF, or nil.
+        attr_accessor :drive8, :drive9
+
+        # The SIDCard at $FE80-$FE9F, or nil.
+        attr_accessor :sid_card
+
+        def initialize(bus)
           @bus = bus
-          @drive8 = drive8
-          @drive9 = drive9
+          @drive8 = nil
+          @drive9 = nil
+          @sid_card = nil
         end
 
         def peek(addr)
-          return @bus.data if addr < 0xfec0
+          return low_peek(addr) if addr < 0xfec0
 
-          addr < 0xfee0 ? @drive9.peek(addr) : @drive8.peek(addr)
+          tia = addr < 0xfee0 ? @drive9 : @drive8
+          tia ? tia.peek(addr) : @bus.data
         end
 
         def poke(addr, value)
-          return if addr < 0xfec0
+          if addr < 0xfec0
+            sid_card = @sid_card
+            sid_card.poke(addr, value) if sid_card && sid_card?(addr)
+            return
+          end
+
+          tia = addr < 0xfee0 ? @drive9 : @drive8
+          tia&.poke(addr, value)
+        end
+
+        private
+
+        def sid_card?(addr) = (addr & 0xe0) == 0x80
 
-          addr < 0xfee0 ? @drive9.poke(addr, value) : @drive8.poke(addr, value)
+        def low_peek(addr)
+          sid_card = @sid_card
+          sid_card && sid_card?(addr) ? sid_card.peek(addr) : @bus.data
         end
       end
 
@@ -186,7 +242,7 @@ module Badline
         end
 
         def poke(addr, value)
-          return @bus.ram_view.poke(addr, value) if addr >= 0xff40
+          return @bus.top_ram.poke(addr, value) if addr >= 0xff40
 
           case addr
           when 0xff3e then @bus.rom_selected = true
@@ -201,17 +257,29 @@ module Badline
       # What the top page reads above $FF3F: the high ROM bank or RAM.
       attr_reader :top_memory
 
+      # The RAM the CPU sees at $FF00-$FFFF, which a write above $FF3F
+      # reaches.
+      attr_reader :top_ram
+
+      # The RAMExpansion fitted, or nil.
+      attr_reader :ram_expansion
+
       # The CPU sees ROM at $8000-$FFFF.
       attr_reader :rom_selected
 
       # +io+ is the IOPage, +model+ a Model profile, whose KERNAL it maps
       # and whose function ROMs it maps where the model has them, and
-      # +ram_kb+ the RAM fitted.
-      def initialize(ted:, port:, io:, model: Model::PLUS4, ram_kb: model.ram_kb)
+      # +ram_kb+ the RAM fitted. +ram_expansion+ names the kind of
+      # RAMExpansion to fit over 64K of it.
+      def initialize(ted:, port:, io:, model: Model::PLUS4, ram_kb: model.ram_kb, ram_expansion: nil)
         addressable_at(0, length: 2**16)
         size = ram_kb * 1024
         @ram = Memory.new(Array.new(size, RAM_POWER_ON), length: size, start: 0)
         @ram_view = MirroredRAM.new(@ram, size - 1)
+        @ram_expansion = ram_expansion ? RAMExpansion.new(ram_expansion, @ram, @ram_view) : nil
+        @cpu_ram = Array.new(256, @ram_view)
+        @ted_ram = Array.new(256, @ram_view)
+        @top_ram = @ram_view
         @ted = ted
         @open_bus = OpenBus.new(self)
         @low_roms = [ROM.load("plus4/basic.rom", 0x8000), nil, nil, nil]
@@ -220,11 +288,12 @@ module Badline
           @low_roms[1] = ROM.load("plus4/function-low.rom", 0x8000)
           @high_roms[1] = ROM.load("plus4/function-high.rom", 0xc000)
         end
+        @port = port
         @zero_page = ZeroPage.new(port, @ram_view)
         @io_page = io
         io.connect(self)
         @top_page = TopPage.new(self, ted)
-        @tcbm_page = @open_bus
+        @tcbm_page = TCBMPage.new(self)
         @debug_register = nil
         @data = 0
         @read_pages = Array.new(256, @open_bus)
@@ -234,19 +303,29 @@ module Badline
         @low_bank = @high_bank = 0
         @rom_selected = true
         @top_memory = @ram_view
-        map_writes
-        map_reads
+        map_ram
       end
 
       def power_on!
         @ram.clear!(Array.new(@ram.length, RAM_POWER_ON))
+        @ram_expansion&.power_on!
         reset!
       end
 
-      # The RESET line selects ROM and the first bank of each.
+      # The RESET line selects ROM and the first bank of each, and sets a
+      # RAM expansion's register.
       def reset!
         @low_bank = @high_bank = 0
-        self.rom_selected = true
+        @ram_expansion&.reset!
+        @rom_selected = true
+        @ted.rom_selected = true
+        map_ram
+      end
+
+      # A write to a RAM expansion's registers in $FD11-$FD1F.
+      def ram_expansion_written(addr, value)
+        @ram_expansion.poke(addr, value)
+        map_ram
       end
 
       def rom_selected=(selected)
@@ -274,9 +353,23 @@ module Badline
 
       # Plugs in a 1551's TCBM interface, the TIAs at $FEC0-$FEFF.
       def plug_tcbm(drive8:, drive9:)
-        @tcbm_page = TCBMPage.new(self, drive8:, drive9:)
-        map_writes
-        map_reads
+        @tcbm_page.drive8 = drive8
+        @tcbm_page.drive9 = drive9
+      end
+
+      # Puts a SIDCard at $FE80-$FE9F.
+      def plug_sid_card(sid_card)
+        @tcbm_page.sid_card = sid_card
+      end
+
+      # Puts +tia+ where the TCBM interface for +device+, 8 or 9, answers,
+      # or takes the one there out with nil.
+      def plug_tia(device, tia)
+        if device == 9
+          @tcbm_page.drive9 = tia
+        else
+          @tcbm_page.drive8 = tia
+        end
       end
 
       # Puts a cartridge's ROM chips in their slots, as a PLUS4 CARTRIDGE
@@ -334,12 +427,35 @@ module Badline
 
       # A TED fetch of character or bitmap data, from ROM when +rom+.
       def ted_pattern_fetch(addr, rom)
-        @data = rom ? @ted_rom_pages[addr >> 8].peek(addr) : @ram_view.peek(addr)
+        @data = rom ? @ted_rom_pages[addr >> 8].peek(addr) : @ted_ram[addr >> 8].peek(addr)
       end
 
       private
 
+      # Lays out the RAM a RAM expansion banks in, then every page.
+      def map_ram
+        expansion = @ram_expansion
+        if expansion
+          expansion.map(@cpu_ram, @ted_ram)
+          @zero_page = ZeroPage.new(@port, @cpu_ram[0])
+          @top_ram = @cpu_ram[0xff]
+        end
+        map_writes
+        map_reads
+      end
+
+      # Copies the RAM the CPU sees into +pages+, up to the I/O pages.
+      def copy_ram(pages)
+        cpu_ram = @cpu_ram
+        page = 1
+        while page < 0xfd
+          pages[page] = cpu_ram[page]
+          page += 1
+        end
+      end
+
       def map_writes
+        copy_ram(@write_pages) if @ram_expansion
         @write_pages[0x00] = @zero_page
         @write_pages[0xfd] = @debug_register || @io_page
         @write_pages[0xfe] = @tcbm_page
@@ -347,10 +463,14 @@ module Badline
       end
 
       def map_reads
-        @read_pages.fill(@ram_view, 0x00, 0xfd)
+        if @ram_expansion
+          copy_ram(@read_pages)
+        else
+          @read_pages.fill(@ram_view, 0x00, 0xfd)
+        end
         @read_pages[0x00] = @zero_page
-        map_roms(@read_pages) if @rom_selected
-        @top_memory = @rom_selected ? @high_roms[@high_bank] || @open_bus : @ram_view
+        map_roms(@read_pages, @high_bank) if @rom_selected
+        @top_memory = @rom_selected ? @high_roms[@high_bank] || @open_bus : @top_ram
         @read_pages[0xfd] = @io_page
         @read_pages[0xfe] = @tcbm_page
         @read_pages[0xff] = @top_page
@@ -358,16 +478,32 @@ module Badline
       end
 
       def map_ted_reads
-        @ted_pages.fill(@ram_view, 0x80, 0x80)
-        map_roms(@ted_pages) if @rom_selected
-        map_roms(@ted_rom_pages)
-        @ted_pages.fill(@high_roms[@high_bank] || @open_bus, 0xfd, 3) if @rom_selected
-        @ted_rom_pages.fill(@high_roms[@high_bank] || @open_bus, 0xfd, 3)
+        expansion = @ram_expansion
+        if expansion
+          copy_ted_ram
+        else
+          @ted_pages.fill(@ram_view, 0x80, 0x80)
+        end
+        high_bank = expansion&.kernal_for_ted? ? 0 : @high_bank
+        high_rom = @high_roms[high_bank] || @open_bus
+        map_roms(@ted_pages, high_bank) if @rom_selected
+        map_roms(@ted_rom_pages, high_bank)
+        @ted_pages.fill(high_rom, 0xfd, 3) if @rom_selected
+        @ted_rom_pages.fill(high_rom, 0xfd, 3)
+      end
+
+      def copy_ted_ram
+        ted_ram = @ted_ram
+        page = 0
+        while page < 0x100
+          @ted_pages[page] = ted_ram[page]
+          page += 1
+        end
       end
 
-      def map_roms(pages)
+      def map_roms(pages, high_bank)
         pages.fill(@low_roms[@low_bank] || @open_bus, 0x80, 0x40)
-        pages.fill(@high_roms[@high_bank] || @open_bus, 0xc0, 0x3c)
+        pages.fill(@high_roms[high_bank] || @open_bus, 0xc0, 0x3c)
         pages[0xfc] = @high_roms[0]
       end
     end

data/lib/badline/plus4/keyed_modules.rb

@@ -4,11 +4,12 @@ module Badline
   class Plus4
     # The whole machine as keyed snapshot modules (Snapshot::Keyed): BL-MACHINE
     # with the setup, the cartridges' ROMs by slot, the CPU with its port,
-    # the TED, its sound, the keyboard's 6529, the user port's 6529 and the
-    # ACIA where the model has them, the TCBM interface's TIAs where one is
-    # plugged in, the RAM with the ROM bank latch and the ROM/RAM switch
-    # under bus.*, the datasette, device 8 through the traps and the true
-    # drives.
+    # the TED, its sound, the SID card's SID where one is fitted, the
+    # keyboard's 6529, the user port's 6529 and the ACIA where the model
+    # has them, the TCBM interface's TIAs where one is plugged in, the RAM
+    # with the ROM bank latch and the ROM/RAM switch under bus.*, a RAM
+    # expansion's registers and banks, the datasette, device 8 through the
+    # traps and the true drives.
     #
     # A load maps the banks before the chips load, and works out what each
     # unit derives from its fields once every unit is loaded.
@@ -22,6 +23,8 @@ module Badline
           bus.ram.save_fields(out, "ram")
           bus.save_fields(out, "bus.")
         end
+        expansion = bus.ram_expansion
+        sections << Snapshot::Keyed.section("BL-RAMEXP") { |out| expansion.save_fields(out) } if expansion
         sections << Snapshot::Keyed.section("BL-TAPE") { |out| @datasette.save_fields(out) }
         sections << Snapshot::Keyed.section("BL-TRAPDOS") { |out| save_trap_dos_fields(out) } if mounted?
         save_drive_modules(sections)
@@ -38,6 +41,7 @@ module Badline
         bus.ram.load_fields(memory, "ram")
         bus.load_fields(memory, "bus.")
         bus.load_slot_fields(modules.optional("BL-CART") || Snapshot::Keyed::Reader.new("BL-CART"))
+        load_ram_expansion(modules)
         bus.restored!
         load_chip_modules(modules)
         @datasette.load_fields(modules.required("BL-TAPE"))
@@ -50,6 +54,13 @@ module Badline
 
       private
 
+      def load_ram_expansion(modules)
+        expansion = @bus.ram_expansion
+        return if expansion.nil?
+
+        expansion.load_fields(modules.required("BL-RAMEXP"))
+      end
+
       def save_chip_modules(sections)
         sections << Snapshot::Keyed.section("BL-CPU") do |out|
           @cpu.save_fields(out)
@@ -57,6 +68,8 @@ module Badline
         end
         sections << Snapshot::Keyed.section("BL-TED") { |out| @ted.save_fields(out) }
         sections << Snapshot::Keyed.section("BL-TEDSOUND") { |out| @sound.save_fields(out) }
+        sid_card = @sid_card
+        sections << Snapshot::Keyed.section("BL-SID") { |out| sid_card.save_fields(out) } if sid_card
         sections << Snapshot::Keyed.section("BL-KEYPORT") { |out| @keyboard_port.save_fields(out) }
         user_port = @user_port
         sections << Snapshot::Keyed.section("BL-USERPORT") { |out| user_port.save_fields(out) } if user_port
@@ -72,6 +85,7 @@ module Badline
         @port.load_fields(cpu, "port.")
         @ted.load_fields(modules.required("BL-TED"))
         @sound.load_fields(modules.required("BL-TEDSOUND"))
+        @sid_card&.load_fields(modules.required("BL-SID"))
         @keyboard_port.load_fields(modules.required("BL-KEYPORT"))
         @user_port&.load_fields(modules.required("BL-USERPORT"))
         @acia&.load_fields(modules.required("BL-ACIA"))
@@ -83,7 +97,10 @@ module Badline
         @cpu.restored!
         @ted.restored!
         @sound.restored!(@ted)
+        @sid_card&.restored!
         @port.restored!
+        @acia&.restored!
+        schedule
       end
 
       def check_snapshot_setup(setup)

data/lib/badline/plus4/keyed_parts.rb

@@ -53,14 +53,43 @@ module Badline
     end
 
     class ACIA
-      # The command and control registers in a keyed snapshot module
-      # (BL-ACIA).
+      # The registers, the status, the shift register and when the
+      # transmitter's character ends, in a keyed snapshot module (BL-ACIA).
+      # What the device on the user port has still to send stays with the
+      # host, and the receiver starts on it again once loaded (#restored!).
+      # A snapshot from before the transmitter's timing was saved starts
+      # its character clock on load.
       module KeyedState
-        def save_fields(out) = out.int("command", @command).int("control", @control)
+        def save_fields(out)
+          out.int("command", @command).int("control", @control).int("errors", @errors)
+          out.bool("receiver_full", @receiver_full).bool("transmitter_empty", @transmitter_empty).bool("irq", @irq)
+          out.int("receive_data", @receive_data).int("transmit_data", @transmit_data).int("shifting", @shifting)
+          out.int("transmit_at", @transmit_at).int("transmit_remainder", @transmit_remainder)
+        end
 
         def load_fields(input)
           @command = input.byte("command", @command)
           @control = input.byte("control", @control)
+          @errors = input.masked("errors", 0, PARITY_ERROR | FRAMING_ERROR | OVERRUN)
+          @receiver_full = input.bool("receiver_full", false)
+          @transmitter_empty = input.bool("transmitter_empty", true)
+          @irq = input.bool("irq", false)
+          @receive_data = input.byte("receive_data", 0)
+          @transmit_data = input.byte("transmit_data", 0)
+          @shifting = input.int("shifting", IDLE)
+          @transmit_remainder = input.int("transmit_remainder", 0)
+          transmit_at = input.optional_int("transmit_at")
+          @transmit_at = transmit_at || NEVER
+          @clock_lost = transmit_at.nil?
+        end
+
+        def restored!
+          @receive_at = NEVER
+          @lines = modem_lines
+          start_transmitting if @clock_lost && transmitter_on?
+          @clock_lost = false
+          start_receiving
+          changed
         end
       end
 
@@ -126,7 +155,7 @@ module Badline
 
         def restored!
           @ted.rom_selected = @rom_selected
-          map_reads
+          map_ram
         end
 
         private

data/lib/badline/plus4/keyed_state.rb

@@ -16,8 +16,11 @@ module Badline
       # instructions or jammed.
       def settled_for_snapshot? = @cpu.boundary? || @cpu.jammed?
 
-      # The sound's voices, run up to this cycle.
-      def settle_chips_for_snapshot = @sound.catch_up!
+      # The sound's voices and the SID card's, run up to this cycle.
+      def settle_chips_for_snapshot
+        @sound.catch_up!
+        @sid_card&.catch_up!
+      end
 
       def save_machine_fields(out)
         out.text("family", "plus4").text("written_by", VERSION)

data/lib/badline/plus4/ram_expansion.rb

@@ -0,0 +1,145 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # Hannes's RAM expansion, 256K or 1M in 64K banks, and Csory's 256K on
+    # the same board, from Solder's register notes and the board's GAL
+    # equations (plus4world, "256K RAM (Hannes)").
+    #
+    # The control register is a 6529 at $FD16, which reads back what was
+    # written. The expansion decodes $FD10-$FD1F further, so the user port
+    # answers only at $FD10, and the rest of the range is open.
+    #
+    # - Bits 0-1, and bits 2-3 on the 1M: the bank the CPU sees above the
+    #   switch bound. All ones is the standard bank, the RAM below the
+    #   bound, which bits 0-3 pick inverted: bank 3 of the 256K and bank
+    #   15 of the 1M.
+    # - Bit 6: the TED fetches from the CPU's bank when set, and from the
+    #   standard bank when clear.
+    # - Bit 7: the switch bound, $4000 when set, $1000 when clear.
+    # - Bits 4-5: on the Csory board, two different bits switch Csory's
+    #   mapping on (the notes' gate version; its table names 10 and its
+    #   GAL 01).
+    #
+    # The register is all ones at power-on and after a reset, so the
+    # machine starts in the standard bank, with the TED following it.
+    #
+    # Csory's mapping puts one 16K block of the 256K, picked by bits 0-3
+    # of a write-only latch at $FD15, in the 16K window of the CPU's 64K
+    # that bits 6-7 pick. The standard bank holds blocks 0-3. The TED sees
+    # the block too while bit 6 of $FD16 is set. On the Csory board the
+    # TED reads the KERNAL wherever it fetches from the high ROM, whichever
+    # bank the ROM latch selects.
+    class RAMExpansion
+      # Each expansion by name: its 64K banks, and whether it has Csory's
+      # mapping.
+      KINDS = { hannes256: [4, false], hannes1m: [16, false], csory256: [4, true] }.freeze
+
+      # Whose design each is, as the pause menu names it.
+      NAMES = { hannes256: "HANNES", hannes1m: "HANNES", csory256: "CSORY" }.freeze
+
+      CONTROL = 0x06
+      CSORY_LATCH = 0x05
+
+      # The register at $FD16, and Csory's latch at $FD15.
+      attr_reader :kind, :control, :csory_latch
+
+      # +ram+ is the machine's own 64K, the standard bank, and +view+ the
+      # Bus::MirroredRAM the bus reads it through.
+      def initialize(kind, ram, view)
+        @kind = kind
+        count, csory = KINDS.fetch(kind)
+        @csory = csory
+        @mask = count - 1
+        size = (count - 1) * 0x10000
+        @extra = Memory.new(Array.new(size, Bus::RAM_POWER_ON), length: size, start: 0)
+        @banks = [view] + Array.new(count - 1) { |index| Bus::MirroredRAM.new(@extra, 0xffff, index * 0x10000) }
+        @blocks = csory ? Array.new(16) { |block| block_view(ram, block) } : []
+        @control = 0xff
+        @csory_latch = 0
+      end
+
+      # The size in K.
+      def size_kb = (@mask + 1) * 64
+
+      # Whether the TED reads the KERNAL for the whole high ROM.
+      def kernal_for_ted? = @csory
+
+      # A write to $FD11-$FD1F: the control register at $FD16, and on the
+      # Csory board, Csory's latch at $FD15.
+      def poke(addr, value)
+        case addr & 0x0f
+        when CONTROL then @control = value
+        when CSORY_LATCH then @csory_latch = value if @csory
+        end
+      end
+
+      # The RESET line sets the register, as power-on does. Csory's latch
+      # keeps its value.
+      def reset!
+        @control = 0xff
+      end
+
+      def power_on!
+        @extra.clear!(Array.new(@extra.length, Bus::RAM_POWER_ON))
+        @csory_latch = 0
+        reset!
+      end
+
+      # Lays the RAM the CPU sees out in +cpu+ and the RAM the TED sees in
+      # +ted+, a view for each of the 256 pages.
+      def map(cpu, ted)
+        control = @control
+        bound = control.anybits?(0x80) ? 0x40 : 0x10
+        standard = @banks[0]
+        cpu.fill(standard, 0x00, bound)
+        cpu.fill(@banks[~control & @mask], bound, 0x100 - bound)
+        follows = control.anybits?(0x40)
+        if follows
+          page = 0
+          while page < 0x100
+            ted[page] = cpu[page]
+            page += 1
+          end
+        else
+          ted.fill(standard, 0x00, 0x100)
+        end
+        return unless csory_on?
+
+        latch = @csory_latch
+        block = @blocks[latch & 0x0f]
+        window = (latch >> 6) * 0x40
+        cpu.fill(block, window, 0x40)
+        ted.fill(block, window, 0x40) if follows
+      end
+
+      # The banks beyond the standard one, and Csory's latch, in a keyed
+      # snapshot module (BL-RAMEXP).
+      def save_fields(out)
+        out.int("control", @control)
+        out.int("csory_latch", @csory_latch) if @csory
+        @extra.save_fields(out, "ram")
+      end
+
+      def load_fields(input)
+        @control = input.byte("control", @control)
+        @csory_latch = input.byte("csory_latch", @csory_latch)
+        @extra.load_fields(input, "ram")
+      end
+
+      private
+
+      def csory_on?
+        control = @control
+        @csory && control.anybits?(0x10) != control.anybits?(0x20)
+      end
+
+      # Block +block+ of the 256K, from the standard bank's four on.
+      def block_view(ram, block)
+        return Bus::MirroredRAM.new(ram, 0x3fff, block * 0x4000) if block < 4
+
+        Bus::MirroredRAM.new(@extra, 0x3fff, (block - 4) * 0x4000)
+      end
+    end
+  end
+end