badline 0.14.0 → 0.15.0

data/doc/snapshot-format.md

@@ -13,19 +13,20 @@ machine built afresh has: the default below. `word`, `byte` and
 `int & 0x..` are ints cut to the latch's width. A text that lists
 its values takes one of them. An optional int is absent when the
 latch holds nothing. A true drive's modules are named from its
-device number, `BL-D8` to `BL-D11`. Keys with `<N>` stand for each
-numbered unit. A default of "written only" is a key the load
-doesn't read, or reads only when the snapshot has it. Where the
-machines differ, the default is given for each, and a key only
-some of them have names them.
+device number, `BL-D8` to `BL-D11`, and the SIDs past the first
+are `BL-SID2` onwards, in the order they were fitted. Keys with
+`<N>` stand for each numbered unit. A default of "written only" is
+a key the load doesn't read, or reads only when the snapshot has
+it. Where the machines differ, the default is given for each, and a
+key only some of them have names them.
 
 ## BL-MACHINE
 
-Written by the C64, VIC-20, C128.
+Written by the C64, VIC-20, C128, Plus/4.
 
 | Key | Type | Default |
 | --- | --- | --- |
-| `family` | text: c64 vic20 c128 | "c64" |
+| `family` | text: c64 vic20 c128 plus4 | "c64" |
 | `region` | text: pal ntsc ntscold drean | C64: "pal" |
 | `vic_model` | text: mos6569 mos8565 mos8566 mos8564 | C64: "mos6569" |
 | `cia_model` | text: mos6526 mos6526a | C64: "mos6526" |
@@ -36,7 +37,7 @@ Written by the C64, VIC-20, C128.
 | `datasette` | bool | C64: true |
 | `board` | text: c64 pet64 gs max | C64: "c64" |
 | `cycles` | int | 0 |
-| `nmi_asserted` | bool | false |
+| `nmi_asserted` | bool | C64: false; VIC-20: false; C128: false |
 | `cartridge_nmi` | bool | C64: false; C128: false |
 | `restore_pulse` | bool | C64: false; C128: false |
 | `freezing` | bool | C64: false |
@@ -48,7 +49,7 @@ Written by the C64, VIC-20, C128.
 | `ram` | text: unexpanded 3k 8k 16k 24k 32k all | VIC-20: "unexpanded" |
 | `bus.data` | byte | VIC-20: 253; C128: 255 |
 | `bus.video_data` | byte | VIC-20: 0 |
-| `model` | text: c128 c128ntsc c128dcr c128dcrntsc | C128: "c128" |
+| `model` | text: c128 c128ntsc c128dcr c128dcrntsc | C128: "c128"; Plus/4: "plus4" |
 | `mode` | text: c64 c128 | C128: "c64" |
 | `bus.address` | word | C128: 65533 |
 | `clock_bits` | int | C128: 0 |
@@ -60,14 +61,20 @@ Written by the C64, VIC-20, C128.
 | `host.typist.code` | int, optional | C128: absent |
 | `host.typist.wait` | int | C128: 0 |
 | `host.typist.typing` | bool | C128: false |
+| `ram_kb` | int | Plus/4: 64 or 16 |
+| `tcbm` | bool | Plus/4: false |
 
 ## BL-RAM
 
-Written by the C64, VIC-20, C128.
+Written by the C64, VIC-20, C128, Plus/4.
 
 | Key | Type | Default |
 | --- | --- | --- |
-| `ram` | bytes | C64: 65536 values; VIC-20: 49152 values; C128: 131072 values |
+| `ram` | bytes | C64: 65536 values; VIC-20: 49152 values; C128: 131072 values; Plus/4: 65536 × 0 or 16384 × 0 |
+| `bus.low_bank` | int & 0x3 | Plus/4: 0 |
+| `bus.high_bank` | int & 0x3 | Plus/4: 0 |
+| `bus.rom_selected` | bool | Plus/4: true |
+| `bus.data` | byte | Plus/4: 255 |
 
 ## BL-COLORRAM
 
@@ -80,14 +87,14 @@ Written by the C64, VIC-20, C128.
 
 ## BL-CPU
 
-Written by the C64, C128, VIC-20.
+Written by the C64, C128, Plus/4, VIC-20.
 
 | Key | Type | Default |
 | --- | --- | --- |
-| `port.ddr` | byte | C64: 0; C128: 0 |
-| `port.data` | byte | C64: 0; C128: 0 |
+| `port.ddr` | byte | C64: 0; C128: 0; Plus/4: 0 |
+| `port.data` | byte | C64: 0; C128: 0; Plus/4: 0 |
 | `port.floating` | byte | C64: 0; C128: 0 |
-| `pc` | word | C64: 64738; VIC-20: 64802; C128: 65341 |
+| `pc` | word | C64: 64738; VIC-20: 64802; C128: 65341; Plus/4: 65526 |
 | `sp` | byte | 255 |
 | `a` | byte | 0 |
 | `x` | byte | 0 |
@@ -410,16 +417,18 @@ Written by the C64, C128.
 
 ## BL-TAPE
 
-Written by the C64, VIC-20, C128.
+Written by the C64, VIC-20, C128, Plus/4.
 
 | Key | Type | Default |
 | --- | --- | --- |
 | `playing` | bool | false |
 | `motor` | bool | false |
 | `countdown` | int | 0 |
+| `rise_at` | int | 0 |
+| `low_recorded` | bool | false |
 | `tape.bytes` | bytes | [] |
-| `tape.path` | text | C64: "" |
-| `tape.position` | int | C64: 0 |
+| `tape.path` | text | C64: ""; Plus/4: "" |
+| `tape.position` | int | C64: 0; Plus/4: 0 |
 
 ## BL-RAMEXP
 
@@ -476,14 +485,14 @@ Written by the C64.
 
 ## BL-CART
 
-Written by the C64, VIC-20.
+Written by the C64, VIC-20, Plus/4.
 
 | Key | Type | Default |
 | --- | --- | --- |
 | `geo_ram_kb` | int | C64: 0 |
 | `crt` | bytes | C64: [] |
-| `exrom` | int & 0x1 | C64: 1 |
-| `game` | int & 0x1 | C64: 0 |
+| `exrom` | int & 0x1 | C64: 1 or 0 |
+| `game` | int & 0x1 | C64: 0 or 1 |
 | `nmi` | bool | C64: false |
 | `button` | bool | C64: false |
 | `bank` | int | C64: 0 |
@@ -511,9 +520,17 @@ Written by the C64, VIC-20.
 | `flash_high.erasing_sectors` | ints | C64: [] |
 | `flash_high.windows` | ints | C64: [] |
 | `flash_high.status_windows` | ints | C64: [] |
+| `high_bank` | int | C64: 0 |
+| `active` | bool | C64: true |
+| `ram` | bytes | C64: 8192 × 0 |
+| `ram<N>.data` | bytes | C64: 8192 × 0 |
 | `roms` | int | VIC-20: 0 |
 | `rom0.bytes` | bytes | VIC-20: [] |
 | `rom0.start` | word | VIC-20: 0 |
+| `c1lo` | bytes | Plus/4: [] |
+| `c2lo` | bytes | Plus/4: [] |
+| `c1hi` | bytes | Plus/4: [] |
+| `c2hi` | bytes | Plus/4: [] |
 
 ## BL-TRAPDOS
 
@@ -547,29 +564,29 @@ Written by the C64.
 
 ## BL-D8
 
-Written by the C64, C128.
+Written by the C64, C128, Plus/4.
 
 | Key | Type | Default |
 | --- | --- | --- |
-| `model` | text: 1541 1571 1581 | C64: "1541" or "1581"; C128: "1541" or "1571" |
+| `model` | text: 1541 1571 1581 | C64: "1541" or "1581"; C128: "1541" or "1571"; Plus/4: "1541" |
 | `phase` | int | 0 |
 | `cycles` | int | 0 |
 | `so_pending` | bool | false |
-| `serial.host` | int | 255 |
+| `serial.host` | int | C64: 255; C128: 255; Plus/4: 0 |
 | `atn` | bool | C64: true |
 
 ## BL-D8-RAM
 
-Written by the C64, C128.
+Written by the C64, C128, Plus/4.
 
 | Key | Type | Default |
 | --- | --- | --- |
-| `data` | byte | C64: 234 or 175; C128: 234 |
-| `ram` | bytes | C64: 2048 × 0 or 8192 × 0; C128: 2048 × 0 |
+| `data` | byte | C64: 234 or 175; C128: 234; Plus/4: 234 |
+| `ram` | bytes | C64: 2048 × 0 or 8192 × 0; C128: 2048 × 0; Plus/4: 2048 × 0 |
 
 ## BL-D8-VIA1
 
-Written by the C64, C128.
+Written by the C64, C128, Plus/4.
 
 | Key | Type | Default |
 | --- | --- | --- |
@@ -603,7 +620,7 @@ Written by the C64, C128.
 | `ifr.flags` | int & 0x7f | 0 |
 | `ifr.enable` | int & 0x7f | 0 |
 | `ca.control` | int & 0xf | 0 |
-| `ca.c1_high` | bool | true |
+| `ca.c1_high` | bool | C64: true; C128: true; Plus/4: false |
 | `ca.c2_high` | bool | true |
 | `ca.handshake_low` | bool | false |
 | `ca.pulse` | int | 0 |
@@ -617,7 +634,7 @@ Written by the C64, C128.
 
 ## BL-D8-VIA2
 
-Written by the C64, C128.
+Written by the C64, C128, Plus/4.
 
 | Key | Type | Default |
 | --- | --- | --- |
@@ -665,11 +682,11 @@ Written by the C64, C128.
 
 ## BL-D8-CPU
 
-Written by the C64, C128.
+Written by the C64, C128, Plus/4.
 
 | Key | Type | Default |
 | --- | --- | --- |
-| `pc` | word | C64: 60064 or 44836; C128: 60064 |
+| `pc` | word | C64: 60064 or 44836; C128: 60064; Plus/4: 60064 |
 | `sp` | byte | 255 |
 | `a` | byte | 0 |
 | `x` | byte | 0 |
@@ -691,7 +708,7 @@ Written by the C64, C128.
 
 ## BL-D8-DISK
 
-Written by the C64, C128.
+Written by the C64, C128, Plus/4.
 
 | Key | Type | Default |
 | --- | --- | --- |
@@ -706,13 +723,13 @@ Written by the C64, C128.
 
 ## BL-D8-MECH
 
-Written by the C64, C128.
+Written by the C64, C128, Plus/4.
 
 | Key | Type | Default |
 | --- | --- | --- |
-| `half_track` | int | C64: 35; C128: 37 |
-| `slip` | int & 0x3 | C64: 0; C128: 2 |
-| `side` | int | C64: 0 or 1; C128: 85 |
+| `half_track` | int | C64: 35; C128: 37; Plus/4: 35 |
+| `slip` | int & 0x3 | C64: 0; C128: 2; Plus/4: 0 |
+| `side` | int | C64: 0 or 1; C128: 85; Plus/4: 0 |
 | `zone` | int & 0x3 | 3 |
 | `time` | int | 0 |
 | `read_clock_in` | int | 2097152 |
@@ -721,7 +738,7 @@ Written by the C64, C128.
 | `ones` | int | 0 |
 | `bits` | int | 0 |
 | `write_shift` | int | 0 |
-| `motor` | bool | C64: true or false; C128: true |
+| `motor` | bool | C64: true or false; C128: true; Plus/4: true |
 | `led` | bool | true |
 | `sync` | bool | false |
 | `byte_ready` | bool | false |
@@ -843,6 +860,49 @@ Written by the C64, C128.
 | `registers` | ints | C128: [0, 0, 0, 0] |
 | `result` | int | C128: 0 |
 
+## BL-SID2
+
+Written by the C64.
+
+| Key | Type | Default |
+| --- | --- | --- |
+| `address` | word | 54304 |
+| `model` | text: mos6581 mos8580 | "mos6581" |
+| `registers` | bytes | 32 × 0 |
+| `bus_value` | byte | 0 |
+| `bus_ttl` | int | 0 |
+| `voice<N>.wave.accumulator` | int & 0xffffff | 5592405 |
+| `voice<N>.wave.shift_register` | int & 0x7fffff | 8388606 |
+| `voice<N>.wave.shift_register_reset` | int | 0 |
+| `voice<N>.wave.shift_pipeline` | int | 0 |
+| `voice<N>.wave.delayed_triangle` | int & 0xfff | 0 |
+| `voice<N>.wave.delayed_sawtooth` | int & 0xfff | 0 |
+| `voice<N>.wave.msb_rising` | bool | false |
+| `voice<N>.wave.floating` | int & 0xfff | 0 |
+| `voice<N>.wave.floating_ttl` | int | 0 |
+| `voice<N>.wave.pulse` | int & 0xfff | 4095 |
+| `voice<N>.env.state` | text: attack decay_sustain release | "release" |
+| `voice<N>.env.next_state` | text: attack decay_sustain release | "release" |
+| `voice<N>.env.counter` | byte | 0 |
+| `voice<N>.env.env<N>` | byte | 0 |
+| `voice<N>.env.rate_counter` | int & 0x7fff | 0 |
+| `voice<N>.env.rate_period` | int | 8 |
+| `voice<N>.env.reset_rate_counter` | bool | false |
+| `voice<N>.env.exponential_counter` | int | 0 |
+| `voice<N>.env.exponential_period` | int | 1 |
+| `voice<N>.env.state_pipeline` | int | 0 |
+| `voice<N>.env.envelope_pipeline` | int | 0 |
+| `voice<N>.env.exponential_pipeline` | int | 0 |
+| `voice<N>.env.hold_zero` | bool | true |
+| `filter.highpass` | int | 0 |
+| `filter.bandpass` | int | 0 |
+| `filter.lowpass` | int | 0 |
+| `filter.unfiltered` | int | 0 |
+| `filter.input` | int | 0 |
+| `ext.lowpass` | int | 0 |
+| `ext.highpass` | int | 0 |
+| `ext.output` | int | 0 |
+
 ## BL-VICI
 
 Written by the VIC-20.
@@ -1045,3 +1105,93 @@ Written by the C128.
 | `int` | bool | false |
 | `nmi` | bool | false |
 | `nmi_pending` | bool | false |
+
+## BL-TED
+
+Written by the Plus/4.
+
+| Key | Type | Default |
+| --- | --- | --- |
+| `registers` | bytes | 32 × 0 |
+| `interrupt_flags` | byte | 0 |
+| `key_latch` | byte | 255 |
+| `blink` | int & 0xf | 0 |
+| `blink_on` | bool | false |
+| `timer<N>.count` | word | 0 |
+| `timer<N>.running` | bool | false |
+| `timer1.reload` | word | 0 |
+| `column` | int | 0 |
+| `line` | int & 0x1ff | 0 |
+| `ba` | bool | false |
+| `cpu_slots` | int | 1 |
+| `fetch.patterns` | bytes | 40 × 0 |
+| `fetch.pointers` | bytes | 40 × 0 |
+| `fetch.attributes` | bytes | 40 × 0 |
+| `fetch.next_attributes` | bytes | 40 × 0 |
+| `fetch.char_position` | int & 0x3ff | 0 |
+| `fetch.line_position` | int & 0x3ff | 0 |
+| `fetch.row_line` | int & 0x7 | 0 |
+| `fetch.row_active` | bool | false |
+| `fetch.dma` | text: none attributes pointers | "none" |
+| `fetch.patterns_on` | bool | false |
+| `scanline` | int | 0 |
+| `window_open` | bool | false |
+| `line.layout` | int | 0 |
+| `line.painted` | int | 0 |
+| `display` | bytes | 119808 × 0 |
+
+## BL-TEDSOUND
+
+Written by the Plus/4.
+
+| Key | Type | Default |
+| --- | --- | --- |
+| `voice<N>.phase` | int & 0x1 | 1 |
+| `voice<N>.toggle_in` | int, optional | absent |
+| `noise` | byte | 255 |
+| `ran_ago` | int | 0 |
+
+## BL-KEYPORT
+
+Written by the Plus/4.
+
+| Key | Type | Default |
+| --- | --- | --- |
+| `output` | byte | 255 |
+
+## BL-USERPORT
+
+Written by the Plus/4.
+
+| Key | Type | Default |
+| --- | --- | --- |
+| `output` | byte | 255 |
+
+## BL-ACIA
+
+Written by the Plus/4.
+
+| Key | Type | Default |
+| --- | --- | --- |
+| `command` | byte | 0 |
+| `control` | byte | 0 |
+
+## BL-TIA1
+
+Written by the Plus/4.
+
+| Key | Type | Default |
+| --- | --- | --- |
+| `ports` | ints | [0, 0, 0] |
+| `directions` | ints | [0, 0, 0] |
+| `inputs` | ints | [0, 0, 0] |
+
+## BL-TIA2
+
+Written by the Plus/4.
+
+| Key | Type | Default |
+| --- | --- | --- |
+| `ports` | ints | [0, 0, 0] |
+| `directions` | ints | [0, 0, 0] |
+| `inputs` | ints | [0, 0, 0] |

data/doc/snapshots.md

@@ -87,7 +87,9 @@ blocks given to `on_init` that hadn't run yet, which a restore reports.
 Every model saves this way, PAL, NTSC, old NTSC and Drean alike, and so
 does a machine with an REU, with its RAM and its registers. A snapshot
 restores into a machine with the same chip models, region, RAM
-expansion, REU, KERNAL, datasette and board.
+expansion, REU, KERNAL, datasette and board. The second and third SIDs
+the SID player fits for a stereo tune are saved too, each with its
+address and model, and a restore fits them.
 
 Text typed with `type_text` that the machine hasn't taken yet, such as
 autostart's `RUN`, carries over, and so do the keys a C128 is typing on
@@ -123,6 +125,21 @@ do, and holds only badline's modules, so x128 doesn't open it, and
 badline doesn't open x128's. Restoring a C128 snapshot while another machine runs swaps the
 machine in the window, as for the VIC-20.
 
+## The Plus/4
+
+The Plus/4, the C16 and the C116 save and restore the same way. A
+snapshot of one holds its RAM with the ROM bank latch and whether ROM or
+RAM is selected, the cartridges' ROMs in each slot, the CPU with its
+port, the TED with its timers, its counters and its picture, the TED's
+sound, the keyboard's 6529, the Plus/4's user port 6529 and ACIA, a TCBM
+interface's TIAs, the tape with its place on it, the disk or directory
+device 8 serves through the traps and a true 1541 or 1581. It restores
+into a machine of the same model with the same RAM, and the BASIC,
+KERNAL and function ROMs come with the model. Its file names its machine
+`PLUS4`, as xplus4's do, and holds only badline's modules, so xplus4
+doesn't open it, and badline doesn't open xplus4's. `--vice` and
+`computer.export_snapshot(path)` refuse a Plus/4.
+
 ## VICE
 
 Snapshots use VICE's `.vsf` format, and badline's own modules are named

data/lib/badline/audio/bare_player.rb

@@ -93,10 +93,7 @@ module Badline
         sections << Snapshot::Keyed.section("BL-CIA1") { |out| bus.cia1.save_fields(out) }
         sections << Snapshot::Keyed.section("BL-CIA2") { |out| bus.cia2.save_fields(out) }
         sections << Snapshot::Keyed.section("BL-SID") { |out| bus.sid.save_fields(out) }
-        @extras.each_with_index do |sid, index|
-          sections << Snapshot::Keyed.section("BL-SID#{index + 2}") { |out| sid.save_fields(out) }
-        end
-        sections
+        bus.save_extra_sid_modules(sections)
       end
 
       # Takes a rig that hasn't started to where #save_modules found one, in
@@ -152,10 +149,9 @@ module Badline
         bus.vic.load_fields(modules.required("BL-VIC"))
         bus.cia1.load_fields(modules.required("BL-CIA1"))
         bus.cia2.load_fields(modules.required("BL-CIA2"))
-        @stereo.sids.each_with_index do |sid, index|
-          sid.load_fields(modules.required(index.zero? ? "BL-SID" : "BL-SID#{index + 1}"))
-          sid.restored!
-        end
+        bus.sid.load_fields(modules.required("BL-SID"))
+        bus.load_extra_sid_modules(modules)
+        @stereo.sids.each(&:restored!)
         bus.vic.restored!
         bus.cia1.restored!
         bus.cia2.restored!

data/lib/badline/audio/machine_player.rb

@@ -40,23 +40,13 @@ module Badline
       def clock_hz = @computer.region.clock_hz
 
       # The whole machine as its keyed snapshot modules, as it stands between
-      # frames, and the extra SIDs as BL-SID2 and BL-SID3, once it plays.
-      def save_modules
-        sections = @computer.save_modules
-        @extras.each_with_index do |sid, index|
-          sections << Snapshot::Keyed.section("BL-SID#{index + 2}") { |out| sid.save_fields(out) }
-        end
-        sections
-      end
+      # frames, with the extra SIDs as BL-SID2 and BL-SID3, once it plays.
+      def save_modules = @computer.save_modules
 
       # Takes a machine that hasn't started to where #save_modules found one,
       # in place of #start.
       def load_modules(modules)
         @computer.load_modules(modules)
-        @extras.each_with_index do |sid, index|
-          sid.load_fields(modules.required("BL-SID#{index + 2}"))
-          sid.restored!
-        end
         @stereo.synthesize!
         @started = true
       end

data/lib/badline/c128/banks.rb

@@ -21,9 +21,7 @@ module Badline
       # The CR value the KERNAL's table holds for the bank.
       def configuration(bank) = @kernal_rom.peek(CONFIGURATIONS + (bank & 0x0f))
 
-      def write(bank, addr, bytes)
-        bytes.each_with_index { |byte, i| @ram.poke(physical(bank, (addr + i) & 0xffff), byte) }
-      end
+      def poke(bank, addr, value) = @ram.poke(physical(bank, addr), value)
 
       private
 

data/lib/badline/c128/bus.rb

@@ -228,7 +228,25 @@ module Badline
         system_rom_peek(addr)
       end
 
-      def write_bank(bank, addr, bytes) = @banks.write(bank, addr, bytes)
+      # Stores +bytes+ from +addr+ on in the C128 KERNAL's bank number
+      # +bank+, as its INDSTA does, with CR set to the bank's CR value for
+      # each byte and put back after it: into the chips where that value
+      # maps I/O, the MMU's at $D500 among them, into nothing at $FF00-$FF04,
+      # where the configuration registers take the byte, and otherwise into
+      # the RAM the bank reaches (Banks).
+      def write_bank(bank, addr, bytes)
+        cr = @mmu.cr
+        io = @banks.configuration(bank).nobits?(0x01)
+        bytes.each_with_index do |byte, i|
+          address = (addr + i) & 0xffff
+          if io && (address & 0xf000) == 0xd000
+            bank_io_poke(address, byte)
+          elsif !address.between?(0xff00, 0xff04)
+            @banks.poke(bank, address, byte)
+          end
+        end
+        @mmu.poke_configuration(0xff00, cr) unless @mmu.cr == cr
+      end
 
       def install_debug_register(&)
         @debug_page = DebugPage.new(@open_bus, &)

data/lib/badline/c128/mmu_pages.rb

@@ -66,6 +66,13 @@ module Badline
           @bank_io_reads[addr >> 8].peek(addr)
         end
 
+        # Writes the chip at +addr+, in $D000-$DFFF, as C128 mode's I/O maps it.
+        def bank_io_poke(addr, value)
+          lay_out_io(@bank_io_reads, @bank_io_writes)
+          @bank_io_writes[0xd5] = @mmu
+          @bank_io_writes[addr >> 8].poke(addr, value)
+        end
+
         # The bank CR picks, with common RAM in bank 0, then the pages page 0
         # and page 1 move to.
         def map_ram_pages

data/lib/badline/c64/bus/extra_sids.rb

@@ -7,7 +7,16 @@ module Badline
       # them, each over its 32 bytes of the I/O area (SIDSlots). The SID
       # player's machine has nothing else in I/O 1 and 2, so the rest of a
       # page there reads the open bus.
+      #
+      # A snapshot holds each in its own keyed module, BL-SID2 onwards in the
+      # order they were fitted, with the address it sits at and its model
+      # ahead of the SID's own fields.
       module ExtraSIDs
+        SID_MODEL_NAMES = %w[mos6581 mos8580].freeze
+
+        # The SIDs fitted past the first, in the order they were fitted.
+        attr_reader :extra_sids
+
         # Fits a SID at the address it was built at, where it takes its 32
         # bytes over from whatever maps there.
         def add_sid(sid)
@@ -18,14 +27,85 @@ module Badline
             @sid_slots << slots
           end
           slots.place(sid)
+          @extra_sids << sid
+          update_overlays!
+        end
+
+        # Takes the extra SIDs out, giving their addresses back to what maps
+        # there.
+        def remove_extra_sids
+          @sid_slots.clear
+          @extra_sids.clear
           update_overlays!
         end
 
+        def save_extra_sid_modules(sections)
+          @extra_sids.each_with_index do |sid, index|
+            sections << Snapshot::Keyed.section("BL-SID#{index + 2}") do |out|
+              out.int("address", sid.start).text("model", sid.model.to_s)
+              sid.save_fields(out)
+            end
+          end
+          sections
+        end
+
+        # Fits the extra SIDs the snapshot's modules hold and loads them. A
+        # SID already fitted at the same address stays, on the model the
+        # snapshot names, and one the snapshot hasn't comes out. A module
+        # whose address no SID fits at is left out, and reported.
+        def load_extra_sid_modules(modules)
+          addresses = []
+          inputs = extra_sid_inputs(modules, addresses)
+          models = inputs.map { |input| sid_model_named(input.choice("model", SID_MODEL_NAMES, "mos6581")) }
+          refit_sids(addresses, models)
+          @extra_sids.each_with_index do |sid, index|
+            model = models[index]
+            sid.model = model unless sid.model == model
+            sid.load_fields(inputs[index])
+          end
+        end
+
         private
 
         def map_extra_sids
           @sid_slots.each { |slots| @read_pages[slots.page] = @write_pages[slots.page] = slots }
         end
+
+        def extra_sid_inputs(modules, taken)
+          inputs = []
+          number = 2
+          input = modules.optional("BL-SID2")
+          while input
+            address = input.word("address", 0xd420)
+            if sid_fits?(address) && !taken.include?(address)
+              inputs << input
+              taken << address
+            else
+              input.adjust(format("no SID fits at $%04x, so it's left out", address))
+            end
+            number += 1
+            input = modules.optional("BL-SID#{number}")
+          end
+          inputs
+        end
+
+        # A SID's 32 bytes past the first SID's own, in $D420-$D7FF, or in
+        # I/O 1 or 2.
+        def sid_fits?(address)
+          address.nobits?(0x1f) && ((0xd420..0xd7e0).cover?(address) || (0xde00..0xdfe0).cover?(address))
+        end
+
+        def sid_model_named(name) = name == "mos8580" ? :mos8580 : :mos6581
+
+        def refit_sids(addresses, models)
+          fitted = @extra_sids.dup
+          return if fitted.map(&:start) == addresses
+
+          remove_extra_sids
+          addresses.each_with_index do |address, index|
+            add_sid(fitted.find { |sid| sid.start == address } || Chips::SID.new(model: models[index], at: address))
+          end
+        end
       end
     end
   end

data/lib/badline/c64/bus.rb

@@ -91,6 +91,7 @@ module Badline
         @cia1.on_port_b4_change { |high| @vic.lightpen_level(high) }
         @sid = Chips::SID.new(model: sid_model, pots: @control_ports)
         @sid_slots = []
+        @extra_sids = []
 
         @datasette = Drives::Datasette.new
         @datasette.on_flag { @cia1.flag! }

data/lib/badline/c64/cartridge/action_replay.rb

@@ -22,6 +22,10 @@ module Badline
         include Freezer
 
         CONTROL_MODES = %i[rom8k rom16k off ultimax].freeze
+
+        # Ultimax mode with the RAM at ROML and I/O 2 and the first bank at
+        # ROMH, as a freeze leaves the register.
+        FREEZE_CONTROL = 0x23
         IO2_PAGE = 0x1f00
 
         def connect(ram:, open_bus:)
@@ -59,8 +63,7 @@ module Badline
 
         def freeze!
           @active = true
-          @rom = bank(@rom_banks, 0)
-          select(:ultimax, @isolated, io2_ram: true)
+          control(FREEZE_CONTROL)
         end
 
         private
@@ -72,6 +75,7 @@ module Badline
         end
 
         def control(value)
+          @control = value
           self.nmi = false if value.anybits?(0x40)
           @rom = bank(@rom_banks, (value >> 3) & 0x03)
           configure(value)

data/lib/badline/c64/cartridge/comal80.rb

@@ -37,6 +37,7 @@ module Badline
         def windows = [*@roml_banks, *@romh_banks, EMPTY_BANK]
 
         def select(number, mode)
+          @bank = number
           @roml = bank(@roml_banks, number)
           @romh = bank(@romh_banks, number)
           self.mode = mode