badline 0.12.0 → 0.12.1

checksums.yaml

@@ -1,7 +1,7 @@
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data/CHANGELOG.md

@@ -1,5 +1,13 @@
 # Changelog
 
+## [0.12.1](https://github.com/elektronaut/badline/compare/v0.12.0...v0.12.1) (2026-10-10)
+
+
+### Bug Fixes
+
+* keep the 1581's idle deadline within a native build's integers ([a98848f](https://github.com/elektronaut/badline/commit/a98848f0889ca7ad4c12007976b63d54bbbf122b))
+* refuse snapshot values a native build can't hold, on CRuby too ([5ec51e8](https://github.com/elektronaut/badline/commit/5ec51e81cfabfdb585367bb2f8183516ac64d2b0))
+
 ## [0.12.0](https://github.com/elektronaut/badline/compare/v0.11.1...v0.12.0) (2026-10-10)
 
 

data/lib/badline/address_bus/saved_state.rb

@@ -17,15 +17,12 @@ module Badline
 
       # The 6510 port's direction and output registers, and the charge left
       # on its floating bits.
-      def port_state = [@port_ddr, @port_out, @port_floating]
+      def port_state = [@cpu_port.ddr, @cpu_port.data, @cpu_port.floating]
 
       # Sets the port as port_state reads it, as a snapshot restores it,
       # leaving the RAM under $00 and $01 alone.
       def restore_port(ddr, out, floating)
-        @port_ddr = ddr
-        @port_out = out
-        @port_floating = floating
-        update_port!
+        @cpu_port.restore(ddr, out, floating)
       end
 
       # The machine's memory and everything on the bus but the keyboard, the
@@ -33,7 +30,7 @@ module Badline
       # already in the port, built from its setup (Computer#load_state).
       def save_state(out)
         out.marker("BUS")
-        out.int(@port_ddr).int(@port_out).int(@port_floating)
+        out.int(@cpu_port.ddr).int(@cpu_port.data).int(@cpu_port.floating)
         @ram.save_state(out)
         @color_ram.save_state(out)
         @ram_expansion.save_state(out)
@@ -55,10 +52,7 @@ module Badline
         @ram_expansion.load_state(input)
         @cartridge&.load_state(input)
         @datasette.load_state(input)
-        @port_ddr = ddr
-        @port_out = port_out
-        @port_floating = floating
-        @io_port.value = port_value
+        @cpu_port.load(ddr, port_out, floating)
         update_overlays!
         @vic.load_state(input)
         @cia1.load_state(input)

data/lib/badline/address_bus.rb

@@ -52,9 +52,9 @@ module Badline
       def poke(_addr, _value); end
     end
 
+    # The 6510's port pins with pull-ups, and the floating ones (CPUPort).
     PORT_PULLUPS  = 0b0001_0111
     PORT_FLOATING = 0b1100_1000
-    TAPE_SENSE    = 0b0001_0000
 
     # RAM powers on in runs of $00 $00 $FF $FF $FF $FF $00 $00, inverted in
     # the second and fourth 16K: a C64C (ASSY 250469 R4) from
@@ -92,7 +92,7 @@ module Badline
 
       @datasette = Datasette.new
       @datasette.on_flag { @cia1.flag! }
-      @datasette.on_sense_change { @io_port.value = port_value }
+      @datasette.on_sense_change { @cpu_port.refresh }
 
       @color_ram = ColorMemory.new(@vic)
       @vic.vic_bank.connect(cia2: @cia2, color_ram: @color_ram)
@@ -100,10 +100,9 @@ module Badline
       @open_bus = OpenBus.new(@vic)
       @cpu_off_bus = false
 
-      @port_ddr = 0x00
-      @port_out = 0x00
-      @port_floating = 0x00
-      @io_port = PortStatus.new(%i[basic kernal io tape_out tape_switch tape_motor], value: port_value)
+      @cpu_port = CPUPort.new(@datasette, pullups: PORT_PULLUPS, floating: PORT_FLOATING)
+      @cpu_port.on_change { update_overlays! }
+      @io_port = @cpu_port.status
 
       @read_pages = Array.new(256)
       @write_pages = Array.new(256)
@@ -134,9 +133,7 @@ module Badline
     # their charge.
     def reset!
       @ram_expansion.reset!
-      @port_ddr = 0x00
-      @port_out = 0x00
-      update_port!
+      @cpu_port.reset!
     end
 
     def disable_overlays!
@@ -150,7 +147,7 @@ module Badline
     end
 
     def peek(addr)
-      return @port_ddr if addr.zero?
+      return @cpu_port.ddr if addr.zero?
       return @io_port.value if addr == 0x01
 
       @read_pages[addr >> 8].peek(addr)
@@ -162,8 +159,7 @@ module Badline
     def poke(addr, value)
       if addr < 0x02
         @ram.poke(addr, @vic.phi1_data)
-        addr.zero? ? @port_ddr = value : @port_out = value
-        update_port!
+        addr.zero? ? @cpu_port.write_ddr(value) : @cpu_port.write_data(value)
       elsif !@cpu_off_bus
         @write_pages[addr >> 8].poke(addr, value)
       end
@@ -185,21 +181,6 @@ module Badline
 
     private
 
-    def update_port!
-      driven = @port_ddr & PORT_FLOATING
-      @port_floating = (@port_floating & ~driven) | (@port_out & driven)
-      @io_port.value = port_value
-      # $01 bit 5 drives the motor through an inverter: low runs it.
-      @datasette.motor = !@io_port.tape_motor?
-      update_overlays!
-    end
-
-    def port_value
-      input = PORT_PULLUPS | (@port_floating & PORT_FLOATING)
-      input &= ~TAPE_SENSE if @datasette.sense_low?
-      (@port_out & @port_ddr) | (input & ~@port_ddr & 0xff)
-    end
-
     # Banking changes only on $01 writes and cartridge line/bank changes,
     # so reads and writes dispatch through per-page handler tables instead
     # of range checks.

data/lib/badline/audio/bare_player.rb

@@ -116,7 +116,7 @@ module Badline
         cycles
       end
 
-      def clock_hz = @tune.ntsc? ? NTSC_CLOCK_HZ : TimeOfDay::CLOCK_HZ
+      def clock_hz = @tune.ntsc? ? NTSC_CLOCK_HZ : Region::PAL.clock_hz
 
       private
 

data/lib/badline/c128/bus.rb

@@ -47,7 +47,6 @@ module Badline
       PORT_PULLUPS  = 0b0001_0111
       PORT_FLOATING = 0b1000_1000
       CAPS_LOCK     = 0b0100_0000
-      TAPE_SENSE    = 0b0001_0000
 
       # The C64's power-on pattern (AddressBus::RAM_POWER_ON) in both 64K
       # banks. The C128's own DRAMs' pattern is unmeasured.
@@ -126,9 +125,6 @@ module Badline
       # KERNAL and the character ROM's C128 set.
       attr_reader :basic_low_rom, :basic_high_rom, :editor_rom, :c128_kernal_rom, :c128_character_rom
 
-      # Whether CAPS LOCK is down, holding P6 low.
-      attr_reader :caps_lock
-
       # The chips +model+, a Model::Profile, names, with the SID
       # +sid_model+. +mode+ is the mode the MMU resets into.
       def initialize(model, sid_model: model.sid_model, mode: :c64)
@@ -139,7 +135,6 @@ module Badline
         @mmu = MMU.new(mode)
         @cartridge = nil
         @debug_page = nil
-        @caps_lock = false
 
         load_roms
         load_c128_roms
@@ -150,7 +145,7 @@ module Badline
 
         @datasette = Datasette.new
         @datasette.on_flag { @cia1.flag! }
-        @datasette.on_sense_change { @io_port.value = port_value }
+        @datasette.on_sense_change { @cpu_port.refresh }
 
         @color_lines = ColorLines.new(@vic, @cia2, character_rom, @c128_character_rom)
         @color_ram = @color_lines.color_ram(1)
@@ -160,10 +155,8 @@ module Badline
         @configuration_reads = ConfigurationPage.new(@mmu, @open_bus)
         @configuration_writes = ConfigurationPage.new(@mmu, @open_bus)
 
-        @port_ddr = 0x00
-        @port_out = 0x00
-        @port_floating = 0x00
-        @io_port = PortStatus.new(%i[basic kernal io tape_out tape_switch tape_motor], value: port_value)
+        @cpu_port = CPUPort.new(@datasette, pullups: PORT_PULLUPS, floating: PORT_FLOATING, caps_lock: CAPS_LOCK)
+        @io_port = @cpu_port.status
 
         @read_pages = Array.new(256)
         @write_pages = Array.new(256)
@@ -171,6 +164,7 @@ module Badline
         @data = 0
         @io_mapped = false
         @mmu.on_change { update_overlays! }
+        @cpu_port.on_change { update_overlays! }
         update_overlays!
       end
 
@@ -191,19 +185,19 @@ module Badline
         @ram.clear!(RAM_POWER_ON)
       end
 
-      # The RES line clears the port's direction and output registers and
-      # resets the MMU. The port's floating bit keeps its charge.
+      # The RES line resets the MMU and clears the port's direction and
+      # output registers. The port's floating bit keeps its charge.
       def reset!
-        @port_ddr = 0x00
-        @port_out = 0x00
         @mmu.reset!
-        update_port!
+        @cpu_port.reset!
       end
 
+      # Whether CAPS LOCK is down, holding P6 low.
+      def caps_lock = @cpu_port.caps_lock
+
       # Holds CAPS LOCK down, or lets it up.
       def caps_lock=(down)
-        @caps_lock = down
-        @io_port.value = port_value
+        @cpu_port.caps_lock = down
       end
 
       # Calls the block whenever MCR bit 6 takes the machine into C64 mode or
@@ -236,7 +230,7 @@ module Badline
         @data = if addr > 0x01
                   @read_pages[addr >> 8].peek(addr)
                 else
-                  addr.zero? ? @port_ddr : @io_port.value
+                  addr.zero? ? @cpu_port.ddr : @io_port.value
                 end
       end
 
@@ -254,8 +248,7 @@ module Badline
         @data = value
         if addr < 0x02
           @write_pages[0].poke(addr, @vic.phi1_data)
-          addr.zero? ? @port_ddr = value : @port_out = value
-          update_port!
+          addr.zero? ? @cpu_port.write_ddr(value) : @cpu_port.write_data(value)
         else
           @write_pages[addr >> 8].poke(addr, value)
         end
@@ -294,21 +287,6 @@ module Badline
         @vdc = VDC.new(model: model.vdc_model, ram_kb: model.vdc_ram_kb, clock_hz: @region.clock_hz)
       end
 
-      def update_port!
-        driven = @port_ddr & PORT_FLOATING
-        @port_floating = (@port_floating & ~driven) | (@port_out & driven)
-        @io_port.value = port_value
-        @datasette.motor = !@io_port.tape_motor?
-        update_overlays!
-      end
-
-      def port_value
-        input = PORT_PULLUPS | (@port_floating & PORT_FLOATING)
-        input |= CAPS_LOCK unless @caps_lock
-        input &= ~TAPE_SENSE if @datasette.sense_low?
-        (@port_out & @port_ddr) | (input & ~@port_ddr & 0xff)
-      end
-
       def update_overlays!
         @ultimax = @cartridge ? @cartridge.ultimax? : false
         @phi1_ultimax = @cartridge ? @cartridge.phi1_ultimax? : false

data/lib/badline/c128/bus_state.rb

@@ -11,7 +11,7 @@ module Badline
         # host holds. A cartridge is already in the port, built from its setup.
         def save_state(out)
           out.marker("C128 BUS")
-          out.int(@port_ddr).int(@port_out).int(@port_floating).int(@address).int(@data)
+          out.int(@cpu_port.ddr).int(@cpu_port.data).int(@cpu_port.floating).int(@address).int(@data)
           @mmu.save_state(out)
           @ram.save_state(out)
           @color_lines.color_ram(0).save_state(out)
@@ -27,9 +27,9 @@ module Badline
 
         def load_state(input)
           input.marker("C128 BUS")
-          @port_ddr = input.int
-          @port_out = input.int
-          @port_floating = input.int
+          ddr = input.int
+          data = input.int
+          floating = input.int
           @address = input.int
           @data = input.int
           @mmu.load_state(input)
@@ -38,7 +38,7 @@ module Badline
           @color_lines.color_ram(1).load_state(input)
           @cartridge&.load_state(input)
           @datasette.load_state(input)
-          @io_port.value = port_value
+          @cpu_port.load(ddr, data, floating)
           update_overlays!
           @vic.load_state(input)
           @control_ports.extra_rows = 0xf8 | @vic.extra_keyboard_lines

data/lib/badline/c128.rb

@@ -44,6 +44,8 @@ module Badline
   class C128
     include IntegerHelper
     include KeyboardBuffer
+    include Machine::Clocking
+    include Computer::Common
     include Computer::Attachments
     include Computer::KernalTraps
     include Keys
@@ -71,10 +73,6 @@ module Badline
 
     attr_reader :cpu, :cycles, :drive1541, :model, :init_threshold
 
-    # The path of the disk or directory device 8 serves through the traps
-    # (Computer::Attachments), or an empty one.
-    def mounted_path = @drive.nil? ? "" : @drive.path
-
     def family = :c128
 
     def address_bus = @bus
@@ -173,36 +171,6 @@ module Badline
       @cycles += 1
     end
 
-    # Runs `count` cycles, one #cycle! after another.
-    def run_cycles(count)
-      i = 0
-      while i < count
-        cycle!
-        i += 1
-      end
-    end
-
-    # Runs cycles until the block returns true or the cycle count passes
-    # `limit`, checking before each cycle.
-    def run_until(limit)
-      cycle! until yield || @cycles > limit
-    end
-
-    def on_init(&block)
-      if @cycles < init_threshold
-        @init_handlers << block
-      else
-        block.call
-      end
-    end
-
-    # The clock, the raster and the crop of the VIC-IIe's region.
-    def timing
-      region = @bus.region
-      Timing.new(clock_hz: region.clock_hz, cycles_per_line: region.cycles_per_line,
-                 lines_per_frame: region.lines_per_frame, crop: region.crop, pixel_width: 1)
-    end
-
     # The chip whose #display a front end shows: the VIC-IIe, or with
     # :vdc the VDC, whose display paints only while its #render is on.
     def video(chip = :vic) = chip == :vdc ? @vdc : @vic
@@ -217,12 +185,6 @@ module Badline
     # The chip a front end records the machine's sound from.
     def sound_source = @sid
 
-    def load_prg(data)
-      uint16(data[0], data[1]).tap do |load_addr|
-        ram.write(load_addr, data[2..])
-      end
-    end
-
     # A cartridge goes in with the power off.
     def attach_cartridge(cartridge)
       connect_cartridge(cartridge)
@@ -255,19 +217,11 @@ module Badline
       reset_z80
     end
 
-    # CHROUT is at $FFD2 in both KERNALs, and the trap follows the mode.
-    def capture_output
-      @capture_output ||= ChroutTrap.new(cpu:, bus: @bus, layout: trap_layout).tap do |trap|
-        cpu.install_trap(ChroutTrap::ADDRESS) { trap.call }
-      end
-    end
-
-    def inspect
-      "#<#{self.class.name} cycles=#{@cycles} cpu=(#{@cpu.inspect})>"
-    end
-
     private
 
+    # The bus the KERNAL traps read and write through.
+    def trap_bus = @bus
+
     # The C128 KERNAL leaves $D02F at $FF, every extra keyboard row
     # deselected, before it jumps to the C64's reset.
     def enter_c64_mode
@@ -275,15 +229,6 @@ module Badline
       @bus.control_ports.extra_rows = 0xff
     end
 
-    # The NMI line is wired-OR between CIA 2, the cartridge and RESTORE,
-    # and the CPU takes an interrupt on its falling edge.
-    def drive_nmi
-      nmi = @cia2.interrupted? || @cartridge_nmi || @restore_pulse
-      @restore_pulse = false
-      @cpu.nmi = true if nmi && !@nmi_asserted
-      @nmi_asserted = nmi
-    end
-
     # BA halts the CPU on a read cycle.
     def clock_cpu
       @cpu.pending_write? || !@vic.ba_low? ? @cpu.cycle! : @cpu.stall!
@@ -311,9 +256,5 @@ module Badline
       @cpu.cycle!
       @vic.take_cpu_bus(phi1, @bus.data, @bus.vic_access?)
     end
-
-    def handle_init
-      @init_handlers.each(&:call)
-    end
   end
 end

data/lib/badline/computer/attachments.rb

@@ -2,9 +2,9 @@
 
 module Badline
   class Computer
-    # What plugs into the machine besides its chips, the cartridge, the
-    # disk device 8 serves through the traps, its true drives (TrueDrives)
-    # and an REU, and their state for a snapshot.
+    # What plugs into the machine besides its chips, the cartridge, its
+    # true drives (TrueDrives) and an REU, and their state for a snapshot.
+    # The disk device 8 serves through the traps is KernalTraps'.
     module Attachments
       include TrueDrives
 
@@ -17,30 +17,6 @@ module Badline
         address_bus.attach_cartridge(cartridge)
       end
 
-      # Puts the storage in device 8. Mounting again swaps the disk at any
-      # point while the machine runs: the drive keeps its RAM, which only a
-      # drive reset clears, and its status. The traps go on the KERNAL the
-      # machine runs (#trap_layout).
-      def mount(storage)
-        return @drive.insert(storage) if @drive
-
-        @drive = KernalTrap::Drive.new(storage)
-        install_kernal_traps(trap_layout)
-      end
-
-      # Takes device 8's mounted storage out, and with it the LOAD, SAVE and
-      # serial traps, so the KERNAL's routines go out over the serial bus.
-      # Mounting again starts a new drive, with its RAM cleared.
-      def unmount
-        return unless @drive
-
-        remove_kernal_traps
-        @drive = nil
-      end
-
-      # Whether device 8 serves a disk or directory through the traps.
-      def mounted? = !@drive.nil?
-
       # The serial bus, which CIA 2's port A drives through the C64's own
       # inverters and reads back on PA6 and PA7, with or without a drive on
       # it.
@@ -78,26 +54,21 @@ module Badline
         end
       end
 
-      # The disk device 8 serves through the traps, with the traps' own
-      # state: open channels, the drive's status and RAM, a SAVE under way.
-      def save_trap_drive(out)
-        out.boolean(!@drive.nil?)
-        return unless @drive
-
-        @drive.save_state(out)
-        @serial_trap.save_state(out)
-        @save_trap.save_state(out)
+      # A true 1541 on the serial bus, then a 1581. The leading flag is the
+      # bus itself, which every machine now has.
+      def save_serial_bus(out)
+        out.boolean(true).boolean(!@drive1541.nil?)
+        if @drive1541
+          out.int(@drive1541.device)
+          @drive1541.save_state(out)
+        end
+        save_drive1581(out)
       end
 
-      def load_trap_drive(input)
-        return unmount unless input.boolean?
-
-        storage = Storage.reopen(input)
-        unmount
-        mount(storage)
-        @drive.load_state(input)
-        @serial_trap.load_state(input)
-        @save_trap.load_state(input)
+      def load_serial_bus(input)
+        input.boolean?
+        load_drive1541(input)
+        load_drive1581(input)
       end
 
       # The REU, which the setup says the machine has, and whether it has

data/lib/badline/computer/common.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+module Badline
+  class Computer
+    # What the C128 does as the C64 does: the NMI line, a PRG put into RAM
+    # and the region's timing. Computer and C128 each include it.
+    module Common
+      # The clock, the raster and the crop of the machine's region, a pixel
+      # to a window pixel.
+      def timing
+        region = address_bus.region
+        Timing.new(clock_hz: region.clock_hz, cycles_per_line: region.cycles_per_line,
+                   lines_per_frame: region.lines_per_frame, crop: region.crop, pixel_width: 1)
+      end
+
+      def load_prg(data)
+        uint16(data[0], data[1]).tap do |load_addr|
+          ram.write(load_addr, data[2..])
+        end
+      end
+
+      private
+
+      # The NMI line is wired-OR between CIA 2, the cartridge and the RESTORE
+      # key, and the CPU takes an interrupt on its falling edge.
+      def drive_nmi
+        nmi = @cia2.interrupted? || @cartridge_nmi || @restore_pulse
+        @restore_pulse = false
+        @cpu.nmi = true if nmi && !@nmi_asserted
+        @nmi_asserted = nmi
+      end
+    end
+  end
+end

data/lib/badline/computer/kernal_traps.rb

@@ -2,18 +2,56 @@
 
 module Badline
   class Computer
-    # The LOAD, SAVE and serial traps on the KERNAL a KernalTrap::Layout
-    # describes, which serve the disk in device 8 (Attachments#mount).
+    # The disk device 8 serves through the LOAD, SAVE and serial traps, and
+    # CHROUT capture, on the KERNAL the machine runs. Computer, Vic20 and
+    # C128 each include it and answer two private methods: #trap_layout,
+    # the KernalTrap::Layout of that KERNAL, and #trap_bus, the bus the
+    # traps read and write through.
     module KernalTraps
+      # Puts the storage in device 8. Mounting again swaps the disk at any
+      # point while the machine runs: the drive keeps its RAM, which only a
+      # drive reset clears, and its status. The traps go on the KERNAL the
+      # machine runs (#trap_layout).
+      def mount(storage)
+        return @drive.insert(storage) if @drive
+
+        @drive = KernalTrap::Drive.new(storage)
+        install_kernal_traps(trap_layout)
+      end
+
+      # Takes device 8's mounted storage out, and with it the LOAD, SAVE and
+      # serial traps, so the KERNAL's routines go out over the serial bus.
+      # Mounting again starts a new drive, with its RAM cleared.
+      def unmount
+        return unless @drive
+
+        remove_kernal_traps
+        @drive = nil
+      end
+
+      # Whether device 8 serves a disk or directory through the traps.
+      def mounted? = !@drive.nil?
+
+      # The path of the disk or directory device 8 serves through the
+      # traps, or an empty one.
+      def mounted_path = @drive.nil? ? "" : @drive.path
+
+      # Records what the KERNAL prints through CHROUT (ChroutTrap).
+      def capture_output
+        @capture_output ||= ChroutTrap.new(cpu:, bus: trap_bus, layout: trap_layout).tap do |trap|
+          cpu.install_trap(ChroutTrap::ADDRESS) { trap.call }
+        end
+      end
+
       private
 
       def install_kernal_traps(layout)
         @trap_layout = layout
-        load_trap = KernalTrap::Load.new(cpu:, bus: address_bus, layout:, drive: @drive)
+        load_trap = KernalTrap::Load.new(cpu:, bus: trap_bus, layout:, drive: @drive)
         cpu.install_trap(layout.load) { load_trap.call }
-        @serial_trap = KernalTrap::Serial.new(cpu:, bus: address_bus, layout:, drive: @drive,
+        @serial_trap = KernalTrap::Serial.new(cpu:, bus: trap_bus, layout:, drive: @drive,
                                               device: serial_trap_device).install
-        save_trap = @save_trap = KernalTrap::Save.new(cpu:, bus: address_bus, layout:, drive: @drive)
+        save_trap = @save_trap = KernalTrap::Save.new(cpu:, bus: trap_bus, layout:, drive: @drive)
         cpu.install_trap(layout.save) { save_trap.call }
       end
 
@@ -24,6 +62,28 @@ module Badline
         @serial_trap = nil
         @save_trap = nil
       end
+
+      # The disk device 8 serves through the traps, with the traps' own
+      # state: open channels, the drive's status and RAM, a SAVE under way.
+      def save_trap_drive(out)
+        out.boolean(!@drive.nil?)
+        return unless @drive
+
+        @drive.save_state(out)
+        @serial_trap.save_state(out)
+        @save_trap.save_state(out)
+      end
+
+      def load_trap_drive(input)
+        return unmount unless input.boolean?
+
+        storage = Storage.reopen(input)
+        unmount
+        mount(storage)
+        @drive.load_state(input)
+        @serial_trap.load_state(input)
+        @save_trap.load_state(input)
+      end
     end
   end
 end