badline 0.11.1 → 0.12.0

data/lib/badline/drive1581/wd1772.rb

@@ -0,0 +1,216 @@
+# frozen_string_literal: true
+
+require "badline/drive1581/wd1772/registers"
+require "badline/drive1581/wd1772/turn"
+require "badline/drive1581/wd1772/stepping"
+require "badline/drive1581/wd1772/sectors"
+require "badline/drive1581/wd1772/sector_writes"
+require "badline/drive1581/wd1772/tracks"
+require "badline/drive1581/wd1772/state"
+
+module Badline
+  class Drive1581
+    # The WD1772 floppy disk controller at $6000, as the WD177x data sheet
+    # describes it, working on the Mechanism's Track at sector level: it
+    # finds ID and data fields where they lie round the turn and moves
+    # their bytes at the MFM double-density rate, a byte every 32 µs, but
+    # keeps no flux or bitstream.
+    #
+    #   $6000  status (read), command (write)
+    #   $6001  track
+    #   $6002  sector
+    #   $6003  data
+    #
+    # It runs on the drive's clock, 2 MHz here, so the data sheet's times,
+    # given for 8 MHz on the chip's clock pin, come out as BYTE cycles a
+    # byte, STEP_RATES between steps and SETTLE for the head to settle.
+    #
+    # A command runs as a chain of phases, each due at a cycle (@due): a
+    # step, an index pulse, the end of a byte under the head. Between them
+    # nothing happens, so cycle! only counts. BUSY sets as the command is
+    # written, and the chip takes it up START cycles later, 16 µs, so a
+    # command with nothing to do, such as a seek to the track the head is
+    # on, still shows BUSY to the DOS, which polls for it before waiting
+    # for it to clear.
+    #
+    # The 1581 leaves INTRQ and DRQ unconnected and polls the status
+    # register instead (schematic sheet 2), but both are here (intrq?,
+    # drq?). Its DOS sets h in every command, so the motor spin-up wait
+    # never runs; the spindle follows the 8520's /MOTOR line instead.
+    class WD1772
+      include Registers
+      include Turn
+      include Stepping
+      include Sectors
+      include SectorWrites
+      include Tracks
+      include State
+
+      BYTE = 64
+      START = 32
+      STEP_RATES = [12_000, 24_000, 4_000, 6_000].freeze
+      SETTLE = 30_000
+
+      NEVER = 1 << 62
+
+      # Status bits. Bits 1 and 2 report the index pulse and track 0 after
+      # a type I command, and DRQ and lost data after the others; bit 5
+      # reports spin-up after a type I command and a deleted data mark
+      # after a read.
+      BUSY = 0x01
+      INDEX = 0x02
+      DATA_REQUEST = 0x02
+      TRACK0 = 0x04
+      LOST_DATA = 0x04
+      CRC_ERROR = 0x08
+      NOT_FOUND = 0x10
+      SPUN_UP = 0x20
+      DELETED = 0x20
+      PROTECTED = 0x40
+      MOTOR_ON = 0x80
+
+      # Command flags.
+      NO_SPIN_UP = 0x08
+      VERIFY = 0x04
+      SETTLE_DELAY = 0x04
+      MULTIPLE = 0x10
+      UPDATE = 0x10
+      DELETED_MARK = 0x01
+
+      # Phases.
+      IDLE = 0
+      SPIN_UP = 1
+      STEPPED = 2
+      SETTLED = 3
+      SEARCH = 4
+      READ_DATA = 5
+      WRITE_GATE = 6
+      WRITE_DATA = 7
+      READ_TRACK = 8
+      TRACK_INDEX = 9
+      WRITE_TRACK = 10
+      MOTOR_IDLE = 11
+      INDEX_INTERRUPT = 12
+      SETTLE_SEARCH = 13
+      READ_ADDRESS = 14
+      WRITE_TRACK_START = 15
+      STARTING = 16
+
+      # What a search for an ID field is for.
+      READ = 0
+      WRITE = 1
+      ADDRESS = 2
+      VERIFY_TRACK = 3
+
+      attr_reader :now, :track, :sector, :data, :command
+
+      def initialize(mechanism)
+        @mechanism = mechanism
+        @now = 0
+        @due = NEVER
+        @phase = IDLE
+        reset!
+      end
+
+      # The MR line: the registers as the data sheet leaves them, $03 in
+      # the command register and 1 in the sector register, and no command
+      # running.
+      def reset!
+        @command = 0x03
+        @track = 0
+        @sector = 1
+        @data = 0
+        @status = 0
+        @type1 = true
+        @drq = false
+        @intrq = false
+        @motor_on = false
+        @inward = true
+        clear_command
+        idle
+      end
+
+      def cycle!
+        @now += 1
+        advance if @now == @due
+      end
+
+      # How many cycles can go by before the next phase is due.
+      def quiet_cycles = @due - @now - 1
+
+      # Runs +cycles+ cycles at once, as many as quiet_cycles allows.
+      def fast_forward(cycles)
+        @now += cycles
+      end
+
+      def busy? = @phase != IDLE && @phase != MOTOR_IDLE && @phase != INDEX_INTERRUPT
+
+      def drq? = @drq
+
+      def intrq? = @intrq
+
+      def motor_on? = @motor_on
+
+      private
+
+      # A command ends: INTRQ, and the motor turns off after nine more
+      # index pulses unless a command comes first.
+      def finish
+        @intrq = true
+        @phase = MOTOR_IDLE
+        @count = 9
+        count_index
+      end
+
+      # What a command keeps between its phases.
+      def clear_command
+        @steps = 0
+        @count = 0
+        @after_spin_up = IDLE
+        @mode = 0
+        @deadline = NEVER
+        @id_at = NEVER
+        @found = -1
+        @bytes = []
+        @syncs = []
+        @index = 0
+        @crc = 0xffff
+        @crc_good = true
+        @write_id = 0
+        @size = 0
+        @gate_open = false
+        @late = false
+        @settling = false
+      end
+
+      def idle
+        @phase = IDLE
+        @due = NEVER
+      end
+
+      def advance
+        case @phase
+        when STARTING then start_command
+        when SPIN_UP, MOTOR_IDLE, INDEX_INTERRUPT then index_counted
+        when STEPPED then step_done
+        when SETTLED then verify_track
+        when SETTLE_SEARCH then begin_search
+        when SEARCH then id_passed
+        when READ_DATA, READ_ADDRESS then byte_read
+        else advance_write
+        end
+      end
+
+      def advance_write
+        case @phase
+        when WRITE_GATE then write_gate
+        when WRITE_DATA then byte_written
+        when READ_TRACK then track_byte_read
+        when TRACK_INDEX then track_index
+        when WRITE_TRACK_START then write_track_start
+        when WRITE_TRACK then track_byte_written
+        end
+      end
+    end
+  end
+end

data/lib/badline/drive1581.rb

@@ -0,0 +1,233 @@
+# frozen_string_literal: true
+
+require "badline/drive"
+require "badline/drive1581/track"
+require "badline/drive1581/track_bytes"
+require "badline/drive1581/disk"
+require "badline/drive1581/mechanism"
+require "badline/drive1581/wd1772"
+require "badline/drive1581/cpu"
+require "badline/drive1581/serial_port"
+require "badline/drive1581/bus"
+
+module Badline
+  # The 1581 3.5" disk drive: a 6502 at 2 MHz with 8 KB of RAM, an 8520
+  # for the serial bus and the mechanism's lines, a WD1772 for the MFM
+  # disk, and the DOS in 32 KB of ROM (1581 Service Manual). Drive::Core
+  # clocks it against the host.
+  #
+  # The 8520's port B faces the serial bus as VIA 1's does on the 1541,
+  # with the same bits, and ATN reaches its FLAG pin, so ATN going low
+  # interrupts the DOS. Its SP and CNT carry fast serial on DATA and SRQ,
+  # through buffers PB5 turns round (Drive::FastSerial), as the 1571's
+  # 6526 does. The ATN acknowledge differs: a NAND of ATN IN and
+  # ATN ACK pulls DATA, so DATA follows ATN only while ATN is asserted
+  # and PB4 is high, where the 1541's XOR pulls it whenever the two
+  # differ (IECBus::DRIVE_ATN_GATED). Port A drives the motor, the side
+  # and the two LEDs, and reads the switches and the mechanism's /RDY and
+  # /DISK CHNG (SerialPort). Timer B interrupts every 10 ms for the
+  # controller code that runs the WD1772.
+  #
+  # The 8520 differs from the 6526 in its TOD, a 24-bit binary event
+  # counter where the 6526 keeps a BCD clock. The 1581 holds the TOD pin
+  # high when it carries a WD1772 (jumper J1 out), so the counter never
+  # counts, and the DOS's one use of it, writing $00 to the low byte and
+  # reading it back 20 µs later to tell a WD1770 from a WD1772, reads $00
+  # on either chip: the drive's CIA gets no TOD pulses (CIA's tod_hz).
+  class Drive1581
+    include Drive::Core
+    include Drive::FastSerial
+
+    CLOCK_HZ = 2_000_000
+
+    # Where the DOS's idle loop starts over (see Drive::Idle).
+    IDLE_LOOP = 0xb105
+
+    # The host cycles, at about 1 MHz, by which a 1581 switched on with the
+    # machine has run its DOS's reset, the RAM test, the ROM checksum and
+    # the controller's half-second wait, and waits on the bus: 2.32 s,
+    # with a margin.
+    BOOT_CYCLES = 2_700_000
+
+    # The 8520's port A outputs.
+    SIDE = 0x01
+    MOTOR = 0x04
+    POWER_LED = 0x20
+    ACTIVITY_LED = 0x40
+
+    # Port B's ATN acknowledge, and the fast serial direction.
+    ATN_ACK = 0x10
+    FAST_SERIAL_OUT = 0x20
+
+    def cia
+      settle!
+      @cia
+    end
+
+    def fdc
+      settle!
+      @fdc
+    end
+
+    def model_name = "1581"
+
+    # +rom+ covers $8000-$FFFF, and defaults to the DOS image in the ROM
+    # path. +device+ is the number the switches on port A's PA3 and PA4
+    # set, 8 to 11.
+    def initialize(rom: nil, host_clock_hz: Drive1541::CLOCK_HZ, device: 8, debug: false)
+      @device = device
+      @clock_hz = CLOCK_HZ
+      @mechanism = Mechanism.new
+      @fdc = WD1772.new(@mechanism)
+      @serial_port = SerialPort.new(@mechanism, device:)
+      @cia = CIA.new(start: 0x4000, peripheral: @serial_port, tod_hz: 0)
+      @bus = Bus.new(rom: rom || ROM.load("dos1581.rom", 0x8000), cia: @cia, fdc: @fdc, drive: self)
+      @cpu = CPU.new(@bus, debug:)
+      @idle_loop = IDLE_LOOP
+      @host_clock_hz = host_clock_hz
+      @phase = 0
+      @cycles = 0
+      @serial_bus = nil
+      @atn = false
+      @activity = false
+      @power = false
+      init_fast_serial
+      init_idle(debug)
+      ports_written
+      connect(IECBus.new)
+    end
+
+    # The serial bus's RESET line reaches the CPU, the 8520 and the
+    # WD1772. RAM keeps its contents.
+    def reset!
+      settle!
+      @cia.reset!
+      @fdc.reset!
+      ports_written
+      @cpu.reset!
+    end
+
+    def insert(disk)
+      settle!
+      @mechanism.insert(disk, @fdc.now)
+      @fdc.spin_changed
+    end
+
+    # Puts in a Disk from the .d81 image at +path+, write-protected with
+    # `read_only`.
+    def insert_image(path, read_only: false)
+      insert(Disk.open(path, read_only:))
+    end
+
+    # Whether the activity LED is lit. The power LED stays lit, and
+    # flashes on an error.
+    def led_on? = @activity
+
+    def power_led_on? = @power
+
+    # The 8520's port B as it drives the serial bus, in VIA 1's bits, the
+    # ATN acknowledge turned round for the NAND that gates it, with the
+    # fast serial pins above it. It holds still while the drive sleeps, so
+    # reading it leaves the drive asleep.
+    def serial_output
+      lines = @cia.port_b_lines
+      output = (lines & (IECBus::DRIVE_DATA_OUT | IECBus::DRIVE_CLK_OUT)) | IECBus::DRIVE_ATN_GATED | @fast_output
+      lines.anybits?(ATN_ACK) ? output : output | IECBus::DRIVE_ATNA
+    end
+
+    # The 8520's ports drive the motor, the side, the LEDs and the fast
+    # serial buffers: the drive follows them after every write to a port
+    # or direction register.
+    def ports_written
+      fast_serial_out = @cia.port_b_lines.anybits?(FAST_SERIAL_OUT)
+      turn_fast_serial(fast_serial_out) if fast_serial_out != @fast_serial_out
+      lines = @cia.port_a_lines
+      @mechanism.side = lines.anybits?(SIDE) ? 1 : 0
+      @activity = lines.anybits?(ACTIVITY_LED)
+      @power = lines.anybits?(POWER_LED)
+      motor = lines.nobits?(MOTOR)
+      return if motor == @mechanism.motor_on?
+
+      @mechanism.motor(motor, @fdc.now)
+      @fdc.spin_changed
+    end
+
+    # The drive's whole state, as the 1541's (Drive1541#save_state), with
+    # the 8520 and the WD1772 in place of the VIAs.
+    def save_state(out)
+      settle!
+      out.marker("DRIVE1581")
+      out.int(@phase).int(@cycles).boolean(@atn)
+      @serial_port.save_state(out)
+      @cia.save_state(out)
+      @fdc.save_state(out)
+      @bus.save_state(out)
+      @cpu.save_state(out)
+      @mechanism.save_state(out)
+    end
+
+    def load_state(input)
+      settle!
+      input.marker("DRIVE1581")
+      @phase = input.int
+      @cycles = input.int
+      @atn = input.boolean?
+      @serial_port.load_state(input)
+      @cia.load_state(input)
+      @fdc.load_state(input)
+      @bus.load_state(input)
+      @cpu.load_state(input)
+      @mechanism.load_state(input)
+      @fast_serial_out = @cia.port_b_lines.anybits?(FAST_SERIAL_OUT)
+      ports_written
+      push_fast_output(@fast_serial_out ? fast_pins : 0)
+      forget_orbits
+    end
+
+    private
+
+    # One drive cycle: ATN going low pulls FLAG, the WD1772 and the 8520
+    # clock ahead of the CPU, and the 8520 alone pulls IRQ.
+    def step
+      atn = @serial_port.atn_low?
+      if atn != @atn
+        @atn = atn
+        @cia.flag! if atn
+      end
+      @fdc.cycle!
+      @cia.cycle!
+      drive_fast_serial if @fast_serial_out
+      @cpu.irq = @cia.interrupted?
+      @cpu.cycle!
+      @cycles += 1
+    end
+
+    def hear_atn
+      @atn = @serial_port.atn_low?
+    end
+
+    # A pass of the idle loop reads and writes RAM alone, so it repeats
+    # while the 8520 pulls no IRQ, for as long as the 8520's counters and
+    # the WD1772's next phase leave room: until timer B's next interrupt
+    # for the controller code. Neither chip changes but by the clock, so
+    # only the CPU is compared.
+    def busy_for_pass? = @cia.interrupted?
+
+    def quiet_cycles = [@cia.quiet_cycles, @fdc.quiet_cycles].min
+
+    def idle_state = [*@cpu.idle_state, @bus.data, @atn]
+
+    def fast_forward_chips(cycles)
+      @cia.fast_forward(cycles)
+      @fdc.fast_forward(cycles)
+    end
+
+    # Every timer B interrupt reads the 8520, so no orbit (Drive::Orbit)
+    # comes round, and the drive keeps no anchors.
+    def anchor = nil
+
+    def counter_state(_touched) = []
+
+    def skip_chip_orbits(_cycles, _touched) = nil
+  end
+end

data/lib/badline/frontend/app.rb

@@ -10,8 +10,6 @@ module Badline
     # On the C128 it follows the machine between the VIC-IIe's 40 columns
     # and the VDC's 80, and F8 switches them until the machine next does.
     class App
-      DROPFILE = 0x1000
-
       # Takes the frame limit, the pacing, the snapshot path, the sound and
       # the verbosity from Options, and runs the timeline's events.
       def initialize(computer, options, timeline)
@@ -109,7 +107,7 @@ module Badline
           @controls.mouse_button(SDL.event_button(SDL.event), type == SDL::MOUSEBUTTONDOWN)
         when SDL::CONTROLLERDEVICEADDED, SDL::CONTROLLERDEVICEREMOVED
           @gamepads.rescan
-        when DROPFILE then resume(false) unless @menu.drop(@computer, @controls, @sound)
+        when SDL::DROPFILE then resume(false) unless @menu.drop(@computer, @controls, @sound)
         end
       end
 

data/lib/badline/frontend/audio_device.rb

@@ -0,0 +1,67 @@
+# frozen_string_literal: true
+
+module Badline
+  module Frontend
+    # An SDL audio device on SDL's queue: signed 16-bit samples, `channels`
+    # of them interleaved per frame, go in at the device's rate and SDL
+    # plays them out behind us. When #open fails the device stays closed,
+    # with the reason in SDL_GetError for the caller to report.
+    class AudioDevice
+      attr_reader :rate
+
+      def initialize(channels:, rate:, samples:)
+        @channels = channels
+        @rate = rate
+        @samples = samples
+        @device = 0
+        @buffer = IO::Buffer.new(4096)
+      end
+
+      def open? = @device != 0
+
+      # With `exact_rate` false SDL may pick the device's own rate instead,
+      # which #rate then reports.
+      def open(exact_rate)
+        return unless SDL.SDL_InitSubSystem(SDL::INIT_AUDIO).zero?
+
+        SDL.spec_freq(SDL.wanted, @rate)
+        SDL.spec_format(SDL.wanted, SDL::AUDIO_S16LSB)
+        SDL.spec_channels(SDL.wanted, @channels)
+        SDL.spec_samples(SDL.wanted, @samples)
+        allowed_changes = exact_rate ? 0 : SDL::ALLOW_FREQUENCY_CHANGE
+        @device = SDL.SDL_OpenAudioDevice(nil, 0, SDL.wanted, SDL.obtained, allowed_changes)
+        @rate = SDL.read_i32(SDL.obtained) if open?
+      end
+
+      # Returns SDL_QueueAudio's result, negative on failure.
+      def queue(samples)
+        count = samples.size
+        bytes = count * 2
+        @buffer.resize(bytes) if bytes > @buffer.size
+        buffer = @buffer
+        i = 0
+        while i < count
+          buffer.set_value(:s16, i * 2, samples[i])
+          i += 1
+        end
+        SDL.SDL_QueueAudio(@device, buffer, bytes)
+      end
+
+      def queued_seconds = SDL.SDL_GetQueuedAudioSize(@device) / (2.0 * @channels * @rate)
+
+      def start = SDL.SDL_PauseAudioDevice(@device, 0)
+
+      def pause = SDL.SDL_PauseAudioDevice(@device, 1)
+
+      def clear = SDL.SDL_ClearQueuedAudio(@device)
+
+      def close
+        return unless open?
+
+        SDL.SDL_CloseAudioDevice(@device)
+        SDL.SDL_QuitSubSystem(SDL::INIT_AUDIO)
+        @device = 0
+      end
+    end
+  end
+end

data/lib/badline/frontend/audio_sink.rb

@@ -2,72 +2,38 @@
 
 module Badline
   module Frontend
-    # The host's audio device for --headless and the SID player, fed through
-    # SDL's queue: stereo signed 16-bit samples, the left and right
-    # interleaved, go in at the device's rate and SDL plays them out behind
-    # us. It answers what Audio::Playback asks of a sink.
+    # The host's audio device for --headless and the SID player: a stereo
+    # AudioDevice, the left and right samples interleaved, that raises on
+    # SDL's failures. It answers what Audio::Playback asks of a sink.
     class AudioSink
       class Error < Audio::Playback::DeviceError; end
 
-      attr_reader :rate
-
       # With `exact_rate` false SDL may pick the device's own rate instead,
       # which #rate then reports.
       def initialize(rate:, exact_rate: false, buffer: 1024)
-        @device = 0
-        @rate = rate
-        @buffer = IO::Buffer.new(4096)
-        check(SDL.SDL_InitSubSystem(SDL::INIT_AUDIO))
-        open_device(rate, exact_rate ? 0 : SDL::ALLOW_FREQUENCY_CHANGE, buffer)
-      end
-
-      def queue(samples)
-        count = samples.size
-        bytes = count * 2
-        @buffer.resize(bytes) if bytes > @buffer.size
-        buffer = @buffer
-        i = 0
-        while i < count
-          buffer.set_value(:s16, i * 2, samples[i])
-          i += 1
-        end
-        check(SDL.SDL_QueueAudio(@device, buffer, bytes))
+        @device = AudioDevice.new(channels: 2, rate:, samples: buffer)
+        @device.open(exact_rate)
+        raise Error, SDL.SDL_GetError unless @device.open?
       end
 
-      def queued_seconds = SDL.SDL_GetQueuedAudioSize(@device) / (4.0 * @rate)
-
-      def start = SDL.SDL_PauseAudioDevice(@device, 0)
-
-      def pause = SDL.SDL_PauseAudioDevice(@device, 1)
-
-      def clear = SDL.SDL_ClearQueuedAudio(@device)
+      def rate = @device.rate
 
-      def close
-        return if @device.zero?
+      def queue(samples)
+        result = @device.queue(samples)
+        raise Error, SDL.SDL_GetError if result.negative?
 
-        SDL.SDL_CloseAudioDevice(@device)
-        SDL.SDL_QuitSubSystem(SDL::INIT_AUDIO)
-        @device = 0
+        result
       end
 
-      private
+      def queued_seconds = @device.queued_seconds
 
-      def open_device(rate, allowed_changes, buffer)
-        SDL.spec_freq(SDL.wanted, rate)
-        SDL.spec_format(SDL.wanted, SDL::AUDIO_S16LSB)
-        SDL.spec_channels(SDL.wanted, 2)
-        SDL.spec_samples(SDL.wanted, buffer)
-        @device = SDL.SDL_OpenAudioDevice(nil, 0, SDL.wanted, SDL.obtained, allowed_changes)
-        raise Error, SDL.SDL_GetError if @device.zero?
+      def start = @device.start
 
-        @rate = SDL.read_i32(SDL.obtained)
-      end
+      def pause = @device.pause
 
-      def check(result)
-        raise Error, SDL.SDL_GetError if result.negative?
+      def clear = @device.clear
 
-        result
-      end
+      def close = @device.close
     end
   end
 end

data/lib/badline/frontend/boot.rb

@@ -16,13 +16,10 @@ module Badline
         return 1
       end
 
-      begin
-        computer = boot(options)
-      rescue Media::TrueDrive::Error, Storage::SIDFile::FormatError, Storage::T64::FormatError,
-             Storage::TAP::FormatError, Storage::CRTFile::FormatError, Storage::G64Image::FormatError,
-             Cartridge::UnsupportedTypeError, Snapshot::FormatError, Media::DiskList::Error,
-             Datasette::Missing, Unsupported => e
-        warn "#{options.program}: #{options.media_path}: #{e.message}"
+      computer = nil
+      problem = media_problem { computer = boot(options) }
+      unless problem.empty?
+        warn "#{options.program}: #{options.media_path}: #{problem}"
         return 1
       end
       timeline = Timeline.new(options)
@@ -30,6 +27,19 @@ module Badline
       timeline.failed? ? 1 : 0
     end
 
+    # Runs the block and returns the message of the error it raised over
+    # media that won't go in or start, or an empty string. Other errors,
+    # a bare ArgumentError among them, go through.
+    def self.media_problem
+      yield
+      ""
+    rescue Unsupported, Media::TrueDrive::Error, Media::DiskList::Error, Media::NotDisk, Datasette::Missing,
+           SystemCallError, Storage::SIDFile::FormatError, Storage::T64::FormatError, Storage::TAP::FormatError,
+           Storage::CRTFile::FormatError, Storage::G64Image::FormatError, Cartridge::UnsupportedTypeError,
+           Snapshot::FormatError => e
+      e.message
+    end
+
     # The machine a .vsf snapshot holds, built as the saved one was, or a
     # new one built from the options with the media attached.
     def self.boot(options)
@@ -88,9 +98,7 @@ module Badline
       return true if extension == ".sid"
       return false unless %w[.prg .p00].include?(extension)
 
-      bytes = File.binread(media).bytes
-      bytes = Storage::P00.data(bytes) if Storage::P00.wraps?(bytes)
-      bytes.length >= 2 && [Media::BASIC_START, Media::BASIC_START - 1].include?(bytes[0] | (bytes[1] << 8))
+      [Media::BASIC_START, Media::BASIC_START - 1].include?(Storage::P00.load_address(media))
     end
 
     # A VIC-20 with the RAM --ram names, or else the RAM `media` needs

data/lib/badline/frontend/buttons.rb

@@ -2,17 +2,17 @@
 
 module Badline
   module Frontend
-    # The SID player's buttons: each is drawn where it goes on every frame,
-    # and remembers its place, so a click finds the action under it. The
-    # one under the pointer lights up, and one that's on is drawn reversed.
-    # They take the player's colours unless given others: the text, the text
-    # under the pointer, the background and, if any, a fill behind each
-    # button.
+    # The buttons of the SID player and the pause menu: each is drawn where
+    # it goes on every frame, and remembers its place, so a click finds the
+    # action under it. The one under the pointer lights up, and one that's
+    # on is drawn reversed. They take their colours from the caller: the
+    # text, the text under the pointer, the background and, if any, a fill
+    # behind each button.
     class Buttons
       PAD = 2
       HEIGHT = Painter::GLYPH + (PAD * 2)
 
-      def initialize(painter, colors = [SIDView::TEXT, SIDView::BRIGHT, PlayerScreen::BACKGROUND])
+      def initialize(painter, colors)
         @painter = painter
         @text = colors[0]
         @bright = colors[1]