badline 0.10.1 → 0.11.0

data/lib/badline/c128/bus.rb

@@ -0,0 +1,347 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The 8502's bus over the 128K of RAM, as the MMU maps it.
+    #
+    # In C128 mode CR picks what the CPU sees: BASIC at $4000-$BFFF, the
+    # screen editor, the character ROM and the KERNAL at $C000-$FFFF, an
+    # empty function ROM socket, or RAM, and I/O at $D000-$DFFF. The MMU's
+    # registers sit at $D500 and its configuration registers at
+    # $FF00-$FF04.
+    #
+    # In C64 mode the 8721 PLA decodes $01's LORAM, HIRAM and CHAREN and the
+    # cartridge's EXROM and GAME as a C64's does (AddressBus::PLA), and the
+    # MMU answers nowhere.
+    #
+    # In both modes the RAM is the bank CR picks, with common RAM in bank 0,
+    # and a page that page 0 or page 1 moves to reaches page 0 or page 1 of
+    # that bank. C128 mode also moves page 0 and page 1 there. The I/O area:
+    #
+    # $D000-$D3FF - the VIC-IIe
+    # $D400-$D4FF - the SID, with no mirrors above it
+    # $D500-$D5FF - the MMU in C128 mode, nothing in C64 mode
+    # $D600-$D6FF - the VDC
+    # $D700-$D7FF - nothing, but for VICE's debug register at $D7FF
+    # $D800-$DBFF - colour RAM
+    # $DC00-$DCFF - CIA 1
+    # $DD00-$DDFF - CIA 2
+    # $DE00-$DFFF - I/O 1 and 2, for cartridges
+    #
+    # An empty page reads the byte the VIC fetched in the preceding phi1
+    # half-cycle, as I/O 1 and 2 do on the C64.
+    #
+    # Colour RAM has two 1K banks (ColorLines).
+    class Bus
+      include Addressable
+      include AddressBus::PLA
+      include AddressBus::ROMs
+      include MMUPages
+      include SavedState
+
+      # The 8502's port has seven pins. P0-P5 are the 6510's, and P6 senses
+      # the CAPS LOCK key, high while it is up. Bit 7 has no pin, and holds
+      # the charge last driven onto it, as the 6510's floating bits do.
+      PORT_PULLUPS  = 0b0001_0111
+      PORT_FLOATING = 0b1000_1000
+      CAPS_LOCK     = 0b0100_0000
+      TAPE_SENSE    = 0b0001_0000
+
+      # The C64's power-on pattern (AddressBus::RAM_POWER_ON) in both 64K
+      # banks. The C128's own DRAMs' pattern is unmeasured.
+      RAM_POWER_ON = Array.new(2**17) { |addr| AddressBus::RAM_POWER_ON[addr & 0xffff] }.freeze
+
+      # The VIC's write side: a write to $D02F also drives the extra
+      # keyboard lines K0-K2 onto the keyboard's rows 8-10.
+      class VICWrites
+        def initialize(vic, control_ports)
+          @vic = vic
+          @control_ports = control_ports
+        end
+
+        def peek(addr) = @vic.peek(addr)
+
+        def poke(addr, value)
+          @vic.poke(addr, value)
+          @control_ports.extra_rows = 0xf8 | @vic.extra_keyboard_lines if (addr & 0x3f) == 0x2f
+        end
+      end
+
+      # The $D7xx page with VICE's debug register at $D7FF: a write there
+      # hands the handler its byte, and the rest of the page is empty.
+      class DebugPage
+        ADDRESS = 0xd7ff
+
+        def initialize(open_bus, &handler)
+          @open_bus = open_bus
+          @handler = handler
+        end
+
+        def peek(addr) = @open_bus.peek(addr)
+
+        def poke(addr, value)
+          @handler.call(value) if addr == ADDRESS
+        end
+      end
+
+      # RAM seen somewhere else: the address's bits in +mask+ from +base+
+      # on. Bank 1 is the whole 64K from $10000, and a relocated page the
+      # low byte from the page it moved to.
+      class RAMWindow
+        attr_accessor :base
+
+        def initialize(ram, base, mask)
+          @ram = ram
+          @base = base
+          @mask = mask
+        end
+
+        def peek(addr) = @ram.peek(@base | (addr & @mask))
+        def poke(addr, value) = @ram.poke(@base | (addr & @mask), value)
+      end
+
+      # The page at $FF00 in C128 mode: CR and the LCRs at $FF00-$FF04, and
+      # whatever CR maps there above them.
+      class ConfigurationPage
+        attr_accessor :below
+
+        def initialize(mmu, below)
+          @mmu = mmu
+          @below = below
+        end
+
+        def peek(addr) = addr < 0xff05 ? @mmu.peek_configuration(addr) : @below.peek(addr)
+
+        def poke(addr, value)
+          addr < 0xff05 ? @mmu.poke_configuration(addr, value) : @below.poke(addr, value)
+        end
+      end
+
+      attr_reader :io_port, :ram, :mmu, :vic, :sid, :vdc, :color_ram, :cia1, :cia2, :keyboard, :joystick1,
+                  :joystick2, :control_ports, :cartridge, :ultimax, :phi1_ultimax, :datasette, :region
+
+      # The C128 mode ROMs: BASIC's two halves, the screen editor, the
+      # KERNAL and the character ROM's C128 set.
+      attr_reader :basic_low_rom, :basic_high_rom, :editor_rom, :c128_kernal_rom, :c128_character_rom
+
+      # Whether CAPS LOCK is down, holding P6 low.
+      attr_reader :caps_lock
+
+      # The chips +model+, a Model::Profile, names, with the SID
+      # +sid_model+. +mode+ is the mode the MMU resets into.
+      def initialize(model, sid_model: model.sid_model, mode: :c64)
+        @region = model.region
+        @ram = Memory.new(RAM_POWER_ON, length: 2**17, start: 0)
+        @bank1 = RAMWindow.new(@ram, 0x10000, 0xffff)
+        @relocated = Array.new(4) { RAMWindow.new(@ram, 0, 0xff) }
+        @mmu = MMU.new(mode)
+        @cartridge = nil
+        @debug_page = nil
+        @caps_lock = false
+
+        load_roms
+        load_c128_roms
+        @banks = Banks.new(@ram, @mmu, @c128_kernal_rom)
+        @c64_mode = @mmu.c64_mode?
+        @on_mode_change = nil
+        plug_chips(model, sid_model)
+
+        @datasette = Datasette.new
+        @datasette.on_flag { @cia1.flag! }
+        @datasette.on_sense_change { @io_port.value = port_value }
+
+        @color_lines = ColorLines.new(@vic, @cia2, character_rom, @c128_character_rom)
+        @color_ram = @color_lines.color_ram(1)
+        @vic_writes = VICWrites.new(@vic, @control_ports)
+        @open_bus = AddressBus::OpenBus.new(@vic)
+        @configuration_reads = ConfigurationPage.new(@mmu, @open_bus)
+        @configuration_writes = ConfigurationPage.new(@mmu, @open_bus)
+
+        @port_ddr = 0x00
+        @port_out = 0x00
+        @port_floating = 0x00
+        @io_port = PortStatus.new(%i[basic kernal io tape_out tape_switch tape_motor], value: port_value)
+
+        @read_pages = Array.new(256)
+        @write_pages = Array.new(256)
+        @address = 0
+        @data = 0
+        @io_mapped = false
+        @mmu.on_change { update_overlays! }
+        update_overlays!
+      end
+
+      def attach_cartridge(cartridge)
+        @cartridge = cartridge
+        cartridge.connect(ram: @ram, open_bus: @open_bus)
+        cartridge.on_change { update_overlays! }
+        update_overlays!
+      end
+
+      # Takes the cartridge out of the expansion port.
+      def detach_cartridge
+        @cartridge = nil
+        update_overlays!
+      end
+
+      def power_on!
+        @ram.clear!(RAM_POWER_ON)
+      end
+
+      # The RES line clears the port's direction and output registers and
+      # resets the MMU. The port's floating bit keeps its charge.
+      def reset!
+        @port_ddr = 0x00
+        @port_out = 0x00
+        @mmu.reset!
+        update_port!
+      end
+
+      # Holds CAPS LOCK down, or lets it up.
+      def caps_lock=(down)
+        @caps_lock = down
+        @io_port.value = port_value
+      end
+
+      # Calls the block whenever MCR bit 6 takes the machine into C64 mode or
+      # a reset brings it back to C128 mode.
+      def on_mode_change(&block)
+        @on_mode_change = block
+      end
+
+      # Whether the CPU sees the C128 KERNAL, in C128 mode with CR's system
+      # ROM at $C000-$FFFF.
+      def system_rom_mapped? = !@mmu.c64_mode? && @mmu.cr.nobits?(0x30)
+
+      # The RAM the C128 KERNAL's bank number +bank+ reaches (Banks).
+      def peek_bank(bank, addr) = @banks.peek(bank, addr)
+
+      def write_bank(bank, addr, bytes) = @banks.write(bank, addr, bytes)
+
+      def install_debug_register(&)
+        @debug_page = DebugPage.new(@open_bus, &)
+        update_overlays!
+      end
+
+      # The address and the byte of the CPU's last access, which a VIC-IIe
+      # in FAST mode fetches in place of its own, and which tells the
+      # machine when an access reached I/O.
+      attr_reader :address, :data
+
+      def peek(addr)
+        @address = addr
+        @data = if addr > 0x01
+                  @read_pages[addr >> 8].peek(addr)
+                else
+                  addr.zero? ? @port_ddr : @io_port.value
+                end
+      end
+
+      # Whether the last access went to a chip at $D000-$DFFF, which runs
+      # at 1 MHz.
+      def io_access? = @io_mapped && (@address & 0xf000) == 0xd000
+
+      # Whether the last access went to the VIC's registers.
+      def vic_access? = @io_mapped && (@address & 0xfc00) == 0xd000
+
+      # A write to $00 or $01 goes to the port, and the RAM below takes the
+      # byte the VIC fetched in the phi1 half of the cycle.
+      def poke(addr, value)
+        @address = addr
+        @data = value
+        if addr < 0x02
+          @write_pages[0].poke(addr, @vic.phi1_data)
+          addr.zero? ? @port_ddr = value : @port_out = value
+          update_port!
+        else
+          @write_pages[addr >> 8].poke(addr, value)
+        end
+      end
+
+      def inspect
+        "#<#{self.class.name} mode=#{@mmu.mode} port=#{format('0x%02x', @io_port.value)} " \
+          "cartridge=#{@cartridge ? @cartridge.class.name : 'none'} " \
+          "ultimax=#{@ultimax}>"
+      end
+
+      private
+
+      def load_c128_roms
+        basic = ROM.read("c128/basic.rom")
+        kernal = ROM.read("c128/kernal.rom")
+        @basic_low_rom = ROM.new(basic[0, 0x4000], length: 0x4000, start: 0x4000)
+        @basic_high_rom = ROM.new(basic[0x4000, 0x4000], length: 0x4000, start: 0x8000)
+        @editor_rom = ROM.new(kernal[0, 0x1000], length: 0x1000, start: 0xc000)
+        @c128_kernal_rom = ROM.new(kernal[0x2000, 0x2000], length: 0x2000, start: 0xe000)
+        characters = ROM.read("c128/character.rom")
+        @c128_character_rom = ROM.new(characters[0x1000, 0x1000], length: 0x1000, start: 0xd000)
+      end
+
+      def plug_chips(model, sid_model)
+        @keyboard = Keyboard.new(matrix: KEYBOARD_MATRIX)
+        @joystick1 = Joystick.new
+        @joystick2 = Joystick.new
+        @control_ports = ControlPorts.new(keyboard: @keyboard, joystick1: @joystick1, joystick2: @joystick2)
+        @vic = VIC.new(model: model.vic_model, region: @region)
+        @cia1 = CIA.new(start: 0xdc00, peripheral: @control_ports, model: model.cia_model, region: @region)
+        @cia2 = CIA.new(start: 0xdd00, model: model.cia_model, region: @region)
+        @control_ports.port_a_source = @cia1
+        @cia1.on_port_b4_change { |high| @vic.lightpen_level(high) }
+        @sid = SID.new(model: sid_model, pots: @control_ports)
+        @vdc = VDC.new(model: model.vdc_model, ram_kb: model.vdc_ram_kb, clock_hz: @region.clock_hz)
+      end
+
+      def update_port!
+        driven = @port_ddr & PORT_FLOATING
+        @port_floating = (@port_floating & ~driven) | (@port_out & driven)
+        @io_port.value = port_value
+        @datasette.motor = !@io_port.tape_motor?
+        update_overlays!
+      end
+
+      def port_value
+        input = PORT_PULLUPS | (@port_floating & PORT_FLOATING)
+        input |= CAPS_LOCK unless @caps_lock
+        input &= ~TAPE_SENSE if @datasette.sense_low?
+        (@port_out & @port_ddr) | (input & ~@port_ddr & 0xff)
+      end
+
+      def update_overlays!
+        @ultimax = @cartridge ? @cartridge.ultimax? : false
+        @phi1_ultimax = @cartridge ? @cartridge.phi1_ultimax? : false
+        @mmu.game = @cartridge ? @cartridge.game : 1
+        @mmu.exrom = @cartridge ? @cartridge.exrom : 1
+        c64_mode = @mmu.c64_mode?
+        port = @io_port.value
+        @color_lines.push(c64_mode, port)
+        @vic.vic_bank.map(@ram, base: @mmu.vic_bank << 16, phi1_ultimax: @phi1_ultimax, ultimax: @ultimax,
+                                romh: @cartridge&.romh)
+        @color_ram = @color_lines.cpu_color_ram(c64_mode, port)
+        c64_mode ? map_pla_pages : map_c128_pages
+        mode_changed if c64_mode != @c64_mode
+      end
+
+      def mode_changed
+        @c64_mode = !@c64_mode
+        @on_mode_change&.call
+      end
+
+      def map_io_pages
+        @io_mapped = true
+        @read_pages.fill(@vic, 0xd0, 4)
+        @write_pages.fill(@vic_writes, 0xd0, 4)
+        @read_pages[0xd4] = @write_pages[0xd4] = @sid
+        @read_pages[0xd5] = @write_pages[0xd5] = @mmu.c64_mode? ? @open_bus : @mmu
+        @read_pages[0xd6] = @write_pages[0xd6] = @vdc
+        @read_pages[0xd7] = @write_pages[0xd7] = @debug_page || @open_bus
+        @read_pages.fill(@color_ram, 0xd8, 4)
+        @write_pages.fill(@color_ram, 0xd8, 4)
+        @read_pages[0xdc] = @write_pages[0xdc] = @cia1
+        @read_pages[0xdd] = @write_pages[0xdd] = @cia2
+        @read_pages.fill(@open_bus, 0xde, 2)
+        @write_pages.fill(@open_bus, 0xde, 2)
+        map_cartridge_io if @cartridge
+      end
+    end
+  end
+end

data/lib/badline/c128/bus_state.rb

@@ -0,0 +1,53 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    class Bus
+      # The bus's state for a snapshot, as AddressBus::SavedState is the
+      # C64's.
+      module SavedState
+        # The machine's memory, the last access and everything on the bus but
+        # the keyboard, the joysticks, the pot devices and CAPS LOCK, which the
+        # host holds. A cartridge is already in the port, built from its setup.
+        def save_state(out)
+          out.marker("C128 BUS")
+          out.int(@port_ddr).int(@port_out).int(@port_floating).int(@address).int(@data)
+          @mmu.save_state(out)
+          @ram.save_state(out)
+          @color_lines.color_ram(0).save_state(out)
+          @color_lines.color_ram(1).save_state(out)
+          @cartridge&.save_state(out)
+          @datasette.save_state(out)
+          @vic.save_state(out)
+          @cia1.save_state(out)
+          @cia2.save_state(out)
+          @sid.save_state(out)
+          @vdc.save_state(out)
+        end
+
+        def load_state(input)
+          input.marker("C128 BUS")
+          @port_ddr = input.int
+          @port_out = input.int
+          @port_floating = input.int
+          @address = input.int
+          @data = input.int
+          @mmu.load_state(input)
+          @ram.load_state(input)
+          @color_lines.color_ram(0).load_state(input)
+          @color_lines.color_ram(1).load_state(input)
+          @cartridge&.load_state(input)
+          @datasette.load_state(input)
+          @io_port.value = port_value
+          update_overlays!
+          @vic.load_state(input)
+          @control_ports.extra_rows = 0xf8 | @vic.extra_keyboard_lines
+          @cia1.load_state(input)
+          @cia2.load_state(input)
+          @sid.load_state(input)
+          @vdc.load_state(input)
+        end
+      end
+    end
+  end
+end

data/lib/badline/c128/color_lines.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The C128's two 1K colour RAM banks, and the colour RAM and character
+    # ROM it pushes into the VIC's bank. In C128 mode the 8502's port picks
+    # them: P0 the colour RAM bank the CPU sees, P1 the one the VIC sees,
+    # and P2 low shows the VIC the character ROM's C128 set. In C64 mode
+    # both see colour RAM bank 1, and the VIC the C64 set.
+    class ColorLines
+      def initialize(vic, cia2, c64_characters, c128_characters)
+        @vic_bank = vic.vic_bank
+        @cia2 = cia2
+        @c64_characters = c64_characters
+        @c128_characters = c128_characters
+        @bank0 = ColorMemory.new(vic)
+        @bank1 = ColorMemory.new(vic)
+      end
+
+      # Colour RAM bank +number+, 0 or 1.
+      def color_ram(number) = number.zero? ? @bank0 : @bank1
+
+      # The colour RAM bank the CPU sees.
+      def cpu_color_ram(c64_mode, port) = c64_mode ? @bank1 : color_ram(port & 0x01)
+
+      # Pushes the colour RAM and the character ROM the VIC sees into its
+      # bank.
+      def push(c64_mode, port)
+        if c64_mode
+          @vic_bank.connect(cia2: @cia2, color_ram: @bank1)
+          @vic_bank.map_character_rom(@c64_characters)
+        else
+          @vic_bank.connect(cia2: @cia2, color_ram: color_ram((port >> 1) & 0x01))
+          @vic_bank.map_character_rom(@c128_characters, shadow: port.nobits?(0x04))
+        end
+      end
+    end
+  end
+end

data/lib/badline/c128/cpu.rb

@@ -0,0 +1,10 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The C128's 8502, on the C128::Bus, which holds its I/O port.
+    class CPU
+      include Badline::CPU::Core
+    end
+  end
+end

data/lib/badline/c128/keys.rb

@@ -0,0 +1,35 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The three keys outside the keyboard matrix: RESTORE, CAPS LOCK and
+    # 40/80 DISPLAY.
+    module Keys
+      # RESTORE pulses NMI for a cycle, as on the C64.
+      def press_restore
+        @restore_pulse = true
+      end
+
+      def release_restore; end
+
+      # CAPS LOCK locks down and up, and holds the 8502's P6 low while down.
+      def press_caps_lock
+        @bus.caps_lock = true
+      end
+
+      def release_caps_lock
+        @bus.caps_lock = false
+      end
+
+      # The 40/80 DISPLAY key locks down and up. The KERNAL reads it at reset
+      # and starts the screen editor on the VDC's 80 columns while it is down.
+      def press_display_key
+        @bus.mmu.display_key = true
+      end
+
+      def release_display_key
+        @bus.mmu.display_key = false
+      end
+    end
+  end
+end

data/lib/badline/c128/mmu.rb

@@ -0,0 +1,182 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The 8722 MMU's registers, $D500-$D50B in C128 mode:
+    #
+    #   $D500 CR: I/O, the ROMs and the RAM bank the CPU sees
+    #   $D501-$D504 PCRA-PCRD: preset configurations
+    #   $D505 MCR: the CPU (bit 0, 1 for the 8502), FSDIR, GAME and EXROM
+    #         in, C64 mode (bit 6) and the 40/80 key
+    #   $D506 RCR: common RAM and the VIC's RAM bank
+    #   $D507-$D50A P0L, P0H, P1L, P1H: page 0 and page 1 relocation
+    #   $D50B VR: the version, 2 banks of version 0
+    #
+    # The rest of the page reads $FF. $FF00 is CR again, and a write to
+    # $FF01-$FF04, the LCRs, copies PCRA-PCRD into CR. Those five answer in
+    # every configuration, whatever CR maps there.
+    #
+    # A write to P0H or P1H waits until the matching P0L or P1L write
+    # takes it.
+    #
+    # On the C128 the Z80 runs first and hands the bus to the 8502. Here the
+    # 8502 runs from reset, with MCR as the Z80 leaves it. A machine built
+    # for C64 mode resets into C64 mode, the state the C128 KERNAL leaves
+    # when C= is held at power-on. In C64 mode the MMU answers nowhere, but
+    # the CPU's RAM bank, common RAM and the VIC's bank it holds stay in
+    # force.
+    class MMU
+      CR = 0
+      MCR = 5
+      RCR = 6
+      P0L = 7
+      P0H = 8
+      P1L = 9
+      P1H = 10
+      VR = 11
+
+      MCR_8502 = 0x01
+      MCR_C64_MODE = 0x40
+      VERSION = 0x20
+
+      # MCR's bits that read back what was written: the CPU, FSDIR and C64
+      # mode. Bits 1 and 2 have no pins and read 1.
+      MCR_WRITABLE = 0x49
+      MCR_UNUSED = 0x06
+      MCR_GAME = 0x10
+      MCR_EXROM = 0x20
+      MCR_DISPLAY_KEY = 0x80
+
+      # The common RAM sizes RCR bits 0-1 pick, in pages.
+      COMMON_PAGES = [4, 16, 32, 64].freeze
+
+      # The registers, CR first.
+      attr_reader :registers
+
+      # Whether the 40/80 DISPLAY key is locked down, which MCR bit 7 reads
+      # as 0 in C128 mode.
+      attr_accessor :display_key
+
+      # The cartridge's GAME and EXROM lines, which MCR bits 4 and 5 read.
+      attr_writer :game, :exrom
+
+      # +mode+ is the mode a reset leaves, :c128 or :c64.
+      def initialize(mode = :c64)
+        @reset_mode = mode
+        @registers = Array.new(12, 0)
+        @display_key = false
+        @game = 1
+        @exrom = 1
+        @on_change = nil
+        reset!
+      end
+
+      # Calls the block whenever the mapping the registers ask for changes.
+      def on_change(&block)
+        @on_change = block
+      end
+
+      def reset!
+        @registers.fill(0)
+        @registers[MCR] = @reset_mode == :c64 ? MCR_C64_MODE | MCR_8502 : MCR_8502
+        @registers[P1L] = 0x01
+        @registers[VR] = VERSION
+        @p0h_latch = 0
+        @p1h_latch = 0
+        @on_change&.call
+      end
+
+      def c64_mode? = @registers[MCR].anybits?(MCR_C64_MODE)
+
+      # :c64 or :c128, the mode MCR bit 6 selects.
+      def mode = c64_mode? ? :c64 : :c128
+
+      # The 64K bank the VIC sees, RCR bit 6. Bit 7 picks banks a 256K
+      # machine has.
+      def vic_bank = (@registers[RCR] >> 6) & 0x01
+
+      # The RAM bank the CPU sees, CR bit 6.
+      def cpu_bank = (@registers[CR] >> 6) & 0x01
+
+      def cr = @registers[CR]
+
+      # The pages from $0000 up that common RAM keeps in bank 0, or 0.
+      def common_low_pages = @registers[RCR].anybits?(0x04) ? common_pages : 0
+
+      # The first page of the common RAM below $FFFF, or 256 for none.
+      def common_high_start = @registers[RCR].anybits?(0x08) ? 256 - common_pages : 256
+
+      # The page and the bank page 0 moves to.
+      def p0_page = @registers[P0L]
+      def p0_bank = @registers[P0H] & 0x01
+
+      # The page and the bank page 1 moves to.
+      def p1_page = @registers[P1L]
+      def p1_bank = @registers[P1H] & 0x01
+
+      # The registers at $D500-$D5FF.
+      def peek(addr)
+        offset = addr & 0xff
+        case offset
+        when MCR then mcr
+        when P0H, P1H then 0xf0 | @registers[offset]
+        when 0..VR then @registers[offset]
+        else 0xff
+        end
+      end
+
+      def poke(addr, value)
+        offset = addr & 0xff
+        case offset
+        when P0H then @p0h_latch = value & 0x0f
+        when P1H then @p1h_latch = value & 0x0f
+        when P0L then relocate(P0L, P0H, @p0h_latch, value)
+        when P1L then relocate(P1L, P1H, @p1h_latch, value)
+        when CR..RCR then write(offset, value)
+        end
+      end
+
+      # The registers and the P0H and P1H writes waiting for P0L and P1L.
+      # The bus maps the restored registers once its own state is back.
+      def save_state(out)
+        out.ints(@registers).int(@p0h_latch).int(@p1h_latch)
+      end
+
+      def load_state(input)
+        input.ints_into(@registers)
+        @p0h_latch = input.int
+        @p1h_latch = input.int
+      end
+
+      # CR and the LCRs at $FF00-$FF04: an LCR reads its PCR.
+      def peek_configuration(addr) = @registers[addr & 0x07]
+
+      def poke_configuration(addr, value)
+        offset = addr & 0x07
+        write(CR, offset.zero? ? value : @registers[offset])
+      end
+
+      private
+
+      def common_pages = COMMON_PAGES[@registers[RCR] & 0x03]
+
+      def mcr
+        value = (@registers[MCR] & MCR_WRITABLE) | MCR_UNUSED
+        value |= MCR_GAME if @game == 1
+        value |= MCR_EXROM if @exrom == 1
+        value |= MCR_DISPLAY_KEY unless @display_key
+        value
+      end
+
+      def relocate(low, high, latch, value)
+        @registers[high] = latch
+        write(low, value)
+      end
+
+      def write(offset, value)
+        @registers[offset] = value
+        @on_change&.call
+      end
+    end
+  end
+end