axi_tdl 0.2.5 → 0.2.7

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (1713) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +3 -3
  3. data/.github/workflows/ruby.yml +1 -1
  4. data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +0 -0
  5. data/lib/axi/AXI4/axi4_direct.sv +0 -0
  6. data/lib/axi/AXI4/axi4_direct_A1.sv +0 -0
  7. data/lib/axi/AXI4/axi4_direct_B1.sv +0 -0
  8. data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv +0 -0
  9. data/lib/axi/AXI4/axi4_direct_verb.sv +0 -0
  10. data/lib/axi/AXI4/axi4_direct_verc.sv +0 -0
  11. data/lib/axi/AXI4/axi4_dpram_cache.rb +0 -0
  12. data/lib/axi/AXI4/axi4_dpram_cache.sv +0 -0
  13. data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +0 -0
  14. data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +0 -0
  15. data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +2 -1
  16. data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +0 -0
  17. data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +0 -0
  18. data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +0 -0
  19. data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +0 -0
  20. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +0 -0
  21. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +0 -0
  22. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +0 -0
  23. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +0 -0
  24. data/lib/axi/AXI4/axi4_ram_cache.rb +0 -0
  25. data/lib/axi/AXI4/axi4_ram_cache.sv +0 -0
  26. data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +0 -0
  27. data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +0 -0
  28. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +0 -0
  29. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +0 -0
  30. data/lib/axi/AXI4/axi4_rd_burst_track.sv +0 -0
  31. data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +0 -0
  32. data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +0 -0
  33. data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +0 -0
  34. data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +0 -0
  35. data/lib/axi/AXI4/axi4_wr_burst_track.sv +0 -0
  36. data/lib/axi/AXI4/axi_stream_add_addr_len.sv +0 -0
  37. data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +54 -8
  38. data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +0 -0
  39. data/lib/axi/AXI4/axis_to_axi4_wr.rb +0 -0
  40. data/lib/axi/AXI4/axis_to_axi4_wr.sv +0 -0
  41. data/lib/axi/AXI4/full_axi4_to_axis.sv +0 -0
  42. data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +0 -0
  43. data/lib/axi/AXI4/id_record.sv +0 -0
  44. data/lib/axi/AXI4/idata_pool_axi4.sv +0 -0
  45. data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +0 -0
  46. data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +0 -0
  47. data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +0 -0
  48. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +0 -0
  49. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +0 -0
  50. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +0 -0
  51. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +0 -0
  52. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +0 -0
  53. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +0 -0
  54. data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +0 -0
  55. data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +0 -0
  56. data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +0 -0
  57. data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +1 -1
  58. data/lib/axi/AXI4/odata_pool_axi4.sv +0 -0
  59. data/lib/axi/AXI4/odata_pool_axi4_A1.sv +0 -0
  60. data/lib/axi/AXI4/odata_pool_axi4_A2.sv +0 -0
  61. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +0 -0
  62. data/lib/axi/AXI4/odata_pool_axi4_A4.sv +0 -0
  63. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +0 -0
  64. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +0 -0
  65. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv +0 -0
  66. data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +0 -0
  67. data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +0 -0
  68. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +0 -0
  69. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +12 -4
  70. data/lib/axi/AXI4/packet_merge/axi4_merge.sv +0 -0
  71. data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +0 -0
  72. data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +0 -0
  73. data/lib/axi/AXI4/packet_partition/axi4_partition.sv +0 -0
  74. data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +3 -2
  75. data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +0 -0
  76. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +0 -0
  77. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +16 -7
  78. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +13 -9
  79. data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +0 -0
  80. data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +11 -10
  81. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +0 -0
  82. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
  83. data/lib/axi/AXI4/packet_partition/data_inf_partition_A1.rb +298 -0
  84. data/lib/axi/AXI4/packet_partition/data_inf_partition_A1.sv +316 -0
  85. data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +0 -0
  86. data/lib/axi/AXI4/vcs_axi4_comptable.sv +0 -0
  87. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +0 -0
  88. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb.bk +150 -0
  89. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +2 -2
  90. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +0 -0
  91. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +0 -0
  92. data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +0 -0
  93. data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +0 -0
  94. data/lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv +0 -0
  95. data/lib/axi/AXI4/width_convert/data_combin.sv +0 -0
  96. data/lib/axi/AXI4/width_convert/data_combin.sv.bak +0 -0
  97. data/lib/axi/AXI4/width_convert/data_destruct.sv +0 -0
  98. data/lib/axi/AXI4/width_convert/feed_check.sv +0 -0
  99. data/lib/axi/AXI4/width_convert/len_convert.sv.bak +0 -0
  100. data/lib/axi/AXI4/width_convert/odd_width_convert.sv +0 -0
  101. data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +0 -0
  102. data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +0 -0
  103. data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +0 -0
  104. data/lib/axi/AXI4/width_convert/width_combin.sv +0 -0
  105. data/lib/axi/AXI4/width_convert/width_convert.sv +0 -0
  106. data/lib/axi/AXI4/width_convert/width_convert_verb.sv +0 -0
  107. data/lib/axi/AXI4/width_convert/width_destruct.sv +0 -0
  108. data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +0 -0
  109. data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +0 -0
  110. data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +0 -0
  111. data/lib/axi/AXI_BFM/axi4_error_chk.sv +0 -0
  112. data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +0 -0
  113. data/lib/axi/AXI_BFM/axi_lite_master.sv +0 -0
  114. data/lib/axi/AXI_BFM/axi_lite_tb.sv +0 -0
  115. data/lib/axi/AXI_BFM/axi_master.sv +0 -0
  116. data/lib/axi/AXI_BFM/axi_mirror.sv +0 -0
  117. data/lib/axi/AXI_BFM/axi_mm_tb.sv +0 -0
  118. data/lib/axi/AXI_BFM/axi_slaver.sv.bak +0 -0
  119. data/lib/axi/AXI_BFM/axistreambfm.sv +0 -0
  120. data/lib/axi/AXI_Lite/axi4_to_lite.sv +0 -0
  121. data/lib/axi/AXI_Lite/axi_lite_configure.sv +0 -0
  122. data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +0 -0
  123. data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +0 -0
  124. data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +0 -0
  125. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +4 -5
  126. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +0 -0
  127. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M_verb.sv +322 -0
  128. data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +0 -0
  129. data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +0 -0
  130. data/lib/axi/AXI_Lite/axil_direct.sv +0 -0
  131. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +0 -0
  132. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +0 -0
  133. data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +0 -0
  134. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +0 -0
  135. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +0 -0
  136. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +0 -0
  137. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +0 -0
  138. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +0 -0
  139. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +0 -0
  140. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +0 -0
  141. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +0 -0
  142. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +0 -0
  143. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +0 -0
  144. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv +0 -0
  145. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +0 -0
  146. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +0 -0
  147. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +0 -0
  148. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +26 -5
  149. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +0 -0
  150. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +0 -0
  151. data/lib/axi/AXI_stream/axi_stream_latency.sv +0 -0
  152. data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +0 -0
  153. data/lib/axi/AXI_stream/axi_stream_partition.sv +0 -0
  154. data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +0 -0
  155. data/lib/axi/AXI_stream/axi_stream_planer.sv +0 -0
  156. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +0 -0
  157. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +26 -26
  158. data/lib/axi/AXI_stream/axi_streams_combin.sv +0 -0
  159. data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +0 -0
  160. data/lib/axi/AXI_stream/axi_streams_scaler.sv +0 -0
  161. data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +0 -0
  162. data/lib/axi/AXI_stream/axis_append.sv +0 -0
  163. data/lib/axi/AXI_stream/axis_append_A1.sv +0 -0
  164. data/lib/axi/AXI_stream/axis_base_pipe.sv +0 -0
  165. data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +0 -0
  166. data/lib/axi/AXI_stream/axis_connect_pipe.sv +0 -0
  167. data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +0 -0
  168. data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +0 -0
  169. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +0 -0
  170. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +0 -0
  171. data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +0 -0
  172. data/lib/axi/AXI_stream/axis_direct.sv +0 -0
  173. data/lib/axi/AXI_stream/axis_direct_A1.sv +0 -0
  174. data/lib/axi/AXI_stream/axis_ex_status.sv +97 -0
  175. data/lib/axi/AXI_stream/axis_ex_status.sv.bk +97 -0
  176. data/lib/axi/AXI_stream/axis_filter.sv +0 -0
  177. data/lib/axi/AXI_stream/axis_full_to_data_c.sv +0 -0
  178. data/lib/axi/AXI_stream/axis_head_cut.sv +0 -0
  179. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +0 -0
  180. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +0 -0
  181. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +6 -6
  182. data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +0 -0
  183. data/lib/axi/AXI_stream/axis_insert_copy.rb +0 -0
  184. data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -0
  185. data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +0 -0
  186. data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +0 -0
  187. data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +0 -0
  188. data/lib/axi/AXI_stream/axis_length_cut.sv +1 -1
  189. data/lib/axi/AXI_stream/axis_length_fill.sv +0 -0
  190. data/lib/axi/AXI_stream/axis_length_fill_verb.sv +195 -0
  191. data/lib/axi/AXI_stream/axis_length_split.sv +0 -0
  192. data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +0 -0
  193. data/lib/axi/AXI_stream/axis_length_split_with_addr_A1.sv +128 -0
  194. data/lib/axi/AXI_stream/axis_length_split_with_user.sv +0 -0
  195. data/lib/axi/AXI_stream/axis_link_trigger.sv +0 -0
  196. data/lib/axi/AXI_stream/axis_master_empty.sv +0 -0
  197. data/lib/axi/AXI_stream/axis_mirror_to_master.sv +0 -0
  198. data/lib/axi/AXI_stream/axis_mirror_to_master_verb.sv +141 -0
  199. data/lib/axi/AXI_stream/axis_mirrors.sv +0 -0
  200. data/lib/axi/AXI_stream/axis_orthogonal.sv +0 -0
  201. data/lib/axi/AXI_stream/axis_padding.rb +44 -0
  202. data/lib/axi/AXI_stream/axis_padding.sv +65 -0
  203. data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +0 -0
  204. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -0
  205. data/lib/axi/AXI_stream/axis_ram_buffer.sv +0 -0
  206. data/lib/axi/AXI_stream/axis_rom_contect.rb +0 -0
  207. data/lib/axi/AXI_stream/axis_rom_contect.sv +0 -0
  208. data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +0 -0
  209. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -0
  210. data/lib/axi/AXI_stream/axis_sim_master_model.rb +0 -0
  211. data/lib/axi/AXI_stream/axis_sim_master_model.sv +0 -0
  212. data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +0 -0
  213. data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +0 -0
  214. data/lib/axi/AXI_stream/axis_slaver_empty.sv +0 -0
  215. data/lib/axi/AXI_stream/axis_slaver_pipe.sv +0 -0
  216. data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +0 -0
  217. data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +0 -0
  218. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +0 -0
  219. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +3 -3
  220. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +0 -0
  221. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +0 -0
  222. data/lib/axi/AXI_stream/axis_to_data_inf.sv +0 -0
  223. data/lib/axi/AXI_stream/axis_to_lite_rd.sv +0 -0
  224. data/lib/axi/AXI_stream/axis_to_lite_wr.sv +0 -0
  225. data/lib/axi/AXI_stream/axis_uncompress.sv +0 -0
  226. data/lib/axi/AXI_stream/axis_uncompress_A1.sv +0 -0
  227. data/lib/axi/AXI_stream/axis_uncompress_verb.rb +0 -0
  228. data/lib/axi/AXI_stream/axis_uncompress_verb.sv +0 -0
  229. data/lib/axi/AXI_stream/axis_valve.sv +0 -0
  230. data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +0 -0
  231. data/lib/axi/AXI_stream/axis_vector_master_empty.rb +0 -0
  232. data/lib/axi/AXI_stream/axis_vector_master_empty.sv +0 -0
  233. data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +0 -0
  234. data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +0 -0
  235. data/lib/axi/AXI_stream/check_stream_crc.sv +0 -0
  236. data/lib/axi/AXI_stream/data_c_to_axis_full.sv +0 -0
  237. data/lib/axi/AXI_stream/data_to_axis_inf.sv +0 -0
  238. data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +0 -0
  239. data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +0 -0
  240. data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +0 -0
  241. data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +0 -0
  242. data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +0 -0
  243. data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +0 -0
  244. data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +0 -0
  245. data/lib/axi/AXI_stream/gen_big_field_table.sv +0 -0
  246. data/lib/axi/AXI_stream/gen_common_frame_table.sv +0 -0
  247. data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +0 -0
  248. data/lib/axi/AXI_stream/gen_origin_axis.sv +0 -0
  249. data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +0 -0
  250. data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +0 -0
  251. data/lib/axi/AXI_stream/gen_origin_axis_A3.sv +0 -0
  252. data/lib/axi/AXI_stream/gen_simple_axis.sv +0 -0
  253. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +8 -5
  254. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +9 -7
  255. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +0 -0
  256. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +0 -0
  257. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +0 -0
  258. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +0 -0
  259. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +0 -0
  260. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +0 -0
  261. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +5 -4
  262. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo_A1.sv +221 -0
  263. data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +0 -0
  264. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +0 -0
  265. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep_A1.sv +0 -0
  266. data/lib/axi/AXI_stream/parse_big_field_table.sv +0 -0
  267. data/lib/axi/AXI_stream/parse_big_field_table_A1.sv +0 -0
  268. data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +0 -0
  269. data/lib/axi/AXI_stream/parse_big_field_table_main.sv +0 -0
  270. data/lib/axi/AXI_stream/parse_big_field_table_mirror.sv +0 -0
  271. data/lib/axi/AXI_stream/parse_big_field_table_slaver.sv +162 -0
  272. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +0 -0
  273. data/lib/axi/AXI_stream/parse_common_frame_table.sv +0 -0
  274. data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv +0 -0
  275. data/lib/axi/AXI_stream/parse_common_frame_table_A2.sv +0 -0
  276. data/lib/axi/AXI_stream/parse_common_frame_table_slaver.sv +546 -0
  277. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache.sv +0 -0
  278. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_35bit.sv +0 -0
  279. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_36_71bit.sv +1 -1
  280. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit.sv +0 -0
  281. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit_with_keep.sv +0 -0
  282. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_96_143bit.sv +0 -0
  283. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_A1.sv +0 -0
  284. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_B1.sv +0 -0
  285. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_compact_verb.sv +58 -0
  286. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +0 -0
  287. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_verb.sv +0 -0
  288. data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +0 -0
  289. data/lib/axi/AXI_stream/stream_crc.sv +0 -0
  290. data/lib/axi/AXI_stream/vcs_axis_comptable.sv +0 -0
  291. data/lib/axi/LICENSE +0 -0
  292. data/lib/axi/ReadME.md +0 -0
  293. data/lib/axi/SIM/tb_axi4_partition_20201105.sv +0 -0
  294. data/lib/axi/SIM/tb_axis_bfm_0504.sv +0 -0
  295. data/lib/axi/SIM/tb_axis_partitiom_0929.sv +0 -0
  296. data/lib/axi/SIM/tb_axis_s2m_pipe_1023.sv +0 -0
  297. data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +0 -0
  298. data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +0 -0
  299. data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +0 -0
  300. data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +0 -0
  301. data/lib/axi/SIM/tb_wide_axis_to_axi4_wr.sv +0 -0
  302. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip.sv +0 -0
  303. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C1.sv +0 -0
  304. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv +0 -0
  305. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verb.sv +0 -0
  306. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verc.sv +0 -0
  307. data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv +0 -0
  308. data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_wrapper_sim.sv +0 -0
  309. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_axi4_to_axis.sv +0 -0
  310. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo.sv +0 -0
  311. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A1.sv +0 -0
  312. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv +0 -0
  313. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv +0 -0
  314. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_verb.sv +0 -0
  315. data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +0 -0
  316. data/lib/axi/axi4_to_xilinx_ddr_native/tb_ddr3_ip_wrapper_sim.sv +0 -0
  317. data/lib/axi/cfg.yml +0 -0
  318. data/lib/axi/common/ClockSameDomain.sv +0 -0
  319. data/lib/axi/common/common_ram_sim_wrapper.rb +0 -0
  320. data/lib/axi/common/common_ram_sim_wrapper.sv +0 -0
  321. data/lib/axi/common/common_ram_wrapper.rb +0 -0
  322. data/lib/axi/common/common_ram_wrapper.sv +2 -2
  323. data/lib/axi/common/data_c_interface_dram.rb +0 -0
  324. data/lib/axi/common/data_c_interface_dram.sv +0 -0
  325. data/lib/axi/common/mem_format.coe +0 -0
  326. data/lib/axi/common/pipe_vld.sv +0 -0
  327. data/lib/axi/common/test_write_mem.sv +0 -0
  328. data/lib/axi/common/xilinx_hdl_dpram.sv +0 -0
  329. data/lib/axi/common/xilinx_hdl_dpram_sim.sv +0 -0
  330. data/lib/axi/common_fifo/common_fifo.sv +2 -1
  331. data/lib/axi/common_fifo/common_stack.sv +0 -0
  332. data/lib/axi/common_fifo/independent_clock_fifo.sv +0 -0
  333. data/lib/axi/common_fifo/independent_clock_fifo_a1.sv +0 -0
  334. data/lib/axi/common_fifo/independent_stack.sv +0 -0
  335. data/lib/axi/data_interface/data_connect_pipe.sv +0 -0
  336. data/lib/axi/data_interface/data_inf_A2B.sv +0 -0
  337. data/lib/axi/data_interface/data_inf_B2A.sv +0 -0
  338. data/lib/axi/data_interface/data_inf_c/data_bind.sv +0 -0
  339. data/lib/axi/data_interface/data_inf_c/data_c_cache.sv +0 -0
  340. data/lib/axi/data_interface/data_inf_c/data_c_direct.sv +0 -0
  341. data/lib/axi/data_interface/data_inf_c/data_c_direct_mirror.sv +0 -0
  342. data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.rb.bak +0 -0
  343. data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.sv +0 -0
  344. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld.sv +0 -0
  345. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +0 -0
  346. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv +0 -0
  347. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_A1.sv +0 -0
  348. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_left_shift.sv +0 -0
  349. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift.sv +0 -0
  350. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift_verb.sv +0 -0
  351. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1.sv +0 -0
  352. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1_with_id.sv +0 -0
  353. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_last.sv +0 -0
  354. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv +0 -0
  355. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin.sv +0 -0
  356. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin_with_id.sv +0 -0
  357. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc.sv +0 -0
  358. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv +0 -0
  359. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv +0 -0
  360. data/lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv +0 -0
  361. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv +0 -0
  362. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb +0 -0
  363. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
  364. data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +0 -0
  365. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +0 -0
  366. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +0 -0
  367. data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +0 -0
  368. data/lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv +0 -0
  369. data/lib/axi/data_interface/data_inf_c/data_condition_mirror.sv +0 -0
  370. data/lib/axi/data_interface/data_inf_c/data_condition_valve.sv +0 -0
  371. data/lib/axi/data_interface/data_inf_c/data_connect_pipe_inf.sv +0 -0
  372. data/lib/axi/data_interface/data_inf_c/data_inf_c_M2S_with_addr_and_id.sv +0 -0
  373. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_M2S_with_id.sv +0 -0
  374. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv +0 -0
  375. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_A1.sv +0 -0
  376. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_with_lazy.sv +0 -0
  377. data/lib/axi/data_interface/data_inf_c/data_inf_c_interconnect_M2S.sv +0 -0
  378. data/lib/axi/data_interface/data_inf_c/data_inf_c_pipe_condition.sv +0 -0
  379. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer.sv +0 -0
  380. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv +0 -0
  381. data/lib/axi/data_interface/data_inf_c/data_intc_M2S_force_robin.sv +0 -0
  382. data/lib/axi/data_interface/data_inf_c/data_mirrors.sv +0 -0
  383. data/lib/axi/data_interface/data_inf_c/data_mirrors_verb.sv.bak +0 -0
  384. data/lib/axi/data_interface/data_inf_c/data_uncompress.sv +0 -0
  385. data/lib/axi/data_interface/data_inf_c/data_valve.sv +0 -0
  386. data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +0 -0
  387. data/lib/axi/data_interface/data_inf_c/next_prio.sv +0 -0
  388. data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv +0 -0
  389. data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c_A1.sv +0 -0
  390. data/lib/axi/data_interface/data_inf_c/trigger_ready_ctrl.sv +0 -0
  391. data/lib/axi/data_interface/data_inf_c/vcs_data_c_comptable.sv +0 -0
  392. data/lib/axi/data_interface/data_inf_cross_clk.sv +0 -0
  393. data/lib/axi/data_interface/data_inf_intc_M2S_force_addr_with_id.sv +0 -0
  394. data/lib/axi/data_interface/data_inf_intc_M2S_prio.sv +0 -0
  395. data/lib/axi/data_interface/data_inf_intc_M2S_prio_with_id.sv +0 -0
  396. data/lib/axi/data_interface/data_inf_interconnect_M2S_noaddr.sv +0 -0
  397. data/lib/axi/data_interface/data_inf_interconnect_M2S_with_id_noaddr.sv +0 -0
  398. data/lib/axi/data_interface/data_inf_planer.sv +0 -0
  399. data/lib/axi/data_interface/data_inf_planer_A1.sv +0 -0
  400. data/lib/axi/data_interface/data_inf_ticktock.sv +0 -0
  401. data/lib/axi/data_interface/data_interface.sv +0 -0
  402. data/lib/axi/data_interface/data_interface_pkg.sv +0 -0
  403. data/lib/axi/data_interface/data_pair_map.sv +0 -0
  404. data/lib/axi/data_interface/data_pair_map_A1.sv +0 -0
  405. data/lib/axi/data_interface/data_pair_map_A2.sv +0 -0
  406. data/lib/axi/data_interface/data_pipe_intc_M2S_addr.sv.bak +0 -0
  407. data/lib/axi/data_interface/data_pipe_interconnect.sv +0 -0
  408. data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv +0 -0
  409. data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv.bak1012 +0 -0
  410. data/lib/axi/data_interface/data_pipe_interconnect_M2S_A1.sv +0 -0
  411. data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv +0 -0
  412. data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv.bad_work +0 -0
  413. data/lib/axi/data_interface/data_pipe_interconnect_S2M.sv +0 -0
  414. data/lib/axi/data_interface/data_pipe_interconnect_S2M_A1.sv +0 -0
  415. data/lib/axi/data_interface/data_pipe_interconnect_S2M_verb.sv +0 -0
  416. data/lib/axi/data_interface/data_streams_combin.sv +0 -0
  417. data/lib/axi/data_interface/data_streams_combin_A1.sv +0 -0
  418. data/lib/axi/data_interface/data_streams_scaler.sv +0 -0
  419. data/lib/axi/data_interface/datainf_c_master_empty.sv +0 -0
  420. data/lib/axi/data_interface/datainf_c_slaver_empty.sv +0 -0
  421. data/lib/axi/data_interface/datainf_master_empty.sv +0 -0
  422. data/lib/axi/data_interface/datainf_slaver_empty.sv +0 -0
  423. data/lib/axi/data_interface/part_data_pair_map.sv +0 -0
  424. data/lib/axi/interface_define/axi_aux_inf.sv +0 -0
  425. data/lib/axi/interface_define/axi_inf.sv +0 -0
  426. data/lib/axi/interface_define/axi_inf_verb.sv +0 -0
  427. data/lib/axi/interface_define/axi_interface_instance.svo +0 -0
  428. data/lib/axi/interface_define/axi_lite_inf.sv +0 -0
  429. data/lib/axi/interface_define/axi_stream_inf.sv +0 -0
  430. data/lib/axi/interface_define/bak/axi_aux_inf.sv +0 -0
  431. data/lib/axi/interface_define/bak/axi_inf_verb.sv +0 -0
  432. data/lib/axi/interface_define/bak/axi_interface_instance.svo +0 -0
  433. data/lib/axi/interface_define/bak/microblaze_inf.sv +0 -0
  434. data/lib/axi/interface_define/bak/xilinx_axi4_to_axi4.sv +0 -0
  435. data/lib/axi/interface_define/bak/xilinx_lite_to_lite.sv +0 -0
  436. data/lib/axi/interface_define/lite_inf2_to_inf.sv +0 -0
  437. data/lib/axi/interface_define/xilinx_axi4_to_axi4.sv +0 -0
  438. data/lib/axi/interface_define/xilinx_lite_to_lite.sv +0 -0
  439. data/lib/axi/macro/RTL/define_macro.sv +0 -0
  440. data/lib/axi/macro/SIM/define_macro.sv +0 -0
  441. data/lib/axi/macro/axil_macro.sv +0 -0
  442. data/lib/axi/macro/bak/axi4_base_files_add_to_vivado.tcl +0 -0
  443. data/lib/axi/macro/bak/axi_macro.sv +0 -0
  444. data/lib/axi/macro/bak/axis_base_files_add_to_vivado.tcl +0 -0
  445. data/lib/axi/macro/bak/base_files_add_to_vivado.tcl +0 -0
  446. data/lib/axi/macro/bak/data_inf_base_files_add_to_vivado.tcl +0 -0
  447. data/lib/axi/macro/bak/lite_inf_base_files_add_to_vivado.tcl +0 -0
  448. data/lib/axi/macro/bak/standard_tcl.rb +0 -0
  449. data/lib/axi/macro/bak/system_macro.sv +0 -0
  450. data/lib/axi/macro/bak/tcl_axi4_base_files_add_to_vivado.tcl +0 -0
  451. data/lib/axi/macro/bak/tcl_axis_base_files_add_to_vivado.tcl +0 -0
  452. data/lib/axi/macro/bak/tcl_base_files_add_to_vivado.tcl +0 -0
  453. data/lib/axi/macro/bak/tcl_data_inf_base_files_add_to_vivado.tcl +0 -0
  454. data/lib/axi/macro/bak/tcl_lite_inf_base_files_add_to_vivado.tcl +0 -0
  455. data/lib/axi/macro/bak/tcl_tmp.tcl +0 -0
  456. data/lib/axi/macro/bak/tmp.tcl +0 -0
  457. data/lib/axi/platform_ip/fifo_10_18bit_long.sv +0 -0
  458. data/lib/axi/platform_ip/fifo_145_216bit_A1.sv +0 -0
  459. data/lib/axi/platform_ip/fifo_217_288bit_A1.sv +0 -0
  460. data/lib/axi/platform_ip/fifo_36bit.sv +0 -0
  461. data/lib/axi/platform_ip/fifo_36bit_A1.sv +0 -0
  462. data/lib/axi/platform_ip/fifo_36kb_long.sv +11 -5
  463. data/lib/axi/platform_ip/fifo_37_72bit.sv +0 -0
  464. data/lib/axi/platform_ip/fifo_505_576bit_A1.sv +0 -0
  465. data/lib/axi/platform_ip/fifo_73_96bit.sv +0 -0
  466. data/lib/axi/platform_ip/fifo_97_144bit.sv +0 -0
  467. data/lib/axi/platform_ip/fifo_97_144bit_A1.sv +0 -0
  468. data/lib/axi/platform_ip/fifo_ku.sv +0 -0
  469. data/lib/axi/platform_ip/fifo_ku.sv.bak +0 -0
  470. data/lib/axi/platform_ip/fifo_ku_18bit.sv +0 -0
  471. data/lib/axi/platform_ip/fifo_ku_36bit.sv +0 -0
  472. data/lib/axi/platform_ip/fifo_ku_36kb_long.sv +0 -0
  473. data/lib/axi/platform_ip/fifo_ku_xbit_8192.sv.bak +0 -0
  474. data/lib/axi/platform_ip/fifo_wr_rd_mark.sv +0 -0
  475. data/lib/axi/platform_ip/ku_long_fifo_4bit.sv +0 -0
  476. data/lib/axi/platform_ip/long_fifo.sv +0 -0
  477. data/lib/axi/platform_ip/long_fifo_4bit.sv +0 -0
  478. data/lib/axi/platform_ip/long_fifo_4bit_8192.sv +0 -0
  479. data/lib/axi/platform_ip/long_fifo_4bit_SL8192.sv +0 -0
  480. data/lib/axi/platform_ip/long_fifo_9bit_SL4096.sv.new +138 -0
  481. data/lib/axi/platform_ip/long_fifo_verb.sv +0 -0
  482. data/lib/axi/platform_ip/long_fifo_xbit.sv.new +132 -0
  483. data/lib/axi/platform_ip/long_fifo_xbit_SL.sv.new +147 -0
  484. data/lib/axi/platform_ip/wide_fifo.sv +0 -0
  485. data/lib/axi/platform_ip/wide_fifo_7series.sv +0 -0
  486. data/lib/axi/platform_ip/xilinx_fifo.sv +0 -0
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  734. data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +0 -0
  735. data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +0 -0
  736. data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +0 -0
  737. data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +0 -0
  738. data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +0 -0
  739. data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +0 -0
  740. data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +0 -0
  741. data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +0 -0
  742. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +0 -0
  743. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +0 -0
  744. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +0 -0
  745. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +0 -0
  746. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +0 -0
  747. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +0 -0
  748. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +0 -0
  749. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +0 -0
  750. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +0 -0
  751. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +0 -0
  752. data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +0 -0
  753. data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +0 -0
  754. data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +0 -0
  755. data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +0 -0
  756. data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +0 -0
  757. data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +0 -0
  758. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +0 -0
  759. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +0 -0
  760. data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +0 -0
  761. data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +0 -0
  762. data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +0 -0
  763. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +0 -0
  764. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +0 -0
  765. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +0 -0
  766. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +0 -0
  767. data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +0 -0
  768. data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +0 -0
  769. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +0 -0
  770. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +0 -0
  771. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +0 -0
  772. data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +0 -0
  773. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +0 -0
  774. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +0 -0
  775. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +0 -0
  776. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +0 -0
  777. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +0 -0
  778. data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +0 -0
  779. data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +0 -0
  780. data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +0 -0
  781. data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +0 -0
  782. data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +0 -0
  783. data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +0 -0
  784. data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +0 -0
  785. data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +0 -0
  786. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +0 -0
  787. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +0 -0
  788. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +0 -0
  789. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +0 -0
  790. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +0 -0
  791. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +0 -0
  792. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +0 -0
  793. data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +0 -0
  794. data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +0 -0
  795. data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +0 -0
  796. data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +0 -0
  797. data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +0 -0
  798. data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +0 -0
  799. data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +0 -0
  800. data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +0 -0
  801. data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +0 -0
  802. data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +0 -0
  803. data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +0 -0
  804. data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +0 -0
  805. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +0 -0
  806. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +0 -0
  807. data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +0 -0
  808. data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +0 -0
  809. data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +0 -0
  810. data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +0 -0
  811. data/lib/tdl/SDL/fifo/common_stack_sdl.rb +0 -0
  812. data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +0 -0
  813. data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +0 -0
  814. data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +0 -0
  815. data/lib/tdl/SDL/path_lib.rb +0 -0
  816. data/lib/tdl/SDL/vcs_axi4_comptable.rb +0 -0
  817. data/lib/tdl/SDL/vcs_axis_comptable.rb +0 -0
  818. data/lib/tdl/SDL/vcs_data_c_comptable.rb +0 -0
  819. data/lib/tdl/VideoInf/simple_video_gen.rb +0 -0
  820. data/lib/tdl/VideoInf/video_from_axi4.rb +0 -0
  821. data/lib/tdl/VideoInf/video_lib.rb +0 -0
  822. data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +0 -0
  823. data/lib/tdl/VideoInf/video_to_axi4.rb +0 -0
  824. data/lib/tdl/auto_script/auto_gen_tdl.rb +0 -0
  825. data/lib/tdl/auto_script/autogensdl.rb +0 -0
  826. data/lib/tdl/auto_script/autogentdl_a2.rb +0 -0
  827. data/lib/tdl/auto_script/import_hdl.rb +0 -0
  828. data/lib/tdl/auto_script/import_sdl.rb +0 -0
  829. data/lib/tdl/auto_script/test_autogensdl.rb +0 -0
  830. data/lib/tdl/auto_script/tmp/MAC_FCS_sdl.rb +13 -0
  831. data/lib/tdl/auto_script/tmp/TPU_reprogram_wrapper_verb_sdl.rb +16 -0
  832. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_B1_sdl.rb +20 -0
  833. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_gray_sdl.rb +19 -0
  834. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_sdl.rb +19 -0
  835. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verb_sdl.rb +19 -0
  836. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_diffr_pca9557_sdl.rb +18 -0
  837. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_diffr_sdl.rb +19 -0
  838. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_sdl.rb +19 -0
  839. data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_x7_gray_sdl.rb +19 -0
  840. data/lib/tdl/auto_script/tmp/adc_1015_tpu_wrapper_sdl.rb +20 -0
  841. data/lib/tdl/auto_script/tmp/aec_alarm_check_A1_sdl.rb +14 -0
  842. data/lib/tdl/auto_script/tmp/aec_alarm_check_A2_sdl.rb +14 -0
  843. data/lib/tdl/auto_script/tmp/aec_alarm_check_A3_sdl.rb +14 -0
  844. data/lib/tdl/auto_script/tmp/aec_alarm_check_A4_sdl.rb +14 -0
  845. data/lib/tdl/auto_script/tmp/aec_alarm_check_A5_sdl.rb +14 -0
  846. data/lib/tdl/auto_script/tmp/aec_alarm_check_A6_sdl.rb +14 -0
  847. data/lib/tdl/auto_script/tmp/arp_tpu_wrapper_sdl.rb +16 -0
  848. data/lib/tdl/auto_script/tmp/axi4_combin_wr_rd_batch_sdl.rb +11 -0
  849. data/lib/tdl/auto_script/tmp/axi4_data_convert_verb_sdl.rb +12 -0
  850. data/lib/tdl/auto_script/tmp/axi4_direct_A1_sdl.rb +15 -0
  851. data/lib/tdl/auto_script/tmp/axi4_direct_B1_sdl.rb +10 -0
  852. data/lib/tdl/auto_script/tmp/axi4_direct_algin_addr_step_sdl.rb +20 -0
  853. data/lib/tdl/auto_script/tmp/axi4_direct_verc_sdl.rb +17 -0
  854. data/lib/tdl/auto_script/tmp/axi4_long_to_axi4_wide_B1_sdl.rb +16 -0
  855. data/lib/tdl/auto_script/tmp/axi4_packet_fifo_B1_sdl.rb +16 -0
  856. data/lib/tdl/auto_script/tmp/axi4_partition_OD_sdl.rb +13 -0
  857. data/lib/tdl/auto_script/tmp/axi4_partition_wr_OD_sdl.rb +12 -0
  858. data/lib/tdl/auto_script/tmp/axi4_ps_convert_sdl.rb +12 -0
  859. data/lib/tdl/auto_script/tmp/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +11 -0
  860. data/lib/tdl/auto_script/tmp/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +12 -0
  861. data/lib/tdl/auto_script/tmp/axi4_to_native_for_ddr_ip_C1_sdl.rb +24 -0
  862. data/lib/tdl/auto_script/tmp/axi4_wr_auxiliary_gen_sdl.rb +11 -0
  863. data/lib/tdl/auto_script/tmp/axi4_wr_auxiliary_gen_without_resp_sdl.rb +11 -0
  864. data/lib/tdl/auto_script/tmp/axi4_wr_interconnect_M2S_A1_sdl.rb +11 -0
  865. data/lib/tdl/auto_script/tmp/axi4_wr_pipe_sdl.rb +10 -0
  866. data/lib/tdl/auto_script/tmp/axi_stream_cache_35bit_sdl.rb +10 -0
  867. data/lib/tdl/auto_script/tmp/axi_stream_cache_36_71bit_sdl.rb +10 -0
  868. data/lib/tdl/auto_script/tmp/axi_stream_cache_A1_sdl.rb +11 -0
  869. data/lib/tdl/auto_script/tmp/axi_stream_cache_compact_verb_sdl.rb +10 -0
  870. data/lib/tdl/auto_script/tmp/axi_stream_cache_sdl.rb +10 -0
  871. data/lib/tdl/auto_script/tmp/axi_stream_cache_verb_sdl.rb +10 -0
  872. data/lib/tdl/auto_script/tmp/axi_stream_interconnect_M2S_A1_sdl.rb +12 -0
  873. data/lib/tdl/auto_script/tmp/axi_stream_interconnect_S2M_auto_sdl.rb +12 -0
  874. data/lib/tdl/auto_script/tmp/axi_stream_interconnect_S2M_sdl.rb +13 -0
  875. data/lib/tdl/auto_script/tmp/axi_stream_long_cache_sdl.rb +11 -0
  876. data/lib/tdl/auto_script/tmp/axi_stream_long_fifo_sdl.rb +12 -0
  877. data/lib/tdl/auto_script/tmp/axi_stream_long_fifo_verb_sdl.rb +12 -0
  878. data/lib/tdl/auto_script/tmp/axi_stream_packet_fifo_sdl.rb +11 -0
  879. data/lib/tdl/auto_script/tmp/axi_stream_packet_fifo_with_info_sdl.rb +14 -0
  880. data/lib/tdl/auto_script/tmp/axi_stream_packet_long_fifo_A1_sdl.rb +14 -0
  881. data/lib/tdl/auto_script/tmp/axi_stream_packet_long_fifo_sdl.rb +13 -0
  882. data/lib/tdl/auto_script/tmp/axi_stream_planer_sdl.rb +15 -0
  883. data/lib/tdl/auto_script/tmp/axi_stream_to_axi4_wr_sdl.rb +10 -0
  884. data/lib/tdl/auto_script/tmp/axi_stream_wide_fifo_sdl.rb +11 -0
  885. data/lib/tdl/auto_script/tmp/axi_streams_combin_A1_sdl.rb +16 -0
  886. data/lib/tdl/auto_script/tmp/axi_streams_scaler_A1_sdl.rb +15 -0
  887. data/lib/tdl/auto_script/tmp/axis_append_A1_sdl.rb +19 -0
  888. data/lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_sdl.rb +11 -0
  889. data/lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_verb_sdl.rb +13 -0
  890. data/lib/tdl/auto_script/tmp/axis_connect_pipe_sdl.rb +10 -0
  891. data/lib/tdl/auto_script/tmp/axis_connect_pipe_with_info_sdl.rb +13 -0
  892. data/lib/tdl/auto_script/tmp/axis_direct_A1_sdl.rb +12 -0
  893. data/lib/tdl/auto_script/tmp/axis_direct_sdl.rb +10 -0
  894. data/lib/tdl/auto_script/tmp/axis_ex_status_sdl.rb +13 -0
  895. data/lib/tdl/auto_script/tmp/axis_head_cut_sdl.rb +11 -0
  896. data/lib/tdl/auto_script/tmp/axis_head_cut_verb_sdl.rb +11 -0
  897. data/lib/tdl/auto_script/tmp/axis_intc_S2M_with_addr_inf_sdl.rb +13 -0
  898. data/lib/tdl/auto_script/tmp/axis_length_cut_sdl.rb +11 -0
  899. data/lib/tdl/auto_script/tmp/axis_length_fill_sdl.rb +11 -0
  900. data/lib/tdl/auto_script/tmp/axis_length_fill_verb_sdl.rb +13 -0
  901. data/lib/tdl/auto_script/tmp/axis_length_split_sdl.rb +11 -0
  902. data/lib/tdl/auto_script/tmp/axis_length_split_with_addr_sdl.rb +14 -0
  903. data/lib/tdl/auto_script/tmp/axis_length_split_with_user_sdl.rb +11 -0
  904. data/lib/tdl/auto_script/tmp/axis_master_empty_sdl.rb +9 -0
  905. data/lib/tdl/auto_script/tmp/axis_mirror_to_master_sdl.rb +11 -0
  906. data/lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_A1_sdl.rb +11 -0
  907. data/lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_sdl.rb +11 -0
  908. data/lib/tdl/auto_script/tmp/axis_slaver_empty_sdl.rb +9 -0
  909. data/lib/tdl/auto_script/tmp/axis_slaver_pipe_A1_sdl.rb +11 -0
  910. data/lib/tdl/auto_script/tmp/axis_slaver_pipe_sdl.rb +10 -0
  911. data/lib/tdl/auto_script/tmp/axis_uncompress_A1_sdl.rb +13 -0
  912. data/lib/tdl/auto_script/tmp/axis_uncompress_verb_sdl.rb +13 -0
  913. data/lib/tdl/auto_script/tmp/axis_valve_sdl.rb +11 -0
  914. data/lib/tdl/auto_script/tmp/axis_valve_with_pipe_sdl.rb +12 -0
  915. data/lib/tdl/auto_script/tmp/axis_width_convert_sdl.rb +10 -0
  916. data/lib/tdl/auto_script/tmp/axis_width_convert_verb_sdl.rb +12 -0
  917. data/lib/tdl/auto_script/tmp/axis_width_destruct_sdl.rb +10 -0
  918. data/lib/tdl/auto_script/tmp/board_cs_ctrl_gray_sdl.rb +14 -0
  919. data/lib/tdl/auto_script/tmp/board_cs_ctrl_gray_x7_sdl.rb +14 -0
  920. data/lib/tdl/auto_script/tmp/broaden_and_cross_clk_sdl.rb +17 -0
  921. data/lib/tdl/auto_script/tmp/cbct_chip_reg_dport_wrapper_sdl.rb +20 -0
  922. data/lib/tdl/auto_script/tmp/cbct_chip_reg_wrapper_sdl.rb +19 -0
  923. data/lib/tdl/auto_script/tmp/cbct_iic_bus_tri_wrapper_sdl.rb +18 -0
  924. data/lib/tdl/auto_script/tmp/cbct_iic_bus_wrapper_sdl.rb +14 -0
  925. data/lib/tdl/auto_script/tmp/cbct_lock_lvds_data_sdl.rb +16 -0
  926. data/lib/tdl/auto_script/tmp/cbct_sensor_driver_array_sdl.rb +12 -0
  927. data/lib/tdl/auto_script/tmp/cbct_sensor_driver_clock_A1_sdl.rb +13 -0
  928. data/lib/tdl/auto_script/tmp/cbct_sensor_driver_clock_sdl.rb +12 -0
  929. data/lib/tdl/auto_script/tmp/cbct_single_sensor_lvds_dir_sdl.rb +14 -0
  930. data/lib/tdl/auto_script/tmp/chip_reg_tpu_phase_upgrade_sdl.rb +25 -0
  931. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_gray_sdl.rb +24 -0
  932. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_sdl.rb +25 -0
  933. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_slot_gray_sdl.rb +24 -0
  934. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_speci_gray_sdl.rb +24 -0
  935. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_verb_sdl.rb +24 -0
  936. data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_x7_gray_sdl.rb +24 -0
  937. data/lib/tdl/auto_script/tmp/chip_spi_model_sdl.rb +12 -0
  938. data/lib/tdl/auto_script/tmp/clock_lvds_bitslip_sdl.rb +13 -0
  939. data/lib/tdl/auto_script/tmp/clock_manager_A2_sdl.rb +25 -0
  940. data/lib/tdl/auto_script/tmp/clock_manager_B2_sdl.rb +26 -0
  941. data/lib/tdl/auto_script/tmp/clock_manager_powerlow_sdl.rb +22 -0
  942. data/lib/tdl/auto_script/tmp/clock_manager_sdl.rb +16 -0
  943. data/lib/tdl/auto_script/tmp/clock_rst_verb_sdl.rb +14 -0
  944. data/lib/tdl/auto_script/tmp/clock_rst_verc_sdl.rb +15 -0
  945. data/lib/tdl/auto_script/tmp/cmos_redx_1xN_inner_clock_sdl.rb +33 -0
  946. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0004.coe +18 -0
  947. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0014.coe +18 -0
  948. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0017.coe +18 -0
  949. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0019.coe +18 -0
  950. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0023.coe +18 -0
  951. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0024.coe +18 -0
  952. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0025.coe +18 -0
  953. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0027.coe +18 -0
  954. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0030.coe +18 -0
  955. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0037.coe +18 -0
  956. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0038.coe +18 -0
  957. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0040.coe +18 -0
  958. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0041.coe +18 -0
  959. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0042.coe +18 -0
  960. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0043.coe +18 -0
  961. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0049.coe +18 -0
  962. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0052.coe +18 -0
  963. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0054.coe +18 -0
  964. data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0055.coe +18 -0
  965. data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_0_R0000.coe +9825 -0
  966. data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_1_R0001.coe +9720 -0
  967. data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_2_R0002.coe +9825 -0
  968. data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_3_R0003.coe +9825 -0
  969. data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_R0000.coe +26 -0
  970. data/lib/tdl/auto_script/tmp/coe_uart_tx_inf_R0000.coe +5025 -0
  971. data/lib/tdl/auto_script/tmp/common_axli_flow_sdl.rb +12 -0
  972. data/lib/tdl/auto_script/tmp/common_fifo_sdl.rb +22 -0
  973. data/lib/tdl/auto_script/tmp/common_redx_1xN_ddr_simple_sdl.rb +32 -0
  974. data/lib/tdl/auto_script/tmp/common_redx_1xN_sdr_serdes_simple_sdl.rb +31 -0
  975. data/lib/tdl/auto_script/tmp/common_redx_1xN_sdr_simple_sdl.rb +32 -0
  976. data/lib/tdl/auto_script/tmp/cross_clk_sync_sdl.rb +14 -0
  977. data/lib/tdl/auto_script/tmp/custom_serdes_router_sdl.rb +17 -0
  978. data/lib/tdl/auto_script/tmp/data_c_cache_sdl.rb +10 -0
  979. data/lib/tdl/auto_script/tmp/data_c_direct_sdl.rb +10 -0
  980. data/lib/tdl/auto_script/tmp/data_c_pipe_force_vld_bind_data_sdl.rb +14 -0
  981. data/lib/tdl/auto_script/tmp/data_c_pipe_force_vld_sdl.rb +10 -0
  982. data/lib/tdl/auto_script/tmp/data_c_pipe_inf_sdl.rb +10 -0
  983. data/lib/tdl/auto_script/tmp/data_c_pipe_intc_M2S_best_robin_sdl.rb +12 -0
  984. data/lib/tdl/auto_script/tmp/data_c_pipe_sync_sdl.rb +13 -0
  985. data/lib/tdl/auto_script/tmp/data_c_sim_master_model_sdl.rb +15 -0
  986. data/lib/tdl/auto_script/tmp/data_inf_c_intc_S2M_sdl.rb +13 -0
  987. data/lib/tdl/auto_script/tmp/data_inf_c_planer_A1_sdl.rb +15 -0
  988. data/lib/tdl/auto_script/tmp/data_lvds_bitslip_sdl.rb +12 -0
  989. data/lib/tdl/auto_script/tmp/data_lvds_simple_bitslip_sdl.rb +12 -0
  990. data/lib/tdl/auto_script/tmp/data_mirrors_sdl.rb +15 -0
  991. data/lib/tdl/auto_script/tmp/datainf_c_slaver_empty_sdl.rb +9 -0
  992. data/lib/tdl/auto_script/tmp/ddr3_ip_wrapper_sdl.rb +28 -0
  993. data/lib/tdl/auto_script/tmp/ddr_axi4_to_axis_sdl.rb +11 -0
  994. data/lib/tdl/auto_script/tmp/det_moto_findex_sdl.rb +13 -0
  995. data/lib/tdl/auto_script/tmp/det_start_block_sdl.rb +17 -0
  996. data/lib/tdl/auto_script/tmp/det_start_filter_sdl.rb +15 -0
  997. data/lib/tdl/auto_script/tmp/det_with_pre_A3_sdl.rb +28 -0
  998. data/lib/tdl/auto_script/tmp/det_with_pre_A4_sdl.rb +28 -0
  999. data/lib/tdl/auto_script/tmp/det_with_pre_B1_sdl.rb +29 -0
  1000. data/lib/tdl/auto_script/tmp/det_with_pre_findex_sdl.rb +18 -0
  1001. data/lib/tdl/auto_script/tmp/det_with_pre_verb_sdl.rb +29 -0
  1002. data/lib/tdl/auto_script/tmp/diffr_multi_phase_sample_sdl.rb +17 -0
  1003. data/lib/tdl/auto_script/tmp/diffr_reg_tpu_v3_wrapper_sdl.rb +17 -0
  1004. data/lib/tdl/auto_script/tmp/diffr_reg_tpu_wrapper_sdl.rb +16 -0
  1005. data/lib/tdl/auto_script/tmp/diffr_reg_tpu_wrapper_v2_sdl.rb +16 -0
  1006. data/lib/tdl/auto_script/tmp/dire_accese_flash_sdl.rb +17 -0
  1007. data/lib/tdl/auto_script/tmp/dyn_edge_clock_sdl.rb +15 -0
  1008. data/lib/tdl/auto_script/tmp/edge_generator_sdl.rb +14 -0
  1009. data/lib/tdl/auto_script/tmp/eth4_chip_reg_wrapper_sdl.rb +20 -0
  1010. data/lib/tdl/auto_script/tmp/eth4_lvds_tb_block_sdl.rb +16 -0
  1011. data/lib/tdl/auto_script/tmp/eth4_sensor_driver_array_sdl.rb +17 -0
  1012. data/lib/tdl/auto_script/tmp/eth4_single_chip_Red2S_lvds_dir_sdl.rb +16 -0
  1013. data/lib/tdl/auto_script/tmp/eth_2g5_wrapper_sdl.rb +25 -0
  1014. data/lib/tdl/auto_script/tmp/eth_outShare_wrapper_sdl.rb +28 -0
  1015. data/lib/tdl/auto_script/tmp/eth_to_ddr_with_ack_sdl.rb +13 -0
  1016. data/lib/tdl/auto_script/tmp/eth_to_spi_verb_sdl.rb +20 -0
  1017. data/lib/tdl/auto_script/tmp/eth_to_standard_spi_with_ack_sdl.rb +17 -0
  1018. data/lib/tdl/auto_script/tmp/eth_to_standard_uart_with_ack_sdl.rb +16 -0
  1019. data/lib/tdl/auto_script/tmp/eth_xilinx_ip_sdl.rb +22 -0
  1020. data/lib/tdl/auto_script/tmp/ethernet_wrapper_2d5G_sdl.rb +28 -0
  1021. data/lib/tdl/auto_script/tmp/ethernet_wrapper_sdl.rb +28 -0
  1022. data/lib/tdl/auto_script/tmp/ethernet_wrapper_track_sdl.rb +28 -0
  1023. data/lib/tdl/auto_script/tmp/ext_sync_filter_sdl.rb +14 -0
  1024. data/lib/tdl/auto_script/tmp/fifo_36kb_long_sdl.rb +20 -0
  1025. data/lib/tdl/auto_script/tmp/fifo_73_96bit_sdl.rb +19 -0
  1026. data/lib/tdl/auto_script/tmp/four_chips_Red5_lvds_dir_sdl.rb +15 -0
  1027. data/lib/tdl/auto_script/tmp/four_chips_Red5_lvds_pins_delay_sdl.rb +20 -0
  1028. data/lib/tdl/auto_script/tmp/full_axi4_to_axis_partition_wr_rd_sdl.rb +12 -0
  1029. data/lib/tdl/auto_script/tmp/full_axi4_to_axis_sdl.rb +11 -0
  1030. data/lib/tdl/auto_script/tmp/gen_big_field_table_sdl.rb +15 -0
  1031. data/lib/tdl/auto_script/tmp/gen_common_frame_table_sdl.rb +61 -0
  1032. data/lib/tdl/auto_script/tmp/gen_origin_axis_A2_sdl.rb +14 -0
  1033. data/lib/tdl/auto_script/tmp/gen_origin_axis_A3_sdl.rb +15 -0
  1034. data/lib/tdl/auto_script/tmp/gen_origin_axis_sdl.rb +13 -0
  1035. data/lib/tdl/auto_script/tmp/general_tap_ack_A2_sdl.rb +17 -0
  1036. data/lib/tdl/auto_script/tmp/general_tap_ack_A3_sdl.rb +18 -0
  1037. data/lib/tdl/auto_script/tmp/general_tap_ack_A4_sdl.rb +19 -0
  1038. data/lib/tdl/auto_script/tmp/general_tap_ack_sdl.rb +16 -0
  1039. data/lib/tdl/auto_script/tmp/general_tap_no_ack_sdl.rb +15 -0
  1040. data/lib/tdl/auto_script/tmp/general_tap_send_sdl.rb +19 -0
  1041. data/lib/tdl/auto_script/tmp/gmii_from_mac_sdl.rb +12 -0
  1042. data/lib/tdl/auto_script/tmp/gmii_to_mac_sdl.rb +14 -0
  1043. data/lib/tdl/auto_script/tmp/gt_transceivers_axis_verb_sdl.rb +22 -0
  1044. data/lib/tdl/auto_script/tmp/gt_tx_pack_proto_sdl.rb +12 -0
  1045. data/lib/tdl/auto_script/tmp/gvi_k7_clock_manager_sdl.rb +19 -0
  1046. data/lib/tdl/auto_script/tmp/gvi_k7_ddr3_ip_wrapper_sdl.rb +29 -0
  1047. data/lib/tdl/auto_script/tmp/hardware_date_core_sdl.rb +14 -0
  1048. data/lib/tdl/auto_script/tmp/hdl_test_sdl.rb +13 -0
  1049. data/lib/tdl/auto_script/tmp/iic_gpio_pca9557_array_sdl.rb +14 -0
  1050. data/lib/tdl/auto_script/tmp/independent_clock_fifo_a1_sdl.rb +22 -0
  1051. data/lib/tdl/auto_script/tmp/independent_clock_fifo_sdl.rb +21 -0
  1052. data/lib/tdl/auto_script/tmp/inf_time_delay_ctrl_sdl.rb +10 -0
  1053. data/lib/tdl/auto_script/tmp/inf_time_delay_ctrl_verb_sdl.rb +13 -0
  1054. data/lib/tdl/auto_script/tmp/init_10G_sdl.rb +11 -0
  1055. data/lib/tdl/auto_script/tmp/init_mac_sdl.rb +14 -0
  1056. data/lib/tdl/auto_script/tmp/init_trigger_cfg_10g_sdl.rb +11 -0
  1057. data/lib/tdl/auto_script/tmp/inner_clock_to_sensor_sdl.rb +13 -0
  1058. data/lib/tdl/auto_script/tmp/ip_check_sum_sdl.rb +22 -0
  1059. data/lib/tdl/auto_script/tmp/k7_ethernet_10g_wrapper_B2_sdl.rb +24 -0
  1060. data/lib/tdl/auto_script/tmp/k7_ethernet_multi_10g_wrapper_sdl.rb +23 -0
  1061. data/lib/tdl/auto_script/tmp/keys_filter_sdl.rb +14 -0
  1062. data/lib/tdl/auto_script/tmp/latency_dynamic_sdl.rb +14 -0
  1063. data/lib/tdl/auto_script/tmp/latency_sdl.rb +14 -0
  1064. data/lib/tdl/auto_script/tmp/lock_lvds_data_sdl.rb +19 -0
  1065. data/lib/tdl/auto_script/tmp/lvds2cmos_sdl.rb +11 -0
  1066. data/lib/tdl/auto_script/tmp/lvds_ibufds_array_NOBUFF_sdl.rb +15 -0
  1067. data/lib/tdl/auto_script/tmp/lvds_ibufds_array_r8_1x6_NOBUFF_sdl.rb +16 -0
  1068. data/lib/tdl/auto_script/tmp/lvds_ibufds_array_r8_1x6_OB_sdl.rb +19 -0
  1069. data/lib/tdl/auto_script/tmp/lvds_ibufds_array_sdl.rb +15 -0
  1070. data/lib/tdl/auto_script/tmp/lvds_tb_block_A1_sdl.rb +16 -0
  1071. data/lib/tdl/auto_script/tmp/mac_to_file_sdl.rb +11 -0
  1072. data/lib/tdl/auto_script/tmp/manchester_router_sdl.rb +13 -0
  1073. data/lib/tdl/auto_script/tmp/mdio_model_sdl.rb +11 -0
  1074. data/lib/tdl/auto_script/tmp/mdio_proto_sdl.rb +24 -0
  1075. data/lib/tdl/auto_script/tmp/mirror_mac_arp_iic_sdl.rb +10 -0
  1076. data/lib/tdl/auto_script/tmp/modified_eth_2G5_top_sdl.rb +16 -0
  1077. data/lib/tdl/auto_script/tmp/multiple_steps_676_sdl.rb +15 -0
  1078. data/lib/tdl/auto_script/tmp/multiple_steps_A2_sdl.rb +15 -0
  1079. data/lib/tdl/auto_script/tmp/odata_pool_axi4_A2_sdl.rb +11 -0
  1080. data/lib/tdl/auto_script/tmp/odata_pool_axi4_A3_sdl.rb +14 -0
  1081. data/lib/tdl/auto_script/tmp/outSt_combin_spi_core_sdl.rb +22 -0
  1082. data/lib/tdl/auto_script/tmp/outSt_eth_to_ct_databoard_sdl.rb +13 -0
  1083. data/lib/tdl/auto_script/tmp/outSt_eth_to_multi_spi_with_ack_sdl.rb +19 -0
  1084. data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_sdl.rb +20 -0
  1085. data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_verb_sdl.rb +17 -0
  1086. data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_with_ack_sdl.rb +17 -0
  1087. data/lib/tdl/auto_script/tmp/outSt_spi_core_B1_sdl.rb +21 -0
  1088. data/lib/tdl/auto_script/tmp/pack_ip_mac_B1_sdl.rb +15 -0
  1089. data/lib/tdl/auto_script/tmp/pack_ip_mac_verb_sdl.rb +15 -0
  1090. data/lib/tdl/auto_script/tmp/parse_big_field_table_A2_sdl.rb +19 -0
  1091. data/lib/tdl/auto_script/tmp/parse_big_field_table_main_sdl.rb +15 -0
  1092. data/lib/tdl/auto_script/tmp/parse_big_field_table_mirror_sdl.rb +14 -0
  1093. data/lib/tdl/auto_script/tmp/parse_big_field_table_sdl.rb +18 -0
  1094. data/lib/tdl/auto_script/tmp/parse_big_field_table_slaver_sdl.rb +17 -0
  1095. data/lib/tdl/auto_script/tmp/parse_big_field_table_verb_sdl.rb +17 -0
  1096. data/lib/tdl/auto_script/tmp/parse_common_frame_table_A1_sdl.rb +64 -0
  1097. data/lib/tdl/auto_script/tmp/parse_tap_stream_sdl.rb +10 -0
  1098. data/lib/tdl/auto_script/tmp/phase_red8_sensor_lvds_block_red8_sdl.rb +22 -0
  1099. data/lib/tdl/auto_script/tmp/phase_sensor_sync_ctrl_sdl.rb +17 -0
  1100. data/lib/tdl/auto_script/tmp/platform_shift_ctrl_verb_sdl.rb +22 -0
  1101. data/lib/tdl/auto_script/tmp/poll_udp_tpu_upgrade_sdl.rb +30 -0
  1102. data/lib/tdl/auto_script/tmp/poll_udp_tpu_verb_upgrade_sdl.rb +34 -0
  1103. data/lib/tdl/auto_script/tmp/prim_serdes_filter_decode_sdl.rb +14 -0
  1104. data/lib/tdl/auto_script/tmp/red2s_lock_lvds_data_verc_sdl.rb +20 -0
  1105. data/lib/tdl/auto_script/tmp/red3_lock_lvds_data_verc_sdl.rb +18 -0
  1106. data/lib/tdl/auto_script/tmp/red3_lvds_tb_block_A1_sdl.rb +16 -0
  1107. data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_A1_sdl.rb +20 -0
  1108. data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_A2_sdl.rb +21 -0
  1109. data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_sdl.rb +19 -0
  1110. data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_raw_A1_sdl.rb +20 -0
  1111. data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_sdl.rb +18 -0
  1112. data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_verb_sdl.rb +18 -0
  1113. data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_verc_sdl.rb +22 -0
  1114. data/lib/tdl/auto_script/tmp/red5_lvds_clock_mmcm_sdl.rb +12 -0
  1115. data/lib/tdl/auto_script/tmp/red8_1x6_oneBoard_sdl.rb +30 -0
  1116. data/lib/tdl/auto_script/tmp/red8_chip_reg_wrapper_A2_sdl.rb +21 -0
  1117. data/lib/tdl/auto_script/tmp/redx_1xN_ddr_inner_clock_sdl.rb +36 -0
  1118. data/lib/tdl/auto_script/tmp/redx_1xN_ddr_inner_clock_verb_sdl.rb +38 -0
  1119. data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_A1_sdl.rb +38 -0
  1120. data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_A2_sdl.rb +39 -0
  1121. data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_sdl.rb +35 -0
  1122. data/lib/tdl/auto_script/tmp/redx_1xN_inner_clock_sdl.rb +36 -0
  1123. data/lib/tdl/auto_script/tmp/redx_1xN_sdr_serdes_manual_A1_sdl.rb +36 -0
  1124. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_2B_sdl.rb +25 -0
  1125. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_bitslip_sdl.rb +26 -0
  1126. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_sdl.rb +25 -0
  1127. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_verb_sdl.rb +25 -0
  1128. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_dyn_compact_sdl.rb +26 -0
  1129. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_dyn_sdl.rb +26 -0
  1130. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_raw_sdl.rb +21 -0
  1131. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_raw_verb_sdl.rb +22 -0
  1132. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_sdl.rb +22 -0
  1133. data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_verb_sdl.rb +23 -0
  1134. data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_sdl.rb +21 -0
  1135. data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_multi_phase_DDR_sdl.rb +29 -0
  1136. data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_multi_phase_sdl.rb +28 -0
  1137. data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_sdl.rb +23 -0
  1138. data/lib/tdl/auto_script/tmp/rgmii_to_gmii_wrapper_sdl.rb +17 -0
  1139. data/lib/tdl/auto_script/tmp/riffa_trans_axis_sdl.rb +22 -0
  1140. data/lib/tdl/auto_script/tmp/sct_ddr3_16bit_ip_wrapper_sdl.rb +28 -0
  1141. data/lib/tdl/auto_script/tmp/sct_ddr3_ip_wrapper_sdl.rb +29 -0
  1142. data/lib/tdl/auto_script/tmp/sel_system_ip_mac_sdl.rb +15 -0
  1143. data/lib/tdl/auto_script/tmp/senser_lvds_parse_16bit_diffr_sdl.rb +16 -0
  1144. data/lib/tdl/auto_script/tmp/senser_lvds_parse_24bit_diffr_A1_sdl.rb +16 -0
  1145. data/lib/tdl/auto_script/tmp/senser_lvds_parse_24bit_diffr_sdl.rb +15 -0
  1146. data/lib/tdl/auto_script/tmp/sensor_block_unit_C2_sdl.rb +29 -0
  1147. data/lib/tdl/auto_script/tmp/sensor_block_unit_C2_track_crc8_sdl.rb +29 -0
  1148. data/lib/tdl/auto_script/tmp/sensor_clock_recv_check_sdl.rb +11 -0
  1149. data/lib/tdl/auto_script/tmp/sensor_ctrl_676_28lvds_sdl.rb +18 -0
  1150. data/lib/tdl/auto_script/tmp/sensor_ctrl_676_sdl.rb +17 -0
  1151. data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_SP_sdl.rb +15 -0
  1152. data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_sdl.rb +17 -0
  1153. data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_verb_sdl.rb +18 -0
  1154. data/lib/tdl/auto_script/tmp/sensor_driver_clock_set_A2_sdl.rb +13 -0
  1155. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_SP_sdl.rb +23 -0
  1156. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_edge_sync_sdl.rb +23 -0
  1157. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_sdl.rb +23 -0
  1158. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_verb_sdl.rb +23 -0
  1159. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_sdl.rb +21 -0
  1160. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_sdl.rb +23 -0
  1161. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_A1_sdl.rb +23 -0
  1162. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_red450_sdl.rb +22 -0
  1163. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_sdl.rb +23 -0
  1164. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verc_red450_sdl.rb +22 -0
  1165. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verc_sdl.rb +22 -0
  1166. data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_sdl.rb +21 -0
  1167. data/lib/tdl/auto_script/tmp/serdes_parl_lock_sdl.rb +18 -0
  1168. data/lib/tdl/auto_script/tmp/serdes_to_data_array_sdl.rb +19 -0
  1169. data/lib/tdl/auto_script/tmp/sim_arp_tpu_sdl.rb +17 -0
  1170. data/lib/tdl/auto_script/tmp/sim_auto_wireshark_send_sdl.rb +14 -0
  1171. data/lib/tdl/auto_script/tmp/sim_tpu_update_file_sdl.rb +13 -0
  1172. data/lib/tdl/auto_script/tmp/simple_cbct_lock_lvds_data_sdl.rb +16 -0
  1173. data/lib/tdl/auto_script/tmp/simple_hardware_log_track_sdl.rb +14 -0
  1174. data/lib/tdl/auto_script/tmp/simple_hw_test_top_sdl.rb +19 -0
  1175. data/lib/tdl/auto_script/tmp/simple_test_eth_2g5_subs_sdl.rb +18 -0
  1176. data/lib/tdl/auto_script/tmp/single_chip_Red2S_lvds_dir_sdl.rb +15 -0
  1177. data/lib/tdl/auto_script/tmp/single_chip_Red3_lvds_pins_delay_sdl.rb +17 -0
  1178. data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verb_wrapper_sdl.rb +14 -0
  1179. data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verc_wrapper_sdl.rb +15 -0
  1180. data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verd_wrapper_sdl.rb +15 -0
  1181. data/lib/tdl/auto_script/tmp/single_chip_iic_bus_wrapper_sdl.rb +14 -0
  1182. data/lib/tdl/auto_script/tmp/single_chip_lvds_ddr_dir_sdl.rb +18 -0
  1183. data/lib/tdl/auto_script/tmp/single_chip_lvds_dir_delay_sdl.rb +19 -0
  1184. data/lib/tdl/auto_script/tmp/single_chip_lvds_dir_inner_sdl.rb +17 -0
  1185. data/lib/tdl/auto_script/tmp/single_chip_sensor_lvds_dir_sdl.rb +15 -0
  1186. data/lib/tdl/auto_script/tmp/sketch_to_origin_stream_sdl.rb +13 -0
  1187. data/lib/tdl/auto_script/tmp/slow_lvds_data_d2s_sdl.rb +13 -0
  1188. data/lib/tdl/auto_script/tmp/slow_sensor_inner_clock_sdl.rb +18 -0
  1189. data/lib/tdl/auto_script/tmp/split_ddr3_ip_wrapper_sdl.rb +45 -0
  1190. data/lib/tdl/auto_script/tmp/tcp_aux_tpu_upgrade_sdl.rb +50 -0
  1191. data/lib/tdl/auto_script/tmp/tcp_check_sum_sdl.rb +15 -0
  1192. data/lib/tdl/auto_script/tmp/tcp_ctrl_set_sdl.rb +13 -0
  1193. data/lib/tdl/auto_script/tmp/tcp_option_split_B1_sdl.rb +10 -0
  1194. data/lib/tdl/auto_script/tmp/test_red5dl_lvds_sdl.rb +9 -0
  1195. data/lib/tdl/auto_script/tmp/time_delay_ctrl_sdl.rb +13 -0
  1196. data/lib/tdl/auto_script/tmp/time_enable_scaler_sdl.rb +12 -0
  1197. data/lib/tdl/auto_script/tmp/time_step_module_A1_sdl.rb +14 -0
  1198. data/lib/tdl/auto_script/tmp/time_step_module_sdl.rb +13 -0
  1199. data/lib/tdl/auto_script/tmp/tpu_bypass_iic_upgrade_sdl.rb +29 -0
  1200. data/lib/tdl/auto_script/tmp/tpu_common_iic_upgrade_sdl.rb +25 -0
  1201. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_gray_sdl.rb +19 -0
  1202. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_sdl.rb +20 -0
  1203. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_verb_sdl.rb +19 -0
  1204. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_x7_gray_sdl.rb +19 -0
  1205. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v2_array_sdl.rb +15 -0
  1206. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v3_wrapper_sdl.rb +17 -0
  1207. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v4_wrapper_sdl.rb +19 -0
  1208. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v5_wrapper_sdl.rb +20 -0
  1209. data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_wrapper_sdl.rb +20 -0
  1210. data/lib/tdl/auto_script/tmp/tpu_eth4_iic_bus_wrapper_sdl.rb +15 -0
  1211. data/lib/tdl/auto_script/tmp/tpu_mgm_inf_sdl.rb +28 -0
  1212. data/lib/tdl/auto_script/tmp/tpu_simple_boot_sdl.rb +12 -0
  1213. data/lib/tdl/auto_script/tmp/trigger_data_inf_c_A1_sdl.rb +12 -0
  1214. data/lib/tdl/auto_script/tmp/trigger_data_inf_c_sdl.rb +12 -0
  1215. data/lib/tdl/auto_script/tmp/uart_hp_ddr3_tft800x480_hdmi_ext_sdl.rb +43 -0
  1216. data/lib/tdl/auto_script/tmp/uart_hp_ddr3_tft800x480_hdmi_ext_sim_sdl.rb +43 -0
  1217. data/lib/tdl/auto_script/tmp/uart_rx_core_dma_verb_sdl.rb +13 -0
  1218. data/lib/tdl/auto_script/tmp/uart_top_bypass_sdl.rb +21 -0
  1219. data/lib/tdl/auto_script/tmp/uart_top_sdl.rb +21 -0
  1220. data/lib/tdl/auto_script/tmp/udp_check_sum_sdl.rb +15 -0
  1221. data/lib/tdl/auto_script/tmp/udp_ctrl_set_A1_sdl.rb +18 -0
  1222. data/lib/tdl/auto_script/tmp/udp_fpga_ports_route_sdl.rb +12 -0
  1223. data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_64b_sdl.rb +16 -0
  1224. data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_A3_sdl.rb +14 -0
  1225. data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_B1_sdl.rb +14 -0
  1226. data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_verb_sdl.rb +14 -0
  1227. data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_D1_sdl.rb +16 -0
  1228. data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_tcp_sdl.rb +15 -0
  1229. data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_verd_sdl.rb +13 -0
  1230. data/lib/tdl/auto_script/tmp/vio_wrapper_sdl.rb +11 -0
  1231. data/lib/tdl/auto_script/tmp/wide_axis_to_axi4_wr_sdl.rb +12 -0
  1232. data/lib/tdl/auto_script/tmp/wide_fifo_sdl.rb +19 -0
  1233. data/lib/tdl/auto_script/tmp/width_combin_sdl.rb +21 -0
  1234. data/lib/tdl/auto_script/tmp/width_convert_sdl.rb +21 -0
  1235. data/lib/tdl/auto_script/tmp/xilinx_dna_capture_sdl.rb +12 -0
  1236. data/lib/tdl/auto_script/tmp/xilinx_eth_clock_sdl.rb +13 -0
  1237. data/lib/tdl/auto_script/tmp/xilinx_eth_reset_sdl.rb +15 -0
  1238. data/lib/tdl/auto_script/tmp/xilinx_fifo_A1_sdl.rb +22 -0
  1239. data/lib/tdl/auto_script/tmp/xilinx_fifo_sdl.rb +20 -0
  1240. data/lib/tdl/auto_script/tmp/xilinx_fifo_verb_sdl.rb +23 -0
  1241. data/lib/tdl/auto_script/tmp/xilinx_fifo_verc_sdl.rb +21 -0
  1242. data/lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sdl.rb +29 -0
  1243. data/lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sim_sdl.rb +31 -0
  1244. data/lib/tdl/auto_script/tmp/xilinx_jtag_axil_wrapper_sdl.rb +9 -0
  1245. data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_multi_phase_ddr_wrapper_sdl.rb +17 -0
  1246. data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_multi_phase_wrapper_sdl.rb +17 -0
  1247. data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_phase_wrapper_sdl.rb +17 -0
  1248. data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_wrapper_sdl.rb +13 -0
  1249. data/lib/tdl/auto_script/tmp/zynq_pl_common_dr_sensor_clk_sdl.rb +13 -0
  1250. data/lib/tdl/auto_script/tmp/zynq_pl_common_lvds_sdl.rb +18 -0
  1251. data/lib/tdl/auto_script/tmp.rb +0 -0
  1252. data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +0 -0
  1253. data/lib/tdl/axi4/axi4_direct.rb +0 -0
  1254. data/lib/tdl/axi4/axi4_direct_A1_auto.rb +0 -0
  1255. data/lib/tdl/axi4/axi4_direct_auto.rb +0 -0
  1256. data/lib/tdl/axi4/axi4_direct_verb_auto.rb +0 -0
  1257. data/lib/tdl/axi4/axi4_interconnect_verb.rb +24 -10
  1258. data/lib/tdl/axi4/axi4_lib.rb +0 -0
  1259. data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +0 -0
  1260. data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +0 -0
  1261. data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +0 -0
  1262. data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +0 -0
  1263. data/lib/tdl/axi4/axi4_pipe_auto.rb +0 -0
  1264. data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +0 -0
  1265. data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +0 -0
  1266. data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +0 -0
  1267. data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +0 -0
  1268. data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +0 -0
  1269. data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +0 -0
  1270. data/lib/tdl/axi4/bak/axi4_data_convert.rb +0 -0
  1271. data/lib/tdl/axi4/bak/axi4_direct_auto.rb +0 -0
  1272. data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +0 -0
  1273. data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +0 -0
  1274. data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +0 -0
  1275. data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +0 -0
  1276. data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +0 -0
  1277. data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +0 -0
  1278. data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +0 -0
  1279. data/lib/tdl/axi4/bak/axi4_partition_od.rb +0 -0
  1280. data/lib/tdl/axi4/bak/axi4_pipe_auto.rb +0 -0
  1281. data/lib/tdl/axi4/bak/axi4_wr_auxiliary_gen_without_resp_auto.rb +0 -0
  1282. data/lib/tdl/axi4/bak/axis_to_axi4_wr_auto.rb +0 -0
  1283. data/lib/tdl/axi4/bak/ddr3.rb +0 -0
  1284. data/lib/tdl/axi4/bak/idata_pool_axi4_auto.rb +0 -0
  1285. data/lib/tdl/axi4/bak/odata_pool_axi4_A1_auto.rb +0 -0
  1286. data/lib/tdl/axi4/bak/odata_pool_axi4_auto.rb +0 -0
  1287. data/lib/tdl/axi4/idata_pool_axi4_auto.rb +0 -0
  1288. data/lib/tdl/axi4/odata_pool_axi4_A1_auto.rb +0 -0
  1289. data/lib/tdl/axi4/odata_pool_axi4_auto.rb +0 -0
  1290. data/lib/tdl/axi4/wide_axis_to_axi4_wr.rb +0 -0
  1291. data/lib/tdl/axi4/wide_axis_to_axi4_wr_auto.rb +0 -0
  1292. data/lib/tdl/axi_lite/axi_lite_master_empty_auto.rb +0 -0
  1293. data/lib/tdl/axi_lite/axi_lite_slaver_empty_auto.rb +0 -0
  1294. data/lib/tdl/axi_lite/bak/axi_lite_master_empty_auto.rb +0 -0
  1295. data/lib/tdl/axi_lite/bak/axi_lite_slaver_empty_auto.rb +0 -0
  1296. data/lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb +0 -0
  1297. data/lib/tdl/axi_lite/jtag_to_axilite_wrapper_auto.rb +0 -0
  1298. data/lib/tdl/axi_lite/lite_cmd.rb +0 -0
  1299. data/lib/tdl/axi_lite/prj_lib.rb +0 -0
  1300. data/lib/tdl/axi_stream/axi_stream_cache_35bit_auto.rb +0 -0
  1301. data/lib/tdl/axi_stream/axi_stream_cache_72_95bit_with_keep_auto.rb +0 -0
  1302. data/lib/tdl/axi_stream/axi_stream_cache_B1_auto.rb +0 -0
  1303. data/lib/tdl/axi_stream/axi_stream_cache_auto.rb +0 -0
  1304. data/lib/tdl/axi_stream/axi_stream_cache_mirror_auto.rb +0 -0
  1305. data/lib/tdl/axi_stream/axi_stream_cache_verb_auto.rb +0 -0
  1306. data/lib/tdl/axi_stream/axi_stream_interconnect.rb +0 -0
  1307. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S.rb +0 -0
  1308. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1.rb +0 -0
  1309. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1_auto.rb +0 -0
  1310. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_auto.rb +0 -0
  1311. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_bind_tuser_auto.rb +0 -0
  1312. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M.rb +0 -0
  1313. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto.rb +0 -0
  1314. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto_auto.rb +0 -0
  1315. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +0 -0
  1316. data/lib/tdl/axi_stream/axi_stream_lib.rb +0 -0
  1317. data/lib/tdl/axi_stream/axi_stream_long_cache_auto.rb +0 -0
  1318. data/lib/tdl/axi_stream/axi_stream_long_fifo_auto.rb +0 -0
  1319. data/lib/tdl/axi_stream/axi_stream_long_fifo_verb_auto.rb +0 -0
  1320. data/lib/tdl/axi_stream/axi_stream_packet_fifo_auto.rb +0 -0
  1321. data/lib/tdl/axi_stream/axi_stream_packet_fifo_with_info_auto.rb +0 -0
  1322. data/lib/tdl/axi_stream/axi_stream_partition_A1_auto.rb +0 -0
  1323. data/lib/tdl/axi_stream/axi_stream_partition_auto.rb +0 -0
  1324. data/lib/tdl/axi_stream/axi_stream_wide_fifo_auto.rb +0 -0
  1325. data/lib/tdl/axi_stream/axi_streams_combin_A1_auto.rb +0 -0
  1326. data/lib/tdl/axi_stream/axi_streams_combin_auto.rb +0 -0
  1327. data/lib/tdl/axi_stream/axi_streams_scaler_A1_auto.rb +0 -0
  1328. data/lib/tdl/axi_stream/axi_streams_scaler_auto.rb +0 -0
  1329. data/lib/tdl/axi_stream/axis_append_A1_auto.rb +0 -0
  1330. data/lib/tdl/axi_stream/axis_append_auto.rb +0 -0
  1331. data/lib/tdl/axi_stream/axis_combin_with_fifo_auto.rb +0 -0
  1332. data/lib/tdl/axi_stream/axis_connect_pipe_A1.sv_auto.rb +0 -0
  1333. data/lib/tdl/axi_stream/axis_connect_pipe_auto.rb +0 -0
  1334. data/lib/tdl/axi_stream/axis_connect_pipe_with_info_auto.rb +0 -0
  1335. data/lib/tdl/axi_stream/axis_direct_auto.rb +0 -0
  1336. data/lib/tdl/axi_stream/axis_filter_auto.rb +0 -0
  1337. data/lib/tdl/axi_stream/axis_full_to_data_c_auto.rb +0 -0
  1338. data/lib/tdl/axi_stream/axis_head_cut_auto.rb +0 -0
  1339. data/lib/tdl/axi_stream/axis_length_fill_auto.rb +0 -0
  1340. data/lib/tdl/axi_stream/axis_length_split_auto.rb +0 -0
  1341. data/lib/tdl/axi_stream/axis_length_split_with_addr_auto.rb +0 -0
  1342. data/lib/tdl/axi_stream/axis_length_split_writh_user_auto.rb +0 -0
  1343. data/lib/tdl/axi_stream/axis_link_trigger_auto.rb +0 -0
  1344. data/lib/tdl/axi_stream/axis_master_empty_auto.rb +0 -0
  1345. data/lib/tdl/axi_stream/axis_mirror_to_master_auto.rb +0 -0
  1346. data/lib/tdl/axi_stream/axis_mirrors_auto.rb +0 -0
  1347. data/lib/tdl/axi_stream/axis_padding.rb +44 -0
  1348. data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_A1_auto.rb +0 -0
  1349. data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_auto.rb +0 -0
  1350. data/lib/tdl/axi_stream/axis_ram_buffer_auto.rb +0 -0
  1351. data/lib/tdl/axi_stream/axis_slaver_empty_auto.rb +0 -0
  1352. data/lib/tdl/axi_stream/axis_slaver_pipe_A1_auto.rb +0 -0
  1353. data/lib/tdl/axi_stream/axis_slaver_pipe_auto.rb +0 -0
  1354. data/lib/tdl/axi_stream/axis_to_axi4_or_lite_auto.rb +0 -0
  1355. data/lib/tdl/axi_stream/axis_to_data_inf_auto.rb +0 -0
  1356. data/lib/tdl/axi_stream/axis_to_lite_rd_auto.rb +0 -0
  1357. data/lib/tdl/axi_stream/axis_to_lite_wr_auto.rb +0 -0
  1358. data/lib/tdl/axi_stream/axis_uncompress_auto.rb +0 -0
  1359. data/lib/tdl/axi_stream/axis_valve_auto.rb +0 -0
  1360. data/lib/tdl/axi_stream/axis_valve_with_pipe_auto.rb +0 -0
  1361. data/lib/tdl/axi_stream/axis_width_combin_A1_auto.rb +0 -0
  1362. data/lib/tdl/axi_stream/axis_width_combin_auto.rb +0 -0
  1363. data/lib/tdl/axi_stream/axis_width_convert_auto.rb +0 -0
  1364. data/lib/tdl/axi_stream/axis_width_destruct_A1.sv_auto.rb +0 -0
  1365. data/lib/tdl/axi_stream/axis_width_destruct_auto.rb +0 -0
  1366. data/lib/tdl/axi_stream/bak/__axi_stream_interconnect_S2M.rb +0 -0
  1367. data/lib/tdl/axi_stream/bak/_axis_mirrors.rb +0 -0
  1368. data/lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb +0 -0
  1369. data/lib/tdl/axi_stream/bak/axi_stream_S2M.rb +0 -0
  1370. data/lib/tdl/axi_stream/bak/axi_stream_cache_35bit_auto.rb +0 -0
  1371. data/lib/tdl/axi_stream/bak/axi_stream_cache_72_95bit_with_keep_auto.rb +0 -0
  1372. data/lib/tdl/axi_stream/bak/axi_stream_cache_B1_auto.rb +0 -0
  1373. data/lib/tdl/axi_stream/bak/axi_stream_cache_auto.rb +0 -0
  1374. data/lib/tdl/axi_stream/bak/axi_stream_cache_mirror_auto.rb +0 -0
  1375. data/lib/tdl/axi_stream/bak/axi_stream_cache_verb_auto.rb +0 -0
  1376. data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_auto.rb +0 -0
  1377. data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +0 -0
  1378. data/lib/tdl/axi_stream/bak/axi_stream_long_fifo_auto.rb +0 -0
  1379. data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_auto.rb +0 -0
  1380. data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_with_info_auto.rb +0 -0
  1381. data/lib/tdl/axi_stream/bak/axi_stream_partition_A1_auto.rb +0 -0
  1382. data/lib/tdl/axi_stream/bak/axi_stream_partition_auto.rb +0 -0
  1383. data/lib/tdl/axi_stream/bak/axi_streams_combin_auto.rb +0 -0
  1384. data/lib/tdl/axi_stream/bak/axi_streams_scaler.rb +0 -0
  1385. data/lib/tdl/axi_stream/bak/axi_streams_scaler_auto.rb +0 -0
  1386. data/lib/tdl/axi_stream/bak/axis_append_A1.rb +0 -0
  1387. data/lib/tdl/axi_stream/bak/axis_append_A1_auto.rb +0 -0
  1388. data/lib/tdl/axi_stream/bak/axis_append_auto.rb +0 -0
  1389. data/lib/tdl/axi_stream/bak/axis_combin_with_fifo_auto.rb +0 -0
  1390. data/lib/tdl/axi_stream/bak/axis_connect_pipe.rb.bak +0 -0
  1391. data/lib/tdl/axi_stream/bak/axis_connect_pipe_A1.sv_auto.rb +0 -0
  1392. data/lib/tdl/axi_stream/bak/axis_connect_pipe_auto.rb +0 -0
  1393. data/lib/tdl/axi_stream/bak/axis_connect_pipe_with_info_auto.rb +0 -0
  1394. data/lib/tdl/axi_stream/bak/axis_direct_auto.rb +0 -0
  1395. data/lib/tdl/axi_stream/bak/axis_filter_auto.rb +0 -0
  1396. data/lib/tdl/axi_stream/bak/axis_length_fill_auto.rb +0 -0
  1397. data/lib/tdl/axi_stream/bak/axis_length_split_auto.rb +0 -0
  1398. data/lib/tdl/axi_stream/bak/axis_length_split_with_addr_auto.rb +0 -0
  1399. data/lib/tdl/axi_stream/bak/axis_master_empty_auto.rb +0 -0
  1400. data/lib/tdl/axi_stream/bak/axis_mirrors_auto.rb +0 -0
  1401. data/lib/tdl/axi_stream/bak/axis_pkt_fifo_filter_keep_auto.rb +0 -0
  1402. data/lib/tdl/axi_stream/bak/axis_ram_buffer_auto.rb +0 -0
  1403. data/lib/tdl/axi_stream/bak/axis_slaver_empty_auto.rb +0 -0
  1404. data/lib/tdl/axi_stream/bak/axis_slaver_pipe_A1_auto.rb +0 -0
  1405. data/lib/tdl/axi_stream/bak/axis_slaver_pipe_auto.rb +0 -0
  1406. data/lib/tdl/axi_stream/bak/axis_to_axi4_wr_auto.rb +0 -0
  1407. data/lib/tdl/axi_stream/bak/axis_to_data_inf_auto.rb +0 -0
  1408. data/lib/tdl/axi_stream/bak/axis_uncompress_auto.rb +0 -0
  1409. data/lib/tdl/axi_stream/bak/axis_valve_auto.rb +0 -0
  1410. data/lib/tdl/axi_stream/bak/axis_valve_with_pipe_auto.rb +0 -0
  1411. data/lib/tdl/axi_stream/bak/axis_width_combin_auto.rb +0 -0
  1412. data/lib/tdl/axi_stream/bak/axis_width_convert_auto.rb +0 -0
  1413. data/lib/tdl/axi_stream/bak/axis_width_destruct_auto.rb +0 -0
  1414. data/lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb +0 -0
  1415. data/lib/tdl/axi_stream/bak/check_stream_crc_auto.rb +0 -0
  1416. data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1.rb +0 -0
  1417. data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1_auto.rb +0 -0
  1418. data/lib/tdl/axi_stream/bak/data_to_axis_inf_auto.rb +0 -0
  1419. data/lib/tdl/axi_stream/bak/datainf_c_master_empty_auto.rb +0 -0
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  1422. data/lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb +0 -0
  1423. data/lib/tdl/axi_stream/bak/dynamic_port_cfg_auto.rb +0 -0
  1424. data/lib/tdl/axi_stream/bak/dynnamic_addr_cfg_auto.rb +0 -0
  1425. data/lib/tdl/axi_stream/bak/gen_big_field_table_auto.rb +0 -0
  1426. data/lib/tdl/axi_stream/bak/gen_origin_axis_auto.rb +0 -0
  1427. data/lib/tdl/axi_stream/bak/gen_simple_axis_auto.rb +0 -0
  1428. data/lib/tdl/axi_stream/bak/idata_pool_axi4_auto.rb +0 -0
  1429. data/lib/tdl/axi_stream/bak/parse_big_field_table_A1_auto.rb +0 -0
  1430. data/lib/tdl/axi_stream/bak/parse_big_field_table_A2_auto.rb +0 -0
  1431. data/lib/tdl/axi_stream/bak/parse_big_field_table_auto.rb +0 -0
  1432. data/lib/tdl/axi_stream/bak/part_data_pair_map_auto.rb +0 -0
  1433. data/lib/tdl/axi_stream/bak/simple_video_gen_A2.rb +0 -0
  1434. data/lib/tdl/axi_stream/bak/simple_video_gen_A2_auto.rb +0 -0
  1435. data/lib/tdl/axi_stream/bak/stream_crc_auto.rb +0 -0
  1436. data/lib/tdl/axi_stream/bak/udp_server_bfm_auto.rb +0 -0
  1437. data/lib/tdl/axi_stream/bak/udp_server_ctrl_bfm_auto.rb +0 -0
  1438. data/lib/tdl/axi_stream/bak/video_to_VDMA.rb +0 -0
  1439. data/lib/tdl/axi_stream/bak/video_to_VDMA_auto.rb +0 -0
  1440. data/lib/tdl/axi_stream/check_stream_crc_auto.rb +0 -0
  1441. data/lib/tdl/axi_stream/data_c_to_axis_full_auto.rb +0 -0
  1442. data/lib/tdl/axi_stream/data_to_axis_inf_A1_auto.rb +0 -0
  1443. data/lib/tdl/axi_stream/data_to_axis_inf_auto.rb +0 -0
  1444. data/lib/tdl/axi_stream/gen_big_field_table_auto.rb +0 -0
  1445. data/lib/tdl/axi_stream/gen_origin_axis_A1_auto.rb +0 -0
  1446. data/lib/tdl/axi_stream/gen_origin_axis_auto.rb +0 -0
  1447. data/lib/tdl/axi_stream/gen_simple_axis_auto.rb +0 -0
  1448. data/lib/tdl/axi_stream/parse_big_field_table_A1_auto.rb +0 -0
  1449. data/lib/tdl/axi_stream/parse_big_field_table_A2_auto.rb +0 -0
  1450. data/lib/tdl/axi_stream/parse_big_field_table_auto.rb +0 -0
  1451. data/lib/tdl/axi_stream/stream_crc_auto.rb +0 -0
  1452. data/lib/tdl/basefunc.rb +0 -0
  1453. data/lib/tdl/bfm/axi4_illegal_bfm.rb +0 -0
  1454. data/lib/tdl/bfm/axi_stream/axi_stream_bfm.rb +0 -0
  1455. data/lib/tdl/bfm/axi_stream/axis_bfm_exp.yml +0 -0
  1456. data/lib/tdl/bfm/axi_stream/axis_bfm_module_build.rb +0 -0
  1457. data/lib/tdl/bfm/axi_stream/axis_bfm_parse.rb +0 -0
  1458. data/lib/tdl/bfm/axi_stream/axis_slice_to_logic.rb +0 -0
  1459. data/lib/tdl/bfm/bfm_lib.rb +0 -0
  1460. data/lib/tdl/bfm/logic_initial_block.rb +0 -0
  1461. data/lib/tdl/cfg.yml +0 -0
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  1463. data/lib/tdl/class_hdl/hdl_always_ff.rb +0 -0
  1464. data/lib/tdl/class_hdl/hdl_assign.rb +0 -0
  1465. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +0 -0
  1466. data/lib/tdl/class_hdl/hdl_data.rb +0 -0
  1467. data/lib/tdl/class_hdl/hdl_ex_defarraychain.rb +0 -0
  1468. data/lib/tdl/class_hdl/hdl_foreach.rb +0 -0
  1469. data/lib/tdl/class_hdl/hdl_function.rb +0 -0
  1470. data/lib/tdl/class_hdl/hdl_generate.rb +0 -0
  1471. data/lib/tdl/class_hdl/hdl_initial.rb +0 -0
  1472. data/lib/tdl/class_hdl/hdl_module_def.rb +16 -0
  1473. data/lib/tdl/class_hdl/hdl_package.rb +0 -0
  1474. data/lib/tdl/class_hdl/hdl_parameter.rb +0 -0
  1475. data/lib/tdl/class_hdl/hdl_random.rb +0 -0
  1476. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +18 -1
  1477. data/lib/tdl/class_hdl/hdl_struct.rb +0 -0
  1478. data/lib/tdl/class_hdl/hdl_verify.rb +0 -0
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  1480. data/lib/tdl/data_inf/bak/_data_mirrors.rb +0 -0
  1481. data/lib/tdl/data_inf/bak/common_fifo_auto.rb +0 -0
  1482. data/lib/tdl/data_inf/bak/data_bind_auto.rb +0 -0
  1483. data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +0 -0
  1484. data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +0 -0
  1485. data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +0 -0
  1486. data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +0 -0
  1487. data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +0 -0
  1488. data/lib/tdl/data_inf/bak/data_connect_pipe.rb +0 -0
  1489. data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +0 -0
  1490. data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +0 -0
  1491. data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +0 -0
  1492. data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +0 -0
  1493. data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +0 -0
  1494. data/lib/tdl/data_inf/bak/data_inf_planer.rb +0 -0
  1495. data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +0 -0
  1496. data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
  1497. data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +0 -0
  1498. data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +0 -0
  1499. data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +0 -0
  1500. data/lib/tdl/data_inf/bak/data_valve_auto.rb +0 -0
  1501. data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +0 -0
  1502. data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +0 -0
  1503. data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +0 -0
  1504. data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +0 -0
  1505. data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +0 -0
  1506. data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +0 -0
  1507. data/lib/tdl/data_inf/common_fifo_auto.rb +0 -0
  1508. data/lib/tdl/data_inf/data_bind_auto.rb +0 -0
  1509. data/lib/tdl/data_inf/data_c_cache_auto.rb +0 -0
  1510. data/lib/tdl/data_inf/data_c_direct_auto.rb +0 -0
  1511. data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +0 -0
  1512. data/lib/tdl/data_inf/data_c_interconnect.rb +0 -0
  1513. data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +0 -0
  1514. data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +0 -0
  1515. data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +0 -0
  1516. data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +0 -0
  1517. data/lib/tdl/data_inf/data_condition_mirror_auto.rb +0 -0
  1518. data/lib/tdl/data_inf/data_condition_valve_auto.rb +0 -0
  1519. data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +0 -0
  1520. data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +0 -0
  1521. data/lib/tdl/data_inf/data_mirrors_auto.rb +0 -0
  1522. data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +0 -0
  1523. data/lib/tdl/data_inf/data_uncompress_auto.rb +0 -0
  1524. data/lib/tdl/data_inf/data_valve_auto.rb +0 -0
  1525. data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +0 -0
  1526. data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +0 -0
  1527. data/lib/tdl/data_inf/datainf_master_empty_auto.rb +0 -0
  1528. data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +0 -0
  1529. data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +0 -0
  1530. data/lib/tdl/data_inf/part_data_pair_map_auto.rb +0 -0
  1531. data/lib/tdl/data_inf/path_lib.rb +0 -0
  1532. data/lib/tdl/elements/Reset.rb +0 -0
  1533. data/lib/tdl/elements/axi4.rb +0 -0
  1534. data/lib/tdl/elements/axi_lite.rb +0 -0
  1535. data/lib/tdl/elements/axi_stream.rb +0 -0
  1536. data/lib/tdl/elements/clock.rb +0 -0
  1537. data/lib/tdl/elements/common_configure_reg.rb +0 -0
  1538. data/lib/tdl/elements/data_inf.rb +0 -0
  1539. data/lib/tdl/elements/logic.rb +0 -2
  1540. data/lib/tdl/elements/mail_box.rb +0 -0
  1541. data/lib/tdl/elements/originclass.rb +0 -0
  1542. data/lib/tdl/elements/parameter.rb +0 -0
  1543. data/lib/tdl/elements/track_inf.rb +0 -0
  1544. data/lib/tdl/elements/videoinf.rb +0 -0
  1545. data/lib/tdl/examples/10_random/exp_random.rb +0 -0
  1546. data/lib/tdl/examples/10_random/exp_random.sv +0 -0
  1547. data/lib/tdl/examples/11_logic_latency/test_logic_latency.rb +0 -0
  1548. data/lib/tdl/examples/11_logic_latency/test_logic_latency.sv +0 -0
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  1550. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +0 -0
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  1553. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +0 -0
  1554. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +0 -0
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  1556. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +0 -0
  1557. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +0 -0
  1558. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +0 -0
  1559. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +0 -0
  1560. data/lib/tdl/examples/11_test_unit/tu0.sv +0 -0
  1561. data/lib/tdl/examples/11_test_unit/tu1.sv +0 -0
  1562. data/lib/tdl/examples/1_define_module/example1.rb +0 -0
  1563. data/lib/tdl/examples/1_define_module/exmple_md.sv +0 -0
  1564. data/lib/tdl/examples/2_hdl_class/always_comb.rb +0 -0
  1565. data/lib/tdl/examples/2_hdl_class/always_ff.rb +0 -0
  1566. data/lib/tdl/examples/2_hdl_class/case.rb +0 -0
  1567. data/lib/tdl/examples/2_hdl_class/foreach.rb +0 -0
  1568. data/lib/tdl/examples/2_hdl_class/function.rb +0 -0
  1569. data/lib/tdl/examples/2_hdl_class/generate.rb +0 -0
  1570. data/lib/tdl/examples/2_hdl_class/module_def.rb +0 -0
  1571. data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +0 -0
  1572. data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +0 -0
  1573. data/lib/tdl/examples/2_hdl_class/package.rb +0 -0
  1574. data/lib/tdl/examples/2_hdl_class/package2.rb +0 -0
  1575. data/lib/tdl/examples/2_hdl_class/simple_assign.rb +0 -0
  1576. data/lib/tdl/examples/2_hdl_class/state_case.rb +0 -0
  1577. data/lib/tdl/examples/2_hdl_class/struct.rb +0 -0
  1578. data/lib/tdl/examples/2_hdl_class/struct_function.rb +0 -0
  1579. data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +0 -0
  1580. data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +0 -0
  1581. data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +0 -0
  1582. data/lib/tdl/examples/2_hdl_class/test_module_port.rb +0 -0
  1583. data/lib/tdl/examples/2_hdl_class/test_module_var.rb +0 -0
  1584. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +0 -0
  1585. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +0 -0
  1586. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +0 -0
  1587. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +0 -0
  1588. data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +0 -0
  1589. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +0 -0
  1590. data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +0 -0
  1591. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +0 -0
  1592. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +0 -0
  1593. data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +0 -0
  1594. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +0 -0
  1595. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +0 -0
  1596. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +0 -0
  1597. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +0 -0
  1598. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +0 -0
  1599. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +0 -0
  1600. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
  1601. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +0 -0
  1602. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +0 -0
  1603. data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +0 -0
  1604. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +0 -0
  1605. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  1606. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +0 -0
  1607. data/lib/tdl/examples/2_hdl_class/vcs_string.rb +0 -0
  1608. data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +0 -0
  1609. data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +0 -0
  1610. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +0 -0
  1611. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +0 -0
  1612. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +0 -0
  1613. data/lib/tdl/examples/4_generate/example.rb +0 -0
  1614. data/lib/tdl/examples/4_generate/test_generate.sv +0 -0
  1615. data/lib/tdl/examples/5_logic_combin/login_combin.rb +0 -0
  1616. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +0 -0
  1617. data/lib/tdl/examples/6_module_with_interface/example.rb +0 -0
  1618. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +0 -0
  1619. data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +0 -0
  1620. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +0 -0
  1621. data/lib/tdl/examples/7_module_with_package/body_package.rb +0 -0
  1622. data/lib/tdl/examples/7_module_with_package/body_package.sv +0 -0
  1623. data/lib/tdl/examples/7_module_with_package/example_pkg.rb +0 -0
  1624. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +0 -0
  1625. data/lib/tdl/examples/7_module_with_package/head_package.rb +0 -0
  1626. data/lib/tdl/examples/7_module_with_package/head_package.sv +0 -0
  1627. data/lib/tdl/examples/8_top_module/dve.tcl +0 -0
  1628. data/lib/tdl/examples/8_top_module/example.rb +0 -0
  1629. data/lib/tdl/examples/8_top_module/pins.yml +0 -0
  1630. data/lib/tdl/examples/8_top_module/tb_test_top.sv +0 -0
  1631. data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +0 -0
  1632. data/lib/tdl/examples/8_top_module/test_top.sv +26 -7
  1633. data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +8 -8
  1634. data/lib/tdl/examples/8_top_module/test_top_sim.sv +7 -26
  1635. data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +0 -0
  1636. data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +0 -0
  1637. data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +0 -0
  1638. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +0 -0
  1639. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +0 -0
  1640. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +0 -0
  1641. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +0 -0
  1642. data/lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv +0 -0
  1643. data/lib/tdl/examples/9_itegration/dve.tcl +0 -0
  1644. data/lib/tdl/examples/9_itegration/pins.yml +0 -0
  1645. data/lib/tdl/examples/9_itegration/tb_test_top.sv +0 -0
  1646. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +0 -0
  1647. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
  1648. data/lib/tdl/examples/9_itegration/test_top.sv +0 -0
  1649. data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +0 -0
  1650. data/lib/tdl/examples/9_itegration/test_tttop.sv +0 -0
  1651. data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +0 -0
  1652. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +1 -1
  1653. data/lib/tdl/examples/9_itegration/top.rb +2 -2
  1654. data/lib/tdl/examples/readme.md +0 -0
  1655. data/lib/tdl/exlib/axis_eth_ex.rb +0 -0
  1656. data/lib/tdl/exlib/axis_verify.rb +0 -0
  1657. data/lib/tdl/exlib/clock_reset_verify.rb +0 -0
  1658. data/lib/tdl/exlib/common_cfg_reg_inf.rb +0 -0
  1659. data/lib/tdl/exlib/constraints.rb +0 -0
  1660. data/lib/tdl/exlib/constraints_verb.rb +4 -4
  1661. data/lib/tdl/exlib/dve_tcl.rb +0 -0
  1662. data/lib/tdl/exlib/element_class_vars.rb +0 -0
  1663. data/lib/tdl/exlib/global_param.rb +0 -0
  1664. data/lib/tdl/exlib/integral_test/bak/integral_test.rb +0 -0
  1665. data/lib/tdl/exlib/integral_test/clock_itest.rb +0 -0
  1666. data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +0 -0
  1667. data/lib/tdl/exlib/integral_test/io_itest.rb +0 -0
  1668. data/lib/tdl/exlib/integral_test/reset_itest.rb +0 -0
  1669. data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +0 -0
  1670. data/lib/tdl/exlib/itegration.rb +0 -0
  1671. data/lib/tdl/exlib/itegration_test_unit.rb +0 -0
  1672. data/lib/tdl/exlib/itegration_verb.rb +129 -13
  1673. data/lib/tdl/exlib/logic_verify.rb +0 -0
  1674. data/lib/tdl/exlib/parse_argv.rb +0 -0
  1675. data/lib/tdl/exlib/sdlmodule_sim.bak.rb +0 -0
  1676. data/lib/tdl/exlib/test_point.rb +4 -4
  1677. data/lib/tdl/exlib/test_point.rb.bak +0 -0
  1678. data/lib/tdl/global_scan.rb +0 -0
  1679. data/lib/tdl/rebuild_ele/axi4.rb +0 -0
  1680. data/lib/tdl/rebuild_ele/axi_lite.rb +0 -0
  1681. data/lib/tdl/rebuild_ele/axi_stream.rb +0 -0
  1682. data/lib/tdl/rebuild_ele/cm_ram_inf.sv +0 -0
  1683. data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +0 -0
  1684. data/lib/tdl/rebuild_ele/data_inf.rb +0 -0
  1685. data/lib/tdl/rebuild_ele/data_inf_c.rb +0 -0
  1686. data/lib/tdl/rebuild_ele/ele_base.rb +0 -0
  1687. data/lib/tdl/rebuild_ele/readme.md +0 -0
  1688. data/lib/tdl/sdlimplement/resource.yml +0 -0
  1689. data/lib/tdl/sdlimplement/sdl_impl_module.rb +0 -0
  1690. data/lib/tdl/sdlimplement/sdl_impl_param.rb +0 -0
  1691. data/lib/tdl/sdlimplement/test.rb +0 -0
  1692. data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +0 -0
  1693. data/lib/tdl/sdlmodule/generator_block_module.rb +0 -0
  1694. data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +0 -0
  1695. data/lib/tdl/sdlmodule/sdlmodule.rb +0 -0
  1696. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +0 -0
  1697. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +0 -0
  1698. data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +0 -0
  1699. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +0 -0
  1700. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +3 -3
  1701. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +0 -0
  1702. data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +0 -0
  1703. data/lib/tdl/sdlmodule/techbench_module.rb +0 -0
  1704. data/lib/tdl/sdlmodule/test_unit_module.rb +13 -3
  1705. data/lib/tdl/sdlmodule/test_unit_module.rb.bak +0 -0
  1706. data/lib/tdl/sdlmodule/top_module.rb +0 -0
  1707. data/lib/tdl/sdlmodule/top_module.rb.bak +0 -0
  1708. data/lib/tdl/tdl.rb +0 -0
  1709. data/lib/tdl/tdlerror/tdlerror.rb +0 -0
  1710. data/lib/tdl/testunit/test_all.rb +0 -0
  1711. data/lib/tdl/testunit/test_array_chain.rb +0 -0
  1712. data/lib/tdl/testunit/test_tmp.rb +0 -0
  1713. metadata +448 -6
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data/.github/workflows/gem-push.yml CHANGED
@@ -28,10 +28,10 @@ jobs:
28
28
 
29
29
  steps:
30
30
  - uses: actions/checkout@v3
31
- - name: Set up Ruby 2.6
31
+ - name: Set up Ruby 3.0
32
32
  uses: ruby/setup-ruby@477b21f02be01bcb8030d50f37cfec92bfa615b6
33
33
  with:
34
- ruby-version: 2.6
34
+ ruby-version: 3.0
35
35
  - run: bundle install
36
36
 
37
37
  - name: Publish to GPR
@@ -53,7 +53,7 @@ jobs:
53
53
  chmod 0600 $HOME/.gem/credentials
54
54
  printf -- "---\n:rubygems_api_key: ${RUBYGEMS_API_KEY}\n" > $HOME/.gem/credentials
55
55
  gem build *.gemspec
56
- gem push *.gem
56
+ gem push *.gem --key rubygems --host https://rubygems.org
57
57
  env:
58
58
  GEM_HOST_API_KEY: "${{secrets.RUBYGEMS_AUTH_TOKEN}}"
59
59
  GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
data/.github/workflows/ruby.yml CHANGED
@@ -19,7 +19,7 @@ jobs:
19
19
  runs-on: ubuntu-latest
20
20
  strategy:
21
21
  matrix:
22
- ruby-version: ['2.6','2.7', '3.0']
22
+ ruby-version: ['3.0']
23
23
 
24
24
  steps:
25
25
  - uses: actions/checkout@v2
data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_direct.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_direct_A1.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_direct_B1.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_direct_verb.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_direct_verc.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_dpram_cache.rb CHANGED
File without changes
data/lib/axi/AXI4/axi4_dpram_cache.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv CHANGED
@@ -20,6 +20,7 @@ madified:
20
20
  module axi4_long_to_axi4_wide_B1 #(
21
21
  parameter PIPE = "OFF",
22
22
  parameter PARTITION = "ON", //ON OFF
23
+ parameter MAX_DATA_LEN = 1024*2, // LEN AT MASTER.DSIZE
23
24
  `parameter_string MODE = "BOTH_to_BOTH", //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
24
25
  `parameter_string SLAVER_MODE = "BOTH", //
25
26
  `parameter_string MASTER_MODE = "BOTH" //
@@ -137,7 +138,7 @@ endgenerate
137
138
  axi4_packet_fifo_B1 #( //
138
139
  .PIPE (PIPE ),
139
140
  .DEPTH (4 ),
140
- .MAX_DATA_LEN (1024*2),
141
+ .MAX_DATA_LEN (MAX_DATA_LEN),
141
142
  .SLAVER_MODE (SLAVER_MODE ), //
142
143
  .MASTER_MODE (MASTER_MODE ) //
143
144
  )axi4_packet_fifo_inst(
data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_ram_cache.rb CHANGED
File without changes
data/lib/axi/AXI4/axi4_ram_cache.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_rd_burst_track.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv CHANGED
File without changes
data/lib/axi/AXI4/axi4_wr_burst_track.sv CHANGED
File without changes
data/lib/axi/AXI4/axi_stream_add_addr_len.sv CHANGED
File without changes
data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv CHANGED
@@ -17,9 +17,22 @@ module axi_stream_to_axi4_wr (
17
17
  localparam FIELD_LEN = 64/axis_in.DSIZE + (64%axis_in.DSIZE != 0);
18
18
 
19
19
  axi_stream_inf #(.DSIZE(axis_in.DSIZE)) ps_inf (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(axis_in.aclken));
20
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE)) ps_cache_inf (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(axis_in.aclken));
21
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE)) ps_mirror_inf (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(axis_in.aclken));
22
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE)) pipe_ps_inf (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(axis_in.aclken));
20
23
  axi_stream_inf #(.DSIZE(axi_wr_inf.IDSIZE+axi_wr_inf.ASIZE+axi_wr_inf.LSIZE))
21
24
  id_add_len_inf (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(axis_in.aclken));
22
25
 
26
+ axi_inf #(
27
+ .DSIZE(axi_wr_inf.DSIZE),
28
+ .IDSIZE(axi_wr_inf.IDSIZE),
29
+ .ASIZE(axi_wr_inf.ASIZE),
30
+ .LSIZE(axi_wr_inf.LSIZE),
31
+ .MODE(axi_wr_inf.MODE),
32
+ .ADDR_STEP(axi_wr_inf.ADDR_STEP),
33
+ .FreqM(axi_wr_inf.FreqM))
34
+ axi_wr_vcs_cp_R0000 (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
35
+
23
36
  logic[axis_in.DSIZE*FIELD_LEN-1:0] value;
24
37
 
25
38
  logic [31:0] addr;
@@ -28,6 +41,7 @@ logic addr_len_vld;
28
41
 
29
42
  assign {addr,length} = value[63:0];
30
43
 
44
+
31
45
  parse_big_field_table #(
32
46
  .DSIZE (axis_in.DSIZE ),
33
47
  .FIELD_LEN (FIELD_LEN ), //MAX 16*8
@@ -39,22 +53,54 @@ parse_big_field_table #(
39
53
  /* output logic */ .out_valid (addr_len_vld ),
40
54
  /* axi_stream_inf.slaver */ .cm_tb_s (axis_in ),
41
55
  /* axi_stream_inf.master */ .cm_tb_m (ps_inf ),
42
- /* axi_stream_inf.mirror */ .cm_mirror (axis_in )
56
+ /* axi_stream_inf.mirror */ .cm_mirror (ps_mirror_inf )
57
+ );
58
+
59
+ axi_stream_cache_verb axi_stream_cache_verb_inst(
60
+ /* axi_stream_inf.slaver */ .axis_in (ps_inf ),
61
+ /* axi_stream_inf.master */ .axis_out (ps_cache_inf )
43
62
  );
44
63
 
45
- assign ps_inf.axis_tready = axi_wr_inf.axi_awready || axi_wr_inf.axi_wready;
64
+ assign ps_mirror_inf.axis_tvalid = 1'b0;
65
+ assign ps_mirror_inf.axis_tready = 1'b0;
46
66
 
47
67
  assign id_add_len_inf.axis_tvalid = addr_len_vld;
48
68
  assign id_add_len_inf.axis_tdata = {{axi_wr_inf.IDSIZE{1'b0}},addr[axi_wr_inf.ASIZE-1:0],length[axi_wr_inf.LSIZE-1:0]};
49
69
 
50
- axi4_wr_auxiliary_gen axi4_wr_auxiliary_gen_inst(
51
- /* axi_stream_inf.slaver */ .id_add_len_in (id_add_len_inf ), //tlast is not necessary
52
- /* axi_inf.master_wr_aux */ .axi_wr_aux (axi_wr_inf )
70
+ // axi4_wr_auxiliary_gen axi4_wr_auxiliary_gen_inst(
71
+ // /* axi_stream_inf.slaver */ .id_add_len_in (id_add_len_inf ), //tlast is not necessary
72
+ // /* axi_inf.master_wr_aux */ .axi_wr_aux (axi_wr_inf )
73
+ // );
74
+
75
+ logic stream_en;
76
+
77
+ axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
78
+ /* output */.stream_en (stream_en ),
79
+ /* axi_stream_inf.slaver */.id_add_len_in (id_add_len_inf ),
80
+ /* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R0000 )
53
81
  );
54
82
 
55
- assign axi_wr_inf.axi_wdata = ps_inf.axis_tdata;
56
- assign axi_wr_inf.axi_wvalid = ps_inf.axis_tvalid;
57
- assign axi_wr_inf.axi_wlast = ps_inf.axis_tlast;
83
+ vcs_axi4_comptable #(
84
+ .ORIGIN ("master_wr_aux_no_resp" ),
85
+ .TO ("master_wr" )
86
+ )vcs_axi4_comptable_axi_wr_aux_R0001_axi_wr_inst(
87
+ /* input */.origin (axi_wr_vcs_cp_R0000 ),
88
+ /* output */.to (axi_wr_inf )
89
+ );
90
+
91
+ axis_valve_with_pipe #(
92
+ .MODE ("OUT" )
93
+ )axis_valve_with_pipe_inst(
94
+ /* input */.button (stream_en ),
95
+ /* axi_stream_inf.slaver */.axis_in (ps_cache_inf ),
96
+ /* axi_stream_inf.master */.axis_out (pipe_ps_inf )
97
+ );
98
+
99
+ assign pipe_ps_inf.axis_tready = axi_wr_inf.axi_awready || axi_wr_inf.axi_wready;
100
+
101
+ assign axi_wr_inf.axi_wdata = pipe_ps_inf.axis_tdata;
102
+ assign axi_wr_inf.axi_wvalid = pipe_ps_inf.axis_tvalid;
103
+ assign axi_wr_inf.axi_wlast = pipe_ps_inf.axis_tlast;
58
104
 
59
105
  assign axi_wr_inf.axi_wstrb = '1;
60
106
 
data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak CHANGED
File without changes
data/lib/axi/AXI4/axis_to_axi4_wr.rb CHANGED
File without changes
data/lib/axi/AXI4/axis_to_axi4_wr.sv CHANGED
File without changes
data/lib/axi/AXI4/full_axi4_to_axis.sv CHANGED
File without changes
data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv CHANGED
File without changes
data/lib/axi/AXI4/id_record.sv CHANGED
File without changes
data/lib/axi/AXI4/idata_pool_axi4.sv CHANGED
File without changes
data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv CHANGED
File without changes
data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak CHANGED
File without changes
data/lib/axi/AXI4/long_axis_to_axi4_wr.rb CHANGED
File without changes
data/lib/axi/AXI4/long_axis_to_axi4_wr.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- creaded: XXXX.XX.XX
8
+ creaded:
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/axi/AXI4/odata_pool_axi4.sv CHANGED
File without changes
data/lib/axi/AXI4/odata_pool_axi4_A1.sv CHANGED
File without changes
data/lib/axi/AXI4/odata_pool_axi4_A2.sv CHANGED
File without changes
data/lib/axi/AXI4/odata_pool_axi4_A3.sv CHANGED
File without changes
data/lib/axi/AXI4/odata_pool_axi4_A4.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv CHANGED
@@ -130,10 +130,18 @@ axi_stream_inf #(
130
130
  // /* axi_stream_inf.master */ .axis_out (axis_valve_slaver )
131
131
  // );
132
132
 
133
- axi_stream_packet_long_fifo #(
134
- .DEPTH (DEPTH), //2-4
135
- .BYTE_DEPTH (MAX_DATA_LEN)
136
- )axi_stream_packet_fifo_inst(
133
+ // axi_stream_packet_long_fifo #(
134
+ // .DEPTH (DEPTH), //2-4
135
+ // .BYTE_DEPTH (MAX_DATA_LEN)
136
+ // )axi_stream_packet_fifo_inst(
137
+ // /* axi_stream_inf.slaver */ .axis_in (axis_in ),
138
+ // /* axi_stream_inf.master */ .axis_out (axis_valve_slaver )
139
+ // );
140
+
141
+ axi_stream_long_fifo #(
142
+ .DEPTH (DEPTH ),
143
+ .BYTE_DEPTH (MAX_DATA_LEN )
144
+ )axi_stream_long_fifo_inst(
137
145
  /* axi_stream_inf.slaver */ .axis_in (axis_in ),
138
146
  /* axi_stream_inf.master */ .axis_out (axis_valve_slaver )
139
147
  );
data/lib/axi/AXI4/packet_merge/axi4_merge.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_partition/axi4_partition.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv CHANGED
@@ -13,7 +13,7 @@ madified:
13
13
  `timescale 1ns/1ps
14
14
  module axi4_partition_OD #(
15
15
  parameter PSIZE = 128, //master side
16
- // parameter real ADDR_STEP = 1
16
+ parameter EXIDSIZE = 4,
17
17
  parameter FORCE_MODE = 99 // 0: BOTH ,1: WRITE, 2: READ
18
18
  )(
19
19
  axi_inf.slaver slaver,
@@ -44,7 +44,8 @@ end
44
44
  generate
45
45
  if((FORCE_MODE>2 && (slaver.MODE=="BOTH" || slaver.MODE=="ONLY_WRITE")) || FORCE_MODE==0 || FORCE_MODE==1)
46
46
  axi4_partition_wr_OD #(
47
- .PSIZE (PSIZE )
47
+ .PSIZE (PSIZE ),
48
+ .EXIDSIZE (EXIDSIZE )
48
49
  // .ADDR_STEP (ADDR_STEP )
49
50
  )axi4_partition_wr_inst(
50
51
  /* axi_inf.slaver_wr */ .axi_in (`slaver_vcs_cptWrite ),
data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb CHANGED
@@ -1,6 +1,6 @@
1
1
  add_to_tdl_paths __dir__
2
2
  require_sdl 'data_inf_partition.rb'
3
-
3
+ require_shdl 'data_inf_partition_A1'
4
4
  TdlBuild.axi4_partition_rd_verb(__dir__) do
5
5
  parameter.PSIZE 128
6
6
  port.axi4.slaver_rd - 'long_inf'
@@ -9,17 +9,26 @@ TdlBuild.axi4_partition_rd_verb(__dir__) do
9
9
  long_inf.clock_reset_taps('clock','rst_n')
10
10
 
11
11
  data_inf_c(clock: clock,reset: rst_n,dsize: "#{long_inf.IDSIZE}+#{long_inf.LSIZE}+#{long_inf.ASIZE}".to_nq) - 'pre_partition_data_inf'
12
- data_inf_c(clock: clock,reset: rst_n,dsize: "#{short_inf.IDSIZE}+#{long_inf.LSIZE}+#{long_inf.ASIZE}".to_nq) - 'post_partition_data_inf'
12
+ data_inf_c(clock: clock,reset: rst_n,dsize: "#{short_inf.IDSIZE}+#{short_inf.LSIZE}+#{short_inf.ASIZE}".to_nq) - 'post_partition_data_inf'
13
13
  data_inf_c(clock: clock,reset: rst_n,dsize: 1) - 'partition_pulse_inf'
14
14
  data_inf_c(clock: clock,reset: rst_n,dsize: 1) - 'wait_last_inf'
15
15
 
16
- data_inf_partition.data_inf_partition_inst do |h|
16
+ data_inf_partition_A1.data_inf_partition_inst do |h|
17
17
  h.param.PLEN param.PSIZE
18
- h.param.IDSIZE long_inf.IDSIZE
19
- h.param.LSIZE long_inf.LSIZE
18
+ # h.param.IDSIZE long_inf.IDSIZE
19
+ # h.param.LSIZE long_inf.LSIZE
20
+
21
+ h.param.IASIZE long_inf.ASIZE
22
+ h.param.ILSIZE long_inf.LSIZE
23
+ h.param.IIDSIZE long_inf.IDSIZE
24
+
25
+ h.param.OASIZE short_inf.ASIZE
26
+ h.param.OLSIZE short_inf.LSIZE
27
+ h.param.OIDSIZE short_inf.IDSIZE
28
+
20
29
  h.param.ADDR_STEP long_inf.ADDR_STEP
21
- h.port.data_inf_c.slaver.data_in pre_partition_data_inf #[in ID..][ADDR...][LENGTH| LSIZE-1:0] length `0 mean 1
22
- h.port.data_inf_c.master.data_out post_partition_data_inf #[out ID 4bit][in ID..][LENGTH| LSIZE-1:0]
30
+ h.port.data_inf_c.slaver.data_in pre_partition_data_inf #[in ID][ADDR...][LENGTH| LSIZE-1:0] length `0 mean 1
31
+ h.port.data_inf_c.master.data_out post_partition_data_inf #[out ID][in ID..][LENGTH| LSIZE-1:0]
23
32
  h.port.data_inf_c.master.partition_pulse_inf partition_pulse_inf
24
33
  h.port.data_inf_c.master.wait_last_inf wait_last_inf
25
34
  end
data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- creaded:
8
+ created: 2025-11-23 20:52:34 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -21,18 +21,22 @@ module axi4_partition_rd_verb #(
21
21
  //-------- define ----------------------------------------------------------
22
22
  logic clock;
23
23
  logic rst_n;
24
- (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_empty;
25
- (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_full;
24
+ logic fifo_empty;
25
+ logic fifo_full;
26
26
  data_inf_c #(.DSIZE(long_inf.IDSIZE+long_inf.LSIZE+long_inf.ASIZE),.FreqM(long_inf.FreqM)) pre_partition_data_inf (.clock(clock),.rst_n(rst_n)) ;
27
- data_inf_c #(.DSIZE(short_inf.IDSIZE+long_inf.LSIZE+long_inf.ASIZE),.FreqM(long_inf.FreqM)) post_partition_data_inf (.clock(clock),.rst_n(rst_n)) ;
27
+ data_inf_c #(.DSIZE(short_inf.IDSIZE+short_inf.LSIZE+short_inf.ASIZE),.FreqM(long_inf.FreqM)) post_partition_data_inf (.clock(clock),.rst_n(rst_n)) ;
28
28
  data_inf_c #(.DSIZE(1),.FreqM(long_inf.FreqM)) partition_pulse_inf (.clock(clock),.rst_n(rst_n)) ;
29
29
  data_inf_c #(.DSIZE(1),.FreqM(long_inf.FreqM)) wait_last_inf (.clock(clock),.rst_n(rst_n)) ;
30
30
  //==========================================================================
31
31
  //-------- instance --------------------------------------------------------
32
- data_inf_partition #(
32
+ data_inf_partition_A1 #(
33
33
  .PLEN (PSIZE ),
34
- .LSIZE (long_inf.LSIZE ),
35
- .IDSIZE (long_inf.IDSIZE ),
34
+ .IASIZE (long_inf.ASIZE ),
35
+ .ILSIZE (long_inf.LSIZE ),
36
+ .IIDSIZE (long_inf.IDSIZE ),
37
+ .OASIZE (short_inf.ASIZE ),
38
+ .OLSIZE (short_inf.LSIZE ),
39
+ .OIDSIZE (short_inf.IDSIZE ),
36
40
  .ADDR_STEP (long_inf.ADDR_STEP )
37
41
  )data_inf_partition_inst(
38
42
  /* data_inf_c.slaver */.data_in (pre_partition_data_inf ),
@@ -41,8 +45,8 @@ data_inf_partition #(
41
45
  /* data_inf_c.master */.wait_last_inf (wait_last_inf )
42
46
  );
43
47
  common_fifo #(
44
- .DEPTH (6 ),
45
- .DSIZE (1 )
48
+ .DEPTH (6 ),
49
+ .DSIZE (1 )
46
50
  )common_fifo_inst(
47
51
  /* input */.clock (clock ),
48
52
  /* input */.rst_n (rst_n ),
data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv CHANGED
File without changes
data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv CHANGED
@@ -11,7 +11,8 @@ madified:
11
11
  ***********************************************/
12
12
  `timescale 1ns/1ps
13
13
  module axi4_partition_wr_OD #(
14
- parameter PSIZE = 128
14
+ parameter PSIZE = 128,
15
+ parameter EXIDSIZE = 4
15
16
  // parameter real ADDR_STEP = 1
16
17
  )(
17
18
  axi_inf.slaver_wr axi_in,
@@ -20,13 +21,13 @@ module axi4_partition_wr_OD #(
20
21
 
21
22
  import SystemPkg::*;
22
23
 
23
- initial begin
24
- assert(axi_in.IDSIZE+4 == axi_out.IDSIZE)
25
- else begin
26
- $error("SLAVER AXIS IDSIZE+4 != MASTER AXIS IDSIZE");
27
- $stop;
28
- end
29
- end
24
+ // initial begin
25
+ // assert(axi_in.IDSIZE+EXIDSIZE == axi_out.IDSIZE)
26
+ // else begin
27
+ // $error("SLAVER AXIS IDSIZE+4 != MASTER AXIS IDSIZE");
28
+ // $stop;
29
+ // end
30
+ // end
30
31
 
31
32
  logic clock,rst_n;
32
33
 
@@ -284,7 +285,7 @@ assign axi_out.axi_wlast = axis_out.axis_tlast;
284
285
  assign axis_out.axis_tready= axi_out.axi_wready;
285
286
  //----<< DATA STREAM >>------------------------
286
287
  //---->> WID CTRL <<---------------------------
287
- logic [axi_in.IDSIZE+4-1:0] awid;
288
+ logic [15:0] awid;
288
289
  always@(posedge clock,negedge rst_n)
289
290
  if(~rst_n) awid <= '0;
290
291
  else begin
@@ -292,7 +293,7 @@ always@(posedge clock,negedge rst_n)
292
293
  awid <= axi_in.axi_awid;
293
294
  else if(axi_out.axi_awvalid && axi_out.axi_awready)begin
294
295
  if(length > PSIZE)
295
- awid[3:0] <= awid[3:0] + 1'b1;
296
+ awid[15:0] <= awid[15:0] + 1'b1;
296
297
  else awid <= '0;
297
298
  end else awid <= awid;
298
299
  end
data/lib/axi/AXI4/packet_partition/data_inf_partition.rb CHANGED
File without changes
data/lib/axi/AXI4/packet_partition/data_inf_partition.sv CHANGED
@@ -41,8 +41,8 @@ logic track_st5;
41
41
  //==========================================================================
42
42
  //-------- instance --------------------------------------------------------
43
43
  common_fifo #(
44
- .DEPTH (6 ),
45
- .DSIZE (data_out.DSIZE )
44
+ .DEPTH (6 ),
45
+ .DSIZE (data_out.DSIZE )
46
46
  )common_fifo_inst(
47
47
  /* input */.clock (data_in.clock ),
48
48
  /* input */.rst_n (data_in.rst_n ),