axi_tdl 0.2.4 → 0.2.7
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +3 -3
- data/.github/workflows/ruby.yml +1 -1
- data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +0 -0
- data/lib/axi/AXI4/axi4_direct.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_B1.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +0 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +0 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +2 -1
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_ram_cache.rb +0 -0
- data/lib/axi/AXI4/axi4_ram_cache.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +0 -0
- data/lib/axi/AXI4/axi_stream_add_addr_len.sv +0 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +54 -8
- data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +0 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +0 -0
- data/lib/axi/AXI4/full_axi4_to_axis.sv +0 -0
- data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +0 -0
- data/lib/axi/AXI4/id_record.sv +0 -0
- data/lib/axi/AXI4/idata_pool_axi4.sv +0 -0
- data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +4 -2
- data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +4 -2
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +0 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI4/odata_pool_axi4.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A1.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A2.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A4.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +12 -4
- data/lib/axi/AXI4/packet_merge/axi4_merge.sv +0 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +0 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +3 -2
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +20 -9
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +13 -9
- data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +11 -10
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +0 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI4/packet_partition/data_inf_partition_A1.rb +298 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition_A1.sv +316 -0
- data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +0 -0
- data/lib/axi/AXI4/vcs_axi4_comptable.sv +0 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb.bk +150 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +2 -2
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv +0 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv.bak +0 -0
- data/lib/axi/AXI4/width_convert/data_destruct.sv +0 -0
- data/lib/axi/AXI4/width_convert/feed_check.sv +0 -0
- data/lib/axi/AXI4/width_convert/len_convert.sv.bak +0 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +0 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_combin.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_destruct.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +0 -0
- data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +0 -0
- data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +0 -0
- data/lib/axi/AXI_BFM/axi4_error_chk.sv +0 -0
- data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +0 -0
- data/lib/axi/AXI_BFM/axi_lite_master.sv +0 -0
- data/lib/axi/AXI_BFM/axi_lite_tb.sv +0 -0
- data/lib/axi/AXI_BFM/axi_master.sv +0 -0
- data/lib/axi/AXI_BFM/axi_mirror.sv +0 -0
- data/lib/axi/AXI_BFM/axi_mm_tb.sv +0 -0
- data/lib/axi/AXI_BFM/axi_slaver.sv.bak +0 -0
- data/lib/axi/AXI_BFM/axistreambfm.sv +0 -0
- data/lib/axi/AXI_Lite/axi4_to_lite.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +4 -5
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M_verb.sv +322 -0
- data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +0 -0
- data/lib/axi/AXI_Lite/axil_direct.sv +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +0 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +0 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +26 -5
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_latency.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_partition.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_planer.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +0 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +26 -26
- data/lib/axi/AXI_stream/axi_streams_combin.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_append.sv +0 -0
- data/lib/axi/AXI_stream/axis_append_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_base_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +0 -0
- data/lib/axi/AXI_stream/axis_direct.sv +0 -0
- data/lib/axi/AXI_stream/axis_direct_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_ex_status.sv +97 -0
- data/lib/axi/AXI_stream/axis_ex_status.sv.bk +97 -0
- data/lib/axi/AXI_stream/axis_filter.sv +0 -0
- data/lib/axi/AXI_stream/axis_full_to_data_c.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +6 -6
- data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +0 -0
- data/lib/axi/AXI_stream/axis_insert_copy.rb +0 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -0
- data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_cut.sv +1 -1
- data/lib/axi/AXI_stream/axis_length_fill.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_fill_verb.sv +195 -0
- data/lib/axi/AXI_stream/axis_length_split.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr_A1.sv +128 -0
- data/lib/axi/AXI_stream/axis_length_split_with_user.sv +0 -0
- data/lib/axi/AXI_stream/axis_link_trigger.sv +0 -0
- data/lib/axi/AXI_stream/axis_master_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master.sv +0 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master_verb.sv +141 -0
- data/lib/axi/AXI_stream/axis_mirrors.sv +0 -0
- data/lib/axi/AXI_stream/axis_orthogonal.sv +0 -0
- data/lib/axi/AXI_stream/axis_padding.rb +44 -0
- data/lib/axi/AXI_stream/axis_padding.sv +65 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +0 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -0
- data/lib/axi/AXI_stream/axis_ram_buffer.sv +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect.rb +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect.sv +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +0 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +0 -0
- data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +0 -0
- data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +0 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +3 -3
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +0 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_data_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_lite_rd.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_lite_wr.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.rb +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_valve.sv +0 -0
- data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.rb +0 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +0 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +0 -0
- data/lib/axi/AXI_stream/check_stream_crc.sv +0 -0
- data/lib/axi/AXI_stream/data_c_to_axis_full.sv +0 -0
- data/lib/axi/AXI_stream/data_to_axis_inf.sv +0 -0
- data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +0 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +0 -0
- data/lib/axi/AXI_stream/gen_common_frame_table.sv +0 -0
- data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A3.sv +163 -0
- data/lib/axi/AXI_stream/gen_simple_axis.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +8 -5
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +9 -7
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +5 -4
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo_A1.sv +221 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep_A1.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table_A1.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table_main.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table_mirror.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table_slaver.sv +162 -0
- data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +0 -0
- data/lib/axi/AXI_stream/parse_common_frame_table.sv +0 -0
- data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv +0 -0
- data/lib/axi/AXI_stream/parse_common_frame_table_A2.sv +0 -0
- data/lib/axi/AXI_stream/parse_common_frame_table_slaver.sv +546 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_35bit.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_36_71bit.sv +1 -1
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit_with_keep.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_96_143bit.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_A1.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_B1.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_compact_verb.sv +58 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_verb.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +0 -0
- data/lib/axi/AXI_stream/stream_crc.sv +0 -0
- data/lib/axi/AXI_stream/vcs_axis_comptable.sv +0 -0
- data/lib/axi/LICENSE +0 -0
- data/lib/axi/ReadME.md +0 -0
- data/lib/axi/SIM/tb_axi4_partition_20201105.sv +0 -0
- data/lib/axi/SIM/tb_axis_bfm_0504.sv +0 -0
- data/lib/axi/SIM/tb_axis_partitiom_0929.sv +0 -0
- data/lib/axi/SIM/tb_axis_s2m_pipe_1023.sv +0 -0
- data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +0 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +0 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +0 -0
- data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +0 -0
- data/lib/axi/SIM/tb_wide_axis_to_axi4_wr.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C1.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verb.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verc.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_wrapper_sim.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_axi4_to_axis.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A1.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_verb.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/tb_ddr3_ip_wrapper_sim.sv +0 -0
- data/lib/axi/cfg.yml +0 -0
- data/lib/axi/common/ClockSameDomain.sv +0 -0
- data/lib/axi/common/common_ram_sim_wrapper.rb +0 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +0 -0
- data/lib/axi/common/common_ram_wrapper.rb +0 -0
- data/lib/axi/common/common_ram_wrapper.sv +2 -2
- data/lib/axi/common/data_c_interface_dram.rb +0 -0
- data/lib/axi/common/data_c_interface_dram.sv +0 -0
- data/lib/axi/common/mem_format.coe +0 -0
- data/lib/axi/common/pipe_vld.sv +0 -0
- data/lib/axi/common/test_write_mem.sv +0 -0
- data/lib/axi/common/xilinx_hdl_dpram.sv +0 -0
- data/lib/axi/common/xilinx_hdl_dpram_sim.sv +0 -0
- data/lib/axi/common_fifo/common_fifo.sv +2 -1
- data/lib/axi/common_fifo/common_stack.sv +0 -0
- data/lib/axi/common_fifo/independent_clock_fifo.sv +0 -0
- data/lib/axi/common_fifo/independent_clock_fifo_a1.sv +0 -0
- data/lib/axi/common_fifo/independent_stack.sv +0 -0
- data/lib/axi/data_interface/data_connect_pipe.sv +0 -0
- data/lib/axi/data_interface/data_inf_A2B.sv +0 -0
- data/lib/axi/data_interface/data_inf_B2A.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_bind.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_cache.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_direct.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_direct_mirror.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.rb.bak +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_left_shift.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift_verb.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_last.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +14 -14
- data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_condition_mirror.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_condition_valve.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_connect_pipe_inf.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_M2S_with_addr_and_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_M2S_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_with_lazy.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_interconnect_M2S.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_pipe_condition.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_planer.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_intc_M2S_force_robin.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_mirrors.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_mirrors_verb.sv.bak +0 -0
- data/lib/axi/data_interface/data_inf_c/data_uncompress.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_valve.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/next_prio.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/trigger_ready_ctrl.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/vcs_data_c_comptable.sv +0 -0
- data/lib/axi/data_interface/data_inf_cross_clk.sv +0 -0
- data/lib/axi/data_interface/data_inf_intc_M2S_force_addr_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_intc_M2S_prio.sv +0 -0
- data/lib/axi/data_interface/data_inf_intc_M2S_prio_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_interconnect_M2S_noaddr.sv +0 -0
- data/lib/axi/data_interface/data_inf_interconnect_M2S_with_id_noaddr.sv +0 -0
- data/lib/axi/data_interface/data_inf_planer.sv +0 -0
- data/lib/axi/data_interface/data_inf_planer_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_ticktock.sv +0 -0
- data/lib/axi/data_interface/data_interface.sv +0 -0
- data/lib/axi/data_interface/data_interface_pkg.sv +0 -0
- data/lib/axi/data_interface/data_pair_map.sv +0 -0
- data/lib/axi/data_interface/data_pair_map_A1.sv +0 -0
- data/lib/axi/data_interface/data_pair_map_A2.sv +0 -0
- data/lib/axi/data_interface/data_pipe_intc_M2S_addr.sv.bak +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv.bak1012 +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv.bad_work +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_S2M.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_S2M_A1.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_S2M_verb.sv +0 -0
- data/lib/axi/data_interface/data_streams_combin.sv +0 -0
- data/lib/axi/data_interface/data_streams_combin_A1.sv +0 -0
- data/lib/axi/data_interface/data_streams_scaler.sv +0 -0
- data/lib/axi/data_interface/datainf_c_master_empty.sv +0 -0
- data/lib/axi/data_interface/datainf_c_slaver_empty.sv +0 -0
- data/lib/axi/data_interface/datainf_master_empty.sv +0 -0
- data/lib/axi/data_interface/datainf_slaver_empty.sv +0 -0
- data/lib/axi/data_interface/part_data_pair_map.sv +0 -0
- data/lib/axi/interface_define/axi_aux_inf.sv +0 -0
- data/lib/axi/interface_define/axi_inf.sv +0 -0
- data/lib/axi/interface_define/axi_inf_verb.sv +0 -0
- data/lib/axi/interface_define/axi_interface_instance.svo +0 -0
- data/lib/axi/interface_define/axi_lite_inf.sv +0 -0
- data/lib/axi/interface_define/axi_stream_inf.sv +0 -0
- data/lib/axi/interface_define/bak/axi_aux_inf.sv +0 -0
- data/lib/axi/interface_define/bak/axi_inf_verb.sv +0 -0
- data/lib/axi/interface_define/bak/axi_interface_instance.svo +0 -0
- data/lib/axi/interface_define/bak/microblaze_inf.sv +0 -0
- data/lib/axi/interface_define/bak/xilinx_axi4_to_axi4.sv +0 -0
- data/lib/axi/interface_define/bak/xilinx_lite_to_lite.sv +0 -0
- data/lib/axi/interface_define/lite_inf2_to_inf.sv +0 -0
- data/lib/axi/interface_define/xilinx_axi4_to_axi4.sv +0 -0
- data/lib/axi/interface_define/xilinx_lite_to_lite.sv +0 -0
- data/lib/axi/macro/RTL/define_macro.sv +0 -0
- data/lib/axi/macro/SIM/define_macro.sv +0 -0
- data/lib/axi/macro/axil_macro.sv +0 -0
- data/lib/axi/macro/bak/axi4_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/axi_macro.sv +0 -0
- data/lib/axi/macro/bak/axis_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/data_inf_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/lite_inf_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/standard_tcl.rb +0 -0
- data/lib/axi/macro/bak/system_macro.sv +0 -0
- data/lib/axi/macro/bak/tcl_axi4_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/tcl_axis_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/tcl_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/tcl_data_inf_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/tcl_lite_inf_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/tcl_tmp.tcl +0 -0
- data/lib/axi/macro/bak/tmp.tcl +0 -0
- data/lib/axi/platform_ip/fifo_10_18bit_long.sv +0 -0
- data/lib/axi/platform_ip/fifo_145_216bit_A1.sv +0 -0
- data/lib/axi/platform_ip/fifo_217_288bit_A1.sv +0 -0
- data/lib/axi/platform_ip/fifo_36bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_36bit_A1.sv +0 -0
- data/lib/axi/platform_ip/fifo_36kb_long.sv +11 -5
- data/lib/axi/platform_ip/fifo_37_72bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_505_576bit_A1.sv +0 -0
- data/lib/axi/platform_ip/fifo_73_96bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_97_144bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_97_144bit_A1.sv +0 -0
- data/lib/axi/platform_ip/fifo_ku.sv +0 -0
- data/lib/axi/platform_ip/fifo_ku.sv.bak +0 -0
- data/lib/axi/platform_ip/fifo_ku_18bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_ku_36bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_ku_36kb_long.sv +0 -0
- data/lib/axi/platform_ip/fifo_ku_xbit_8192.sv.bak +0 -0
- data/lib/axi/platform_ip/fifo_wr_rd_mark.sv +0 -0
- data/lib/axi/platform_ip/ku_long_fifo_4bit.sv +0 -0
- data/lib/axi/platform_ip/long_fifo.sv +0 -0
- data/lib/axi/platform_ip/long_fifo_4bit.sv +0 -0
- data/lib/axi/platform_ip/long_fifo_4bit_8192.sv +0 -0
- data/lib/axi/platform_ip/long_fifo_4bit_SL8192.sv +0 -0
- data/lib/axi/platform_ip/long_fifo_9bit_SL4096.sv.new +138 -0
- data/lib/axi/platform_ip/long_fifo_verb.sv +0 -0
- data/lib/axi/platform_ip/long_fifo_xbit.sv.new +132 -0
- data/lib/axi/platform_ip/long_fifo_xbit_SL.sv.new +147 -0
- data/lib/axi/platform_ip/wide_fifo.sv +0 -0
- data/lib/axi/platform_ip/wide_fifo_7series.sv +0 -0
- data/lib/axi/platform_ip/xilinx_fifo.sv +0 -0
- data/lib/axi/platform_ip/xilinx_fifo_A1.sv +0 -0
- data/lib/axi/platform_ip/xilinx_fifo_verb.sv +0 -0
- data/lib/axi/platform_ip/xilinx_fifo_verc.sv +0 -0
- data/lib/axi/platform_ip/xilinx_stream_packet_fifo_ip.sv +0 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +0 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +0 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.rb +0 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.sv +0 -0
- data/lib/axi/top/axi4_data_convert_2_20_tb.sv +0 -0
- data/lib/axi/top/axi4_data_convert_5_24_tb.sv +0 -0
- data/lib/axi/top/axi4_interconnnect_2_24_tb.sv +0 -0
- data/lib/axi/top/axi4_interconnnect_5_23_tb.sv +0 -0
- data/lib/axi/top/axi4_merge_tb_0331.sv +0 -0
- data/lib/axi/top/axi4_packet_fifo_2_28_tb.sv +0 -0
- data/lib/axi/top/axi4_partition_2_23_tb.sv +0 -0
- data/lib/axi/top/axi_stream_packet_fifo_2_28_tb.sv +0 -0
- data/lib/axi/top/axis_length_cut_2_28_tb.sv +0 -0
- data/lib/axi/top/axis_length_fill_8_18_tb.sv +0 -0
- data/lib/axi/top/common_fifo_2_27_tb.sv +0 -0
- data/lib/axi/top/data_convert_2_16_tb.sv +0 -0
- data/lib/axi/top/independent_fifo_2_27_tb.sv +0 -0
- data/lib/axi/top/long_to_wide_3_1_tb.sv +0 -0
- data/lib/axi/top/odd_width_convert_tb_420.sv +0 -0
- data/lib/axi/top/tb_axis_m2s_A1_0115.sv +0 -0
- data/lib/axi/top/tb_axis_width_combin_0913.sv +0 -0
- data/lib/axi/top/tb_axis_width_test_0914.sv +0 -0
- data/lib/axi/top/tb_data_c_inf_M2S_0823.sv +0 -0
- data/lib/axi/top/tb_data_c_inf_M2S_addr_0824.sv +0 -0
- data/lib/axi/top/tb_data_c_pipe_force_vld_1228.sv +0 -0
- data/lib/axi/top/tb_data_c_scaler_20180413.sv +0 -0
- data/lib/axi/top/tb_data_intc_S2M_0807.sv +0 -0
- data/lib/axi/top/tb_test_ku_fifo_0919.sv +0 -0
- data/lib/axi/top/width_convert_verb_tb_523.sv +0 -0
- data/lib/axi/video/video_stream_2_axi_stream.sv +0 -0
- data/lib/axi/video_interface/video_interface.sv +0 -0
- data/lib/axi/xilinx_clock_reset/xilinx_preclock_block.sv +49 -0
- data/lib/axi/xilinx_clock_reset/xilinx_reset_sync.v +91 -0
- data/lib/axi/xilinx_clock_reset/xilinx_reset_sync_A1.sv +112 -0
- data/lib/axi/xilinx_clock_reset/xilinx_share_reset.sv +123 -0
- data/lib/axi/xilinx_clock_reset/xilinx_sync_block.v +90 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/axi_tdl.rb +3 -0
- data/lib/public_atom_module/CheckPClock.sv +0 -0
- data/lib/public_atom_module/LICENSE.md +0 -0
- data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +0 -0
- data/lib/public_atom_module/bits_decode.sv +0 -0
- data/lib/public_atom_module/bits_decode_verb.sv +0 -0
- data/lib/public_atom_module/bits_decode_verb_sdl.rb +0 -0
- data/lib/public_atom_module/broaden.v +0 -0
- data/lib/public_atom_module/broaden_and_cross_clk.v +0 -0
- data/lib/public_atom_module/ceiling.v +0 -0
- data/lib/public_atom_module/ceiling_A1.v +0 -0
- data/lib/public_atom_module/clock_rst.sv +0 -0
- data/lib/public_atom_module/cross_clk_sync.v +0 -0
- data/lib/public_atom_module/edge_generator.v +0 -0
- data/lib/public_atom_module/flooring.v +0 -0
- data/lib/public_atom_module/latch_data.v +0 -0
- data/lib/public_atom_module/latency.v +0 -0
- data/lib/public_atom_module/latency_dynamic.v +0 -0
- data/lib/public_atom_module/latency_long.v +0 -0
- data/lib/public_atom_module/latency_verb.v +0 -0
- data/lib/public_atom_module/once_event.sv +0 -0
- data/lib/public_atom_module/pipe_reg.v +0 -0
- data/lib/public_atom_module/pipe_reg_2write_ports.v +0 -0
- data/lib/public_atom_module/sim/clock_rst_verb.sv +0 -0
- data/lib/public_atom_module/sim/clock_rst_verc.sv +0 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv +0 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv.bak +0 -0
- data/lib/public_atom_module/sim_system_pkg.sv +0 -0
- data/lib/public_atom_module/synth_system_pkg.sv +0 -0
- data/lib/tdl/LICENSE +0 -0
- data/lib/tdl/Logic/Logic.tar.gz +0 -0
- data/lib/tdl/Logic/clock_rst_verb_auto.rb +0 -0
- data/lib/tdl/Logic/logic_edge.rb +0 -0
- data/lib/tdl/Logic/logic_latency.rb +0 -0
- data/lib/tdl/Logic/logic_main.rb +0 -0
- data/lib/tdl/Logic/logic_operator.rb.bak +0 -0
- data/lib/tdl/Logic/mdio_model_auto.rb +0 -0
- data/lib/tdl/Logic/path_lib.rb +0 -0
- data/lib/tdl/Logic/redefine_operator.rb +0 -0
- data/lib/tdl/ReadMe.md +0 -0
- data/lib/tdl/SDL/axi4/AXI4_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_combin_wr_rd_batch_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_data_convert_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_data_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_direct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_direct_B1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_direct_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_direct_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_direct_verc_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_track_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_merge_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_merge_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_merge_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_mix_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_OD_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_rd_OD_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_batch_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/data_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/feed_check_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/id_record_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_append_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +0 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/common_stack_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +0 -0
- data/lib/tdl/SDL/path_lib.rb +0 -0
- data/lib/tdl/SDL/vcs_axi4_comptable.rb +0 -0
- data/lib/tdl/SDL/vcs_axis_comptable.rb +0 -0
- data/lib/tdl/SDL/vcs_data_c_comptable.rb +0 -0
- data/lib/tdl/VideoInf/simple_video_gen.rb +0 -0
- data/lib/tdl/VideoInf/video_from_axi4.rb +0 -0
- data/lib/tdl/VideoInf/video_lib.rb +0 -0
- data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +0 -0
- data/lib/tdl/VideoInf/video_to_axi4.rb +0 -0
- data/lib/tdl/auto_script/auto_gen_tdl.rb +0 -0
- data/lib/tdl/auto_script/autogensdl.rb +0 -0
- data/lib/tdl/auto_script/autogentdl_a2.rb +0 -0
- data/lib/tdl/auto_script/import_hdl.rb +0 -0
- data/lib/tdl/auto_script/import_sdl.rb +0 -0
- data/lib/tdl/auto_script/test_autogensdl.rb +0 -0
- data/lib/tdl/auto_script/tmp/MAC_FCS_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/TPU_reprogram_wrapper_verb_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_B1_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_gray_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verb_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_diffr_pca9557_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_diffr_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_verc_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_array_x7_gray_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/adc_1015_tpu_wrapper_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A1_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A2_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A3_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A4_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A5_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/aec_alarm_check_A6_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/arp_tpu_wrapper_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/axi4_combin_wr_rd_batch_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axi4_data_convert_verb_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/axi4_direct_A1_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/axi4_direct_B1_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axi4_direct_algin_addr_step_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/axi4_direct_verc_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/axi4_long_to_axi4_wide_B1_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/axi4_packet_fifo_B1_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/axi4_partition_OD_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/axi4_partition_wr_OD_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/axi4_ps_convert_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/axi4_to_native_for_ddr_ip_C1_sdl.rb +24 -0
- data/lib/tdl/auto_script/tmp/axi4_wr_auxiliary_gen_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axi4_wr_auxiliary_gen_without_resp_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axi4_wr_interconnect_M2S_A1_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axi4_wr_pipe_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axi_stream_cache_35bit_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axi_stream_cache_36_71bit_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axi_stream_cache_A1_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axi_stream_cache_compact_verb_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axi_stream_cache_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axi_stream_cache_verb_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axi_stream_interconnect_M2S_A1_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/axi_stream_interconnect_S2M_auto_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/axi_stream_interconnect_S2M_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/axi_stream_long_cache_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axi_stream_long_fifo_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/axi_stream_long_fifo_verb_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/axi_stream_packet_fifo_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axi_stream_packet_fifo_with_info_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/axi_stream_packet_long_fifo_A1_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/axi_stream_packet_long_fifo_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/axi_stream_planer_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/axi_stream_to_axi4_wr_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axi_stream_wide_fifo_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axi_streams_combin_A1_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/axi_streams_scaler_A1_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/axis_append_A1_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_verb_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/axis_connect_pipe_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axis_connect_pipe_with_info_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/axis_direct_A1_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/axis_direct_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axis_ex_status_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/axis_head_cut_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_head_cut_verb_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_intc_S2M_with_addr_inf_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/axis_length_cut_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_length_fill_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_length_fill_verb_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/axis_length_split_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_length_split_with_addr_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/axis_length_split_with_user_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_master_empty_sdl.rb +9 -0
- data/lib/tdl/auto_script/tmp/axis_mirror_to_master_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_A1_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_slaver_empty_sdl.rb +9 -0
- data/lib/tdl/auto_script/tmp/axis_slaver_pipe_A1_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_slaver_pipe_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axis_uncompress_A1_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/axis_uncompress_verb_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/axis_valve_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/axis_valve_with_pipe_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/axis_width_convert_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/axis_width_convert_verb_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/axis_width_destruct_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/board_cs_ctrl_gray_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/board_cs_ctrl_gray_x7_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/broaden_and_cross_clk_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/cbct_chip_reg_dport_wrapper_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/cbct_chip_reg_wrapper_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/cbct_iic_bus_tri_wrapper_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/cbct_iic_bus_wrapper_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/cbct_lock_lvds_data_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/cbct_sensor_driver_array_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/cbct_sensor_driver_clock_A1_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/cbct_sensor_driver_clock_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/cbct_single_sensor_lvds_dir_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_phase_upgrade_sdl.rb +25 -0
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_gray_sdl.rb +24 -0
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_sdl.rb +25 -0
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_slot_gray_sdl.rb +24 -0
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_speci_gray_sdl.rb +24 -0
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_verb_sdl.rb +24 -0
- data/lib/tdl/auto_script/tmp/chip_reg_tpu_wrapper_x7_gray_sdl.rb +24 -0
- data/lib/tdl/auto_script/tmp/chip_spi_model_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/clock_lvds_bitslip_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/clock_manager_A2_sdl.rb +25 -0
- data/lib/tdl/auto_script/tmp/clock_manager_B2_sdl.rb +26 -0
- data/lib/tdl/auto_script/tmp/clock_manager_powerlow_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/clock_manager_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/clock_rst_verb_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/clock_rst_verc_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/cmos_redx_1xN_inner_clock_sdl.rb +33 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0004.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0014.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0017.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0019.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0023.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0024.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0025.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0027.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0030.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0037.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0038.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0040.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0041.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0042.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0043.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0049.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0052.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0054.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_al_log_axis_inf_R0055.coe +18 -0
- data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_0_R0000.coe +9825 -0
- data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_1_R0001.coe +9720 -0
- data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_2_R0002.coe +9825 -0
- data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_3_R0003.coe +9825 -0
- data/lib/tdl/auto_script/tmp/coe_origin_mac_inf_x_R0000.coe +26 -0
- data/lib/tdl/auto_script/tmp/coe_uart_tx_inf_R0000.coe +5025 -0
- data/lib/tdl/auto_script/tmp/common_axli_flow_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/common_fifo_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/common_redx_1xN_ddr_simple_sdl.rb +32 -0
- data/lib/tdl/auto_script/tmp/common_redx_1xN_sdr_serdes_simple_sdl.rb +31 -0
- data/lib/tdl/auto_script/tmp/common_redx_1xN_sdr_simple_sdl.rb +32 -0
- data/lib/tdl/auto_script/tmp/cross_clk_sync_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/custom_serdes_router_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/data_c_cache_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/data_c_direct_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/data_c_pipe_force_vld_bind_data_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/data_c_pipe_force_vld_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/data_c_pipe_inf_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/data_c_pipe_intc_M2S_best_robin_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/data_c_pipe_sync_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/data_c_sim_master_model_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/data_inf_c_intc_S2M_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/data_inf_c_planer_A1_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/data_lvds_bitslip_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/data_lvds_simple_bitslip_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/data_mirrors_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/datainf_c_slaver_empty_sdl.rb +9 -0
- data/lib/tdl/auto_script/tmp/ddr3_ip_wrapper_sdl.rb +28 -0
- data/lib/tdl/auto_script/tmp/ddr_axi4_to_axis_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/det_moto_findex_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/det_start_block_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/det_start_filter_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/det_with_pre_A3_sdl.rb +28 -0
- data/lib/tdl/auto_script/tmp/det_with_pre_A4_sdl.rb +28 -0
- data/lib/tdl/auto_script/tmp/det_with_pre_B1_sdl.rb +29 -0
- data/lib/tdl/auto_script/tmp/det_with_pre_findex_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/det_with_pre_verb_sdl.rb +29 -0
- data/lib/tdl/auto_script/tmp/diffr_multi_phase_sample_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/diffr_reg_tpu_v3_wrapper_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/diffr_reg_tpu_wrapper_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/diffr_reg_tpu_wrapper_v2_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/dire_accese_flash_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/dyn_edge_clock_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/edge_generator_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/eth4_chip_reg_wrapper_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/eth4_lvds_tb_block_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/eth4_sensor_driver_array_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/eth4_single_chip_Red2S_lvds_dir_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/eth_2g5_wrapper_sdl.rb +25 -0
- data/lib/tdl/auto_script/tmp/eth_outShare_wrapper_sdl.rb +28 -0
- data/lib/tdl/auto_script/tmp/eth_to_ddr_with_ack_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/eth_to_spi_verb_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/eth_to_standard_spi_with_ack_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/eth_to_standard_uart_with_ack_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/eth_xilinx_ip_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/ethernet_wrapper_2d5G_sdl.rb +28 -0
- data/lib/tdl/auto_script/tmp/ethernet_wrapper_sdl.rb +28 -0
- data/lib/tdl/auto_script/tmp/ethernet_wrapper_track_sdl.rb +28 -0
- data/lib/tdl/auto_script/tmp/ext_sync_filter_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/fifo_36kb_long_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/fifo_73_96bit_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/four_chips_Red5_lvds_dir_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/four_chips_Red5_lvds_pins_delay_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/full_axi4_to_axis_partition_wr_rd_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/full_axi4_to_axis_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/gen_big_field_table_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/gen_common_frame_table_sdl.rb +61 -0
- data/lib/tdl/auto_script/tmp/gen_origin_axis_A2_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/gen_origin_axis_A3_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/gen_origin_axis_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/general_tap_ack_A2_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/general_tap_ack_A3_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/general_tap_ack_A4_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/general_tap_ack_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/general_tap_no_ack_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/general_tap_send_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/gmii_from_mac_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/gmii_to_mac_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/gt_transceivers_axis_verb_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/gt_tx_pack_proto_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/gvi_k7_clock_manager_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/gvi_k7_ddr3_ip_wrapper_sdl.rb +29 -0
- data/lib/tdl/auto_script/tmp/hardware_date_core_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/hdl_test_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/iic_gpio_pca9557_array_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/independent_clock_fifo_a1_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/independent_clock_fifo_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/inf_time_delay_ctrl_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/inf_time_delay_ctrl_verb_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/init_10G_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/init_mac_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/init_trigger_cfg_10g_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/inner_clock_to_sensor_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/ip_check_sum_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/k7_ethernet_10g_wrapper_B2_sdl.rb +24 -0
- data/lib/tdl/auto_script/tmp/k7_ethernet_multi_10g_wrapper_sdl.rb +23 -0
- data/lib/tdl/auto_script/tmp/keys_filter_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/latency_dynamic_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/latency_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/lock_lvds_data_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/lvds2cmos_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/lvds_ibufds_array_NOBUFF_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/lvds_ibufds_array_r8_1x6_NOBUFF_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/lvds_ibufds_array_r8_1x6_OB_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/lvds_ibufds_array_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/lvds_tb_block_A1_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/mac_to_file_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/manchester_router_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/mdio_model_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/mdio_proto_sdl.rb +24 -0
- data/lib/tdl/auto_script/tmp/mirror_mac_arp_iic_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/modified_eth_2G5_top_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/multiple_steps_676_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/multiple_steps_A2_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/odata_pool_axi4_A2_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/odata_pool_axi4_A3_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/outSt_combin_spi_core_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/outSt_eth_to_ct_databoard_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/outSt_eth_to_multi_spi_with_ack_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_verb_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/outSt_eth_to_spi_with_ack_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/outSt_spi_core_B1_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/pack_ip_mac_B1_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/pack_ip_mac_verb_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/parse_big_field_table_A2_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/parse_big_field_table_main_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/parse_big_field_table_mirror_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/parse_big_field_table_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/parse_big_field_table_slaver_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/parse_big_field_table_verb_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/parse_common_frame_table_A1_sdl.rb +64 -0
- data/lib/tdl/auto_script/tmp/parse_tap_stream_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/phase_red8_sensor_lvds_block_red8_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/phase_sensor_sync_ctrl_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/platform_shift_ctrl_verb_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/poll_udp_tpu_upgrade_sdl.rb +30 -0
- data/lib/tdl/auto_script/tmp/poll_udp_tpu_verb_upgrade_sdl.rb +34 -0
- data/lib/tdl/auto_script/tmp/prim_serdes_filter_decode_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/red2s_lock_lvds_data_verc_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/red3_lock_lvds_data_verc_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/red3_lvds_tb_block_A1_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_A1_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_A2_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/red5_chip_reg_wrapper_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_raw_A1_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_verb_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/red5_lock_lvds_data_verc_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/red5_lvds_clock_mmcm_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/red8_1x6_oneBoard_sdl.rb +30 -0
- data/lib/tdl/auto_script/tmp/red8_chip_reg_wrapper_A2_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/redx_1xN_ddr_inner_clock_sdl.rb +36 -0
- data/lib/tdl/auto_script/tmp/redx_1xN_ddr_inner_clock_verb_sdl.rb +38 -0
- data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_A1_sdl.rb +38 -0
- data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_A2_sdl.rb +39 -0
- data/lib/tdl/auto_script/tmp/redx_1xN_ddr_serdes_manual_sdl.rb +35 -0
- data/lib/tdl/auto_script/tmp/redx_1xN_inner_clock_sdl.rb +36 -0
- data/lib/tdl/auto_script/tmp/redx_1xN_sdr_serdes_manual_A1_sdl.rb +36 -0
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_2B_sdl.rb +25 -0
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_bitslip_sdl.rb +26 -0
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_sdl.rb +25 -0
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_4B_verb_sdl.rb +25 -0
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_dyn_compact_sdl.rb +26 -0
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_dyn_sdl.rb +26 -0
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_raw_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_raw_verb_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/redx_lock_lvds_data_verb_sdl.rb +23 -0
- data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_multi_phase_DDR_sdl.rb +29 -0
- data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_multi_phase_sdl.rb +28 -0
- data/lib/tdl/auto_script/tmp/redx_lvds_dir_to_4B_var_delay_sdl.rb +23 -0
- data/lib/tdl/auto_script/tmp/rgmii_to_gmii_wrapper_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/riffa_trans_axis_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/sct_ddr3_16bit_ip_wrapper_sdl.rb +28 -0
- data/lib/tdl/auto_script/tmp/sct_ddr3_ip_wrapper_sdl.rb +29 -0
- data/lib/tdl/auto_script/tmp/sel_system_ip_mac_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/senser_lvds_parse_16bit_diffr_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/senser_lvds_parse_24bit_diffr_A1_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/senser_lvds_parse_24bit_diffr_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/sensor_block_unit_C2_sdl.rb +29 -0
- data/lib/tdl/auto_script/tmp/sensor_block_unit_C2_track_crc8_sdl.rb +29 -0
- data/lib/tdl/auto_script/tmp/sensor_clock_recv_check_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/sensor_ctrl_676_28lvds_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/sensor_ctrl_676_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_SP_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/sensor_drive_lvds_clk_verb_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/sensor_driver_clock_set_A2_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_SP_sdl.rb +23 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_edge_sync_sdl.rb +23 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_sdl.rb +23 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_findex_verb_sdl.rb +23 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_28lvds_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_sdl.rb +23 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_A1_sdl.rb +23 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_red450_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verb_sdl.rb +23 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verc_red450_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_findex_verc_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/sensor_lvds_block_unit_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/serdes_parl_lock_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/serdes_to_data_array_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/sim_arp_tpu_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/sim_auto_wireshark_send_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/sim_tpu_update_file_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/simple_cbct_lock_lvds_data_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/simple_hardware_log_track_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/simple_hw_test_top_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/simple_test_eth_2g5_subs_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/single_chip_Red2S_lvds_dir_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/single_chip_Red3_lvds_pins_delay_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verb_wrapper_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verc_wrapper_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/single_chip_iic_bus_verd_wrapper_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/single_chip_iic_bus_wrapper_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/single_chip_lvds_ddr_dir_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/single_chip_lvds_dir_delay_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/single_chip_lvds_dir_inner_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/single_chip_sensor_lvds_dir_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/sketch_to_origin_stream_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/slow_lvds_data_d2s_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/slow_sensor_inner_clock_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/split_ddr3_ip_wrapper_sdl.rb +45 -0
- data/lib/tdl/auto_script/tmp/tcp_aux_tpu_upgrade_sdl.rb +50 -0
- data/lib/tdl/auto_script/tmp/tcp_check_sum_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/tcp_ctrl_set_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/tcp_option_split_B1_sdl.rb +10 -0
- data/lib/tdl/auto_script/tmp/test_red5dl_lvds_sdl.rb +9 -0
- data/lib/tdl/auto_script/tmp/time_delay_ctrl_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/time_enable_scaler_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/time_step_module_A1_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/time_step_module_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/tpu_bypass_iic_upgrade_sdl.rb +29 -0
- data/lib/tdl/auto_script/tmp/tpu_common_iic_upgrade_sdl.rb +25 -0
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_gray_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_verb_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_C1_wrapper_x7_gray_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v2_array_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v3_wrapper_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v4_wrapper_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_v5_wrapper_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/tpu_custom_iic_bus_verc_wrapper_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/tpu_eth4_iic_bus_wrapper_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/tpu_mgm_inf_sdl.rb +28 -0
- data/lib/tdl/auto_script/tmp/tpu_simple_boot_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/trigger_data_inf_c_A1_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/trigger_data_inf_c_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/uart_hp_ddr3_tft800x480_hdmi_ext_sdl.rb +43 -0
- data/lib/tdl/auto_script/tmp/uart_hp_ddr3_tft800x480_hdmi_ext_sim_sdl.rb +43 -0
- data/lib/tdl/auto_script/tmp/uart_rx_core_dma_verb_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/uart_top_bypass_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/uart_top_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/udp_check_sum_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/udp_ctrl_set_A1_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp/udp_fpga_ports_route_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_64b_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_A3_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_B1_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/udp_socket_ddr_pump_verb_sdl.rb +14 -0
- data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_D1_sdl.rb +16 -0
- data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_tcp_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/unpack_mac_ip_udp_verd_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/vio_wrapper_sdl.rb +11 -0
- data/lib/tdl/auto_script/tmp/wide_axis_to_axi4_wr_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/wide_fifo_sdl.rb +19 -0
- data/lib/tdl/auto_script/tmp/width_combin_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/width_convert_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/xilinx_dna_capture_sdl.rb +12 -0
- data/lib/tdl/auto_script/tmp/xilinx_eth_clock_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/xilinx_eth_reset_sdl.rb +15 -0
- data/lib/tdl/auto_script/tmp/xilinx_fifo_A1_sdl.rb +22 -0
- data/lib/tdl/auto_script/tmp/xilinx_fifo_sdl.rb +20 -0
- data/lib/tdl/auto_script/tmp/xilinx_fifo_verb_sdl.rb +23 -0
- data/lib/tdl/auto_script/tmp/xilinx_fifo_verc_sdl.rb +21 -0
- data/lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sdl.rb +29 -0
- data/lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sim_sdl.rb +31 -0
- data/lib/tdl/auto_script/tmp/xilinx_jtag_axil_wrapper_sdl.rb +9 -0
- data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_multi_phase_ddr_wrapper_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_multi_phase_wrapper_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_phase_wrapper_sdl.rb +17 -0
- data/lib/tdl/auto_script/tmp/xilinx_recfg_clock_wrapper_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/zynq_pl_common_dr_sensor_clk_sdl.rb +13 -0
- data/lib/tdl/auto_script/tmp/zynq_pl_common_lvds_sdl.rb +18 -0
- data/lib/tdl/auto_script/tmp.rb +0 -0
- data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_A1_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +24 -10
- data/lib/tdl/axi4/axi4_lib.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_pipe_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +0 -0
- data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_data_convert.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_direct_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +0 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_partition_od.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_pipe_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_wr_auxiliary_gen_without_resp_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi4/bak/ddr3.rb +0 -0
- data/lib/tdl/axi4/bak/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/bak/odata_pool_axi4_A1_auto.rb +0 -0
- data/lib/tdl/axi4/bak/odata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/odata_pool_axi4_A1_auto.rb +0 -0
- data/lib/tdl/axi4/odata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/wide_axis_to_axi4_wr.rb +0 -0
- data/lib/tdl/axi4/wide_axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi_lite/axi_lite_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/axi_lite_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/axi_lite_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/axi_lite_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb +0 -0
- data/lib/tdl/axi_lite/jtag_to_axilite_wrapper_auto.rb +0 -0
- data/lib/tdl/axi_lite/lite_cmd.rb +0 -0
- data/lib/tdl/axi_lite/prj_lib.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_35bit_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_72_95bit_with_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_B1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_mirror_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_bind_tuser_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_lib.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_fifo_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_packet_fifo_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_partition_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_partition_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_wide_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_combin_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_scaler_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_scaler_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_append_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_append_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_combin_with_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_direct_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_filter_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_full_to_data_c_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_head_cut_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_fill_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_with_addr_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_writh_user_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_link_trigger_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_mirror_to_master_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_mirrors_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_padding.rb +44 -0
- data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_ram_buffer_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_pipe_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_axi4_or_lite_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_data_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_lite_rd_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_lite_wr_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_uncompress_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_valve_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_valve_with_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_combin_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_convert_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_destruct_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_destruct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/__axi_stream_interconnect_S2M.rb +0 -0
- data/lib/tdl/axi_stream/bak/_axis_mirrors.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_S2M.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_35bit_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_72_95bit_with_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_B1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_mirror_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_long_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_partition_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_partition_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_scaler.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_scaler_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_A1.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_combin_with_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe.rb.bak +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_direct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_filter_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_fill_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_split_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_split_with_addr_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_mirrors_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_pkt_fifo_filter_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_ram_buffer_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_pipe_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_to_data_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_uncompress_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_valve_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_valve_with_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_convert_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_destruct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/check_stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/dynamic_port_cfg_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/dynnamic_addr_cfg_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_origin_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_simple_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/simple_video_gen_A2.rb +0 -0
- data/lib/tdl/axi_stream/bak/simple_video_gen_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/udp_server_bfm_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/udp_server_ctrl_bfm_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/video_to_VDMA.rb +0 -0
- data/lib/tdl/axi_stream/bak/video_to_VDMA_auto.rb +0 -0
- data/lib/tdl/axi_stream/check_stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_c_to_axis_full_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_to_axis_inf_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_to_axis_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_origin_axis_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_origin_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_simple_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/stream_crc_auto.rb +0 -0
- data/lib/tdl/basefunc.rb +0 -0
- data/lib/tdl/bfm/axi4_illegal_bfm.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axi_stream_bfm.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_exp.yml +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_module_build.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_parse.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_slice_to_logic.rb +0 -0
- data/lib/tdl/bfm/bfm_lib.rb +0 -0
- data/lib/tdl/bfm/logic_initial_block.rb +0 -0
- data/lib/tdl/cfg.yml +0 -0
- data/lib/tdl/class_hdl/hdl_always_comb.rb +0 -0
- data/lib/tdl/class_hdl/hdl_always_ff.rb +0 -0
- data/lib/tdl/class_hdl/hdl_assign.rb +0 -0
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +0 -0
- data/lib/tdl/class_hdl/hdl_data.rb +0 -0
- data/lib/tdl/class_hdl/hdl_ex_defarraychain.rb +0 -0
- data/lib/tdl/class_hdl/hdl_foreach.rb +0 -0
- data/lib/tdl/class_hdl/hdl_function.rb +0 -0
- data/lib/tdl/class_hdl/hdl_generate.rb +0 -0
- data/lib/tdl/class_hdl/hdl_initial.rb +0 -0
- data/lib/tdl/class_hdl/hdl_module_def.rb +16 -0
- data/lib/tdl/class_hdl/hdl_package.rb +0 -0
- data/lib/tdl/class_hdl/hdl_parameter.rb +0 -0
- data/lib/tdl/class_hdl/hdl_random.rb +0 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +18 -1
- data/lib/tdl/class_hdl/hdl_struct.rb +0 -0
- data/lib/tdl/class_hdl/hdl_verify.rb +0 -0
- data/lib/tdl/data_inf/_data_mirrors.rb +0 -0
- data/lib/tdl/data_inf/bak/_data_mirrors.rb +0 -0
- data/lib/tdl/data_inf/bak/common_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_bind_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_connect_pipe.rb +0 -0
- data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_planer.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/data_inf/common_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/data_bind_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_direct_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_interconnect.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/data_condition_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/data_condition_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +0 -0
- data/lib/tdl/data_inf/data_mirrors_auto.rb +0 -0
- data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +0 -0
- data/lib/tdl/data_inf/data_uncompress_auto.rb +0 -0
- data/lib/tdl/data_inf/data_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/data_inf/path_lib.rb +0 -0
- data/lib/tdl/elements/Reset.rb +0 -0
- data/lib/tdl/elements/axi4.rb +0 -0
- data/lib/tdl/elements/axi_lite.rb +0 -0
- data/lib/tdl/elements/axi_stream.rb +0 -0
- data/lib/tdl/elements/clock.rb +0 -0
- data/lib/tdl/elements/common_configure_reg.rb +0 -0
- data/lib/tdl/elements/data_inf.rb +0 -0
- data/lib/tdl/elements/logic.rb +0 -2
- data/lib/tdl/elements/mail_box.rb +0 -0
- data/lib/tdl/elements/originclass.rb +0 -0
- data/lib/tdl/elements/parameter.rb +0 -0
- data/lib/tdl/elements/track_inf.rb +0 -0
- data/lib/tdl/elements/videoinf.rb +0 -0
- data/lib/tdl/examples/10_random/exp_random.rb +0 -0
- data/lib/tdl/examples/10_random/exp_random.sv +0 -0
- data/lib/tdl/examples/11_logic_latency/test_logic_latency.rb +0 -0
- data/lib/tdl/examples/11_logic_latency/test_logic_latency.sv +0 -0
- data/lib/tdl/examples/11_test_unit/dve.tcl +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tu1.sv +0 -0
- data/lib/tdl/examples/1_define_module/example1.rb +0 -0
- data/lib/tdl/examples/1_define_module/exmple_md.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/always_comb.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/always_ff.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/case.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/foreach.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/function.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/generate.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/package.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/package2.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/simple_assign.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/state_case.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/struct.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/struct_function.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_module_port.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_module_var.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/vcs_string.rb +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +0 -0
- data/lib/tdl/examples/4_generate/example.rb +0 -0
- data/lib/tdl/examples/4_generate/test_generate.sv +0 -0
- data/lib/tdl/examples/5_logic_combin/login_combin.rb +0 -0
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +0 -0
- data/lib/tdl/examples/6_module_with_interface/example.rb +0 -0
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +0 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +0 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/body_package.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/body_package.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/head_package.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/head_package.sv +0 -0
- data/lib/tdl/examples/8_top_module/dve.tcl +0 -0
- data/lib/tdl/examples/8_top_module/example.rb +0 -0
- data/lib/tdl/examples/8_top_module/pins.yml +0 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +0 -0
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +0 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +8 -8
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +0 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +0 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +0 -0
- data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv +0 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +0 -0
- data/lib/tdl/examples/9_itegration/pins.yml +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/test_top.sv +0 -0
- data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +0 -0
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +0 -0
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
- data/lib/tdl/examples/9_itegration/top.rb +2 -2
- data/lib/tdl/examples/readme.md +0 -0
- data/lib/tdl/exlib/axis_eth_ex.rb +0 -0
- data/lib/tdl/exlib/axis_verify.rb +0 -0
- data/lib/tdl/exlib/clock_reset_verify.rb +0 -0
- data/lib/tdl/exlib/common_cfg_reg_inf.rb +0 -0
- data/lib/tdl/exlib/constraints.rb +0 -0
- data/lib/tdl/exlib/constraints_verb.rb +4 -4
- data/lib/tdl/exlib/dve_tcl.rb +0 -0
- data/lib/tdl/exlib/element_class_vars.rb +0 -0
- data/lib/tdl/exlib/global_param.rb +0 -0
- data/lib/tdl/exlib/integral_test/bak/integral_test.rb +0 -0
- data/lib/tdl/exlib/integral_test/clock_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/io_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/reset_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +0 -0
- data/lib/tdl/exlib/itegration.rb +0 -0
- data/lib/tdl/exlib/itegration_test_unit.rb +0 -0
- data/lib/tdl/exlib/itegration_verb.rb +129 -13
- data/lib/tdl/exlib/logic_verify.rb +0 -0
- data/lib/tdl/exlib/parse_argv.rb +0 -0
- data/lib/tdl/exlib/sdlmodule_sim.bak.rb +0 -0
- data/lib/tdl/exlib/test_point.rb +4 -4
- data/lib/tdl/exlib/test_point.rb.bak +0 -0
- data/lib/tdl/global_scan.rb +0 -0
- data/lib/tdl/rebuild_ele/axi4.rb +0 -0
- data/lib/tdl/rebuild_ele/axi_lite.rb +0 -0
- data/lib/tdl/rebuild_ele/axi_stream.rb +0 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf.sv +0 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +0 -0
- data/lib/tdl/rebuild_ele/data_inf.rb +0 -0
- data/lib/tdl/rebuild_ele/data_inf_c.rb +0 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +0 -0
- data/lib/tdl/rebuild_ele/readme.md +0 -0
- data/lib/tdl/sdlimplement/resource.yml +0 -0
- data/lib/tdl/sdlimplement/sdl_impl_module.rb +0 -0
- data/lib/tdl/sdlimplement/sdl_impl_param.rb +0 -0
- data/lib/tdl/sdlimplement/test.rb +0 -0
- data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +0 -0
- data/lib/tdl/sdlmodule/generator_block_module.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +3 -3
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +0 -0
- data/lib/tdl/sdlmodule/techbench_module.rb +0 -0
- data/lib/tdl/sdlmodule/test_unit_module.rb +13 -3
- data/lib/tdl/sdlmodule/test_unit_module.rb.bak +0 -0
- data/lib/tdl/sdlmodule/top_module.rb +0 -0
- data/lib/tdl/sdlmodule/top_module.rb.bak +0 -0
- data/lib/tdl/tdl.rb +0 -0
- data/lib/tdl/tdlerror/tdlerror.rb +0 -0
- data/lib/tdl/testunit/test_all.rb +0 -0
- data/lib/tdl/testunit/test_array_chain.rb +0 -0
- data/lib/tdl/testunit/test_tmp.rb +0 -0
- metadata +449 -6
|
@@ -0,0 +1,26 @@
|
|
|
1
|
+
@0000 0
|
|
2
|
+
@0001 0
|
|
3
|
+
@0002 0
|
|
4
|
+
@0003 0
|
|
5
|
+
@0004 0
|
|
6
|
+
@0005 0
|
|
7
|
+
@0006 0
|
|
8
|
+
@0007 0
|
|
9
|
+
@0008 0
|
|
10
|
+
@0009 0
|
|
11
|
+
@000a a00
|
|
12
|
+
@000b a01
|
|
13
|
+
@000c a02
|
|
14
|
+
@000d a03
|
|
15
|
+
@000e a04
|
|
16
|
+
@000f a05
|
|
17
|
+
@0010 a06
|
|
18
|
+
@0011 a07
|
|
19
|
+
@0012 a08
|
|
20
|
+
@0013 a09
|
|
21
|
+
@0014 a0a
|
|
22
|
+
@0015 a0b
|
|
23
|
+
@0016 a0c
|
|
24
|
+
@0017 a0d
|
|
25
|
+
@0018 a0e
|
|
26
|
+
@0019 b0f
|