axi_tdl 0.2.4 → 0.2.5
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- checksums.yaml +4 -4
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +4 -2
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +4 -2
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +4 -2
- data/lib/axi/AXI_stream/gen_origin_axis_A3.sv +163 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +12 -12
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +7 -26
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +26 -7
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
- metadata +3 -2
checksums.yaml
CHANGED
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@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: cbd04437f9a54f453a70249ea3800e0ad83b7afca7b2eb8aa4e968160a44b714
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data.tar.gz: 4e0e182673271971834246838aa7f2d2735bf6c16ec8d02bf6cecacc63ef9f9d
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 756a91a926f7933d0b9f282bc10effc50f7505026b31b15ae4af55e0229bd515687fe30ba35b4d5593ba313655e46643e29089292456079475c7ac6baa9ea562
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data.tar.gz: 5100e94f2d061d83cf6f0caae29401bfaefefa15bb5f911d6fbf9b84c5aba9bcb891bee496761b76c9e6b1627a57917d7a9e0ac60e4c549699ef475894c7dd3a
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@@ -12,7 +12,8 @@ madified:
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***********************************************/
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`timescale 1ns/1ps
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module axi4_mix_interconnect_M2S #(
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-
parameter NUM = 8
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parameter NUM = 8,
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parameter MASTER_IDSIZE = 8
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)(
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axi_inf.slaver slaver [NUM-1:0],
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axi_inf.master master
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@@ -38,7 +39,8 @@ axi4_wr_interconnect_M2S_A1 #( //axi4 dont support write burst out-of-order
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// );
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axi4_rd_mix_interconnect_M2S_A2 #(
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-
.NUM
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.NUM (NUM ),
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.MASTER_IDSIZE (MASTER_IDSIZE)
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)axi4_rd_mix_interconnect_M2S_inst(
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/* axi_inf.slaver_rd */ .slaver (`slaver_vcs_cptRead ), //[NUM-1:0],
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/* axi_inf.master_rd */ .master (`master_vcs_cptRead )
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@@ -14,7 +14,8 @@ madified:
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***********************************************/
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`timescale 1ns/1ps
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module axi4_rd_mix_interconnect_M2S_A2 #(
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parameter NUM = 8
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parameter NUM = 8,
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parameter MASTER_IDSIZE = 8
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)(
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axi_inf.slaver_rd slaver [NUM-1:0],
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axi_inf.master_rd master
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@@ -24,7 +25,8 @@ localparam NSIZE = $clog2(NUM);
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import SystemPkg::*;
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// localparam LAZISE = slaver[0].IDSIZE;
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-
localparam LAZISE = master.IDSIZE - NSIZE;
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// localparam LAZISE = master.IDSIZE - NSIZE;
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localparam LAZISE = MASTER_IDSIZE - NSIZE;
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initial begin
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// assert(slaver[0].IDSIZE+NSIZE == master.IDSIZE)
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@@ -44,8 +44,10 @@ TdlBuild.axi4_partition_rd_verb(__dir__) do
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h.input.wr_en partition_pulse_inf.vld_rdy
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h.output['DSIZE'].rdata ''.to_nq
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h.input.rd_en short_inf.axi_rvalid & short_inf.axi_rready & short_inf.axi_rlast
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h.output.logic.empty debugLogic.fifo_empty
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h.output.logic.full debugLogic.fifo_full
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# h.output.logic.empty debugLogic.fifo_empty
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# h.output.logic.full debugLogic.fifo_full
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h.output.logic.empty logic.fifo_empty
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h.output.logic.full logic.fifo_full
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end
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Assign do
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.1.0
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addr start num
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Version: VERA.2.0
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length can be 1
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Version: VERA.3.0
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can be reset
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creaded:
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module gen_origin_axis_A3 #(
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`parameter_string MODE = "RANGE"
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)(
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input reset,
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input enable,
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output logic ready,
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input [31:0] length, // '1' meet 1 length
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input [31:0] start,
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axi_stream_inf.master axis_out
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);
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import DataInterfacePkg::*;
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wire clock,rst_n;
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assign clock = axis_out.aclk;
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assign rst_n = axis_out.aresetn;
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assign axis_out.axis_tuser = 1'b0;
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assign axis_out.axis_tkeep = '1;
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typedef enum {IDLE,SEND_DATA,FRAME_DONE} STATUS;
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STATUS cstate,nstate;
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always@(posedge clock/*,negedge rst_n*/)
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if(~rst_n || reset)
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cstate <= IDLE;
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else cstate <= nstate;
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// logic data_ok;
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always@(*)
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case(cstate)
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IDLE:
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if(enable && ready)
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nstate = SEND_DATA;
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else nstate = IDLE;
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SEND_DATA:
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if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.axis_tlast && axis_out.aclken)
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nstate = IDLE;
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else nstate = SEND_DATA;
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FRAME_DONE:
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// if(!enable)
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nstate = IDLE;
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// else nstate = FRAME_DONE;
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default: nstate = IDLE;
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endcase
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// always@(posedge clock/*,negedge rst_n*/)
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// if(~rst_n) axis_out.axis_tdata <= start;
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// else begin
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// if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.aclken)
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// if(axis_out.axis_tdata < (start+length-1))begin
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// if(MODE == "RANGE")
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// axis_out.axis_tdata <= axis_out.axis_tdata + 1'b1;
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// else axis_out.axis_tdata <= start;
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// end
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// else axis_out.axis_tdata <= start;
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// else axis_out.axis_tdata <= axis_out.axis_tdata;
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// end
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always@(posedge clock/*,negedge rst_n*/)
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if(~rst_n || reset) axis_out.axis_tdata <= start;
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else
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case(nstate)
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IDLE: axis_out.axis_tdata <= start;
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SEND_DATA:begin
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if(enable && ready)
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axis_out.axis_tdata <= start;
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else if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.aclken)begin
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// axis_out.axis_tdata <= axis_out.axis_tdata + 1'b1;
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if(MODE == "RANGE")
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axis_out.axis_tdata <= axis_out.axis_tdata + 1'b1;
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else axis_out.axis_tdata <= start;
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end else
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axis_out.axis_tdata <= axis_out.axis_tdata;
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end
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default:;
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endcase
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always@(posedge clock/*,negedge rst_n*/)
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if(~rst_n || reset) axis_out.axis_tvalid <= 1'b0;
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else
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case(nstate)
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SEND_DATA: axis_out.axis_tvalid <= 1'b1;
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default: axis_out.axis_tvalid <= 1'b0;
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endcase
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// reg [31:0] cnt ;
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// always@(posedge clock/*,negedge rst_n*/)
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// if(~rst_n) cnt <= '0;
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// else begin
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// if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.aclken)
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// if(cnt < (length-1))
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// cnt <= cnt + 1'b1;
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// else cnt <= '0;
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// else cnt <= cnt;
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// end
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//
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logic [31:0] lock_length;
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always@(posedge clock/*,negedge rst_n*/)begin
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if(~rst_n || reset) lock_length <= '0;
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else begin
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if(enable && ready)
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lock_length <= length;
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else lock_length <= lock_length;
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end
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end
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always@(posedge clock/*,negedge rst_n*/)
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if(~rst_n || reset) axis_out.axis_tlast <= 1'b0;
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else begin
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// if(axis_out.aclken)
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// if(length > 1)
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// axis_out.axis_tlast <= pipe_last_func(axis_out.axis_tvalid,axis_out.axis_tready,axis_out.axis_tlast,(cnt==length-2));
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// else axis_out.axis_tlast <= 1'b1;
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// else axis_out.axis_tlast <= 1'b0;
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if(axis_out.aclken)begin
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if(enable && ready)begin
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axis_out.axis_tlast <= length < 2;
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end else if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.axis_tlast && axis_out.aclken)begin
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axis_out.axis_tlast <= 1'b0;
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end else if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.axis_tcnt==lock_length-2 && axis_out.aclken )begin
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axis_out.axis_tlast <= 1'b1;
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end else begin
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axis_out.axis_tlast <= axis_out.axis_tlast;
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end
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end else begin
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axis_out.axis_tlast <= axis_out.axis_tlast;
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end
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end
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// assign data_ok = axis_out.axis_tlast && axis_out.axis_tready && axis_out.axis_tvalid;
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always@(posedge clock/*,negedge rst_n*/)
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if(~rst_n || reset) ready <= 1'b0;
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else
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case(nstate)
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IDLE: ready <= 1'b1;
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default: ready <= 1'b0;
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endcase
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endmodule
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@@ -4,8 +4,8 @@ ___________ Cook Darwin __________
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_______________________________________
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descript:
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6
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author : Cook.Darwin
|
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7
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-
Version:
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8
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-
creaded:
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Version: VERA.0.0
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8
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creaded:
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madified:
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***********************************************/
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11
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`timescale 1ns/1ps
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@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
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endgenerate
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//-------- CLOCKs Total 2 ----------------------
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//--->> CheckClock <<----------------
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-
logic
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-
integer
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-
ClockSameDomain
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logic cc_done_28,cc_same_28;
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integer cc_afreq_28,cc_bfreq_28;
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ClockSameDomain CheckPClock_inst_28(
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/* input */ .aclk (in_inf.clock ),
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/* input */ .bclk (out_inf.clock ),
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/* output logic */ .done (
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-
/* output logic */ .same (
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-
/* output integer */ .aFreqK (
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-
/* output integer */ .bFreqK (
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/* output logic */ .done (cc_done_28),
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/* output logic */ .same (cc_same_28),
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/* output integer */ .aFreqK (cc_afreq_28),
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/* output integer */ .bFreqK (cc_bfreq_28)
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60
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);
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61
61
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initial begin
|
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63
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-
wait(
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64
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-
assert(
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63
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wait(cc_done_28);
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assert(cc_same_28)
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65
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else begin
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66
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-
$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/
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$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_28, 1000000.0/cc_bfreq_28);
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67
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repeat(10)begin
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@(posedge in_inf.clock);
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69
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end
|
data/lib/axi_tdl/version.rb
CHANGED
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created:
|
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8
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+
created: 2023-08-16 21:22:47 +0800
|
|
9
9
|
madified:
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10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -19,7 +19,7 @@ module test_module_var #(
|
|
|
19
19
|
|
|
20
20
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//==========================================================================
|
|
21
21
|
//-------- define ----------------------------------------------------------
|
|
22
|
-
localparam ASIZE = 20
|
|
22
|
+
localparam ASIZE = 20;
|
|
23
23
|
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
24
24
|
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
25
25
|
axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295),.FreqM(100)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
|
|
@@ -1,28 +1,9 @@
|
|
|
1
|
-
/**********************************************
|
|
2
|
-
_______________________________________
|
|
3
|
-
___________ Cook Darwin __________
|
|
4
|
-
_______________________________________
|
|
5
|
-
descript:
|
|
6
|
-
author : Cook.Darwin
|
|
7
|
-
Version: VERA.0.0
|
|
8
|
-
created: 2023-02-17 21:27:53 +0800
|
|
9
|
-
madified:
|
|
10
|
-
***********************************************/
|
|
11
|
-
`timescale 1ns/1ps
|
|
12
|
-
|
|
13
|
-
module test_top (
|
|
14
|
-
input sys_clock,
|
|
15
|
-
output logic[3:0] odata
|
|
16
|
-
);
|
|
17
|
-
|
|
18
|
-
//==========================================================================
|
|
19
|
-
//-------- define ----------------------------------------------------------
|
|
20
|
-
|
|
21
|
-
|
|
22
|
-
//==========================================================================
|
|
23
|
-
//-------- instance --------------------------------------------------------
|
|
24
|
-
|
|
25
|
-
//==========================================================================
|
|
26
|
-
//-------- expression ------------------------------------------------------
|
|
27
1
|
|
|
2
|
+
`timescale 1ns/1ps
|
|
3
|
+
module test_top();
|
|
4
|
+
initial begin
|
|
5
|
+
#(1us);
|
|
6
|
+
$warning("Check TopModule.sim,please!!!");
|
|
7
|
+
$stop;
|
|
8
|
+
end
|
|
28
9
|
endmodule
|
|
@@ -1,9 +1,28 @@
|
|
|
1
|
-
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.0.0
|
|
8
|
+
created: 2023-08-16 21:22:32 +0800
|
|
9
|
+
madified:
|
|
10
|
+
***********************************************/
|
|
2
11
|
`timescale 1ns/1ps
|
|
3
|
-
|
|
4
|
-
|
|
5
|
-
|
|
6
|
-
|
|
7
|
-
|
|
8
|
-
|
|
12
|
+
|
|
13
|
+
module test_top_sim (
|
|
14
|
+
input sys_clock,
|
|
15
|
+
output logic[3:0] odata
|
|
16
|
+
);
|
|
17
|
+
|
|
18
|
+
//==========================================================================
|
|
19
|
+
//-------- define ----------------------------------------------------------
|
|
20
|
+
|
|
21
|
+
|
|
22
|
+
//==========================================================================
|
|
23
|
+
//-------- instance --------------------------------------------------------
|
|
24
|
+
|
|
25
|
+
//==========================================================================
|
|
26
|
+
//-------- expression ------------------------------------------------------
|
|
27
|
+
|
|
9
28
|
endmodule
|
|
@@ -1,40 +1,9 @@
|
|
|
1
|
-
/**********************************************
|
|
2
|
-
_______________________________________
|
|
3
|
-
___________ Cook Darwin __________
|
|
4
|
-
_______________________________________
|
|
5
|
-
descript:
|
|
6
|
-
author : Cook.Darwin
|
|
7
|
-
Version: VERA.0.0
|
|
8
|
-
created: 2022-07-10 11:21:57 +0800
|
|
9
|
-
madified:
|
|
10
|
-
***********************************************/
|
|
11
|
-
`timescale 1ns/1ps
|
|
12
|
-
|
|
13
|
-
module test_tttop (
|
|
14
|
-
input global_sys_clk
|
|
15
|
-
);
|
|
16
|
-
|
|
17
|
-
//==========================================================================
|
|
18
|
-
//-------- define ----------------------------------------------------------
|
|
19
|
-
logic clock_100M;
|
|
20
|
-
logic rstn_100M;
|
|
21
|
-
axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
|
|
22
|
-
//==========================================================================
|
|
23
|
-
//-------- instance --------------------------------------------------------
|
|
24
|
-
simple_clock simple_clock_inst(
|
|
25
|
-
/* input clock */.sys_clk (global_sys_clk ),
|
|
26
|
-
/* output clock */.clock (clock_100M ),
|
|
27
|
-
/* output reset */.rst_n (rstn_100M )
|
|
28
|
-
);
|
|
29
|
-
a_test_md a_test_md_inst(
|
|
30
|
-
/* input clock */.clock (clock_100M ),
|
|
31
|
-
/* input reset */.rst (~rstn_100M ),
|
|
32
|
-
/* axi_stream_inf.master */.origin_inf (x_origin_inf )
|
|
33
|
-
);
|
|
34
|
-
//==========================================================================
|
|
35
|
-
//-------- expression ------------------------------------------------------
|
|
36
|
-
assign x_origin_inf.axis_tvalid = 1'b0;
|
|
37
|
-
assign x_origin_inf.axis_tdata = '0;
|
|
38
|
-
assign x_origin_inf.axis_tlast = 1'b0;
|
|
39
1
|
|
|
2
|
+
`timescale 1ns/1ps
|
|
3
|
+
module test_tttop();
|
|
4
|
+
initial begin
|
|
5
|
+
#(1us);
|
|
6
|
+
$warning("Check TopModule.sim,please!!!");
|
|
7
|
+
$stop;
|
|
8
|
+
end
|
|
40
9
|
endmodule
|
|
@@ -1,9 +1,40 @@
|
|
|
1
|
-
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.0.0
|
|
8
|
+
created: 2023-08-16 21:22:16 +0800
|
|
9
|
+
madified:
|
|
10
|
+
***********************************************/
|
|
2
11
|
`timescale 1ns/1ps
|
|
3
|
-
|
|
4
|
-
|
|
5
|
-
|
|
6
|
-
|
|
7
|
-
|
|
8
|
-
|
|
12
|
+
|
|
13
|
+
module test_tttop_sim (
|
|
14
|
+
input global_sys_clk
|
|
15
|
+
);
|
|
16
|
+
|
|
17
|
+
//==========================================================================
|
|
18
|
+
//-------- define ----------------------------------------------------------
|
|
19
|
+
logic clock_100M;
|
|
20
|
+
logic rstn_100M;
|
|
21
|
+
axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
|
|
22
|
+
//==========================================================================
|
|
23
|
+
//-------- instance --------------------------------------------------------
|
|
24
|
+
simple_clock simple_clock_inst(
|
|
25
|
+
/* input clock */.sys_clk (global_sys_clk ),
|
|
26
|
+
/* output clock */.clock (clock_100M ),
|
|
27
|
+
/* output reset */.rst_n (rstn_100M )
|
|
28
|
+
);
|
|
29
|
+
a_test_md a_test_md_inst(
|
|
30
|
+
/* input clock */.clock (clock_100M ),
|
|
31
|
+
/* input reset */.rst (~rstn_100M ),
|
|
32
|
+
/* axi_stream_inf.master */.origin_inf (x_origin_inf )
|
|
33
|
+
);
|
|
34
|
+
//==========================================================================
|
|
35
|
+
//-------- expression ------------------------------------------------------
|
|
36
|
+
assign x_origin_inf.axis_tvalid = 1'b0;
|
|
37
|
+
assign x_origin_inf.axis_tdata = '0;
|
|
38
|
+
assign x_origin_inf.axis_tlast = 1'b0;
|
|
39
|
+
|
|
9
40
|
endmodule
|
metadata
CHANGED
|
@@ -1,14 +1,14 @@
|
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
|
2
2
|
name: axi_tdl
|
|
3
3
|
version: !ruby/object:Gem::Version
|
|
4
|
-
version: 0.2.
|
|
4
|
+
version: 0.2.5
|
|
5
5
|
platform: ruby
|
|
6
6
|
authors:
|
|
7
7
|
- Cook.Darwin
|
|
8
8
|
autorequire:
|
|
9
9
|
bindir: exe
|
|
10
10
|
cert_chain: []
|
|
11
|
-
date: 2023-
|
|
11
|
+
date: 2023-08-16 00:00:00.000000000 Z
|
|
12
12
|
dependencies:
|
|
13
13
|
- !ruby/object:Gem::Dependency
|
|
14
14
|
name: rake
|
|
@@ -310,6 +310,7 @@ files:
|
|
|
310
310
|
- lib/axi/AXI_stream/gen_origin_axis.sv
|
|
311
311
|
- lib/axi/AXI_stream/gen_origin_axis_A1.sv
|
|
312
312
|
- lib/axi/AXI_stream/gen_origin_axis_A2.sv
|
|
313
|
+
- lib/axi/AXI_stream/gen_origin_axis_A3.sv
|
|
313
314
|
- lib/axi/AXI_stream/gen_simple_axis.sv
|
|
314
315
|
- lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv
|
|
315
316
|
- lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv
|