axi_tdl 0.1.8 → 0.2.0

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Files changed (74) hide show
  1. checksums.yaml +4 -4
  2. data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv +223 -0
  3. data/lib/axi/AXI4/axi4_direct_verc.sv +60 -5
  4. data/lib/axi/AXI4/axi4_dpram_cache.rb +2 -2
  5. data/lib/axi/AXI4/axi4_dpram_cache.sv +3 -3
  6. data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +146 -0
  7. data/lib/axi/AXI4/axi4_ram_cache.rb +23 -0
  8. data/lib/axi/AXI4/axi4_ram_cache.sv +39 -0
  9. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +112 -0
  10. data/lib/axi/AXI4/axis_to_axi4_wr.sv +5 -5
  11. data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +113 -0
  12. data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +125 -0
  13. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +12 -4
  14. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv +62 -0
  15. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +4 -3
  16. data/lib/axi/AXI4/vcs_axi4_comptable.sv +35 -9
  17. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +1 -1
  18. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +6 -6
  19. data/lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv +280 -0
  20. data/lib/axi/AXI4/width_convert/odd_width_convert.sv +1 -1
  21. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv +80 -0
  22. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +5 -2
  23. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +26 -23
  24. data/lib/axi/AXI_stream/axis_append_A1.sv +15 -2
  25. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +4 -4
  26. data/lib/axi/AXI_stream/axis_uncompress_verb.sv +9 -9
  27. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +3 -2
  28. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
  30. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
  31. data/lib/axi/interface_define/axi_inf.sv +1 -1
  32. data/lib/axi/macro/RTL/define_macro.sv +210 -0
  33. data/lib/axi/macro/SIM/define_macro.sv +194 -0
  34. data/lib/axi_tdl/version.rb +1 -1
  35. data/lib/tdl/Logic/logic_edge.rb +14 -6
  36. data/lib/tdl/Logic/logic_latency.rb +16 -13
  37. data/lib/tdl/auto_script/import_hdl.rb +1 -0
  38. data/lib/tdl/auto_script/import_sdl.rb +46 -1
  39. data/lib/tdl/axi4/axi4_interconnect_verb.rb +83 -22
  40. data/lib/tdl/class_hdl/hdl_data.rb +1 -1
  41. data/lib/tdl/class_hdl/hdl_generate.rb +1 -1
  42. data/lib/tdl/examples/11_logic_latency/test_logic_latency.rb +11 -0
  43. data/lib/tdl/examples/11_logic_latency/test_logic_latency.sv +46 -0
  44. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +5 -4
  45. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
  46. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
  47. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +3 -14
  48. data/lib/tdl/examples/11_test_unit/tu0.sv +2 -5
  49. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
  50. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  51. data/lib/tdl/examples/8_top_module/dve.tcl +0 -6
  52. data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
  53. data/lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv +35 -0
  54. data/lib/tdl/examples/9_itegration/dve.tcl +2 -155
  55. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +2 -2
  56. data/lib/tdl/examples/9_itegration/test_tttop.sv +38 -7
  57. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +7 -38
  58. data/lib/tdl/examples/9_itegration/top.rb +1 -1
  59. data/lib/tdl/exlib/axis_eth_ex.rb +1 -1
  60. data/lib/tdl/exlib/axis_verify.rb +2 -2
  61. data/lib/tdl/exlib/itegration_test_unit.rb +13 -0
  62. data/lib/tdl/exlib/itegration_verb.rb +22 -17
  63. data/lib/tdl/exlib/logic_verify.rb +1 -1
  64. data/lib/tdl/rebuild_ele/axi4.rb +6 -2
  65. data/lib/tdl/rebuild_ele/axi_stream.rb +3 -3
  66. data/lib/tdl/rebuild_ele/data_inf_c.rb +2 -2
  67. data/lib/tdl/rebuild_ele/ele_base.rb +15 -3
  68. data/lib/tdl/sdlmodule/sdlmodule.rb +17 -1
  69. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -0
  70. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +1 -1
  71. data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +3 -3
  72. data/lib/tdl/sdlmodule/test_unit_module.rb +15 -17
  73. data/lib/tdl/tdl.rb +1 -0
  74. metadata +18 -2
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data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv ADDED
@@ -0,0 +1,223 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
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+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.1.0
8
+ just fot tdl
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+ Version: VERC.0.0
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+ just fot tdl, use class parameter
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+ creaded: 2017/4/5
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+ madified:
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+ ***********************************************/
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+ `timescale 1ns/1ps
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+ `include "define_macro.sv"
16
+ module axi4_direct_algin_addr_step #(
17
+ // parameter ABANDON = "MASTER";
18
+ parameter SLAVER_ADDR_STEP = 1024,
19
+ // parameter MASTER_ADDR_STEP = 1024,
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+ parameter TERMENAL_ADDR_STEP = 1024,
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+ parameter TERMENAL_DSIZE = 128,
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+ `parameter_string MODE = "BOTH_to_BOTH", //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
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+ `parameter_string SLAVER_MODE = "BOTH", //
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+ `parameter_string MASTER_MODE = "BOTH", //
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+ //(* show = "false" *)
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+ `parameter_string IGNORE_IDSIZE = "FALSE", //(* show = "false" *)
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+ `parameter_string IGNORE_DSIZE = "FALSE", //(* show = "false" *)
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+ `parameter_string IGNORE_ASIZE = "FALSE", //(* show = "false" *)
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+ `parameter_string IGNORE_LSIZE = "FALSE" //(* show = "false" *)
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+ )(
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+ axi_inf.slaver slaver_inf,
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+ axi_inf.master master_inf
33
+ );
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+
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+
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+ import SystemPkg::*;
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+
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+ initial begin
39
+ #(1us);
40
+ if(IGNORE_IDSIZE == "FALSE")begin
41
+ assert(slaver_inf.IDSIZE <= master_inf.IDSIZE) //idsize of slaver_inf can be smaller thane master_inf's
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+ else begin
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+ $error("SLAVER AXIS IDSIZE != MASTER AXIS IDSIZE");
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+ $finish;
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+ end
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+ end
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+ if(IGNORE_DSIZE == "FALSE")begin
48
+ assert(slaver_inf.DSIZE == master_inf.DSIZE)
49
+ else $error("SLAVER AXIS DSIZE != MASTER AXIS DSIZE");
50
+ end
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+ // if(IGNORE_ASIZE == "FALSE")begin
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+ // assert(slaver_inf.ASIZE == master_inf.ASIZE)
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+ // else $error("SLAVER AXIS ASIZE != MASTER AXIS ASIZE");
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+ // end
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+ if(IGNORE_LSIZE == "FALSE")begin
56
+ assert(slaver_inf.LSIZE == master_inf.LSIZE)
57
+ else $error("SLAVER AXIS LSIZE != MASTER AXIS LSIZE");
58
+ end
59
+ case(MODE)
60
+ "BOTH_to_BOTH","BOTH_to_ONLY_READ","BOTH_to_ONLY_WRITE":
61
+ assert(slaver_inf.MODE =="BOTH" && SLAVER_MODE=="BOTH")
62
+ else $error("SLAVER AXIS MODE<%s> != BOTH",slaver_inf.MODE);
63
+ "ONLY_READ_to_BOTH":
64
+ assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
65
+ else $error("SLAVER AXIS MODE != ONLY_READ");
66
+ "ONLY_WRITE_to_BOTH","ONLY_WRITE_to_ONLY_WRITE":
67
+ assert(slaver_inf.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
68
+ else begin
69
+ $error("SLAVER AXIS MODE != ONLY_WRITE");
70
+ $finish;
71
+ end
72
+ "ONLY_READ_to_ONLY_READ","ONLY_READ_TO_ONLY_READ":
73
+ assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
74
+ else $error("SLAVER AXIS MODE != ONLY_READ");
75
+ "ONLY_WRITE_TO_ONLY_WRITE":
76
+ assert(slaver_inf.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
77
+ else $error("SLAVER AXIS MODE != ONLY_WRITE");
78
+ default:
79
+ assert(slaver_inf.MODE == "_____")
80
+ else $error("SLAVER AXIS MODE ERROR") ;
81
+ endcase
82
+
83
+ case(MODE)
84
+ "ONLY_WRITE_to_BOTH","ONLY_READ_to_BOTH","BOTH_to_BOTH":
85
+ assert(master_inf.MODE == "BOTH" && MASTER_MODE=="BOTH")
86
+ else $error("MASTER AXIS MODE != BOTH");
87
+ "BOTH_to_ONLY_READ":
88
+ assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READY")
89
+ else $error("MASTER AXIS MODE != ONLY_READ");
90
+ "BOTH_to_ONLY_WRITE","ONLY_WRITE_to_ONLY_WRITE":
91
+ assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
92
+ else $error("MASTER AXIS MODE != ONLY_WRITE");
93
+ "ONLY_READ_to_ONLY_READ","ONLY_READ_TO_ONLY_READ":
94
+ assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
95
+ else $error("MASTER AXIS MODE != ONLY_READ");
96
+ "ONLY_WRITE_TO_ONLY_WRITE":
97
+ assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
98
+ else $error("MASTER AXIS MODE != ONLY_WRITE");
99
+ default:
100
+ assert(master_inf.MODE == "_____")
101
+ else $error("MASTER AXIS MODE<%0s> ERROR",MODE);
102
+ endcase
103
+
104
+ end
105
+
106
+ localparam RF = $clog2(TERMENAL_DSIZE) - $clog2(slaver_inf.DSIZE) + $clog2(SLAVER_ADDR_STEP) - $clog2(TERMENAL_ADDR_STEP);
107
+
108
+ localparam FR = $clog2(TERMENAL_DSIZE) + $clog2(SLAVER_ADDR_STEP);
109
+ localparam FL = $clog2(slaver_inf.DSIZE) + $clog2(TERMENAL_ADDR_STEP);
110
+
111
+ generate
112
+ if( (MASTER_MODE=="ONLY_WRITE") || (MASTER_MODE=="BOTH" && (SLAVER_MODE=="ONLY_WRITE" || SLAVER_MODE=="BOTH") ) )begin
113
+ assign master_inf.axi_awid = slaver_inf.axi_awid ;
114
+
115
+ if(FR == FL)
116
+ assign master_inf.axi_awaddr = slaver_inf.axi_awaddr ;
117
+ else if(FR < FL)
118
+ assign master_inf.axi_awaddr = slaver_inf.axi_awaddr << (FL - FR) ;
119
+ else if(FR > FL)
120
+ assign master_inf.axi_awaddr = slaver_inf.axi_awaddr >> (FR - FL) ;
121
+
122
+ assign master_inf.axi_awlen = slaver_inf.axi_awlen ;
123
+ assign master_inf.axi_awsize = slaver_inf.axi_awsize ;
124
+ assign master_inf.axi_awburst = slaver_inf.axi_awburst;
125
+ assign master_inf.axi_awlock = slaver_inf.axi_awlock ;
126
+ assign master_inf.axi_awcache = slaver_inf.axi_awcache;
127
+ assign master_inf.axi_awprot = slaver_inf.axi_awprot ;
128
+ assign master_inf.axi_awqos = slaver_inf.axi_awqos ;
129
+ assign master_inf.axi_awvalid = slaver_inf.axi_awvalid;
130
+ assign slaver_inf.axi_awready = master_inf.axi_awready;
131
+ assign master_inf.axi_wdata = slaver_inf.axi_wdata ;
132
+ assign master_inf.axi_wstrb = slaver_inf.axi_wstrb ;
133
+ assign master_inf.axi_wlast = slaver_inf.axi_wlast ;
134
+ assign master_inf.axi_wvalid = slaver_inf.axi_wvalid ;
135
+ assign slaver_inf.axi_wready = master_inf.axi_wready ;
136
+ assign master_inf.axi_bready = slaver_inf.axi_bready ;
137
+ assign slaver_inf.axi_bid = master_inf.axi_bid ;
138
+ assign slaver_inf.axi_bresp = master_inf.axi_bresp ;
139
+ assign slaver_inf.axi_bvalid = master_inf.axi_bvalid ;
140
+ end
141
+ endgenerate
142
+
143
+
144
+ generate
145
+ if( (MASTER_MODE=="ONLY_READ") || (MASTER_MODE=="BOTH" && (SLAVER_MODE=="ONLY_READ" || SLAVER_MODE=="BOTH") ) )begin
146
+ assign master_inf.axi_arid = slaver_inf.axi_arid ;
147
+ // assign master_inf.axi_araddr = slaver_inf.axi_araddr ;
148
+
149
+ if(FR == FL)
150
+ assign master_inf.axi_araddr = slaver_inf.axi_araddr ;
151
+ else if(FR < FL)
152
+ assign master_inf.axi_araddr = slaver_inf.axi_araddr << (FL - FR) ;
153
+ else if(FR > FL)
154
+ assign master_inf.axi_araddr = slaver_inf.axi_araddr >> (FR - FL) ;
155
+
156
+ assign master_inf.axi_arlen = slaver_inf.axi_arlen ;
157
+ assign master_inf.axi_arsize = slaver_inf.axi_arsize ;
158
+ assign master_inf.axi_arburst = slaver_inf.axi_arburst;
159
+ assign master_inf.axi_arlock = slaver_inf.axi_arlock ;
160
+ assign master_inf.axi_arcache = slaver_inf.axi_arcache;
161
+ assign master_inf.axi_arprot = slaver_inf.axi_arprot ;
162
+ assign master_inf.axi_arqos = slaver_inf.axi_arqos ;
163
+ assign master_inf.axi_arvalid = slaver_inf.axi_arvalid;
164
+ assign slaver_inf.axi_arready = master_inf.axi_arready;
165
+ assign master_inf.axi_rready = slaver_inf.axi_rready ;
166
+ assign slaver_inf.axi_rid = master_inf.axi_rid ;
167
+ assign slaver_inf.axi_rdata = master_inf.axi_rdata ;
168
+ assign slaver_inf.axi_rresp = master_inf.axi_rresp ;
169
+ assign slaver_inf.axi_rlast = master_inf.axi_rlast ;
170
+ assign slaver_inf.axi_rvalid = master_inf.axi_rvalid ;
171
+ end
172
+ endgenerate
173
+
174
+ generate
175
+ if(MASTER_MODE=="BOTH")begin
176
+ if(SLAVER_MODE == "ONLY_READ")begin
177
+ assign master_inf.axi_awid = '0;
178
+ assign master_inf.axi_awaddr = '0;
179
+ assign master_inf.axi_awlen = '0;
180
+ assign master_inf.axi_awsize = '0;
181
+ assign master_inf.axi_awburst = '0;
182
+ assign master_inf.axi_awlock = '0;
183
+ assign master_inf.axi_awcache = '0;
184
+ assign master_inf.axi_awprot = '0;
185
+ assign master_inf.axi_awqos = '0;
186
+ assign master_inf.axi_awvalid = '0;
187
+ assign master_inf.axi_wdata = '0;
188
+ assign master_inf.axi_wstrb = '0;
189
+ assign master_inf.axi_wlast = '0;
190
+ assign master_inf.axi_wvalid = '0;
191
+ assign master_inf.axi_bready = 1'b1;
192
+ end if(SLAVER_MODE == "ONLY_WRITE")begin
193
+ assign master_inf.axi_arid = '0;
194
+ assign master_inf.axi_araddr = '0;
195
+ assign master_inf.axi_arlen = '0;
196
+ assign master_inf.axi_arsize = '0;
197
+ assign master_inf.axi_arburst = '0;
198
+ assign master_inf.axi_arlock = '0;
199
+ assign master_inf.axi_arcache = '0;
200
+ assign master_inf.axi_arprot = '0;
201
+ assign master_inf.axi_arqos = '0;
202
+ assign master_inf.axi_arvalid = '0;
203
+ assign master_inf.axi_rready = 1'b1;
204
+ end
205
+ end else if(SLAVER_MODE == "BOTH")begin
206
+ if(MASTER_MODE == "ONLY_READ")begin
207
+ assign slaver_inf.axi_awready = 1'b1;
208
+ assign slaver_inf.axi_wready = 1'b1;
209
+ assign slaver_inf.axi_bid = '0;
210
+ assign slaver_inf.axi_bresp = '0;
211
+ assign slaver_inf.axi_bvalid = '0;
212
+ end else if(SLAVER_MODE == "ONLY_WRITE")begin
213
+ assign slaver_inf.axi_arready = 1'b1;
214
+ assign slaver_inf.axi_rid = '0;
215
+ assign slaver_inf.axi_rdata = '0;
216
+ assign slaver_inf.axi_rresp = '0;
217
+ assign slaver_inf.axi_rlast = '0;
218
+ assign slaver_inf.axi_rvalid = '0;
219
+ end
220
+ end
221
+ endgenerate
222
+
223
+ endmodule
data/lib/axi/AXI4/axi4_direct_verc.sv CHANGED
@@ -67,9 +67,12 @@ initial begin
67
67
  $error("SLAVER AXIS MODE != ONLY_WRITE");
68
68
  $finish;
69
69
  end
70
- "ONLY_READ_to_ONLY_READ":
70
+ "ONLY_READ_to_ONLY_READ","ONLY_READ_TO_ONLY_READ":
71
71
  assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
72
72
  else $error("SLAVER AXIS MODE != ONLY_READ");
73
+ "ONLY_WRITE_TO_ONLY_WRITE":
74
+ assert(slaver_inf.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
75
+ else $error("SLAVER AXIS MODE != ONLY_WRITE");
73
76
  default:
74
77
  assert(slaver_inf.MODE == "_____")
75
78
  else $error("SLAVER AXIS MODE ERROR") ;
@@ -85,18 +88,21 @@ initial begin
85
88
  "BOTH_to_ONLY_WRITE","ONLY_WRITE_to_ONLY_WRITE":
86
89
  assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
87
90
  else $error("MASTER AXIS MODE != ONLY_WRITE");
88
- "ONLY_READ_to_ONLY_READ":
91
+ "ONLY_READ_to_ONLY_READ","ONLY_READ_TO_ONLY_READ":
89
92
  assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
90
93
  else $error("MASTER AXIS MODE != ONLY_READ");
94
+ "ONLY_WRITE_TO_ONLY_WRITE":
95
+ assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
96
+ else $error("MASTER AXIS MODE != ONLY_WRITE");
91
97
  default:
92
98
  assert(master_inf.MODE == "_____")
93
- else $error("MASTER AXIS MODE ERROR");
99
+ else $error("MASTER AXIS MODE<%0s> ERROR",MODE);
94
100
  endcase
95
101
 
96
102
  end
97
103
 
98
104
  generate
99
- if(MASTER_MODE!="ONLY_READ")begin
105
+ if( (MASTER_MODE=="ONLY_WRITE") || (MASTER_MODE=="BOTH" && (SLAVER_MODE=="ONLY_WRITE" || SLAVER_MODE=="BOTH") ) )begin
100
106
  assign master_inf.axi_awid = slaver_inf.axi_awid ;
101
107
  assign master_inf.axi_awaddr = slaver_inf.axi_awaddr ;
102
108
  assign master_inf.axi_awlen = slaver_inf.axi_awlen ;
@@ -122,7 +128,7 @@ endgenerate
122
128
 
123
129
 
124
130
  generate
125
- if(MASTER_MODE!="ONLY_WRITE")begin
131
+ if( (MASTER_MODE=="ONLY_READ") || (MASTER_MODE=="BOTH" && (SLAVER_MODE=="ONLY_READ" || SLAVER_MODE=="BOTH") ) )begin
126
132
  assign master_inf.axi_arid = slaver_inf.axi_arid ;
127
133
  assign master_inf.axi_araddr = slaver_inf.axi_araddr ;
128
134
  assign master_inf.axi_arlen = slaver_inf.axi_arlen ;
@@ -143,4 +149,53 @@ generate
143
149
  end
144
150
  endgenerate
145
151
 
152
+ generate
153
+ if(MASTER_MODE=="BOTH")begin
154
+ if(SLAVER_MODE == "ONLY_READ")begin
155
+ assign master_inf.axi_awid = '0;
156
+ assign master_inf.axi_awaddr = '0;
157
+ assign master_inf.axi_awlen = '0;
158
+ assign master_inf.axi_awsize = '0;
159
+ assign master_inf.axi_awburst = '0;
160
+ assign master_inf.axi_awlock = '0;
161
+ assign master_inf.axi_awcache = '0;
162
+ assign master_inf.axi_awprot = '0;
163
+ assign master_inf.axi_awqos = '0;
164
+ assign master_inf.axi_awvalid = '0;
165
+ assign master_inf.axi_wdata = '0;
166
+ assign master_inf.axi_wstrb = '0;
167
+ assign master_inf.axi_wlast = '0;
168
+ assign master_inf.axi_wvalid = '0;
169
+ assign master_inf.axi_bready = 1'b1;
170
+ end if(SLAVER_MODE == "ONLY_WRITE")begin
171
+ assign master_inf.axi_arid = '0;
172
+ assign master_inf.axi_araddr = '0;
173
+ assign master_inf.axi_arlen = '0;
174
+ assign master_inf.axi_arsize = '0;
175
+ assign master_inf.axi_arburst = '0;
176
+ assign master_inf.axi_arlock = '0;
177
+ assign master_inf.axi_arcache = '0;
178
+ assign master_inf.axi_arprot = '0;
179
+ assign master_inf.axi_arqos = '0;
180
+ assign master_inf.axi_arvalid = '0;
181
+ assign master_inf.axi_rready = 1'b1;
182
+ end
183
+ end else if(SLAVER_MODE == "BOTH")begin
184
+ if(MASTER_MODE == "ONLY_READ")begin
185
+ assign slaver_inf.axi_awready = 1'b1;
186
+ assign slaver_inf.axi_wready = 1'b1;
187
+ assign slaver_inf.axi_bid = '0;
188
+ assign slaver_inf.axi_bresp = '0;
189
+ assign slaver_inf.axi_bvalid = '0;
190
+ end else if(SLAVER_MODE == "ONLY_WRITE")begin
191
+ assign slaver_inf.axi_arready = 1'b1;
192
+ assign slaver_inf.axi_rid = '0;
193
+ assign slaver_inf.axi_rdata = '0;
194
+ assign slaver_inf.axi_rresp = '0;
195
+ assign slaver_inf.axi_rlast = '0;
196
+ assign slaver_inf.axi_rvalid = '0;
197
+ end
198
+ end
199
+ endgenerate
200
+
146
201
  endmodule
data/lib/axi/AXI4/axi4_dpram_cache.rb CHANGED
@@ -14,8 +14,8 @@ TdlBuild.axi4_dpram_cache(__dir__) do
14
14
  cm_ram_inf(dsize: a_inf.dsize,rsize: a_inf.asize,msize: a_inf.DSIZE/8) - 'xram_inf'
15
15
 
16
16
  initial do
17
- assert(a_inf.ASIZE == b_inf.ASIZE,"a_inf.ASIZE != b_inf.ASIZE")
18
- assert(a_inf.DSIZE == b_inf.DSIZE,"a_inf.ASIZE != b_inf.ASIZE")
17
+ assert(a_inf.ASIZE == b_inf.ASIZE,"a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>", a_inf.ASIZE, b_inf.ASIZE)
18
+ assert(a_inf.DSIZE == b_inf.DSIZE,"a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>", a_inf.DSIZE, b_inf.DSIZE)
19
19
  end
20
20
 
21
21
  full_axi4_to_axis.full_axi4_to_axis_ainst do |h|
data/lib/axi/AXI4/axi4_dpram_cache.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-04-16 17:01:03 +0800
8
+ creaded: XXXX.XX.XX
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -70,11 +70,11 @@ common_ram_wrapper #(
70
70
  //-------- expression ------------------------------------------------------
71
71
  initial begin
72
72
  assert(a_inf.ASIZE==b_inf.ASIZE)else begin
73
- $error("a_inf.ASIZE != b_inf.ASIZE");
73
+ $error("a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>",a_inf.ASIZE,b_inf.ASIZE);
74
74
  $stop;
75
75
  end
76
76
  assert(a_inf.DSIZE==b_inf.DSIZE)else begin
77
- $error("a_inf.ASIZE != b_inf.ASIZE");
77
+ $error("a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>",a_inf.DSIZE,b_inf.DSIZE);
78
78
  $stop;
79
79
  end
80
80
  end
data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv ADDED
@@ -0,0 +1,146 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.1 2017/5/24
8
+ use axi4_data_convert_A1
9
+ Version: VERA.1.0 2017/9/30
10
+ can discard partition
11
+ Version: VERB.0.0 2017/12/7
12
+ if slaver_inf.DSIZE is not 2**N,then 'width_convert' fisrt
13
+ Version: VERB.1.0 2021/10/03
14
+ axi4_direct_verc replace axi4_direct_verb
15
+ creaded: 2017/3/1
16
+ madified:
17
+ ***********************************************/
18
+ `timescale 1ns/1ps
19
+ `include "define_macro.sv"
20
+ module axi4_long_to_axi4_wide_B1 #(
21
+ parameter PIPE = "OFF",
22
+ parameter PARTITION = "ON", //ON OFF
23
+ `parameter_string MODE = "BOTH_to_BOTH", //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
24
+ `parameter_string SLAVER_MODE = "BOTH", //
25
+ `parameter_string MASTER_MODE = "BOTH" //
26
+ )(
27
+ axi_inf.slaver slaver_inf,
28
+ axi_inf.master master_inf //wide ADDR_STEP == 1
29
+ );
30
+
31
+ // localparam real ADDR_STEP = slaver_inf.DSIZE/(master_inf.DSIZE/8.0); //addr burst == 8
32
+
33
+ import SystemPkg::*;
34
+
35
+ initial begin
36
+ assert(slaver_inf.MODE == master_inf.MODE)
37
+ else begin
38
+ $error("SLAVER AXIS MODE != MASTER AXIS MODE");
39
+ $stop;
40
+ end
41
+ end
42
+
43
+
44
+ //--->> width first <<------------------------------
45
+
46
+ localparam WCSIZE = 2**($clog2(slaver_inf.DSIZE));
47
+
48
+ axi_inf #(
49
+ .IDSIZE (slaver_inf.IDSIZE ),
50
+ .ASIZE (slaver_inf.ASIZE ),
51
+ .LSIZE (slaver_inf.LSIZE ),
52
+ .DSIZE (WCSIZE ),
53
+ .MODE (slaver_inf.MODE ),
54
+ .ADDR_STEP (slaver_inf.ADDR_STEP*WCSIZE/slaver_inf.DSIZE )
55
+ )axi_inf_first_wc(
56
+ .axi_aclk (slaver_inf.axi_aclk ),
57
+ .axi_aresetn (slaver_inf.axi_aresetn )
58
+ );
59
+
60
+ generate
61
+ if(WCSIZE != slaver_inf.DSIZE)
62
+ axi4_data_convert_A1 axi4_data_convert_inst(
63
+ /* axi_inf.slaver_inf */ .axi_in (slaver_inf ),
64
+ /* axi_inf.master_inf */ .axi_out (axi_inf_first_wc )
65
+ );
66
+ else
67
+ axi4_direct_verc #(
68
+ .MODE (MODE), //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
69
+ .SLAVER_MODE (SLAVER_MODE), //
70
+ .MASTER_MODE (MASTER_MODE) //
71
+ )axi4_direct_verc_inst(
72
+ /* axi_inf.slaver_inf */ .slaver_inf (slaver_inf ),
73
+ /* axi_inf.master_inf */ .master_inf (axi_inf_first_wc )
74
+ );
75
+ endgenerate
76
+ //---<< width first >>------------------------------
77
+
78
+ axi_inf #(
79
+ .IDSIZE (master_inf.IDSIZE ),
80
+ .ASIZE (axi_inf_first_wc.ASIZE ),
81
+ .LSIZE (axi_inf_first_wc.LSIZE ),
82
+ .DSIZE (axi_inf_first_wc.DSIZE ),
83
+ .MODE (axi_inf_first_wc.MODE ),
84
+ .ADDR_STEP (axi_inf_first_wc.ADDR_STEP )
85
+ )axi_inf_pout(
86
+ .axi_aclk (slaver_inf.axi_aclk ),
87
+ .axi_aresetn (slaver_inf.axi_aresetn )
88
+ );
89
+
90
+ axi_inf #(
91
+ .IDSIZE (master_inf.IDSIZE ),
92
+ .ASIZE (master_inf.ASIZE ),
93
+ .LSIZE (master_inf.LSIZE ),
94
+ .DSIZE (master_inf.DSIZE ),
95
+ .MODE (axi_inf_first_wc.MODE ),
96
+ .ADDR_STEP (master_inf.ADDR_STEP )
97
+ )axi_inf_cdout(
98
+ .axi_aclk (slaver_inf.axi_aclk ),
99
+ .axi_aresetn (slaver_inf.axi_aresetn )
100
+ );
101
+
102
+
103
+ // localparam PSIZE = (((128/slaver_inf.DSIZE) * (slaver_inf.DSIZE+0.0)) * master_inf.DSIZE) / slaver_inf.DSIZE;
104
+ generate
105
+ if(PARTITION == "ON" || PARTITION == "TRUE")begin
106
+ axi4_partition_OD #(
107
+ // .PSIZE (master_inf.DSIZE*128/slaver_inf.DSIZE ),
108
+ .PSIZE (int'((((128/axi_inf_first_wc.DSIZE) * (axi_inf_first_wc.DSIZE+0.0)) * master_inf.DSIZE) / axi_inf_first_wc.DSIZE ))
109
+ // .ADDR_STEP (slaver_inf.DSIZE/(master_inf.DSIZE/8.0) )
110
+ // .ADDR_STEP (4*slaver_inf.DSIZE/16.0 )
111
+ )axi4_partition_inst(
112
+ /* axi_inf.slaver_inf */ .slaver_inf (axi_inf_first_wc ),
113
+ /* axi_inf.master_inf */ .master_inf (axi_inf_pout )
114
+ );
115
+
116
+ axi4_data_convert_verb #(
117
+ .SLAVER_MODE (SLAVER_MODE), //
118
+ .MASTER_MODE (MASTER_MODE) //
119
+ )axi4_data_convert_inst(
120
+ /* axi_inf.slaver_inf */ .axi_in (axi_inf_pout ),
121
+ /* axi_inf.master_inf */ .axi_out (axi_inf_cdout )
122
+ );
123
+ end else begin
124
+ axi4_data_convert_verb #(
125
+ .SLAVER_MODE (SLAVER_MODE), //
126
+ .MASTER_MODE (MASTER_MODE) //
127
+ )axi4_data_convert_inst(
128
+ /* axi_inf.slaver_inf */ .axi_in (axi_inf_first_wc ),
129
+ /* axi_inf.master_inf */ .axi_out (axi_inf_cdout )
130
+ );
131
+
132
+ end
133
+ endgenerate
134
+
135
+
136
+ axi4_packet_fifo_verb #( //512
137
+ .PIPE (PIPE ),
138
+ .DEPTH (4 ),
139
+ .SLAVER_MODE (SLAVER_MODE ), //
140
+ .MASTER_MODE (MASTER_MODE ) //
141
+ )axi4_packet_fifo_inst(
142
+ /* axi_inf.slaver_inf */ .axi_in (axi_inf_cdout ),
143
+ /* axi_inf.master_inf */ .axi_out (master_inf )
144
+ );
145
+
146
+ endmodule
data/lib/axi/AXI4/axi4_ram_cache.rb ADDED
@@ -0,0 +1,23 @@
1
+ require_shdl 'axi4_dpram_cache'
2
+
3
+ TdlBuild.axi4_ram_cache(__dir__) do
4
+ parameter.INIT_FILE ''
5
+ port.axi4.slaver - 'a_inf'
6
+
7
+ axi4_dpram_cache.axi4_dpram_cache_inst do |h|
8
+ h.parameter.INIT_FILE param.INIT_FILE
9
+ h.port.axi4.slaver.a_inf a_inf
10
+ h.port.axi4.slaver.b_inf a_inf.copy(name: 'b_inf')
11
+ end
12
+
13
+ Assign do
14
+ b_inf.axi_awvalid <= 1.b0
15
+ b_inf.axi_arvalid <= 1.b0
16
+
17
+ b_inf.axi_wvalid <= 1.b0
18
+ b_inf.axi_rready <= 1.b1
19
+
20
+ b_inf.axi_bready <= 1.b1
21
+ end
22
+
23
+ end
data/lib/axi/AXI4/axi4_ram_cache.sv ADDED
@@ -0,0 +1,39 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: XXXX.XX.XX
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+
13
+ module axi4_ram_cache #(
14
+ parameter INIT_FILE = ""
15
+ )(
16
+ axi_inf.slaver a_inf
17
+ );
18
+
19
+ //==========================================================================
20
+ //-------- define ----------------------------------------------------------
21
+
22
+ axi_inf #(.DSIZE(a_inf.DSIZE),.IDSIZE(a_inf.IDSIZE),.ASIZE(a_inf.ASIZE),.LSIZE(a_inf.LSIZE),.MODE(a_inf.MODE),.ADDR_STEP(a_inf.ADDR_STEP),.FreqM(a_inf.FreqM)) b_inf (.axi_aclk(a_inf.axi_aclk),.axi_aresetn(a_inf.axi_aresetn)) ;
23
+ //==========================================================================
24
+ //-------- instance --------------------------------------------------------
25
+ axi4_dpram_cache #(
26
+ .INIT_FILE (INIT_FILE )
27
+ )axi4_dpram_cache_inst(
28
+ /* axi_inf.slaver */.a_inf (a_inf ),
29
+ /* axi_inf.slaver */.b_inf (b_inf )
30
+ );
31
+ //==========================================================================
32
+ //-------- expression ------------------------------------------------------
33
+ assign b_inf.axi_awvalid = 1'b0;
34
+ assign b_inf.axi_arvalid = 1'b0;
35
+ assign b_inf.axi_wvalid = 1'b0;
36
+ assign b_inf.axi_rready = 1'b1;
37
+ assign b_inf.axi_bready = 1'b1;
38
+
39
+ endmodule