axi_tdl 0.1.3 → 0.1.5
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- checksums.yaml +4 -4
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +1 -1
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +1 -1
- data/lib/axi/common/test_write_mem.sv +1 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +1 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +6 -6
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/public_atom_module/sim_system_pkg.sv +4 -0
- data/lib/public_atom_module/synth_system_pkg.sv +4 -0
- data/lib/tdl/examples/11_test_unit/dve.tcl +153 -6
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +33 -7
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +2 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +1 -2
- data/lib/tdl/examples/11_test_unit/tu0.sv +4 -4
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +1 -1
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +1 -1
- data/lib/tdl/examples/8_top_module/dve.tcl +6 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -2
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -3
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -2
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +1 -1
- data/lib/tdl/tdl.rb +0 -10
- metadata +3 -1
checksums.yaml
CHANGED
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@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: '048d045e78b400e945ff441c154ef78f8073619c51a1547e84526cb9345d72f4'
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data.tar.gz: baa90f99cf5d67251033740eb77a6314a74b445520159da7fba098d57cffd7f7
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 95f82468aeffc02b0c0bc09574d9805eef139180474f02a736fb85f8081a874947eb9d4730ebca7197e5d2051c9d8c73f8404b2732d1b3810eab9e4ffbf4cd71
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data.tar.gz: ec8a233a0df4d3b6f47f4a5078f08ee538acf7153e09c62d0cba18f4e95bcecfca253c211cfa298d51d3486686bb9c487a3e5cbc45b41d2f699c90ac5c36d95a
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-04-03
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created: 2021-04-03 14:03:23 +0800
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madified:
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***********************************************/
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`timescale 1ns/1ps
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@@ -47,11 +47,11 @@ axis_sim_master_model #(
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.LOOP ("TRUE" ),
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.RAM_DEPTH (246 )
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)sim_model_inst_origin_inf(
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/* input */.enable (
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/* input */.load_trigger (1'b0
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/* input */.total_length (246
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/* input */.mem_file ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/
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/* axi_stream_inf.master */.out_inf (origin_inf
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/* input */.enable (1'b1 ),
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/* input */.load_trigger (1'b0 ),
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/* input */.total_length (246 ),
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/* input */.mem_file ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/coe_origin_inf_R1699.coe" ),
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/* axi_stream_inf.master */.out_inf (origin_inf )
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);
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axis_sim_verify_by_coe #(
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.RAM_DEPTH (21 ),
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data/lib/axi_tdl/version.rb
CHANGED
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@@ -12,8 +12,128 @@ gui_set_time_units 1ps
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## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
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## ==== [add_signal] ===== ##
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## -------------- sub_md0_logic -------------------------
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set _wave_session_group_sub_md0_logic sub_md0_logic
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# set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
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set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.cnt} }
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## ============== sub_md0_logic =========================
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## -------------- sub_md0_interface -------------------------
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set _wave_session_group_sub_md0_interface sub_md0_interface
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# set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
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set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.axis_in} }
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## ============== sub_md0_interface =========================
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## -------------- sub_md0_default -------------------------
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set _wave_session_group_sub_md0_default sub_md0_default
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# set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
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set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" { }
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## ============== sub_md0_default =========================
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## -------------- sub_md0_default.inter_tf -------------------------
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## set _wave_session_group_sub_md0_default_inter_tf Group1
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## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
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set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
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append _wave_session_group_sub_md0_default_inter_tf inter_tf
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set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
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# set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.inter_tf} }
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## ============== sub_md0_default.inter_tf =========================
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## -------------- sub_md1_default -------------------------
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set _wave_session_group_sub_md1_default sub_md1_default
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# set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
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set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
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}
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set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.cnt} {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.axis_out} {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.enable} }
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## ============== sub_md1_default =========================
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## -------------- sub_md1_inner -------------------------
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set _wave_session_group_sub_md1_inner sub_md1_inner
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# set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
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set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
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}
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set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" { }
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## ============== sub_md1_inner =========================
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## -------------- sub_md1_inner.inter_tf -------------------------
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## set _wave_session_group_sub_md1_inner_inter_tf Group1
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## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
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set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
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append _wave_session_group_sub_md1_inner_inter_tf inter_tf
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set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
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# set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.inter_tf} }
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## ============== sub_md1_inner.inter_tf =========================
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## -------------- exp_test_unit_sim_default -------------------------
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set _wave_session_group_exp_test_unit_sim_default exp_test_unit_sim_default
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# set _wave_session_group_exp_test_unit_sim_default [gui_sg_generate_new_name -seed exp_test_unit_sim_default]
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if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_sim_default"]} {
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set _wave_session_group_exp_test_unit_sim_default [gui_sg_generate_new_name]
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}
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set Group2_exp_test_unit_sim_default "$_wave_session_group_exp_test_unit_sim_default"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_sim_default" { }
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## ============== exp_test_unit_sim_default =========================
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## -------------- exp_test_unit_sim_default.axis_data_inf -------------------------
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## set _wave_session_group_exp_test_unit_sim_default_axis_data_inf Group1
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## set _wave_session_group_exp_test_unit_sim_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_sim_default ]
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set _wave_session_group_exp_test_unit_sim_default_axis_data_inf $_wave_session_group_exp_test_unit_sim_default|
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append _wave_session_group_exp_test_unit_sim_default_axis_data_inf axis_data_inf
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set exp_test_unit_sim_default|axis_data_inf "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf"
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# set Group2_exp_test_unit_sim_default_axis_data_inf "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf" { {Sim:tb_exp_test_unit_sim.rtl_top.axis_data_inf} }
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## ============== exp_test_unit_sim_default.axis_data_inf =========================
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## 创建波形窗口
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if {![info exists useOldWindow]} {
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@@ -42,9 +162,33 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
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## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
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## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
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## === [add_signal_wave] === ##
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-
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-
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## -------------- Group2_sub_md0_logic -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
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## ============== Group2_sub_md0_logic =========================
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## -------------- Group2_sub_md0_interface -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
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## ============== Group2_sub_md0_interface =========================
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## -------------- Group2_sub_md0_default -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
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## ============== Group2_sub_md0_default =========================
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## -------------- sub_md0_default|inter_tf -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
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## ============== sub_md0_default|inter_tf =========================
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## -------------- Group2_sub_md1_default -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
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## ============== Group2_sub_md1_default =========================
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## -------------- Group2_sub_md1_inner -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
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## ============== Group2_sub_md1_inner =========================
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## -------------- sub_md1_inner|inter_tf -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
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## ============== sub_md1_inner|inter_tf =========================
|
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186
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## -------------- Group2_exp_test_unit_sim_default -------------------------
|
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187
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_sim_default}]
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## ============== Group2_exp_test_unit_sim_default =========================
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## -------------- exp_test_unit_sim_default|axis_data_inf -------------------------
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190
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_sim_default|axis_data_inf}]
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+
## ============== exp_test_unit_sim_default|axis_data_inf =========================
|
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48
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49
193
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gui_seek_criteria -id ${Wave.3} {Any Edge}
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50
194
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@@ -61,9 +205,12 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
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gui_list_set_filter -id ${Wave.3} -text {*}
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##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
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## === [add_bar] === ##
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gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_logic} -position in
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gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_interface} -position in
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gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_default} -position in
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gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_default} -position in
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gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_inner} -position in
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gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_exp_test_unit_sim_default} -position in
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gui_marker_move -id ${Wave.3} {C1} 560248001
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gui_view_scroll -id ${Wave.3} -vertical -set 35
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@@ -1,35 +1,9 @@
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-04-03 13:14:45 +0800
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module exp_test_unit (
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input clock,
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input rst_n
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic enable;
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axi_stream_inf #(.DSIZE(8),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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sub_md1 sub_md1_inst(
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/* axi_stream_inf.master */.axis_out (axis_data_inf ),
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/* output */.enable (enable )
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);
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sub_md0 sub_md0_inst(
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/* axi_stream_inf.slaver */.axis_in (axis_data_inf ),
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/* input */.enable (enable )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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`timescale 1ns/1ps
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module exp_test_unit();
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initial begin
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#(1us);
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$warning("Check TopModule.sim,please!!!");
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$stop;
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end
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endmodule
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-04-03 14:05:10 +0800
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module exp_test_unit_sim (
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input clock,
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input rst_n
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic enable;
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axi_stream_inf #(.DSIZE(8),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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sub_md1 sub_md1_inst(
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/* axi_stream_inf.master */.axis_out (axis_data_inf ),
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/* output */.enable (enable )
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);
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sub_md0 sub_md0_inst(
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/* axi_stream_inf.slaver */.axis_in (axis_data_inf ),
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/* input */.enable (enable )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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endmodule
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@@ -5,10 +5,11 @@ _______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-04-03 13:
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created: 2021-04-03 13:47:04 +0800
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madified:
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***********************************************/
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module tb_exp_test_unit();
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//==========================================================================
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@@ -5,11 +5,10 @@ _______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-04-03
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created: 2021-04-03 14:05:10 +0800
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madified:
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***********************************************/
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module tb_exp_test_unit_sim();
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//==========================================================================
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@@ -5,7 +5,7 @@ _______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-04-03
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created: 2021-04-03 14:05:10 +0800
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***********************************************/
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`timescale 1ns/1ps
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@@ -27,10 +27,10 @@ module tu0 (
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initial begin
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to_down_pass = 1'b0;
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wait(from_up_pass);
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$root.
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$root.
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$root.tb_exp_test_unit_sim.test_unit_region = "tu0";
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$root.tb_exp_test_unit_sim.rtl_top.sub_md1_inst.enable = 1'b1;
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#(1us);
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$root.
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$root.tb_exp_test_unit_sim.rtl_top.sub_md1_inst.enable = 1'b0;
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#(500us);
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to_down_pass = 1'b1;
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end
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@@ -5,7 +5,7 @@ _______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-04-03 13:
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created: 2021-04-03 13:35:52 +0800
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***********************************************/
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`timescale 1ns/1ps
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@@ -19,7 +19,7 @@ module test_module_var #(
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//==========================================================================
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//-------- define ----------------------------------------------------------
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localparam ASIZE = 20
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localparam ASIZE = 20;
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axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
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axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
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@@ -13,6 +13,8 @@ gui_set_time_units 1ps
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## ==== [add_signal] ===== ##
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## 创建波形窗口
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if {![info exists useOldWindow]} {
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set useOldWindow true
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@@ -42,6 +44,8 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
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## === [add_signal_wave] === ##
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gui_seek_criteria -id ${Wave.3} {Any Edge}
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@@ -59,6 +63,8 @@ gui_list_set_filter -id ${Wave.3} -text {*}
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## === [add_bar] === ##
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gui_marker_move -id ${Wave.3} {C1} 560248001
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gui_view_scroll -id ${Wave.3} -vertical -set 35
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gui_show_grid -id ${Wave.3} -enable false
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@@ -5,11 +5,10 @@ _______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-04-03
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created: 2021-04-03 14:05:10 +0800
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***********************************************/
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module tb_test_top();
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//==========================================================================
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@@ -12,6 +12,128 @@ gui_set_time_units 1ps
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## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
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## ==== [add_signal] ===== ##
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## -------------- sub_md0_logic -------------------------
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set _wave_session_group_sub_md0_logic sub_md0_logic
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# set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
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set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.cnt} }
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## ============== sub_md0_logic =========================
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## -------------- sub_md0_interface -------------------------
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set _wave_session_group_sub_md0_interface sub_md0_interface
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# set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
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set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.axis_in} }
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## ============== sub_md0_interface =========================
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## -------------- sub_md0_default -------------------------
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set _wave_session_group_sub_md0_default sub_md0_default
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# set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
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set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" { }
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## ============== sub_md0_default =========================
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## -------------- sub_md0_default.inter_tf -------------------------
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## set _wave_session_group_sub_md0_default_inter_tf Group1
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## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
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set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
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append _wave_session_group_sub_md0_default_inter_tf inter_tf
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set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
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# set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.inter_tf} }
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## ============== sub_md0_default.inter_tf =========================
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## -------------- sub_md1_default -------------------------
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set _wave_session_group_sub_md1_default sub_md1_default
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# set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
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set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
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}
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set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.cnt} {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.axis_out} {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.enable} }
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## ============== sub_md1_default =========================
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## -------------- sub_md1_inner -------------------------
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set _wave_session_group_sub_md1_inner sub_md1_inner
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# set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
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set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
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}
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set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" { }
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## ============== sub_md1_inner =========================
|
|
93
|
+
|
|
94
|
+
|
|
95
|
+
## -------------- sub_md1_inner.inter_tf -------------------------
|
|
96
|
+
## set _wave_session_group_sub_md1_inner_inter_tf Group1
|
|
97
|
+
## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
|
|
98
|
+
|
|
99
|
+
set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
|
|
100
|
+
append _wave_session_group_sub_md1_inner_inter_tf inter_tf
|
|
101
|
+
set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
|
|
102
|
+
|
|
103
|
+
# set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
|
|
104
|
+
|
|
105
|
+
## 添加信号到 group
|
|
106
|
+
gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.inter_tf} }
|
|
107
|
+
## ============== sub_md1_inner.inter_tf =========================
|
|
108
|
+
|
|
109
|
+
|
|
110
|
+
## -------------- exp_test_unit_sim_default -------------------------
|
|
111
|
+
set _wave_session_group_exp_test_unit_sim_default exp_test_unit_sim_default
|
|
112
|
+
# set _wave_session_group_exp_test_unit_sim_default [gui_sg_generate_new_name -seed exp_test_unit_sim_default]
|
|
113
|
+
if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_sim_default"]} {
|
|
114
|
+
set _wave_session_group_exp_test_unit_sim_default [gui_sg_generate_new_name]
|
|
115
|
+
}
|
|
116
|
+
set Group2_exp_test_unit_sim_default "$_wave_session_group_exp_test_unit_sim_default"
|
|
117
|
+
|
|
118
|
+
## 添加信号到 group
|
|
119
|
+
gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_sim_default" { }
|
|
120
|
+
## ============== exp_test_unit_sim_default =========================
|
|
121
|
+
|
|
122
|
+
|
|
123
|
+
## -------------- exp_test_unit_sim_default.axis_data_inf -------------------------
|
|
124
|
+
## set _wave_session_group_exp_test_unit_sim_default_axis_data_inf Group1
|
|
125
|
+
## set _wave_session_group_exp_test_unit_sim_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_sim_default ]
|
|
126
|
+
|
|
127
|
+
set _wave_session_group_exp_test_unit_sim_default_axis_data_inf $_wave_session_group_exp_test_unit_sim_default|
|
|
128
|
+
append _wave_session_group_exp_test_unit_sim_default_axis_data_inf axis_data_inf
|
|
129
|
+
set exp_test_unit_sim_default|axis_data_inf "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf"
|
|
130
|
+
|
|
131
|
+
# set Group2_exp_test_unit_sim_default_axis_data_inf "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf"
|
|
132
|
+
|
|
133
|
+
## 添加信号到 group
|
|
134
|
+
gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf" { {Sim:tb_exp_test_unit_sim.rtl_top.axis_data_inf} }
|
|
135
|
+
## ============== exp_test_unit_sim_default.axis_data_inf =========================
|
|
136
|
+
|
|
15
137
|
|
|
16
138
|
## 创建波形窗口
|
|
17
139
|
if {![info exists useOldWindow]} {
|
|
@@ -40,7 +162,33 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
|
|
|
40
162
|
## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
|
|
41
163
|
## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
|
|
42
164
|
## === [add_signal_wave] === ##
|
|
43
|
-
|
|
165
|
+
## -------------- Group2_sub_md0_logic -------------------------
|
|
166
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
|
|
167
|
+
## ============== Group2_sub_md0_logic =========================
|
|
168
|
+
## -------------- Group2_sub_md0_interface -------------------------
|
|
169
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
|
|
170
|
+
## ============== Group2_sub_md0_interface =========================
|
|
171
|
+
## -------------- Group2_sub_md0_default -------------------------
|
|
172
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
|
|
173
|
+
## ============== Group2_sub_md0_default =========================
|
|
174
|
+
## -------------- sub_md0_default|inter_tf -------------------------
|
|
175
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
|
|
176
|
+
## ============== sub_md0_default|inter_tf =========================
|
|
177
|
+
## -------------- Group2_sub_md1_default -------------------------
|
|
178
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
|
|
179
|
+
## ============== Group2_sub_md1_default =========================
|
|
180
|
+
## -------------- Group2_sub_md1_inner -------------------------
|
|
181
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
|
|
182
|
+
## ============== Group2_sub_md1_inner =========================
|
|
183
|
+
## -------------- sub_md1_inner|inter_tf -------------------------
|
|
184
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
|
|
185
|
+
## ============== sub_md1_inner|inter_tf =========================
|
|
186
|
+
## -------------- Group2_exp_test_unit_sim_default -------------------------
|
|
187
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_sim_default}]
|
|
188
|
+
## ============== Group2_exp_test_unit_sim_default =========================
|
|
189
|
+
## -------------- exp_test_unit_sim_default|axis_data_inf -------------------------
|
|
190
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_sim_default|axis_data_inf}]
|
|
191
|
+
## ============== exp_test_unit_sim_default|axis_data_inf =========================
|
|
44
192
|
|
|
45
193
|
gui_seek_criteria -id ${Wave.3} {Any Edge}
|
|
46
194
|
|
|
@@ -57,7 +205,12 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
|
|
|
57
205
|
gui_list_set_filter -id ${Wave.3} -text {*}
|
|
58
206
|
##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
|
|
59
207
|
## === [add_bar] === ##
|
|
60
|
-
|
|
208
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_logic} -position in
|
|
209
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_interface} -position in
|
|
210
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_default} -position in
|
|
211
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_default} -position in
|
|
212
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_inner} -position in
|
|
213
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_exp_test_unit_sim_default} -position in
|
|
61
214
|
|
|
62
215
|
gui_marker_move -id ${Wave.3} {C1} 560248001
|
|
63
216
|
gui_view_scroll -id ${Wave.3} -vertical -set 35
|
|
@@ -5,12 +5,10 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-04-03 13:
|
|
8
|
+
created: 2021-04-03 13:47:04 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
12
|
-
`timescale 1ns/1ps
|
|
13
|
-
`timescale 1ns/1ps
|
|
14
12
|
|
|
15
13
|
module tb_test_tttop();
|
|
16
14
|
//==========================================================================
|
|
@@ -5,11 +5,10 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-04-03
|
|
8
|
+
created: 2021-04-03 14:05:10 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
12
|
-
`timescale 1ns/1ps
|
|
13
12
|
|
|
14
13
|
module tb_test_tttop_sim();
|
|
15
14
|
//==========================================================================
|
|
@@ -1,40 +1,9 @@
|
|
|
1
|
-
/**********************************************
|
|
2
|
-
_______________________________________
|
|
3
|
-
___________ Cook Darwin __________
|
|
4
|
-
_______________________________________
|
|
5
|
-
descript:
|
|
6
|
-
author : Cook.Darwin
|
|
7
|
-
Version: VERA.0.0
|
|
8
|
-
created: 2021-04-03 13:14:45 +0800
|
|
9
|
-
madified:
|
|
10
|
-
***********************************************/
|
|
11
|
-
`timescale 1ns/1ps
|
|
12
|
-
|
|
13
|
-
module test_tttop (
|
|
14
|
-
input global_sys_clk
|
|
15
|
-
);
|
|
16
|
-
|
|
17
|
-
//==========================================================================
|
|
18
|
-
//-------- define ----------------------------------------------------------
|
|
19
|
-
logic clock_100M;
|
|
20
|
-
logic rstn_100M;
|
|
21
|
-
axi_stream_inf #(.DSIZE(16),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
|
|
22
|
-
//==========================================================================
|
|
23
|
-
//-------- instance --------------------------------------------------------
|
|
24
|
-
simple_clock simple_clock_inst(
|
|
25
|
-
/* input clock */.sys_clk (global_sys_clk ),
|
|
26
|
-
/* output clock */.clock (clock_100M ),
|
|
27
|
-
/* output reset */.rst_n (rstn_100M )
|
|
28
|
-
);
|
|
29
|
-
a_test_md a_test_md_inst(
|
|
30
|
-
/* input clock */.clock (clock_100M ),
|
|
31
|
-
/* input reset */.rst (~rstn_100M ),
|
|
32
|
-
/* axi_stream_inf.master */.origin_inf (x_origin_inf )
|
|
33
|
-
);
|
|
34
|
-
//==========================================================================
|
|
35
|
-
//-------- expression ------------------------------------------------------
|
|
36
|
-
assign x_origin_inf.axis_tvalid = 1'b0;
|
|
37
|
-
assign x_origin_inf.axis_tdata = '0;
|
|
38
|
-
assign x_origin_inf.axis_tlast = 1'b0;
|
|
39
1
|
|
|
2
|
+
`timescale 1ns/1ps
|
|
3
|
+
module test_tttop();
|
|
4
|
+
initial begin
|
|
5
|
+
#(1us);
|
|
6
|
+
$warning("Check TopModule.sim,please!!!");
|
|
7
|
+
$stop;
|
|
8
|
+
end
|
|
40
9
|
endmodule
|
|
@@ -1,9 +1,40 @@
|
|
|
1
|
-
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.0.0
|
|
8
|
+
created: 2021-04-03 14:05:10 +0800
|
|
9
|
+
madified:
|
|
10
|
+
***********************************************/
|
|
2
11
|
`timescale 1ns/1ps
|
|
3
|
-
|
|
4
|
-
|
|
5
|
-
|
|
6
|
-
|
|
7
|
-
|
|
8
|
-
|
|
12
|
+
|
|
13
|
+
module test_tttop_sim (
|
|
14
|
+
input global_sys_clk
|
|
15
|
+
);
|
|
16
|
+
|
|
17
|
+
//==========================================================================
|
|
18
|
+
//-------- define ----------------------------------------------------------
|
|
19
|
+
logic clock_100M;
|
|
20
|
+
logic rstn_100M;
|
|
21
|
+
axi_stream_inf #(.DSIZE(16),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
|
|
22
|
+
//==========================================================================
|
|
23
|
+
//-------- instance --------------------------------------------------------
|
|
24
|
+
simple_clock simple_clock_inst(
|
|
25
|
+
/* input clock */.sys_clk (global_sys_clk ),
|
|
26
|
+
/* output clock */.clock (clock_100M ),
|
|
27
|
+
/* output reset */.rst_n (rstn_100M )
|
|
28
|
+
);
|
|
29
|
+
a_test_md a_test_md_inst(
|
|
30
|
+
/* input clock */.clock (clock_100M ),
|
|
31
|
+
/* input reset */.rst (~rstn_100M ),
|
|
32
|
+
/* axi_stream_inf.master */.origin_inf (x_origin_inf )
|
|
33
|
+
);
|
|
34
|
+
//==========================================================================
|
|
35
|
+
//-------- expression ------------------------------------------------------
|
|
36
|
+
assign x_origin_inf.axis_tvalid = 1'b0;
|
|
37
|
+
assign x_origin_inf.axis_tdata = '0;
|
|
38
|
+
assign x_origin_inf.axis_tlast = 1'b0;
|
|
39
|
+
|
|
9
40
|
endmodule
|
|
@@ -57,7 +57,7 @@ class SdlModule
|
|
|
57
57
|
|
|
58
58
|
head_str,body_str = build_module_verb(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
|
|
59
59
|
new_str = head_str+body_str
|
|
60
|
-
if body_str.gsub(
|
|
60
|
+
if body_str.gsub(/\/\/.*/,"").strip != old_str
|
|
61
61
|
File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f|
|
|
62
62
|
f.print new_str
|
|
63
63
|
end
|
data/lib/tdl/tdl.rb
CHANGED
|
@@ -271,16 +271,6 @@ class Tdl
|
|
|
271
271
|
puts(pagination("SUMMARY"))
|
|
272
272
|
puts "#{TopModule.sim ? 'SIM' : 'SYNTH'} RUN SPEND #{Time.now - $__start_time__} sec @ TIME : #{Time.now}"
|
|
273
273
|
|
|
274
|
-
## -----------
|
|
275
|
-
# TopModule.current.ref_modules.uniq.each do |e|
|
|
276
|
-
# unless e.is_a? ClassHDL::ClearSdlModule
|
|
277
|
-
# puts "#{e.real_sv_path}: #{e.module_name}"
|
|
278
|
-
# end
|
|
279
|
-
# end
|
|
280
|
-
## ===========
|
|
281
|
-
# File.open("/home/myw357/work/FPGA/mammo_tcp_20210315/tmp.tcl", "w") do |f|
|
|
282
|
-
# f.puts SdlModule.call_module('test_mac_1g_verb').gen_dev_wave_tcl
|
|
283
|
-
# end
|
|
284
274
|
end
|
|
285
275
|
|
|
286
276
|
end
|
metadata
CHANGED
|
@@ -1,7 +1,7 @@
|
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
|
2
2
|
name: axi_tdl
|
|
3
3
|
version: !ruby/object:Gem::Version
|
|
4
|
-
version: 0.1.
|
|
4
|
+
version: 0.1.5
|
|
5
5
|
platform: ruby
|
|
6
6
|
authors:
|
|
7
7
|
- Cook.Darwin
|
|
@@ -577,6 +577,8 @@ files:
|
|
|
577
577
|
- lib/public_atom_module/sim/clock_rst_verb.sv
|
|
578
578
|
- lib/public_atom_module/sim/latency_long_tb.sv
|
|
579
579
|
- lib/public_atom_module/sim/latency_long_tb.sv.bak
|
|
580
|
+
- lib/public_atom_module/sim_system_pkg.sv
|
|
581
|
+
- lib/public_atom_module/synth_system_pkg.sv
|
|
580
582
|
- lib/spec/spec_helper.rb
|
|
581
583
|
- lib/tdl/LICENSE
|
|
582
584
|
- lib/tdl/Logic/Logic.tar.gz
|