axi_tdl 0.1.19 → 0.1.20
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/Logic/logic_latency.rb +10 -7
- data/lib/tdl/examples/11_logic_latency/test_logic_latency.rb +11 -0
- data/lib/tdl/examples/11_logic_latency/test_logic_latency.sv +46 -0
- data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +33 -7
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +7 -33
- data/lib/tdl/examples/11_test_unit/tu0.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/dve.tcl +0 -6
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
- metadata +4 -2
checksums.yaml
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metadata.gz:
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metadata.gz: a8eaf43500813537ef34b6dc527aa5bde8fc7ae089b89dfc27876f6461a8d484
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data.tar.gz: 1f05d920964b4123e8e1b8fdbb32b2b96e017d734364b3a325dfd6d2adc77b97
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metadata.gz:
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metadata.gz: 70fcc7a0e276e48ecf4ab38633398bd875e02bf354b9f25ee474855c4cd249cc2a57e042f3fdc42caaa21d9e2aef8beac71b1cd76de4d847de977428af20581d
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data.tar.gz: b0d765030302b31efab0434bd7f44aec26425a2c6ebb01196a1ba4df43da7198a28aaba06467429982c4ff8d405b7451b23d7e165e245c36ca72c283af15dc57
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data/lib/axi_tdl/version.rb
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@@ -77,12 +77,14 @@ cross_clk_sync #(
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return new_l
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end
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def broaden_and_cross_clk(phase: "POSITIVE",len:4,lat:2,wclk: nil,
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def broaden_and_cross_clk(phase: "POSITIVE",len:4,lat:2,wclk: nil,rclk: nil,wreset: "1'b1".to_nq,rreset: "1'b1".to_nq,name: nil)
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new_l = nil
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ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
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if wclk.nil? || rclk.nil?
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raise TdlError.new("\n #{self.to_s} BROADEN_AND_CROSS_CLK <clock = nil> \n")
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end
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new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{belong_to_module._auto_name_incr_index_()}",dsize:1)
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large_name_len(phase,len,wclk,wreset,rclk,rreset)
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body =
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"
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broaden_and_cross_clk #(
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/* output */ .q (#{align_signal(new_l,q_mark=false)})
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);
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"
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belong_to_module.Logic_draw << page(tag:"BROADEN_AND_CROSS_CLK",body:body)
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end
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return new_l
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end
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require_relative '../../tdl.rb'
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TdlBuild.test_logic_latency(__dir__) do
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input - 'data'
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input.clock(100) - 'clock'
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input.reset('low') - 'rst_n'
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output.logic - 'od'
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Assign do
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od <= data.broaden_and_cross_clk(wclk: clock,rclk: clock)
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end
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end
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-09-30 21:20:42 +0800
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module test_logic_latency (
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input data,
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input clock,
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input rst_n,
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output logic od
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic broaden_and_cross_clk_R0000;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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//==========================================================================
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//-------- expression ------------------------------------------------------
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//----<<<< BROADEN_AND_CROSS_CLK >>>>---------------------------------------
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broaden_and_cross_clk #(
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.PHASE ("POSITIVE"), //POSITIVE NEGATIVE
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.LEN (4 ),
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.LAT (2 )
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)broaden_and_cross_clk_R0000_inst_R0001(
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/* input */ .rclk (clock ),
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/* input */ .rd_rst_n (1'b1 ),
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/* input */ .wclk (clock ),
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/* input */ .wr_rst_n (1'b1 ),
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/* input */ .d (data ),
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/* output */ .q (broaden_and_cross_clk_R0000)
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);
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//====>>>> BROADEN_AND_CROSS_CLK <<<<=======================================
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assign od = broaden_and_cross_clk_R0000;
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endmodule
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## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
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## ==== [add_signal] ===== ##
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## -------------- sub_md0_logic -------------------------
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set _wave_session_group_sub_md0_logic sub_md0_logic
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# set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
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set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
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-
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.cnt} }
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## ============== sub_md0_logic =========================
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## -------------- sub_md0_interface -------------------------
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set _wave_session_group_sub_md0_interface sub_md0_interface
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# set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
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set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.axis_in} }
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## ============== sub_md0_interface =========================
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## -------------- sub_md0_default -------------------------
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set _wave_session_group_sub_md0_default sub_md0_default
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# set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
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set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" { }
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## ============== sub_md0_default =========================
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## -------------- sub_md0_default.inter_tf -------------------------
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## set _wave_session_group_sub_md0_default_inter_tf Group1
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## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
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set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
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append _wave_session_group_sub_md0_default_inter_tf inter_tf
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set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
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# set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.inter_tf} }
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## ============== sub_md0_default.inter_tf =========================
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## -------------- sub_md1_default -------------------------
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set _wave_session_group_sub_md1_default sub_md1_default
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# set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
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set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
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}
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set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.cnt} {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.axis_out} {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.enable} }
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## ============== sub_md1_default =========================
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## -------------- sub_md1_inner -------------------------
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set _wave_session_group_sub_md1_inner sub_md1_inner
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# set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
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set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
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}
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set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" { }
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## ============== sub_md1_inner =========================
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## -------------- sub_md1_inner.inter_tf -------------------------
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## set _wave_session_group_sub_md1_inner_inter_tf Group1
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## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
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set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
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append _wave_session_group_sub_md1_inner_inter_tf inter_tf
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set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
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# set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.inter_tf} }
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## ============== sub_md1_inner.inter_tf =========================
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## -------------- exp_test_unit_sim_default -------------------------
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set _wave_session_group_exp_test_unit_sim_default exp_test_unit_sim_default
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# set _wave_session_group_exp_test_unit_sim_default [gui_sg_generate_new_name -seed exp_test_unit_sim_default]
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if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_sim_default"]} {
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set _wave_session_group_exp_test_unit_sim_default [gui_sg_generate_new_name]
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}
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set Group2_exp_test_unit_sim_default "$_wave_session_group_exp_test_unit_sim_default"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_sim_default" { }
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## ============== exp_test_unit_sim_default =========================
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## -------------- exp_test_unit_sim_default.axis_data_inf -------------------------
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## set _wave_session_group_exp_test_unit_sim_default_axis_data_inf Group1
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## set _wave_session_group_exp_test_unit_sim_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_sim_default ]
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set _wave_session_group_exp_test_unit_sim_default_axis_data_inf $_wave_session_group_exp_test_unit_sim_default|
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append _wave_session_group_exp_test_unit_sim_default_axis_data_inf axis_data_inf
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set exp_test_unit_sim_default|axis_data_inf "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf"
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# set Group2_exp_test_unit_sim_default_axis_data_inf "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf" { {Sim:tb_exp_test_unit_sim.rtl_top.axis_data_inf} }
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## ============== exp_test_unit_sim_default.axis_data_inf =========================
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## 创建波形窗口
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if {![info exists useOldWindow]} {
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## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
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## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
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## === [add_signal_wave] === ##
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## -------------- Group2_sub_md0_interface -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
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## ============== Group2_sub_md0_interface =========================
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## -------------- Group2_sub_md0_default -------------------------
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|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
|
|
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|
-
## ============== Group2_sub_md0_default =========================
|
|
174
|
-
## -------------- sub_md0_default|inter_tf -------------------------
|
|
175
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
|
|
176
|
-
## ============== sub_md0_default|inter_tf =========================
|
|
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|
-
## -------------- Group2_sub_md1_default -------------------------
|
|
178
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
|
|
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|
-
## ============== Group2_sub_md1_default =========================
|
|
180
|
-
## -------------- Group2_sub_md1_inner -------------------------
|
|
181
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
|
|
182
|
-
## ============== Group2_sub_md1_inner =========================
|
|
183
|
-
## -------------- sub_md1_inner|inter_tf -------------------------
|
|
184
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
|
|
185
|
-
## ============== sub_md1_inner|inter_tf =========================
|
|
186
|
-
## -------------- Group2_exp_test_unit_sim_default -------------------------
|
|
187
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_sim_default}]
|
|
188
|
-
## ============== Group2_exp_test_unit_sim_default =========================
|
|
189
|
-
## -------------- exp_test_unit_sim_default|axis_data_inf -------------------------
|
|
190
|
-
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_sim_default|axis_data_inf}]
|
|
191
|
-
## ============== exp_test_unit_sim_default|axis_data_inf =========================
|
|
45
|
+
|
|
46
|
+
|
|
47
|
+
|
|
192
48
|
|
|
193
49
|
gui_seek_criteria -id ${Wave.3} {Any Edge}
|
|
194
50
|
|
|
@@ -205,12 +61,9 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
|
|
|
205
61
|
gui_list_set_filter -id ${Wave.3} -text {*}
|
|
206
62
|
##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
|
|
207
63
|
## === [add_bar] === ##
|
|
208
|
-
|
|
209
|
-
|
|
210
|
-
|
|
211
|
-
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_default} -position in
|
|
212
|
-
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_inner} -position in
|
|
213
|
-
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_exp_test_unit_sim_default} -position in
|
|
64
|
+
|
|
65
|
+
|
|
66
|
+
|
|
214
67
|
|
|
215
68
|
gui_marker_move -id ${Wave.3} {C1} 560248001
|
|
216
69
|
gui_view_scroll -id ${Wave.3} -vertical -set 35
|
|
@@ -1,9 +1,35 @@
|
|
|
1
|
-
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.0.0
|
|
8
|
+
created: 2021-09-30 21:21:22 +0800
|
|
9
|
+
madified:
|
|
10
|
+
***********************************************/
|
|
2
11
|
`timescale 1ns/1ps
|
|
3
|
-
|
|
4
|
-
|
|
5
|
-
|
|
6
|
-
|
|
7
|
-
|
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8
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-
|
|
12
|
+
|
|
13
|
+
module exp_test_unit (
|
|
14
|
+
input clock,
|
|
15
|
+
input rst_n
|
|
16
|
+
);
|
|
17
|
+
|
|
18
|
+
//==========================================================================
|
|
19
|
+
//-------- define ----------------------------------------------------------
|
|
20
|
+
logic enable;
|
|
21
|
+
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
22
|
+
//==========================================================================
|
|
23
|
+
//-------- instance --------------------------------------------------------
|
|
24
|
+
sub_md1 sub_md1_inst(
|
|
25
|
+
/* axi_stream_inf.master */.axis_out (axis_data_inf ),
|
|
26
|
+
/* output */.enable (enable )
|
|
27
|
+
);
|
|
28
|
+
sub_md0 sub_md0_inst(
|
|
29
|
+
/* axi_stream_inf.slaver */.axis_in (axis_data_inf ),
|
|
30
|
+
/* input */.enable (enable )
|
|
31
|
+
);
|
|
32
|
+
//==========================================================================
|
|
33
|
+
//-------- expression ------------------------------------------------------
|
|
34
|
+
|
|
9
35
|
endmodule
|
|
@@ -1,35 +1,9 @@
|
|
|
1
|
-
/**********************************************
|
|
2
|
-
_______________________________________
|
|
3
|
-
___________ Cook Darwin __________
|
|
4
|
-
_______________________________________
|
|
5
|
-
descript:
|
|
6
|
-
author : Cook.Darwin
|
|
7
|
-
Version: VERA.0.0
|
|
8
|
-
created: 2021-09-24 23:32:18 +0800
|
|
9
|
-
madified:
|
|
10
|
-
***********************************************/
|
|
11
|
-
`timescale 1ns/1ps
|
|
12
|
-
|
|
13
|
-
module exp_test_unit_sim (
|
|
14
|
-
input clock,
|
|
15
|
-
input rst_n
|
|
16
|
-
);
|
|
17
|
-
|
|
18
|
-
//==========================================================================
|
|
19
|
-
//-------- define ----------------------------------------------------------
|
|
20
|
-
logic enable;
|
|
21
|
-
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
22
|
-
//==========================================================================
|
|
23
|
-
//-------- instance --------------------------------------------------------
|
|
24
|
-
sub_md1 sub_md1_inst(
|
|
25
|
-
/* axi_stream_inf.master */.axis_out (axis_data_inf ),
|
|
26
|
-
/* output */.enable (enable )
|
|
27
|
-
);
|
|
28
|
-
sub_md0 sub_md0_inst(
|
|
29
|
-
/* axi_stream_inf.slaver */.axis_in (axis_data_inf ),
|
|
30
|
-
/* input */.enable (enable )
|
|
31
|
-
);
|
|
32
|
-
//==========================================================================
|
|
33
|
-
//-------- expression ------------------------------------------------------
|
|
34
1
|
|
|
2
|
+
`timescale 1ns/1ps
|
|
3
|
+
module exp_test_unit_sim();
|
|
4
|
+
initial begin
|
|
5
|
+
#(1us);
|
|
6
|
+
$warning("Check TopModule.sim,please!!!");
|
|
7
|
+
$stop;
|
|
8
|
+
end
|
|
35
9
|
endmodule
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-09-
|
|
8
|
+
created: 2021-09-30 21:21:22 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -27,9 +27,9 @@ module tu0 (
|
|
|
27
27
|
initial begin
|
|
28
28
|
to_down_pass = 1'b0;
|
|
29
29
|
wait(from_up_pass);
|
|
30
|
-
$root.
|
|
30
|
+
$root.tb_exp_test_unit.test_unit_region = "tu0";
|
|
31
31
|
$display("--------------- Current test_unit <%0s> --------------------", "tu0");
|
|
32
|
-
$root.
|
|
32
|
+
$root.tb_exp_test_unit.rtl_top.sub_md0_inst.cnt = ($root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable+1);
|
|
33
33
|
to_down_pass = 1'b1;
|
|
34
34
|
end
|
|
35
35
|
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-
|
|
8
|
+
created: 2021-09-30 21:21:22 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -19,7 +19,7 @@ module test_module_var #(
|
|
|
19
19
|
|
|
20
20
|
//==========================================================================
|
|
21
21
|
//-------- define ----------------------------------------------------------
|
|
22
|
-
localparam ASIZE = 20
|
|
22
|
+
localparam ASIZE = 20;
|
|
23
23
|
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
24
24
|
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
25
25
|
axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295),.FreqM(100)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
|
|
@@ -13,8 +13,6 @@ gui_set_time_units 1ps
|
|
|
13
13
|
## ==== [add_signal] ===== ##
|
|
14
14
|
|
|
15
15
|
|
|
16
|
-
|
|
17
|
-
|
|
18
16
|
## 创建波形窗口
|
|
19
17
|
if {![info exists useOldWindow]} {
|
|
20
18
|
set useOldWindow true
|
|
@@ -44,8 +42,6 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
|
|
|
44
42
|
## === [add_signal_wave] === ##
|
|
45
43
|
|
|
46
44
|
|
|
47
|
-
|
|
48
|
-
|
|
49
45
|
gui_seek_criteria -id ${Wave.3} {Any Edge}
|
|
50
46
|
|
|
51
47
|
|
|
@@ -63,8 +59,6 @@ gui_list_set_filter -id ${Wave.3} -text {*}
|
|
|
63
59
|
## === [add_bar] === ##
|
|
64
60
|
|
|
65
61
|
|
|
66
|
-
|
|
67
|
-
|
|
68
62
|
gui_marker_move -id ${Wave.3} {C1} 560248001
|
|
69
63
|
gui_view_scroll -id ${Wave.3} -vertical -set 35
|
|
70
64
|
gui_show_grid -id ${Wave.3} -enable false
|
|
@@ -1,40 +1,9 @@
|
|
|
1
|
-
/**********************************************
|
|
2
|
-
_______________________________________
|
|
3
|
-
___________ Cook Darwin __________
|
|
4
|
-
_______________________________________
|
|
5
|
-
descript:
|
|
6
|
-
author : Cook.Darwin
|
|
7
|
-
Version: VERA.0.0
|
|
8
|
-
created: 2021-09-24 23:32:18 +0800
|
|
9
|
-
madified:
|
|
10
|
-
***********************************************/
|
|
11
|
-
`timescale 1ns/1ps
|
|
12
|
-
|
|
13
|
-
module test_tttop (
|
|
14
|
-
input global_sys_clk
|
|
15
|
-
);
|
|
16
|
-
|
|
17
|
-
//==========================================================================
|
|
18
|
-
//-------- define ----------------------------------------------------------
|
|
19
|
-
logic clock_100M;
|
|
20
|
-
logic rstn_100M;
|
|
21
|
-
axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
|
|
22
|
-
//==========================================================================
|
|
23
|
-
//-------- instance --------------------------------------------------------
|
|
24
|
-
simple_clock simple_clock_inst(
|
|
25
|
-
/* input clock */.sys_clk (global_sys_clk ),
|
|
26
|
-
/* output clock */.clock (clock_100M ),
|
|
27
|
-
/* output reset */.rst_n (rstn_100M )
|
|
28
|
-
);
|
|
29
|
-
a_test_md a_test_md_inst(
|
|
30
|
-
/* input clock */.clock (clock_100M ),
|
|
31
|
-
/* input reset */.rst (~rstn_100M ),
|
|
32
|
-
/* axi_stream_inf.master */.origin_inf (x_origin_inf )
|
|
33
|
-
);
|
|
34
|
-
//==========================================================================
|
|
35
|
-
//-------- expression ------------------------------------------------------
|
|
36
|
-
assign x_origin_inf.axis_tvalid = 1'b0;
|
|
37
|
-
assign x_origin_inf.axis_tdata = '0;
|
|
38
|
-
assign x_origin_inf.axis_tlast = 1'b0;
|
|
39
1
|
|
|
2
|
+
`timescale 1ns/1ps
|
|
3
|
+
module test_tttop();
|
|
4
|
+
initial begin
|
|
5
|
+
#(1us);
|
|
6
|
+
$warning("Check TopModule.sim,please!!!");
|
|
7
|
+
$stop;
|
|
8
|
+
end
|
|
40
9
|
endmodule
|
|
@@ -1,9 +1,40 @@
|
|
|
1
|
-
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.0.0
|
|
8
|
+
created: 2021-09-30 21:21:22 +0800
|
|
9
|
+
madified:
|
|
10
|
+
***********************************************/
|
|
2
11
|
`timescale 1ns/1ps
|
|
3
|
-
|
|
4
|
-
|
|
5
|
-
|
|
6
|
-
|
|
7
|
-
|
|
8
|
-
|
|
12
|
+
|
|
13
|
+
module test_tttop_sim (
|
|
14
|
+
input global_sys_clk
|
|
15
|
+
);
|
|
16
|
+
|
|
17
|
+
//==========================================================================
|
|
18
|
+
//-------- define ----------------------------------------------------------
|
|
19
|
+
logic clock_100M;
|
|
20
|
+
logic rstn_100M;
|
|
21
|
+
axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
|
|
22
|
+
//==========================================================================
|
|
23
|
+
//-------- instance --------------------------------------------------------
|
|
24
|
+
simple_clock simple_clock_inst(
|
|
25
|
+
/* input clock */.sys_clk (global_sys_clk ),
|
|
26
|
+
/* output clock */.clock (clock_100M ),
|
|
27
|
+
/* output reset */.rst_n (rstn_100M )
|
|
28
|
+
);
|
|
29
|
+
a_test_md a_test_md_inst(
|
|
30
|
+
/* input clock */.clock (clock_100M ),
|
|
31
|
+
/* input reset */.rst (~rstn_100M ),
|
|
32
|
+
/* axi_stream_inf.master */.origin_inf (x_origin_inf )
|
|
33
|
+
);
|
|
34
|
+
//==========================================================================
|
|
35
|
+
//-------- expression ------------------------------------------------------
|
|
36
|
+
assign x_origin_inf.axis_tvalid = 1'b0;
|
|
37
|
+
assign x_origin_inf.axis_tdata = '0;
|
|
38
|
+
assign x_origin_inf.axis_tlast = 1'b0;
|
|
39
|
+
|
|
9
40
|
endmodule
|
metadata
CHANGED
|
@@ -1,14 +1,14 @@
|
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
|
2
2
|
name: axi_tdl
|
|
3
3
|
version: !ruby/object:Gem::Version
|
|
4
|
-
version: 0.1.
|
|
4
|
+
version: 0.1.20
|
|
5
5
|
platform: ruby
|
|
6
6
|
authors:
|
|
7
7
|
- Cook.Darwin
|
|
8
8
|
autorequire:
|
|
9
9
|
bindir: exe
|
|
10
10
|
cert_chain: []
|
|
11
|
-
date: 2021-09-
|
|
11
|
+
date: 2021-09-30 00:00:00.000000000 Z
|
|
12
12
|
dependencies:
|
|
13
13
|
- !ruby/object:Gem::Dependency
|
|
14
14
|
name: rake
|
|
@@ -1155,6 +1155,8 @@ files:
|
|
|
1155
1155
|
- lib/tdl/elements/videoinf.rb
|
|
1156
1156
|
- lib/tdl/examples/10_random/exp_random.rb
|
|
1157
1157
|
- lib/tdl/examples/10_random/exp_random.sv
|
|
1158
|
+
- lib/tdl/examples/11_logic_latency/test_logic_latency.rb
|
|
1159
|
+
- lib/tdl/examples/11_logic_latency/test_logic_latency.sv
|
|
1158
1160
|
- lib/tdl/examples/11_test_unit/dve.tcl
|
|
1159
1161
|
- lib/tdl/examples/11_test_unit/exp_test_unit.rb
|
|
1160
1162
|
- lib/tdl/examples/11_test_unit/exp_test_unit.sv
|