axi_tdl 0.0.6 → 0.0.11
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.gitignore +1 -0
- data/.travis.yml +7 -0
- data/Gemfile +4 -0
- data/Gemfile.lock +2 -2
- data/README.EN.md +317 -0
- data/README.md +24 -18
- data/Rakefile +0 -4
- data/axi_tdl.gemspec +2 -2
- data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +4 -4
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +5 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +7 -7
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI_stream/axi_stream_latency.sv +56 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +20 -20
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +99 -43
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +36 -39
- data/lib/axi/AXI_stream/axis_insert_copy.sv +1 -1
- data/lib/axi/AXI_stream/axis_length_split_with_user.sv +87 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +41 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +1 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +37 -16
- data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +3 -2
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv +70 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb +49 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +84 -0
- data/lib/axi_tdl.rb +12 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +1 -0
- data/lib/tdl/SDL/path_lib.rb +1 -1
- data/lib/tdl/SDL/vcs_axi4_comptable.rb +9 -0
- data/lib/tdl/SDL/vcs_axis_comptable.rb +17 -0
- data/lib/tdl/SDL/vcs_data_c_comptable.rb +9 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +15 -3
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +2 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +2 -1
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +3 -1
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +2 -2
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +0 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +0 -1
- data/lib/tdl/exlib/test_point.rb +8 -2
- data/lib/tdl/sdlmodule/sdlmodule.rb +64 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +13 -0
- data/lib/tdl/sdlmodule/top_module.rb +1 -0
- data/lib/tdl/tdl.rb +14 -2
- data/lib/tdl/tdlerror/tdlerror.rb +1 -0
- metadata +118 -5
@@ -58,7 +58,7 @@ always_ff@(posedge clock,negedge rst_n) begin
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end
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end
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else begin
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-
insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_seed-1'b1)&& in_inf_valve.axis_tvalid && in_inf_valve.axis_tready && ( in_inf_valve.axis_tcnt<( insert_seed+insert_len-
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insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_seed-1'b1)&& in_inf_valve.axis_tvalid && in_inf_valve.axis_tready && ( in_inf_valve.axis_tcnt<( ( insert_seed+insert_len)-1'b1))&& ~in_inf.axis_tlast);
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end
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end
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end
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@@ -0,0 +1,87 @@
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/**********************************************
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______________ ______________
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______________ X ______________
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______________ ______________
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descript:
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author : Cook.Darwin
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Version: VERA.0.X 2018/1/25
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use axis_user to detect last
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creaded: 2017/5/19
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madified:
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***********************************************/
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`timescale 1ns/1ps
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(* axi_stream = "true" *)
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module axis_length_split_with_user (
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input [31:0] length, ////[0] mean 0 len
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(* up_stream = "true" *)
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axi_stream_inf.slaver axis_in,
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(* down_stream = "true" *)
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axi_stream_inf.master axis_out
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);
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wire clock,rst_n,clken;
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assign clock = axis_in.aclk;
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assign rst_n = axis_in.aresetn;
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assign clken = axis_in.aclken;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE)) axis_pre (.aclk(clock),.aresetn(rst_n),.aclken(clken));
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logic [31:0] cnt;
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always@(posedge clock,negedge rst_n)
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if(~rst_n) cnt <= '0;
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else begin
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if(axis_in.axis_tvalid && axis_in.axis_tready && axis_in.axis_tlast)
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cnt <= '0;
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else if(axis_in.axis_tvalid && axis_in.axis_tready && (cnt >= (length-1)))
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cnt <= '0;
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else if(axis_in.axis_tvalid && axis_in.axis_tready)
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cnt <= cnt + 1'b1;
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else cnt <= cnt;
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end
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logic new_last;
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always@(posedge clock,negedge rst_n)
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if(~rst_n) new_last <= 1'b0;
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else begin
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if(axis_in.axis_tvalid && axis_in.axis_tready && (new_last||axis_in.axis_tlast))
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new_last <= 1'b0;
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else if(axis_in.axis_tvalid && axis_in.axis_tready && cnt==(length-2))
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new_last <= 1'b1;
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else new_last <= new_last;
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end
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// logic mark_tail;
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//
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// always@(posedge clock,negedge rst_n)
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// if(~rst_n) mark_tail <= 1'b0;
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// else begin
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// if(axis_in.axis_tvalid && axis_in.axis_tready && axis_in.axis_tlast)
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// mark_tail <= 1'b0;
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// else if(axis_in.axis_tvalid && axis_in.axis_tready && axis_in.axis_tcnt==(length-1))
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// mark_tail <= 1'b1;
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// else mark_tail <= mark_tail;
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// end
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assign axis_pre.axis_tvalid = axis_in.axis_tvalid;
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assign axis_pre.axis_tdata = axis_in.axis_tdata;
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assign axis_pre.axis_tlast = new_last || axis_in.axis_tlast;
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assign axis_pre.axis_tkeep = axis_in.axis_tkeep;
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// assign axis_pre.axis_tuser = axis_in.axis_tuser;
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assign axis_pre.axis_tuser = axis_in.axis_tlast;
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assign axis_in.axis_tready = axis_pre.axis_tready;
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axis_connect_pipe axis_connect_pipe_inst(
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/* axi_stream_inf.slaver */ .axis_in (axis_pre ),
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/* axi_stream_inf.master */ .axis_out (axis_out )
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);
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int out_cnt;
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assign out_cnt = axis_out.axis_tcnt;
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endmodule
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require_sdl 'data_c_pipe_sync_seam.rb'
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TdlBuild.axis_pipe_sync_seam(__dir__) do
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parameter.LAT 4
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parameter.DSIZE 32
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## as like: hdl```
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## assign in_datas[0] = in_inf.axis_tdata + 1;
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## assign in_datas[1] = out_datas[0]+1;```
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input[param.LAT,param.DSIZE] - 'in_datas'
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output[param.LAT,param.DSIZE] - 'out_datas'
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port.axis.slaver - 'in_inf'
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port.axis.master - 'out_inf'
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data_inf_c(clock: in_inf.aclk, reset: in_inf.aresetn, dsize: "in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE".to_nq) - 'data_in_inf'
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data_in_inf.copy(name: 'data_out_inf')
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data_c_pipe_sync_seam.data_c_pipe_sync_seam_inst do |h|
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h.parameter.LAT param.LAT
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h.parameter.DSIZE param.DSIZE
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## as like: hdl```
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## assign in_datas[0] = in_inf.data + 1;
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## assign in_datas[1] = out_datas[0]+1;```
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h.input[h.param.LAT,h.param.DSIZE].in_datas in_datas
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h.output[h.param.LAT,h.param.DSIZE].out_datas out_datas
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h.port.data_inf_c.slaver.in_inf data_in_inf
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h.port.data_inf_c.master.out_inf data_out_inf
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end
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Assign do
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data_in_inf.data <= self.>>(in_inf.axis_tuser, in_inf.axis_tkeep, in_inf.axis_tlast, in_inf.axis_tdata)
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data_in_inf.valid <= in_inf.axis_tvalid
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in_inf.axis_tready <= data_in_inf.ready
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logic_bind_(out_inf.axis_tuser, out_inf.axis_tkeep, out_inf.axis_tlast, out_inf.axis_tdata) <= data_out_inf.data
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out_inf.axis_tvalid <= data_out_inf.valid
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data_out_inf.ready <= out_inf.axis_tready
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end
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end
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: xxxx.xx.xx
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axis_pipe_sync_seam #(
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parameter LAT = 4,
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parameter DSIZE = 32
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)(
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input [ DSIZE-1:0] in_datas [LAT-1:0],
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output [ DSIZE-1:0] out_datas [LAT-1:0],
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axi_stream_inf.slaver in_inf,
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axi_stream_inf.master out_inf
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_in_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
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data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_out_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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data_c_pipe_sync_seam #(
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.LAT (LAT ),
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.DSIZE (DSIZE )
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)data_c_pipe_sync_seam_inst(
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/* input */.in_datas (in_datas ),
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/* output */.out_datas (out_datas ),
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/* data_inf_c.slaver */.in_inf (data_in_inf ),
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/* data_inf_c.master */.out_inf (data_out_inf )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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assign data_in_inf.data = {>>{in_inf.axis_tuser,in_inf.axis_tkeep,in_inf.axis_tlast,in_inf.axis_tdata}};
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assign data_in_inf.valid = in_inf.axis_tvalid;
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assign in_inf.axis_tready = data_in_inf.ready;
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assign {out_inf.axis_tuser,out_inf.axis_tkeep,out_inf.axis_tlast,out_inf.axis_tdata} = data_out_inf.data;
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assign out_inf.axis_tvalid = data_out_inf.valid;
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assign data_out_inf.ready = out_inf.axis_tready;
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endmodule
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(* axi_stream = "true" *)
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module axi_stream_packet_long_fifo #(
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parameter DEPTH = 2, //2-4
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parameter BYTE_DEPTH = 8096
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parameter BYTE_DEPTH = 8096,
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parameter USE_KEEP = "OFF"
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)(
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(* up_stream = "true" *)
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axi_stream_inf.slaver axis_in,
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logic data_fifo_empty;
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logic [axis_in.DSIZE-1:0] stream_fifo_data;
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)
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/* input */ .
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/* input */ .
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/* input
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/* input */ .
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/* input
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/*
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/*
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/* output
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)
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generate
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if(USE_KEEP=="OFF" || USE_KEEP=="FALSE")begin
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fifo_36kb_long #(
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.DSIZE (axis_out.DSIZE ),
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.DEPTH (BYTE_DEPTH )
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)fifo_36kb_long_inst(
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/* input */ .wr_clk (axis_in.aclk ),
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/* input */ .wr_rst (~axis_in.aresetn ),
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/* input */ .rd_clk (axis_out.aclk ),
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/* input */ .rd_rst (~axis_out.aresetn ),
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/* input [DSIZE-1:0] */ .din (axis_in.axis_tdata ),
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/* input */ .wr_en ((axis_in.axis_tvalid && !data_fifo_full && axis_in.axis_tready) ),
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/* input */ .rd_en ((axis_out.axis_tvalid && !data_fifo_empty && axis_out.axis_tready) ),
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/* output [DSIZE-1:0] */ .dout (axis_out.axis_tdata ),
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/* output */ .full (data_fifo_full ),
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/* output */ .empty (data_fifo_empty )
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);
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end else begin
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fifo_36kb_long #(
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.DSIZE (axis_out.DSIZE+axis_out.KSIZE ),
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.DEPTH (BYTE_DEPTH )
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)fifo_36kb_long_inst(
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/* input */ .wr_clk (axis_in.aclk ),
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/* input */ .wr_rst (~axis_in.aresetn ),
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/* input */ .rd_clk (axis_out.aclk ),
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/* input */ .rd_rst (~axis_out.aresetn ),
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/* input [DSIZE-1:0] */ .din ({axis_in.axis_tkeep, axis_in.axis_tdata} ),
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/* input */ .wr_en ((axis_in.axis_tvalid && !data_fifo_full && axis_in.axis_tready) ),
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/* input */ .rd_en ((axis_out.axis_tvalid && !data_fifo_empty && axis_out.axis_tready) ),
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/* output [DSIZE-1:0] */ .dout ({axis_out.axis_tkeep, axis_out.axis_tdata} ),
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/* output */ .full (data_fifo_full ),
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/* output */ .empty (data_fifo_empty )
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);
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end
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endgenerate
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// assign axis_out.axis_tdata = axis_out.axis_tvalid? stream_fifo_data : '0;
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//---<< NATIVE FIFO IP >>------------------------------
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parameter DSIZE = 8,
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parameter FIELD_LEN = 16*8, //MAX 16*8
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parameter FIELD_NAME = "Big Filed",
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parameter TRY_PARSE = "OFF"
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parameter TRY_PARSE = "OFF",
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parameter TMP_START = 0
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)(
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input enable,
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output[
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output[TMP_START:DSIZE*FIELD_LEN-1] value,
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output logic out_valid,
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axi_stream_inf.slaver cm_tb_s,
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axi_stream_inf.master cm_tb_m,
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@@ -15,7 +15,7 @@ module data_c_pipe_force_vld_bind_data #(
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parameter HEAD_MODE = "ON", // data in master.head
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parameter SYNC = "master"
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)(
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input [DSIZE-1:0] data, //sync master
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input [DSIZE-1:0] data, //sync master, need bypass
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data_inf_c.slaver slaver,
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data_inf_c.master master
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);
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript: covert A to B
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author : Cook.Darwin
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Version: VERA.0.0
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creaded:
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madified:
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***********************************************/
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`timescale 1ns/1ps
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(* data_inf_c = "true" *)
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module data_c_pipe_sync #(
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parameter DSIZE = 32
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)(
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input [DSIZE-1:0] in_data, // as like: hdl``` assign in_data = in_inf.data + 1;
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output logic [DSIZE-1:0] out_data,
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data_inf_c.slaver in_inf,
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data_inf_c.master out_inf
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);
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initial begin
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assert(in_inf.DSIZE == out_inf.DSIZE)
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else begin
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$error("in_inf DSIZE<%0d> != out_inf DSIZE<%0d>",in_inf.DSIZE,out_inf.DSIZE);
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$stop;
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end
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end
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logic clock;
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logic rst_n;
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assign clock = in_inf.clock;
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assign rst_n = in_inf.rst_n;
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always@(posedge clock,negedge rst_n)
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if(~rst_n) out_inf.valid <= 1'b0;
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else begin
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if(in_inf.valid && in_inf.ready)
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out_inf.valid <= 1'b1;
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else if(out_inf.valid && out_inf.ready)
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out_inf.valid <= 1'b0;
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else out_inf.valid <= out_inf.valid;
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end
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assign in_inf.ready = !out_inf.valid || out_inf.ready;
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// logic[in_inf.DSIZE-1:0] master_origin_data;
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always@(posedge clock,negedge rst_n)
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if(~rst_n)begin
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out_inf.data <= '0;
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out_data <= '0;
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end else begin
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if(in_inf.valid && in_inf.ready)begin
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out_data <= in_data;
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out_inf.data <= in_inf.data;
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end else if(out_inf.valid && out_inf.ready)begin
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out_inf.data <= '0;
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out_data <= '0;
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end else begin
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out_inf.data <= out_inf.data;
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out_data <= out_data;
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end
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end
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endmodule
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require_hdl 'data_c_pipe_sync.sv'
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TdlBuild.data_c_pipe_sync_seam(__dir__) do
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parameter.LAT 4
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parameter.DSIZE 32
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## as like: hdl```
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## assign in_datas[0] = in_inf.data + 1;
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## assign in_datas[1] = out_datas[0]+1;```
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input[param.LAT,param.DSIZE] - 'in_datas'
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output[param.LAT,param.DSIZE] - 'out_datas'
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port.data_inf_c.slaver - 'in_inf'
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port.data_inf_c.master - 'out_inf'
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same_clock_domain(in_inf, out_inf)
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in_inf.copy(name: 'in_inf_array', dimension: [param.LAT])
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out_inf.copy(name: 'out_inf_array', dimension: [param.LAT])
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generate(param.LAT) do |kk|
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data_c_pipe_sync.data_c_pipe_sync_inst do |h|
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h.parameter.DSIZE param.DSIZE
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h.input['DSIZE'].in_data in_datas[kk] ##// as like: hdl``` assign in_data = in_inf.data + 1;
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h.output['DSIZE'].out_data out_datas[kk]
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h.port.data_inf_c.slaver.in_inf in_inf_array[kk]
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h.port.data_inf_c.master.out_inf out_inf_array[kk]
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end
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IF kk != 0 do
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Assign do
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in_inf_array[kk].valid <= out_inf_array[kk-1].valid
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in_inf_array[kk].data <= out_inf_array[kk-1].data
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out_inf_array[kk-1].ready <= in_inf_array[kk].ready
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end
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end
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end
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Assign do
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in_inf_array[0].valid <= in_inf.valid
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in_inf_array[0].data <= in_inf.data
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in_inf.ready <= in_inf_array[0].ready
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end
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Assign do
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out_inf.data <= out_inf_array[param.LAT-1].data
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out_inf.valid <= out_inf_array[param.LAT-1].valid
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out_inf_array[param.LAT-1].ready <= out_inf.ready
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end
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end
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@@ -0,0 +1,84 @@
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: xxxx.xx.xx
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module data_c_pipe_sync_seam #(
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parameter LAT = 4,
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parameter DSIZE = 32
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)(
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input [ DSIZE-1:0] in_datas [LAT-1:0],
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output [ DSIZE-1:0] out_datas [LAT-1:0],
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data_inf_c.slaver in_inf,
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data_inf_c.master out_inf
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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data_inf_c #(.DSIZE(in_inf.DSIZE)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
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data_inf_c #(.DSIZE(out_inf.DSIZE)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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//==========================================================================
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//-------- expression ------------------------------------------------------
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generate
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for(genvar KK0=0;KK0 < LAT;KK0++)begin
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data_c_pipe_sync #(
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.DSIZE (DSIZE )
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)data_c_pipe_sync_inst(
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/* input */.in_data (in_datas[ KK0] ),
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/* output */.out_data (out_datas[ KK0] ),
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/* data_inf_c.slaver */.in_inf (in_inf_array[ KK0] ),
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/* data_inf_c.master */.out_inf (out_inf_array[ KK0] )
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);
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if( KK0!=0)begin
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assign in_inf_array[ KK0].valid = out_inf_array[ KK0-1].valid;
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assign in_inf_array[ KK0].data = out_inf_array[ KK0-1].data;
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assign out_inf_array[ KK0-1].ready = in_inf_array[ KK0].ready;
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end end
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endgenerate
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//-------- CLOCKs Total 2 ----------------------
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//--->> CheckClock <<----------------
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logic cc_done_10,cc_same_10;
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integer cc_afreq_10,cc_bfreq_10;
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ClockSameDomain CheckPClock_inst_10(
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/* input */ .aclk (in_inf.clock ),
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/* input */ .bclk (out_inf.clock ),
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/* output logic */ .done (cc_done_10),
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/* output logic */ .same (cc_same_10),
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/* output integer */ .aFreqK (cc_afreq_10),
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/* output integer */ .bFreqK (cc_bfreq_10)
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);
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initial begin
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wait(cc_done_10);
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assert(cc_same_10)
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else begin
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$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
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repeat(10)begin
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@(posedge in_inf.clock);
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end
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$stop;
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end
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end
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//---<< CheckClock >>----------------
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//======== CLOCKs Total 2 ======================
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assign in_inf_array[0].valid = in_inf.valid;
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assign in_inf_array[0].data = in_inf.data;
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assign in_inf.ready = in_inf_array[0].ready;
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assign out_inf.data = out_inf_array[ LAT-1].data;
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assign out_inf.valid = out_inf_array[ LAT-1].valid;
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assign out_inf_array[ LAT-1].ready = out_inf.ready;
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endmodule
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