axi_tdl 0.0.6 → 0.0.11

data/lib/axi/AXI_stream/axis_insert_copy.sv

@@ -58,7 +58,7 @@ always_ff@(posedge clock,negedge rst_n) begin
             end
         end
         else begin
-             insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_seed-1'b1)&& in_inf_valve.axis_tvalid && in_inf_valve.axis_tready && ( in_inf_valve.axis_tcnt<( insert_seed+insert_len- 1'b1))&& ~in_inf.axis_tlast);
+             insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_seed-1'b1)&& in_inf_valve.axis_tvalid && in_inf_valve.axis_tready && ( in_inf_valve.axis_tcnt<( ( insert_seed+insert_len)-1'b1))&& ~in_inf.axis_tlast);
         end
     end
 end

data/lib/axi/AXI_stream/axis_length_split_with_user.sv

@@ -0,0 +1,87 @@
+/**********************************************
+______________   ______________
+______________ X ______________
+______________  ______________
+
+descript:
+author : Cook.Darwin
+Version: VERA.0.X 2018/1/25 
+    use axis_user to detect last
+creaded: 2017/5/19 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+(* axi_stream = "true" *)
+module axis_length_split_with_user (
+    input [31:0]           length,      ////[0] mean 0 len
+    (* up_stream = "true" *)
+    axi_stream_inf.slaver  axis_in,
+    (* down_stream = "true" *)
+    axi_stream_inf.master  axis_out
+);
+
+wire    clock,rst_n,clken;
+
+assign  clock   = axis_in.aclk;
+assign  rst_n   = axis_in.aresetn;
+assign  clken   = axis_in.aclken;
+
+axi_stream_inf #(.DSIZE(axis_in.DSIZE)) axis_pre (.aclk(clock),.aresetn(rst_n),.aclken(clken));
+
+
+logic [31:0]        cnt;
+
+always@(posedge clock,negedge rst_n)
+    if(~rst_n)  cnt     <= '0;
+    else begin
+        if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tlast)
+                cnt     <= '0;
+        else if(axis_in.axis_tvalid  && axis_in.axis_tready && (cnt >= (length-1)))
+                cnt     <= '0;
+        else if(axis_in.axis_tvalid  && axis_in.axis_tready)
+                cnt     <= cnt + 1'b1;
+        else    cnt     <= cnt;
+    end
+
+logic   new_last;
+
+always@(posedge clock,negedge rst_n)
+    if(~rst_n)  new_last    <= 1'b0;
+    else begin
+        if(axis_in.axis_tvalid  && axis_in.axis_tready && (new_last||axis_in.axis_tlast))
+                new_last    <= 1'b0;
+        else if(axis_in.axis_tvalid  && axis_in.axis_tready && cnt==(length-2))
+                new_last    <= 1'b1;
+        else    new_last    <= new_last;
+    end
+
+// logic   mark_tail;
+//
+// always@(posedge clock,negedge rst_n)
+//     if(~rst_n)  mark_tail   <= 1'b0;
+//     else begin
+//         if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tlast)
+//                 mark_tail   <= 1'b0;
+//         else if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tcnt==(length-1))
+//                 mark_tail   <= 1'b1;
+//         else    mark_tail   <= mark_tail;
+//     end
+
+assign axis_pre.axis_tvalid = axis_in.axis_tvalid;
+assign axis_pre.axis_tdata  = axis_in.axis_tdata;
+assign axis_pre.axis_tlast  = new_last || axis_in.axis_tlast;
+assign axis_pre.axis_tkeep  = axis_in.axis_tkeep;
+// assign axis_pre.axis_tuser  = axis_in.axis_tuser;
+assign axis_pre.axis_tuser  = axis_in.axis_tlast;
+assign axis_in.axis_tready  = axis_pre.axis_tready;
+
+axis_connect_pipe axis_connect_pipe_inst(
+/*  axi_stream_inf.slaver  */  .axis_in     (axis_pre   ),
+/*  axi_stream_inf.master  */  .axis_out    (axis_out   )
+);
+
+int out_cnt;
+
+assign out_cnt = axis_out.axis_tcnt;
+
+endmodule

data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb

@@ -0,0 +1,41 @@
+require_sdl 'data_c_pipe_sync_seam.rb'
+
+TdlBuild.axis_pipe_sync_seam(__dir__) do 
+    parameter.LAT       4
+    parameter.DSIZE     32
+        ## as like: hdl``` 
+    ## assign in_datas[0] = in_inf.axis_tdata + 1;
+    ## assign in_datas[1] = out_datas[0]+1;```
+    input[param.LAT,param.DSIZE]    - 'in_datas'    
+    output[param.LAT,param.DSIZE]   - 'out_datas'
+    port.axis.slaver                - 'in_inf'
+    port.axis.master                - 'out_inf'
+
+    data_inf_c(clock: in_inf.aclk, reset: in_inf.aresetn, dsize: "in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE".to_nq) - 'data_in_inf'
+    data_in_inf.copy(name: 'data_out_inf')
+
+    data_c_pipe_sync_seam.data_c_pipe_sync_seam_inst do |h|
+        h.parameter.LAT       param.LAT
+        h.parameter.DSIZE     param.DSIZE
+        ## as like: hdl``` 
+        ## assign in_datas[0] = in_inf.data + 1;
+        ## assign in_datas[1] = out_datas[0]+1;```
+        h.input[h.param.LAT,h.param.DSIZE].in_datas         in_datas
+        h.output[h.param.LAT,h.param.DSIZE].out_datas       out_datas
+        h.port.data_inf_c.slaver.in_inf                     data_in_inf
+        h.port.data_inf_c.master.out_inf                    data_out_inf
+    end
+
+    Assign do 
+        data_in_inf.data    <= self.>>(in_inf.axis_tuser, in_inf.axis_tkeep, in_inf.axis_tlast, in_inf.axis_tdata)
+        data_in_inf.valid   <= in_inf.axis_tvalid 
+        in_inf.axis_tready  <= data_in_inf.ready 
+
+
+        logic_bind_(out_inf.axis_tuser, out_inf.axis_tkeep, out_inf.axis_tlast, out_inf.axis_tdata) <= data_out_inf.data 
+        out_inf.axis_tvalid     <= data_out_inf.valid 
+        data_out_inf.ready      <= out_inf.axis_tready
+
+    end
+
+end

data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv

@@ -0,0 +1,48 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module axis_pipe_sync_seam #(
+    parameter  LAT   = 4,
+    parameter  DSIZE = 32
+)(
+    input [ DSIZE-1:0]      in_datas  [LAT-1:0],
+    output [ DSIZE-1:0]     out_datas [LAT-1:0],
+    axi_stream_inf.slaver   in_inf,
+    axi_stream_inf.master   out_inf
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+
+data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_in_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
+data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_out_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+data_c_pipe_sync_seam #(
+    .LAT   (LAT   ),
+    .DSIZE (DSIZE )
+)data_c_pipe_sync_seam_inst(
+/* input             */.in_datas  (in_datas     ),
+/* output            */.out_datas (out_datas    ),
+/* data_inf_c.slaver */.in_inf    (data_in_inf  ),
+/* data_inf_c.master */.out_inf   (data_out_inf )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+assign  data_in_inf.data = {>>{in_inf.axis_tuser,in_inf.axis_tkeep,in_inf.axis_tlast,in_inf.axis_tdata}};
+assign  data_in_inf.valid = in_inf.axis_tvalid;
+assign  in_inf.axis_tready = data_in_inf.ready;
+assign  {out_inf.axis_tuser,out_inf.axis_tkeep,out_inf.axis_tlast,out_inf.axis_tdata} = data_out_inf.data;
+assign  out_inf.axis_tvalid = data_out_inf.valid;
+assign  data_out_inf.ready = out_inf.axis_tready;
+
+endmodule

data/lib/axi/AXI_stream/axis_rom_contect_sim.rb

@@ -1,6 +1,7 @@
 
 require_hdl 'axis_uncompress_A1.sv'
 require_sdl 'common_ram_sim_wrapper.rb'
+require_hdl 'axi_stream_planer.sv'
 
 TdlBuild.axis_rom_contect_sim(__dir__) do 
     # vcs_string(256).INIT_FILE   'template.coe'

data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv

@@ -12,7 +12,8 @@ madified:
 (* axi_stream = "true" *)
 module axi_stream_packet_long_fifo #(
     parameter DEPTH         = 2,   //2-4
-    parameter BYTE_DEPTH    = 8096
+    parameter BYTE_DEPTH    = 8096,
+    parameter USE_KEEP      = "OFF"
 )(
     (* up_stream = "true" *)
     axi_stream_inf.slaver      axis_in,
@@ -27,21 +28,41 @@ logic   data_fifo_full;
 logic   data_fifo_empty;
 logic [axis_in.DSIZE-1:0]   stream_fifo_data;
 
-fifo_36kb_long #(
-    .DSIZE      (axis_out.DSIZE ),
-    .DEPTH      (BYTE_DEPTH     )
-)fifo_36kb_long_inst(
-/*  input              */  .wr_clk      (axis_in.aclk       ),
-/*  input              */  .wr_rst      (~axis_in.aresetn   ),
-/*  input              */  .rd_clk      (axis_out.aclk      ),
-/*  input              */  .rd_rst      (~axis_out.aresetn  ),
-/*  input [DSIZE-1:0]  */  .din         (axis_in.axis_tdata ),
-/*  input              */  .wr_en       ((axis_in.axis_tvalid && !data_fifo_full && axis_in.axis_tready)             ),
-/*  input              */  .rd_en       ((axis_out.axis_tvalid && !data_fifo_empty && axis_out.axis_tready)          ),
-/*  output [DSIZE-1:0] */  .dout        (axis_out.axis_tdata    ),
-/*  output             */  .full        (data_fifo_full         ),
-/*  output             */  .empty       (data_fifo_empty        )
-);
+generate 
+    if(USE_KEEP=="OFF" || USE_KEEP=="FALSE")begin 
+        fifo_36kb_long #(
+            .DSIZE      (axis_out.DSIZE ),
+            .DEPTH      (BYTE_DEPTH     )
+        )fifo_36kb_long_inst(
+        /*  input              */  .wr_clk      (axis_in.aclk       ),
+        /*  input              */  .wr_rst      (~axis_in.aresetn   ),
+        /*  input              */  .rd_clk      (axis_out.aclk      ),
+        /*  input              */  .rd_rst      (~axis_out.aresetn  ),
+        /*  input [DSIZE-1:0]  */  .din         (axis_in.axis_tdata ),
+        /*  input              */  .wr_en       ((axis_in.axis_tvalid && !data_fifo_full && axis_in.axis_tready)             ),
+        /*  input              */  .rd_en       ((axis_out.axis_tvalid && !data_fifo_empty && axis_out.axis_tready)          ),
+        /*  output [DSIZE-1:0] */  .dout        (axis_out.axis_tdata    ),
+        /*  output             */  .full        (data_fifo_full         ),
+        /*  output             */  .empty       (data_fifo_empty        )
+        );
+    end else begin 
+        fifo_36kb_long #(
+            .DSIZE      (axis_out.DSIZE+axis_out.KSIZE ),
+            .DEPTH      (BYTE_DEPTH     )
+        )fifo_36kb_long_inst(
+        /*  input              */  .wr_clk      (axis_in.aclk       ),
+        /*  input              */  .wr_rst      (~axis_in.aresetn   ),
+        /*  input              */  .rd_clk      (axis_out.aclk      ),
+        /*  input              */  .rd_rst      (~axis_out.aresetn  ),
+        /*  input [DSIZE-1:0]  */  .din         ({axis_in.axis_tkeep, axis_in.axis_tdata} ),
+        /*  input              */  .wr_en       ((axis_in.axis_tvalid && !data_fifo_full && axis_in.axis_tready)             ),
+        /*  input              */  .rd_en       ((axis_out.axis_tvalid && !data_fifo_empty && axis_out.axis_tready)          ),
+        /*  output [DSIZE-1:0] */  .dout        ({axis_out.axis_tkeep, axis_out.axis_tdata}    ),
+        /*  output             */  .full        (data_fifo_full         ),
+        /*  output             */  .empty       (data_fifo_empty        )
+        );
+    end
+endgenerate
 
 // assign axis_out.axis_tdata = axis_out.axis_tvalid? stream_fifo_data : '0;
 //---<< NATIVE FIFO IP >>------------------------------

data/lib/axi/AXI_stream/parse_big_field_table_A2.sv

@@ -16,10 +16,11 @@ module parse_big_field_table_A2 #(
     parameter   DSIZE         = 8,
     parameter   FIELD_LEN     = 16*8,     //MAX 16*8
     parameter   FIELD_NAME    = "Big Filed",
-    parameter   TRY_PARSE     = "OFF"
+    parameter   TRY_PARSE     = "OFF",
+    parameter   TMP_START     = 0
 )(
     input                                   enable,
-    output[0:DSIZE*FIELD_LEN-1]             value,
+    output[TMP_START:DSIZE*FIELD_LEN-1]     value,
     output logic                            out_valid,
     axi_stream_inf.slaver                   cm_tb_s,
     axi_stream_inf.master                   cm_tb_m,

data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv

@@ -15,7 +15,7 @@ module data_c_pipe_force_vld_bind_data #(
     parameter   HEAD_MODE = "ON",        // data in master.head
     parameter   SYNC = "master"
 )(
-    input [DSIZE-1:0]           data,   //sync master
+    input [DSIZE-1:0]           data,   //sync master, need bypass
     data_inf_c.slaver           slaver,
     data_inf_c.master           master
 );

data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv

@@ -0,0 +1,70 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:   covert A to B
+author : Cook.Darwin
+Version: VERA.0.0
+creaded: 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+(* data_inf_c = "true" *)
+module data_c_pipe_sync #(
+    parameter   DSIZE = 32
+
+)(
+    input [DSIZE-1:0]           in_data,   // as like: hdl``` assign in_data = in_inf.data + 1;
+    output logic [DSIZE-1:0]    out_data,
+    data_inf_c.slaver           in_inf,
+    data_inf_c.master           out_inf
+);
+
+initial begin
+    assert(in_inf.DSIZE == out_inf.DSIZE)
+    else begin
+        $error("in_inf DSIZE<%0d> != out_inf DSIZE<%0d>",in_inf.DSIZE,out_inf.DSIZE);
+        $stop;
+    end
+end
+
+logic   clock;
+logic   rst_n;
+
+assign  clock   = in_inf.clock;
+assign  rst_n   = in_inf.rst_n;
+
+always@(posedge clock,negedge rst_n)
+    if(~rst_n)  out_inf.valid    <= 1'b0;
+    else begin
+        if(in_inf.valid && in_inf.ready)
+                out_inf.valid    <= 1'b1;
+        else if(out_inf.valid && out_inf.ready)
+                out_inf.valid    <= 1'b0;
+        else    out_inf.valid    <= out_inf.valid;
+    end
+
+assign in_inf.ready = !out_inf.valid || out_inf.ready;
+
+// logic[in_inf.DSIZE-1:0] master_origin_data;
+
+
+always@(posedge clock,negedge rst_n)
+    if(~rst_n)begin  
+        out_inf.data     <= '0;
+        out_data        <= '0;
+    end else begin
+        if(in_inf.valid && in_inf.ready)begin 
+            out_data        <= in_data;
+            out_inf.data     <= in_inf.data;
+        end else if(out_inf.valid && out_inf.ready)begin 
+            out_inf.data     <= '0;
+            out_data        <= '0;
+        end else begin 
+            out_inf.data     <= out_inf.data;
+            out_data        <= out_data;
+        end
+    end
+   
+
+endmodule

data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb

@@ -0,0 +1,49 @@
+require_hdl 'data_c_pipe_sync.sv'
+
+TdlBuild.data_c_pipe_sync_seam(__dir__) do 
+    parameter.LAT       4 
+    parameter.DSIZE     32
+    ## as like: hdl``` 
+    ## assign in_datas[0] = in_inf.data + 1;
+    ## assign in_datas[1] = out_datas[0]+1;```
+    input[param.LAT,param.DSIZE]        - 'in_datas'    
+    output[param.LAT,param.DSIZE]       - 'out_datas'
+    port.data_inf_c.slaver              - 'in_inf'
+    port.data_inf_c.master              - 'out_inf'
+
+    same_clock_domain(in_inf, out_inf)
+
+    in_inf.copy(name: 'in_inf_array', dimension: [param.LAT])
+    out_inf.copy(name: 'out_inf_array', dimension: [param.LAT])
+
+    generate(param.LAT) do |kk|
+        data_c_pipe_sync.data_c_pipe_sync_inst do |h|
+            h.parameter.DSIZE           param.DSIZE 
+            h.input['DSIZE'].in_data    in_datas[kk]   ##// as like: hdl``` assign in_data = in_inf.data + 1;
+            h.output['DSIZE'].out_data  out_datas[kk]
+            h.port.data_inf_c.slaver.in_inf     in_inf_array[kk]
+            h.port.data_inf_c.master.out_inf    out_inf_array[kk]
+        end
+
+        IF kk != 0 do 
+            Assign do 
+                in_inf_array[kk].valid     <= out_inf_array[kk-1].valid
+                in_inf_array[kk].data      <= out_inf_array[kk-1].data
+                out_inf_array[kk-1].ready  <= in_inf_array[kk].ready
+            end     
+        end
+    end
+
+    Assign do 
+        in_inf_array[0].valid     <= in_inf.valid
+        in_inf_array[0].data      <= in_inf.data
+        in_inf.ready              <= in_inf_array[0].ready
+    end
+
+    Assign do 
+        out_inf.data  <= out_inf_array[param.LAT-1].data
+        out_inf.valid <= out_inf_array[param.LAT-1].valid
+        out_inf_array[param.LAT-1].ready    <= out_inf.ready
+    end
+
+end

data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv

@@ -0,0 +1,84 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module data_c_pipe_sync_seam #(
+    parameter  LAT   = 4,
+    parameter  DSIZE = 32
+)(
+    input [ DSIZE-1:0]  in_datas  [LAT-1:0],
+    output [ DSIZE-1:0] out_datas [LAT-1:0],
+    data_inf_c.slaver   in_inf,
+    data_inf_c.master   out_inf
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+
+data_inf_c #(.DSIZE(in_inf.DSIZE)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
+data_inf_c #(.DSIZE(out_inf.DSIZE)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+
+//==========================================================================
+//-------- expression ------------------------------------------------------
+generate
+for(genvar KK0=0;KK0 < LAT;KK0++)begin
+    data_c_pipe_sync #(
+        .DSIZE (DSIZE )
+    )data_c_pipe_sync_inst(
+    /* input             */.in_data  (in_datas[ KK0]      ),
+    /* output            */.out_data (out_datas[ KK0]     ),
+    /* data_inf_c.slaver */.in_inf   (in_inf_array[ KK0]  ),
+    /* data_inf_c.master */.out_inf  (out_inf_array[ KK0] )
+    );
+    if( KK0!=0)begin
+        assign  in_inf_array[ KK0].valid = out_inf_array[ KK0-1].valid;
+        assign  in_inf_array[ KK0].data = out_inf_array[ KK0-1].data;
+        assign  out_inf_array[ KK0-1].ready = in_inf_array[ KK0].ready;
+    end end
+endgenerate
+//-------- CLOCKs Total 2 ----------------------
+//--->> CheckClock <<----------------
+logic cc_done_10,cc_same_10;
+integer cc_afreq_10,cc_bfreq_10;
+ClockSameDomain CheckPClock_inst_10(
+/*  input         */      .aclk     (in_inf.clock           ),
+/*  input         */      .bclk     (out_inf.clock          ),
+/*  output logic  */      .done     (cc_done_10),
+/*  output logic  */      .same     (cc_same_10),
+/*  output integer */     .aFreqK   (cc_afreq_10),
+/*  output integer */     .bFreqK   (cc_bfreq_10)
+);
+
+initial begin
+    wait(cc_done_10);
+    assert(cc_same_10)
+    else begin
+        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
+        repeat(10)begin 
+            @(posedge in_inf.clock);
+        end
+        $stop;
+    end
+end
+//---<< CheckClock >>----------------
+
+//======== CLOCKs Total 2 ======================
+assign  in_inf_array[0].valid = in_inf.valid;
+assign  in_inf_array[0].data = in_inf.data;
+assign  in_inf.ready = in_inf_array[0].ready;
+
+assign  out_inf.data = out_inf_array[ LAT-1].data;
+assign  out_inf.valid = out_inf_array[ LAT-1].valid;
+assign  out_inf_array[ LAT-1].ready = out_inf.ready;
+
+endmodule