axi_tdl 0.0.15 → 0.1.5
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +4 -2
- data/Rakefile +7 -0
- data/axi_tdl.gemspec +0 -1
- data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
- data/lib/axi/AXI4/axi4_direct_B1.sv +23 -23
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
- data/lib/axi/AXI4/axi4_dpram_cache.sv +34 -34
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +1 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +24 -24
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +33 -33
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +2 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +72 -72
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +2 -1
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +21 -21
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +7 -1
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +45 -40
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +6 -2
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +30 -30
- data/lib/axi/AXI_stream/axis_insert_copy.rb +18 -4
- data/lib/axi/AXI_stream/axis_insert_copy.sv +29 -16
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +9 -9
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +38 -38
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +30 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
- data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +26 -0
- data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +101 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +2 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +4 -4
- data/lib/axi/common/common_ram_sim_wrapper.sv +10 -10
- data/lib/axi/common/common_ram_wrapper.sv +13 -13
- data/lib/axi/common/test_write_mem.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +27 -27
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +72 -0
- data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +58 -0
- data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +64 -0
- data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +70 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +150 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.rb +69 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.sv +125 -0
- data/lib/axi_tdl.rb +1 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/public_atom_module/CheckPClock.sv +53 -0
- data/lib/public_atom_module/LICENSE.md +674 -0
- data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
- data/lib/public_atom_module/bits_decode.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
- data/lib/public_atom_module/broaden.v +43 -0
- data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
- data/lib/public_atom_module/ceiling.v +39 -0
- data/lib/public_atom_module/ceiling_A1.v +42 -0
- data/lib/public_atom_module/clock_rst.sv +64 -0
- data/lib/public_atom_module/cross_clk_sync.v +37 -0
- data/lib/public_atom_module/edge_generator.v +50 -0
- data/lib/public_atom_module/flooring.v +36 -0
- data/lib/public_atom_module/latch_data.v +30 -0
- data/lib/public_atom_module/latency.v +48 -0
- data/lib/public_atom_module/latency_dynamic.v +83 -0
- data/lib/public_atom_module/latency_long.v +84 -0
- data/lib/public_atom_module/latency_verb.v +52 -0
- data/lib/public_atom_module/once_event.sv +65 -0
- data/lib/public_atom_module/pipe_reg.v +93 -0
- data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
- data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
- data/lib/public_atom_module/sim_system_pkg.sv +4 -0
- data/lib/public_atom_module/synth_system_pkg.sv +4 -0
- data/lib/tdl/Logic/logic_edge.rb +1 -1
- data/lib/tdl/auto_script/autogensdl.rb +16 -5
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +49 -10
- data/lib/tdl/basefunc.rb +1 -0
- data/lib/tdl/class_hdl/hdl_always_comb.rb +8 -4
- data/lib/tdl/class_hdl/hdl_always_ff.rb +49 -8
- data/lib/tdl/class_hdl/hdl_assign.rb +12 -4
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +18 -16
- data/lib/tdl/class_hdl/hdl_foreach.rb +4 -4
- data/lib/tdl/class_hdl/hdl_function.rb +8 -6
- data/lib/tdl/class_hdl/hdl_generate.rb +9 -5
- data/lib/tdl/class_hdl/hdl_initial.rb +36 -13
- data/lib/tdl/class_hdl/hdl_module_def.rb +27 -7
- data/lib/tdl/class_hdl/hdl_package.rb +45 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +117 -24
- data/lib/tdl/class_hdl/hdl_struct.rb +3 -3
- data/lib/tdl/class_hdl/hdl_verify.rb +1 -1
- data/lib/tdl/elements/Reset.rb +5 -9
- data/lib/tdl/elements/clock.rb +5 -9
- data/lib/tdl/elements/data_inf.rb +0 -17
- data/lib/tdl/elements/logic.rb +9 -31
- data/lib/tdl/elements/mail_box.rb +6 -1
- data/lib/tdl/elements/originclass.rb +23 -48
- data/lib/tdl/elements/parameter.rb +6 -7
- data/lib/tdl/examples/10_random/exp_random.sv +3 -3
- data/lib/tdl/examples/11_test_unit/dve.tcl +155 -2
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +9 -8
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +35 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +6 -3
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +5 -5
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +9 -4
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +5 -5
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +9 -9
- data/lib/tdl/examples/11_test_unit/tu1.sv +1 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +13 -13
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +60 -60
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +17 -17
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +9 -9
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +10 -10
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +7 -7
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +4 -4
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +7 -7
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
- data/lib/tdl/examples/4_generate/test_generate.sv +11 -11
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +3 -3
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/body_package.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +5 -5
- data/lib/tdl/examples/7_module_with_package/head_package.sv +1 -1
- data/lib/tdl/examples/8_top_module/dve.tcl +6 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +9 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +13 -0
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +34 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +2 -2
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +2 -4
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +38 -0
- data/lib/tdl/examples/9_itegration/test_top.sv +4 -4
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +40 -0
- data/lib/tdl/examples/9_itegration/top.rb +1 -0
- data/lib/tdl/exlib/axis_eth_ex.rb +95 -0
- data/lib/tdl/exlib/axis_verify.rb +265 -0
- data/lib/tdl/exlib/clock_reset_verify.rb +29 -0
- data/lib/tdl/exlib/dve_tcl.rb +30 -11
- data/lib/tdl/exlib/itegration.rb +15 -3
- data/lib/tdl/exlib/itegration_verb.rb +167 -130
- data/lib/tdl/exlib/logic_verify.rb +88 -0
- data/lib/tdl/exlib/test_point.rb +96 -94
- data/lib/tdl/exlib/test_point.rb.bak +293 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +9 -9
- data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +34 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +79 -65
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +81 -16
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
- data/lib/tdl/sdlmodule/test_unit_module.rb +283 -33
- data/lib/tdl/sdlmodule/test_unit_module.rb.bak +143 -0
- data/lib/tdl/sdlmodule/top_module.rb +62 -58
- data/lib/tdl/sdlmodule/top_module.rb.bak +547 -0
- data/lib/tdl/tdl.rb +15 -10
- data/lib/tdl/tdlerror/tdlerror.rb +1 -1
- metadata +56 -107
- data/CODE_OF_CONDUCT.md +0 -74
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA256:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: '048d045e78b400e945ff441c154ef78f8073619c51a1547e84526cb9345d72f4'
|
4
|
+
data.tar.gz: baa90f99cf5d67251033740eb77a6314a74b445520159da7fba098d57cffd7f7
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: 95f82468aeffc02b0c0bc09574d9805eef139180474f02a736fb85f8081a874947eb9d4730ebca7197e5d2051c9d8c73f8404b2732d1b3810eab9e4ffbf4cd71
|
7
|
+
data.tar.gz: ec8a233a0df4d3b6f47f4a5078f08ee538acf7153e09c62d0cba18f4e95bcecfca253c211cfa298d51d3486686bb9c487a3e5cbc45b41d2f699c90ac5c36d95a
|
@@ -35,8 +35,10 @@ jobs:
|
|
35
35
|
mkdir -p $HOME/.gem
|
36
36
|
touch $HOME/.gem/credentials
|
37
37
|
chmod 0600 $HOME/.gem/credentials
|
38
|
-
printf -- "---\n:rubygems_api_key: ${
|
38
|
+
printf -- "---\n:rubygems_api_key: ${RUBYGEMS_API_KEY}\n" > $HOME/.gem/credentials
|
39
39
|
gem build *.gemspec
|
40
40
|
gem push *.gem
|
41
41
|
env:
|
42
|
-
|
42
|
+
GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
|
43
|
+
RUBYGEMS_API_KEY: ${{secrets.RUBYGEMS_API_KEY}}
|
44
|
+
# RELEASE_COMMAND: rake release
|
data/Rakefile
CHANGED
@@ -12,3 +12,10 @@ Rake::TestTask.new(:test) do |t|
|
|
12
12
|
# t.ruby_opts = ["-c"]
|
13
13
|
# t.verbose = true
|
14
14
|
end
|
15
|
+
|
16
|
+
desc "编译TB"
|
17
|
+
task :tb do
|
18
|
+
require_relative "./lib/axi_tdl.rb"
|
19
|
+
puts AxiTdl::VERSION
|
20
|
+
require_relative "./lib/axi/techbench/tb_axi_stream_split_channel.rb"
|
21
|
+
end
|
data/axi_tdl.gemspec
CHANGED
@@ -53,7 +53,7 @@ initial begin
|
|
53
53
|
case(MODE)
|
54
54
|
"BOTH_to_BOTH","BOTH_to_ONLY_READ","BOTH_to_ONLY_WRITE":
|
55
55
|
assert(slaver.MODE =="BOTH")
|
56
|
-
else $error("SLAVER AXIS MODE<%
|
56
|
+
else $error("SLAVER AXIS MODE<%0s> != BOTH",slaver.MODE);
|
57
57
|
"ONLY_READ_to_BOTH":
|
58
58
|
assert(slaver.MODE == "ONLY_READ")
|
59
59
|
else $error("SLAVER AXIS MODE != ONLY_READ");
|
@@ -12,61 +12,61 @@ madified:
|
|
12
12
|
(* axi4 = "true" *)
|
13
13
|
module axi4_direct_B1 (
|
14
14
|
(* up_stream = "true" *)
|
15
|
-
axi_inf.slaver
|
15
|
+
axi_inf.slaver slaver_inf,
|
16
16
|
(* down_stream = "true" *)
|
17
|
-
axi_inf.master
|
17
|
+
axi_inf.master master_inf
|
18
18
|
);
|
19
19
|
|
20
20
|
|
21
21
|
generate
|
22
|
-
if(
|
22
|
+
if(slaver_inf.MODE == "ONLY_READ" && master_inf.MODE == "ONLY_READ")
|
23
23
|
axi4_direct_A1 #(
|
24
24
|
.MODE ("ONLY_READ_to_ONLY_READ") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
25
25
|
)axi4_direct_inst_ONLY_READ_to_ONLY_READ(
|
26
|
-
/* axi_inf.slaver */ .slaver (
|
27
|
-
/* axi_inf.master */ .master (
|
26
|
+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
27
|
+
/* axi_inf.master */ .master (master_inf )
|
28
28
|
);
|
29
|
-
else if(
|
29
|
+
else if(slaver_inf.MODE == "ONLY_READ" && master_inf.MODE == "BOTH")
|
30
30
|
axi4_direct_A1 #(
|
31
31
|
.MODE ("ONLY_READ_to_BOTH") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
32
32
|
)axi4_direct_inst_ONLY_READ_to_BOTH(
|
33
|
-
/* axi_inf.slaver */ .slaver (
|
34
|
-
/* axi_inf.master */ .master (
|
33
|
+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
34
|
+
/* axi_inf.master */ .master (master_inf )
|
35
35
|
);
|
36
|
-
else if(
|
36
|
+
else if(slaver_inf.MODE == "ONLY_WRITE" && master_inf.MODE == "BOTH")
|
37
37
|
axi4_direct_A1 #(
|
38
38
|
.MODE ("ONLY_WRITE_to_BOTH") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
39
39
|
)axi4_direct_inst_ONLY_WRITE_to_BOTH(
|
40
|
-
/* axi_inf.slaver */ .slaver (
|
41
|
-
/* axi_inf.master */ .master (
|
40
|
+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
41
|
+
/* axi_inf.master */ .master (master_inf )
|
42
42
|
);
|
43
|
-
else if(
|
43
|
+
else if(slaver_inf.MODE == "ONLY_WRITE" && master_inf.MODE == "ONLY_WRITE")
|
44
44
|
axi4_direct_A1 #(
|
45
45
|
.MODE ("ONLY_WRITE_to_ONLY_WRITE") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
46
46
|
)axi4_direct_inst_ONLY_WRITE_to_ONLY_WRITE(
|
47
|
-
/* axi_inf.slaver */ .slaver (
|
48
|
-
/* axi_inf.master */ .master (
|
47
|
+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
48
|
+
/* axi_inf.master */ .master (master_inf )
|
49
49
|
);
|
50
|
-
else if(
|
50
|
+
else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "ONLY_WRITE")
|
51
51
|
axi4_direct_A1 #(
|
52
52
|
.MODE ("BOTH_to_ONLY_WRITE") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
53
53
|
)axi4_direct_inst_BOTH_to_ONLY_WRITE(
|
54
|
-
/* axi_inf.slaver */ .slaver (
|
55
|
-
/* axi_inf.master */ .master (
|
54
|
+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
55
|
+
/* axi_inf.master */ .master (master_inf )
|
56
56
|
);
|
57
|
-
else if(
|
57
|
+
else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "ONLY_READ")
|
58
58
|
axi4_direct_A1 #(
|
59
59
|
.MODE ("BOTH_to_ONLY_READ") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
60
60
|
)axi4_direct_inst_BOTH_to_ONLY_READ(
|
61
|
-
/* axi_inf.slaver */ .slaver (
|
62
|
-
/* axi_inf.master */ .master (
|
61
|
+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
62
|
+
/* axi_inf.master */ .master (master_inf )
|
63
63
|
);
|
64
|
-
else if(
|
64
|
+
else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "BOTH")
|
65
65
|
axi4_direct_A1 #(
|
66
66
|
.MODE ("BOTH_to_BOTH") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
67
67
|
)axi4_direct_inst_BOTH_to_BOTH(
|
68
|
-
/* axi_inf.slaver */ .slaver (
|
69
|
-
/* axi_inf.master */ .master (
|
68
|
+
/* axi_inf.slaver */ .slaver (slaver_inf ),
|
69
|
+
/* axi_inf.master */ .master (master_inf )
|
70
70
|
);
|
71
71
|
|
72
72
|
endgenerate
|
@@ -25,9 +25,9 @@ module axi4_direct_verc #(
|
|
25
25
|
`parameter_string IGNORE_LSIZE = "FALSE" //(* show = "false" *)
|
26
26
|
)(
|
27
27
|
(* axi4_up = "true" *)
|
28
|
-
axi_inf.slaver
|
28
|
+
axi_inf.slaver slaver_inf,
|
29
29
|
(* axi4_down = "true" *)
|
30
|
-
axi_inf.master
|
30
|
+
axi_inf.master master_inf
|
31
31
|
);
|
32
32
|
|
33
33
|
|
@@ -36,60 +36,60 @@ import SystemPkg::*;
|
|
36
36
|
initial begin
|
37
37
|
#(1us);
|
38
38
|
if(IGNORE_IDSIZE == "FALSE")begin
|
39
|
-
assert(
|
39
|
+
assert(slaver_inf.IDSIZE <= master_inf.IDSIZE) //idsize of slaver_inf can be smaller thane master_inf's
|
40
40
|
else begin
|
41
41
|
$error("SLAVER AXIS IDSIZE != MASTER AXIS IDSIZE");
|
42
42
|
$finish;
|
43
43
|
end
|
44
44
|
end
|
45
45
|
if(IGNORE_DSIZE == "FALSE")begin
|
46
|
-
assert(
|
46
|
+
assert(slaver_inf.DSIZE == master_inf.DSIZE)
|
47
47
|
else $error("SLAVER AXIS DSIZE != MASTER AXIS DSIZE");
|
48
48
|
end
|
49
49
|
if(IGNORE_ASIZE == "FALSE")begin
|
50
|
-
assert(
|
50
|
+
assert(slaver_inf.ASIZE == master_inf.ASIZE)
|
51
51
|
else $error("SLAVER AXIS ASIZE != MASTER AXIS ASIZE");
|
52
52
|
end
|
53
53
|
if(IGNORE_LSIZE == "FALSE")begin
|
54
|
-
assert(
|
54
|
+
assert(slaver_inf.LSIZE == master_inf.LSIZE)
|
55
55
|
else $error("SLAVER AXIS LSIZE != MASTER AXIS LSIZE");
|
56
56
|
end
|
57
57
|
case(MODE)
|
58
58
|
"BOTH_to_BOTH","BOTH_to_ONLY_READ","BOTH_to_ONLY_WRITE":
|
59
|
-
assert(
|
60
|
-
else $error("SLAVER AXIS MODE<%s> != BOTH",
|
59
|
+
assert(slaver_inf.MODE =="BOTH" && SLAVER_MODE=="BOTH")
|
60
|
+
else $error("SLAVER AXIS MODE<%s> != BOTH",slaver_inf.MODE);
|
61
61
|
"ONLY_READ_to_BOTH":
|
62
|
-
assert(
|
62
|
+
assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
|
63
63
|
else $error("SLAVER AXIS MODE != ONLY_READ");
|
64
64
|
"ONLY_WRITE_to_BOTH","ONLY_WRITE_to_ONLY_WRITE":
|
65
|
-
assert(
|
65
|
+
assert(slaver_inf.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
|
66
66
|
else begin
|
67
67
|
$error("SLAVER AXIS MODE != ONLY_WRITE");
|
68
68
|
$finish;
|
69
69
|
end
|
70
70
|
"ONLY_READ_to_ONLY_READ":
|
71
|
-
assert(
|
71
|
+
assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
|
72
72
|
else $error("SLAVER AXIS MODE != ONLY_READ");
|
73
73
|
default:
|
74
|
-
assert(
|
74
|
+
assert(slaver_inf.MODE == "_____")
|
75
75
|
else $error("SLAVER AXIS MODE ERROR") ;
|
76
76
|
endcase
|
77
77
|
|
78
78
|
case(MODE)
|
79
79
|
"ONLY_WRITE_to_BOTH","ONLY_READ_to_BOTH","BOTH_to_BOTH":
|
80
|
-
assert(
|
80
|
+
assert(master_inf.MODE == "BOTH" && MASTER_MODE=="BOTH")
|
81
81
|
else $error("MASTER AXIS MODE != BOTH");
|
82
82
|
"BOTH_to_ONLY_READ":
|
83
|
-
assert(
|
83
|
+
assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READY")
|
84
84
|
else $error("MASTER AXIS MODE != ONLY_READ");
|
85
85
|
"BOTH_to_ONLY_WRITE","ONLY_WRITE_to_ONLY_WRITE":
|
86
|
-
assert(
|
86
|
+
assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
|
87
87
|
else $error("MASTER AXIS MODE != ONLY_WRITE");
|
88
88
|
"ONLY_READ_to_ONLY_READ":
|
89
|
-
assert(
|
89
|
+
assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
|
90
90
|
else $error("MASTER AXIS MODE != ONLY_READ");
|
91
91
|
default:
|
92
|
-
assert(
|
92
|
+
assert(master_inf.MODE == "_____")
|
93
93
|
else $error("MASTER AXIS MODE ERROR");
|
94
94
|
endcase
|
95
95
|
|
@@ -97,49 +97,49 @@ end
|
|
97
97
|
|
98
98
|
generate
|
99
99
|
if(MASTER_MODE!="ONLY_READ")begin
|
100
|
-
assign
|
101
|
-
assign
|
102
|
-
assign
|
103
|
-
assign
|
104
|
-
assign
|
105
|
-
assign
|
106
|
-
assign
|
107
|
-
assign
|
108
|
-
assign
|
109
|
-
assign
|
110
|
-
assign
|
111
|
-
assign
|
112
|
-
assign
|
113
|
-
assign
|
114
|
-
assign
|
115
|
-
assign
|
116
|
-
assign
|
117
|
-
assign
|
118
|
-
assign
|
119
|
-
assign
|
100
|
+
assign master_inf.axi_awid = slaver_inf.axi_awid ;
|
101
|
+
assign master_inf.axi_awaddr = slaver_inf.axi_awaddr ;
|
102
|
+
assign master_inf.axi_awlen = slaver_inf.axi_awlen ;
|
103
|
+
assign master_inf.axi_awsize = slaver_inf.axi_awsize ;
|
104
|
+
assign master_inf.axi_awburst = slaver_inf.axi_awburst;
|
105
|
+
assign master_inf.axi_awlock = slaver_inf.axi_awlock ;
|
106
|
+
assign master_inf.axi_awcache = slaver_inf.axi_awcache;
|
107
|
+
assign master_inf.axi_awprot = slaver_inf.axi_awprot ;
|
108
|
+
assign master_inf.axi_awqos = slaver_inf.axi_awqos ;
|
109
|
+
assign master_inf.axi_awvalid = slaver_inf.axi_awvalid;
|
110
|
+
assign slaver_inf.axi_awready = master_inf.axi_awready;
|
111
|
+
assign master_inf.axi_wdata = slaver_inf.axi_wdata ;
|
112
|
+
assign master_inf.axi_wstrb = slaver_inf.axi_wstrb ;
|
113
|
+
assign master_inf.axi_wlast = slaver_inf.axi_wlast ;
|
114
|
+
assign master_inf.axi_wvalid = slaver_inf.axi_wvalid ;
|
115
|
+
assign slaver_inf.axi_wready = master_inf.axi_wready ;
|
116
|
+
assign master_inf.axi_bready = slaver_inf.axi_bready ;
|
117
|
+
assign slaver_inf.axi_bid = master_inf.axi_bid ;
|
118
|
+
assign slaver_inf.axi_bresp = master_inf.axi_bresp ;
|
119
|
+
assign slaver_inf.axi_bvalid = master_inf.axi_bvalid ;
|
120
120
|
end
|
121
121
|
endgenerate
|
122
122
|
|
123
123
|
|
124
124
|
generate
|
125
125
|
if(MASTER_MODE!="ONLY_WRITE")begin
|
126
|
-
assign
|
127
|
-
assign
|
128
|
-
assign
|
129
|
-
assign
|
130
|
-
assign
|
131
|
-
assign
|
132
|
-
assign
|
133
|
-
assign
|
134
|
-
assign
|
135
|
-
assign
|
136
|
-
assign
|
137
|
-
assign
|
138
|
-
assign
|
139
|
-
assign
|
140
|
-
assign
|
141
|
-
assign
|
142
|
-
assign
|
126
|
+
assign master_inf.axi_arid = slaver_inf.axi_arid ;
|
127
|
+
assign master_inf.axi_araddr = slaver_inf.axi_araddr ;
|
128
|
+
assign master_inf.axi_arlen = slaver_inf.axi_arlen ;
|
129
|
+
assign master_inf.axi_arsize = slaver_inf.axi_arsize ;
|
130
|
+
assign master_inf.axi_arburst = slaver_inf.axi_arburst;
|
131
|
+
assign master_inf.axi_arlock = slaver_inf.axi_arlock ;
|
132
|
+
assign master_inf.axi_arcache = slaver_inf.axi_arcache;
|
133
|
+
assign master_inf.axi_arprot = slaver_inf.axi_arprot ;
|
134
|
+
assign master_inf.axi_arqos = slaver_inf.axi_arqos ;
|
135
|
+
assign master_inf.axi_arvalid = slaver_inf.axi_arvalid;
|
136
|
+
assign slaver_inf.axi_arready = master_inf.axi_arready;
|
137
|
+
assign master_inf.axi_rready = slaver_inf.axi_rready ;
|
138
|
+
assign slaver_inf.axi_rid = master_inf.axi_rid ;
|
139
|
+
assign slaver_inf.axi_rdata = master_inf.axi_rdata ;
|
140
|
+
assign slaver_inf.axi_rresp = master_inf.axi_rresp ;
|
141
|
+
assign slaver_inf.axi_rlast = master_inf.axi_rlast ;
|
142
|
+
assign slaver_inf.axi_rvalid = master_inf.axi_rvalid ;
|
143
143
|
end
|
144
144
|
endgenerate
|
145
145
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
5
5
|
descript:
|
6
6
|
author : Cook.Darwin
|
7
7
|
Version: VERA.0.0
|
8
|
-
|
8
|
+
creaded: XXXX.XX.XX
|
9
9
|
madified:
|
10
10
|
***********************************************/
|
11
11
|
`timescale 1ns/1ps
|
@@ -20,7 +20,7 @@ module axi4_dpram_cache #(
|
|
20
20
|
//==========================================================================
|
21
21
|
//-------- define ----------------------------------------------------------
|
22
22
|
|
23
|
-
cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE(
|
23
|
+
cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE((a_inf.DSIZE / 8))) xram_inf();
|
24
24
|
axi_stream_inf #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1),.USIZE(1)) a_axis_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
|
25
25
|
axi_stream_inf #(.DSIZE(a_inf.DSIZE),.USIZE(1)) a_axis_rd_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
|
26
26
|
data_inf_c #(.DSIZE(a_inf.ASIZE+1)) a_datac_rd_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
|
@@ -69,44 +69,44 @@ common_ram_wrapper #(
|
|
69
69
|
//==========================================================================
|
70
70
|
//-------- expression ------------------------------------------------------
|
71
71
|
initial begin
|
72
|
-
assert(
|
73
|
-
|
74
|
-
|
72
|
+
assert(a_inf.ASIZE==b_inf.ASIZE)else begin
|
73
|
+
$error("a_inf.ASIZE != b_inf.ASIZE");
|
74
|
+
$stop;
|
75
75
|
end
|
76
|
-
assert(
|
77
|
-
|
78
|
-
|
76
|
+
assert(a_inf.DSIZE==b_inf.DSIZE)else begin
|
77
|
+
$error("a_inf.ASIZE != b_inf.ASIZE");
|
78
|
+
$stop;
|
79
79
|
end
|
80
80
|
end
|
81
81
|
|
82
|
-
assign
|
83
|
-
assign
|
84
|
-
assign
|
82
|
+
assign a_axis_inf.axis_tready = a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1] || (a_datac_rd_inf.ready && !a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1]);
|
83
|
+
assign a_datac_rd_inf.data = {a_axis_inf.axis_tlast,a_axis_inf.axis_tdata[(a_inf.ASIZE+a_inf.DSIZE+1-1)-1:(a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1]};
|
84
|
+
assign a_datac_rd_inf.valid = a_axis_inf.axis_tvalid && !a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1];
|
85
85
|
|
86
|
-
assign
|
87
|
-
assign
|
88
|
-
assign
|
89
|
-
assign
|
90
|
-
assign
|
91
|
-
assign
|
92
|
-
assign
|
93
|
-
assign
|
94
|
-
assign
|
95
|
-
assign
|
86
|
+
assign a_axis_rd_inf.axis_tvalid = a_datac_rd_rel_inf.valid;
|
87
|
+
assign a_axis_rd_inf.axis_tdata = a_datac_rd_rel_inf.data[a_inf.DSIZE-1:0];
|
88
|
+
assign a_axis_rd_inf.axis_tlast = a_datac_rd_rel_inf.data[a_inf.ASIZE+a_inf.DSIZE+1-1];
|
89
|
+
assign a_datac_rd_rel_inf.ready = a_axis_rd_inf.axis_tready;
|
90
|
+
assign xram_inf.addra = a_axis_inf.axis_tdata[(a_inf.ASIZE+a_inf.DSIZE+1-1)-1:(a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1];
|
91
|
+
assign xram_inf.dia = a_axis_inf.axis_tdata[a_inf.DSIZE-1:0];
|
92
|
+
assign xram_inf.wea = {xram_inf.MSIZE{a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1]}};
|
93
|
+
assign xram_inf.ena = 1'b1;
|
94
|
+
assign xram_inf.clka = a_inf.axi_aclk;
|
95
|
+
assign xram_inf.rsta = ~a_inf.axi_aresetn;
|
96
96
|
|
97
|
-
assign
|
98
|
-
assign
|
99
|
-
assign
|
97
|
+
assign b_axis_inf.axis_tready = b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1] || (b_datac_rd_inf.ready && !b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1]);
|
98
|
+
assign b_datac_rd_inf.data = {b_axis_inf.axis_tlast,b_axis_inf.axis_tdata[(b_inf.ASIZE+b_inf.DSIZE+1-1)-1:(b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1]};
|
99
|
+
assign b_datac_rd_inf.valid = b_axis_inf.axis_tvalid && !b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1];
|
100
100
|
|
101
|
-
assign
|
102
|
-
assign
|
103
|
-
assign
|
104
|
-
assign
|
105
|
-
assign
|
106
|
-
assign
|
107
|
-
assign
|
108
|
-
assign
|
109
|
-
assign
|
110
|
-
assign
|
101
|
+
assign b_axis_rd_inf.axis_tvalid = b_datac_rd_rel_inf.valid;
|
102
|
+
assign b_axis_rd_inf.axis_tdata = b_datac_rd_rel_inf.data[b_inf.DSIZE-1:0];
|
103
|
+
assign b_axis_rd_inf.axis_tlast = b_datac_rd_rel_inf.data[b_inf.ASIZE+b_inf.DSIZE+1-1];
|
104
|
+
assign b_datac_rd_rel_inf.ready = b_axis_rd_inf.axis_tready;
|
105
|
+
assign xram_inf.addrb = b_axis_inf.axis_tdata[(b_inf.ASIZE+b_inf.DSIZE+1-1)-1:(b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1];
|
106
|
+
assign xram_inf.dib = b_axis_inf.axis_tdata[b_inf.DSIZE-1:0];
|
107
|
+
assign xram_inf.web = {xram_inf.MSIZE{b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1]}};
|
108
|
+
assign xram_inf.enb = 1'b1;
|
109
|
+
assign xram_inf.clkb = b_inf.axi_aclk;
|
110
|
+
assign xram_inf.rstb = ~b_inf.axi_aresetn;
|
111
111
|
|
112
112
|
endmodule
|
@@ -6,6 +6,7 @@ require_hdl 'axis_length_split_with_addr.sv'
|
|
6
6
|
require_hdl 'axi_stream_long_fifo.sv'
|
7
7
|
require_hdl 'axi4_wr_auxiliary_gen_without_resp.sv'
|
8
8
|
require_hdl 'axis_valve_with_pipe.sv'
|
9
|
+
require_hdl 'independent_clock_fifo.sv'
|
9
10
|
|
10
11
|
new_m = SdlModule.new(name:File.basename(__FILE__,".rb"),out_sv_path:__dir__)
|
11
12
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
5
5
|
descript:
|
6
6
|
author : Cook.Darwin
|
7
7
|
Version: VERA.0.0
|
8
|
-
|
8
|
+
creaded: XXXX.XX.XX
|
9
9
|
madified:
|
10
10
|
***********************************************/
|
11
11
|
`timescale 1ns/1ps
|
@@ -56,7 +56,7 @@ logic stream_en;
|
|
56
56
|
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
|
57
57
|
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
58
58
|
axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
59
|
-
axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP))
|
59
|
+
axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R186 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
|
60
60
|
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
61
61
|
//==========================================================================
|
62
62
|
//-------- instance --------------------------------------------------------
|
@@ -92,16 +92,16 @@ independent_clock_fifo #(
|
|
92
92
|
/* output */.full (fifo_full )
|
93
93
|
);
|
94
94
|
axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
|
95
|
-
/* output */.stream_en (stream_en
|
96
|
-
/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in
|
97
|
-
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (
|
95
|
+
/* output */.stream_en (stream_en ),
|
96
|
+
/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
|
97
|
+
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R186 )
|
98
98
|
);
|
99
99
|
vcs_axi4_comptable #(
|
100
100
|
.ORIGIN ("master_wr_aux_no_resp" ),
|
101
101
|
.TO ("master_wr" )
|
102
|
-
)
|
103
|
-
/* input */.origin (
|
104
|
-
/* output */.to (axi_wr
|
102
|
+
)vcs_axi4_comptable_axi_wr_aux_R282_axi_wr_inst(
|
103
|
+
/* input */.origin (axi_wr_vcs_cp_R186 ),
|
104
|
+
/* output */.to (axi_wr )
|
105
105
|
);
|
106
106
|
axis_valve_with_pipe #(
|
107
107
|
.MODE ("BOTH" )
|
@@ -112,30 +112,30 @@ axis_valve_with_pipe #(
|
|
112
112
|
);
|
113
113
|
//==========================================================================
|
114
114
|
//-------- expression ------------------------------------------------------
|
115
|
-
|
115
|
+
always@(posedge axis_in.aclk,negedge axis_in.aresetn) begin
|
116
116
|
if(~axis_in.aresetn)begin
|
117
|
-
|
117
|
+
id <= 0;
|
118
118
|
end
|
119
119
|
else if(split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast)begin
|
120
|
-
|
120
|
+
id <= (id+1);
|
121
121
|
end
|
122
122
|
else begin
|
123
|
-
|
123
|
+
id <= id;
|
124
124
|
end
|
125
125
|
end
|
126
126
|
|
127
|
-
assign
|
128
|
-
assign
|
129
|
-
assign
|
130
|
-
assign
|
131
|
-
assign
|
132
|
-
assign
|
127
|
+
assign addr_s = addr_cur;
|
128
|
+
assign len_s = split_out.axis_tcnt;
|
129
|
+
assign id_add_len_in.axis_tvalid = ~fifo_empty;
|
130
|
+
assign id_add_len_in.axis_tdata = fifo_rdata;
|
131
|
+
assign id_add_len_in.axis_tlast = "1'b1";
|
132
|
+
assign rd_en = id_add_len_in.axis_tready;
|
133
133
|
|
134
|
-
assign
|
135
|
-
assign
|
136
|
-
assign
|
137
|
-
assign
|
138
|
-
assign
|
139
|
-
assign
|
134
|
+
assign axi_wr.axi_wdata = pipe_axis.axis_tdata;
|
135
|
+
assign axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
|
136
|
+
assign axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
|
137
|
+
assign axi_wr.axi_wlast = pipe_axis.axis_tlast;
|
138
|
+
assign axi_wr.axi_bready = 1'b1;
|
139
|
+
assign pipe_axis.axis_tready = axi_wr.axi_wready;
|
140
140
|
|
141
141
|
endmodule
|