apple-data 1.0.1 → 1.0.388
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/apple_data/boot_args.rb +0 -1
- data/lib/apple_data/fdr.rb +0 -1
- data/lib/apple_data/ioreg.rb +0 -1
- data/lib/apple_data/lockdown.rb +0 -1
- data/lib/apple_data/macho.rb +0 -1
- data/lib/apple_data/version.rb +1 -1
- data/lib/apple_data.rb +0 -1
- data/share/4cc.yaml +293 -297
- data/share/apns.yaml +364 -367
- data/share/backup.yaml +44 -47
- data/share/baseband.yaml +1 -290
- data/share/bluetooth.yaml +71 -75
- data/share/boot_args.yaml +855 -863
- data/share/bridgeos.yaml +131 -174
- data/share/bundles.yaml +60 -56
- data/share/cores.yaml +68 -33
- data/share/dnssd.yaml +166 -171
- data/share/fdr.yaml +148 -150
- data/share/homekit.yaml +14 -14
- data/share/icloud.yaml +8 -11
- data/share/img4.yaml +453 -454
- data/share/ioreg.yaml +5642 -5647
- data/share/ipsw.yaml +1099 -51505
- data/share/kext.yaml +1718 -3491
- data/share/lightning.yaml +23 -26
- data/share/lockdownd.yaml +71 -74
- data/share/mach_o.yaml +172 -204
- data/share/mobile_assets.yaml +127 -113
- data/share/mobile_gestalt.yaml +2444 -2447
- data/share/nvram.yaml +441 -463
- data/share/ota.yaml +1 -4
- data/share/pki.yaml +99 -103
- data/share/platforms.yaml +31 -35
- data/share/pmu.yaml +26 -52
- data/share/registers.yaml +1603 -1579
- data/share/resources.yaml +198 -202
- data/share/sep.yaml +206 -210
- data/share/services.yaml +636 -641
- data/share/syscfg.yaml +1 -4
- metadata +2 -46
- data/lib/apple_data/ipsw.rb +0 -25
- data/lib/apple_data/keybag.rb +0 -56
- data/share/baseband/qualcomm/mav13.yaml +0 -26
- data/share/baseband/qualcomm/mav20.yaml +0 -45
- data/share/baseband/qualcomm/mav21.yaml +0 -254
- data/share/coprocessor.yaml +0 -64
- data/share/debug.yaml +0 -13
- data/share/defaults.yaml +0 -5
- data/share/entitlements.yaml +0 -10391
- data/share/environment_variables.yaml +0 -354
- data/share/esim.yaml +0 -7
- data/share/firmware.yaml +0 -1310
- data/share/iboot.yaml +0 -143
- data/share/keybags/7000.yaml +0 -44342
- data/share/keybags/7001.yaml +0 -19430
- data/share/keybags/7002.yaml +0 -292
- data/share/keybags/8000.yaml +0 -82065
- data/share/keybags/8001.yaml +0 -29655
- data/share/keybags/8004.yaml +0 -295
- data/share/keybags/8006.yaml +0 -65
- data/share/keybags/8010.yaml +0 -23899
- data/share/keybags/8011.yaml +0 -4409
- data/share/keybags/8015.yaml +0 -23626
- data/share/keybags/8020.yaml +0 -4488
- data/share/keybags/8027.yaml +0 -43
- data/share/keybags/8030.yaml +0 -8687
- data/share/keybags/8101.yaml +0 -8595
- data/share/keybags/8720.yaml +0 -2026
- data/share/keybags/8900.yaml +0 -2344
- data/share/keybags/8920.yaml +0 -6761
- data/share/keybags/8922.yaml +0 -3141
- data/share/keybags/8930.yaml +0 -20583
- data/share/keybags/8940.yaml +0 -36319
- data/share/keybags/8942.yaml +0 -17343
- data/share/keybags/8945.yaml +0 -23360
- data/share/keybags/8947.yaml +0 -1384
- data/share/keybags/8950.yaml +0 -16258
- data/share/keybags/8955.yaml +0 -52163
- data/share/keybags/8960.yaml +0 -49499
- data/share/keys.yaml +0 -56
- data/share/sip.yaml +0 -64
- data/share/smc.yaml +0 -7
- data/share/tipw_sync.yaml +0 -79103
- data/share/vmapple.yaml +0 -35
data/share/registers.yaml
CHANGED
|
@@ -1,8 +1,7 @@
|
|
|
1
1
|
---
|
|
2
|
-
|
|
3
|
-
|
|
4
|
-
|
|
5
|
-
- https://gist.github.com/bazad/42054285391c6e0dcd0ede4b5f969ad2
|
|
2
|
+
description: Representations of registers and instructions for various CPU elements
|
|
3
|
+
credits:
|
|
4
|
+
- https://gist.github.com/bazad/42054285391c6e0dcd0ede4b5f969ad2
|
|
6
5
|
aarch64:
|
|
7
6
|
pstate:
|
|
8
7
|
0b011: 'UAO'
|
|
@@ -11,2493 +10,2518 @@ aarch64:
|
|
|
11
10
|
0b110: 'DAIFSet'
|
|
12
11
|
0b111: 'DAIFClr'
|
|
13
12
|
msr:
|
|
14
|
-
S1_0_c7_c1_0:
|
|
15
|
-
|
|
13
|
+
'S1_0_c7_c1_0':
|
|
14
|
+
- name: 'IC IALLUIS'
|
|
16
15
|
description: 'Instruction Cache Invalidate All to PoU, Inner Shareable'
|
|
17
|
-
S1_0_c7_c5_0:
|
|
18
|
-
|
|
16
|
+
'S1_0_c7_c5_0':
|
|
17
|
+
- name: 'IC IALLU'
|
|
19
18
|
description: 'Instruction Cache Invalidate All to PoU'
|
|
20
|
-
S1_0_c7_c6_1:
|
|
21
|
-
|
|
19
|
+
'S1_0_c7_c6_1':
|
|
20
|
+
- name: 'DC IVAC'
|
|
22
21
|
description: 'Data or unified Cache line Invalidate by VA to PoC'
|
|
23
|
-
S1_0_c7_c6_2:
|
|
24
|
-
|
|
22
|
+
'S1_0_c7_c6_2':
|
|
23
|
+
- name: 'DC ISW'
|
|
25
24
|
description: 'Data or unified Cache line Invalidate by Set/Way'
|
|
26
|
-
S1_0_c7_c6_3:
|
|
27
|
-
|
|
25
|
+
'S1_0_c7_c6_3':
|
|
26
|
+
- name: 'DC IGVAC'
|
|
28
27
|
description: 'Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC'
|
|
29
|
-
S1_0_c7_c6_4:
|
|
30
|
-
|
|
28
|
+
'S1_0_c7_c6_4':
|
|
29
|
+
- name: 'DC IGSW'
|
|
31
30
|
description: 'Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by Set/Way'
|
|
32
|
-
S1_0_c7_c6_5:
|
|
33
|
-
|
|
31
|
+
'S1_0_c7_c6_5':
|
|
32
|
+
- name: 'DC IGDVAC'
|
|
34
33
|
description: 'Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC'
|
|
35
|
-
S1_0_c7_c6_6:
|
|
36
|
-
|
|
34
|
+
'S1_0_c7_c6_6':
|
|
35
|
+
- name: 'DC IGDSW'
|
|
37
36
|
description: 'Data, Allocation Tag or unified Cache line Invalidate of Data and Allocation Tags by Set/Way'
|
|
38
|
-
S1_0_c7_c8_0:
|
|
39
|
-
|
|
37
|
+
'S1_0_c7_c8_0':
|
|
38
|
+
- name: 'AT S1E1R'
|
|
40
39
|
description: 'Address Translate Stage 1 EL1 Read'
|
|
41
|
-
S1_0_c7_c8_1:
|
|
42
|
-
|
|
40
|
+
'S1_0_c7_c8_1':
|
|
41
|
+
- name: 'AT S1E1W'
|
|
43
42
|
description: 'Address Translate Stage 1 EL1 Write'
|
|
44
|
-
S1_0_c7_c8_2:
|
|
45
|
-
|
|
43
|
+
'S1_0_c7_c8_2':
|
|
44
|
+
- name: 'AT S1E0R'
|
|
46
45
|
description: 'Address Translate Stage 1 EL0 Read'
|
|
47
|
-
S1_0_c7_c8_3:
|
|
48
|
-
|
|
46
|
+
'S1_0_c7_c8_3':
|
|
47
|
+
- name: 'AT S1E0W'
|
|
49
48
|
description: 'Address Translate Stage 1 EL0 Write'
|
|
50
|
-
S1_0_c7_c9_0:
|
|
51
|
-
|
|
49
|
+
'S1_0_c7_c9_0':
|
|
50
|
+
- name: 'AT S1E1RP'
|
|
52
51
|
description: 'Address Translate Stage 1 EL1 Read PAN'
|
|
53
|
-
S1_0_c7_c9_1:
|
|
54
|
-
|
|
52
|
+
'S1_0_c7_c9_1':
|
|
53
|
+
- name: 'AT S1E1WP'
|
|
55
54
|
description: 'Address Translate Stage 1 EL1 Write PAN'
|
|
56
|
-
S1_0_c7_c10_2:
|
|
57
|
-
|
|
55
|
+
'S1_0_c7_c10_2':
|
|
56
|
+
- name: 'DC CSW'
|
|
58
57
|
description: 'Data or unified Cache line Clean by Set/Way'
|
|
59
|
-
S1_0_c7_c10_4:
|
|
60
|
-
|
|
58
|
+
'S1_0_c7_c10_4':
|
|
59
|
+
- name: 'DC CGSW'
|
|
61
60
|
description: 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by Set/Way'
|
|
62
|
-
S1_0_c7_c10_6:
|
|
63
|
-
|
|
61
|
+
'S1_0_c7_c10_6':
|
|
62
|
+
- name: 'DC CGDSW'
|
|
64
63
|
description: 'Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by Set/Way'
|
|
65
|
-
S1_0_c7_c14_2:
|
|
66
|
-
|
|
64
|
+
'S1_0_c7_c14_2':
|
|
65
|
+
- name: 'DC CISW'
|
|
67
66
|
description: 'Data or unified Cache line Clean and Invalidate by Set/Way'
|
|
68
|
-
S1_0_c7_c14_4:
|
|
69
|
-
|
|
67
|
+
'S1_0_c7_c14_4':
|
|
68
|
+
- name: 'DC CIGSW'
|
|
70
69
|
description: 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by Set/Way'
|
|
71
|
-
S1_0_c7_c14_6:
|
|
72
|
-
|
|
70
|
+
'S1_0_c7_c14_6':
|
|
71
|
+
- name: 'DC CIGDSW'
|
|
73
72
|
description: 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by Set/Way'
|
|
74
|
-
S1_0_c8_c1_0:
|
|
75
|
-
|
|
73
|
+
'S1_0_c8_c1_0':
|
|
74
|
+
- name: 'TLBI VMALLE1OS'
|
|
76
75
|
description: 'TLB Invalidate by VMID, All at stage 1, EL1, Outer Shareable'
|
|
77
|
-
S1_0_c8_c1_1:
|
|
78
|
-
|
|
76
|
+
'S1_0_c8_c1_1':
|
|
77
|
+
- name: 'TLBI VAE1OS'
|
|
79
78
|
description: 'TLB Invalidate by VA, EL1, Outer Shareable'
|
|
80
|
-
S1_0_c8_c1_2:
|
|
81
|
-
|
|
79
|
+
'S1_0_c8_c1_2':
|
|
80
|
+
- name: 'TLBI ASIDE1OS'
|
|
82
81
|
description: 'TLB Invalidate by ASID, EL1, Outer Shareable'
|
|
83
|
-
S1_0_c8_c1_3:
|
|
84
|
-
|
|
82
|
+
'S1_0_c8_c1_3':
|
|
83
|
+
- name: 'TLBI VAAE1OS'
|
|
85
84
|
description: 'TLB Invalidate by VA, All ASID, EL1, Outer Shareable'
|
|
86
|
-
S1_0_c8_c1_5:
|
|
87
|
-
|
|
85
|
+
'S1_0_c8_c1_5':
|
|
86
|
+
- name: 'TLBI VALE1OS'
|
|
88
87
|
description: 'TLB Invalidate by VA, Last level, EL1, Outer Shareable'
|
|
89
|
-
S1_0_c8_c1_7:
|
|
90
|
-
|
|
88
|
+
'S1_0_c8_c1_7':
|
|
89
|
+
- name: 'TLBI VAALE1OS'
|
|
91
90
|
description: 'TLB Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable'
|
|
92
|
-
S1_0_c8_c2_1:
|
|
93
|
-
|
|
91
|
+
'S1_0_c8_c2_1':
|
|
92
|
+
- name: 'TLBI RVAE1IS'
|
|
94
93
|
description: 'TLB Range Invalidate by VA, EL1, Inner Shareable'
|
|
95
|
-
S1_0_c8_c2_3:
|
|
96
|
-
|
|
94
|
+
'S1_0_c8_c2_3':
|
|
95
|
+
- name: 'TLBI RVAAE1IS'
|
|
97
96
|
description: 'TLB Range Invalidate by VA, All ASID, EL1, Inner Shareable'
|
|
98
|
-
S1_0_c8_c2_5:
|
|
99
|
-
|
|
97
|
+
'S1_0_c8_c2_5':
|
|
98
|
+
- name: 'TLBI RVALE1IS'
|
|
100
99
|
description: 'TLB Range Invalidate by VA, Last level, EL1, Inner Shareable'
|
|
101
|
-
S1_0_c8_c2_7:
|
|
102
|
-
|
|
100
|
+
'S1_0_c8_c2_7':
|
|
101
|
+
- name: 'TLBI RVAALE1IS'
|
|
103
102
|
description: 'TLB Range Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable'
|
|
104
|
-
S1_0_c8_c3_0:
|
|
105
|
-
|
|
103
|
+
'S1_0_c8_c3_0':
|
|
104
|
+
- name: 'TLBI VMALLE1IS'
|
|
106
105
|
description: 'TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable'
|
|
107
|
-
S1_0_c8_c3_1:
|
|
108
|
-
|
|
106
|
+
'S1_0_c8_c3_1':
|
|
107
|
+
- name: 'TLBI VAE1IS'
|
|
109
108
|
description: 'TLB Invalidate by VA, EL1, Inner Shareable'
|
|
110
|
-
S1_0_c8_c3_2:
|
|
111
|
-
|
|
109
|
+
'S1_0_c8_c3_2':
|
|
110
|
+
- name: 'TLBI ASIDE1IS'
|
|
112
111
|
description: 'TLB Invalidate by ASID, EL1, Inner Shareable'
|
|
113
|
-
S1_0_c8_c3_3:
|
|
114
|
-
|
|
112
|
+
'S1_0_c8_c3_3':
|
|
113
|
+
- name: 'TLBI VAAE1IS'
|
|
115
114
|
description: 'TLB Invalidate by VA, All ASID, EL1, Inner Shareable'
|
|
116
|
-
S1_0_c8_c3_5:
|
|
117
|
-
|
|
115
|
+
'S1_0_c8_c3_5':
|
|
116
|
+
- name: 'TLBI VALE1IS'
|
|
118
117
|
description: 'TLB Invalidate by VA, Last level, EL1, Inner Shareable'
|
|
119
|
-
S1_0_c8_c3_7:
|
|
120
|
-
|
|
118
|
+
'S1_0_c8_c3_7':
|
|
119
|
+
- name: 'TLBI VAALE1IS'
|
|
121
120
|
description: 'TLB Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable'
|
|
122
|
-
S1_0_c8_c5_1:
|
|
123
|
-
|
|
121
|
+
'S1_0_c8_c5_1':
|
|
122
|
+
- name: 'TLBI RVAE1OS'
|
|
124
123
|
description: 'TLB Range Invalidate by VA, EL1, Outer Shareable'
|
|
125
|
-
S1_0_c8_c5_3:
|
|
126
|
-
|
|
124
|
+
'S1_0_c8_c5_3':
|
|
125
|
+
- name: 'TLBI RVAAE1OS'
|
|
127
126
|
description: 'TLB Range Invalidate by VA, All ASID, EL1, Outer Shareable'
|
|
128
|
-
S1_0_c8_c5_5:
|
|
129
|
-
|
|
127
|
+
'S1_0_c8_c5_5':
|
|
128
|
+
- name: 'TLBI RVALE1OS'
|
|
130
129
|
description: 'TLB Range Invalidate by VA, Last level, EL1, Outer Shareable'
|
|
131
|
-
S1_0_c8_c5_7:
|
|
132
|
-
|
|
130
|
+
'S1_0_c8_c5_7':
|
|
131
|
+
- name: 'TLBI RVAALE1OS'
|
|
133
132
|
description: 'TLB Range Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable'
|
|
134
|
-
S1_0_c8_c6_1:
|
|
135
|
-
|
|
133
|
+
'S1_0_c8_c6_1':
|
|
134
|
+
- name: 'TLBI RVAE1'
|
|
136
135
|
description: 'TLB Range Invalidate by VA, EL1'
|
|
137
|
-
S1_0_c8_c6_3:
|
|
138
|
-
|
|
136
|
+
'S1_0_c8_c6_3':
|
|
137
|
+
- name: 'TLBI RVAAE1'
|
|
139
138
|
description: 'TLB Range Invalidate by VA, All ASID, EL1'
|
|
140
|
-
S1_0_c8_c6_5:
|
|
141
|
-
|
|
139
|
+
'S1_0_c8_c6_5':
|
|
140
|
+
- name: 'TLBI RVALE1'
|
|
142
141
|
description: 'TLB Range Invalidate by VA, Last level, EL1'
|
|
143
|
-
S1_0_c8_c6_7:
|
|
144
|
-
|
|
142
|
+
'S1_0_c8_c6_7':
|
|
143
|
+
- name: 'TLBI RVAALE1'
|
|
145
144
|
description: 'TLB Range Invalidate by VA, All ASID, Last level, EL1'
|
|
146
|
-
S1_0_c8_c7_0:
|
|
147
|
-
|
|
145
|
+
'S1_0_c8_c7_0':
|
|
146
|
+
- name: 'TLBI VMALLE1'
|
|
148
147
|
description: 'TLB Invalidate by VMID, All at stage 1, EL1'
|
|
149
|
-
S1_0_c8_c7_1:
|
|
150
|
-
|
|
148
|
+
'S1_0_c8_c7_1':
|
|
149
|
+
- name: 'TLBI VAE1'
|
|
151
150
|
description: 'TLB Invalidate by VA, EL1'
|
|
152
|
-
S1_0_c8_c7_2:
|
|
153
|
-
|
|
151
|
+
'S1_0_c8_c7_2':
|
|
152
|
+
- name: 'TLBI ASIDE1'
|
|
154
153
|
description: 'TLB Invalidate by ASID, EL1'
|
|
155
|
-
S1_0_c8_c7_3:
|
|
156
|
-
|
|
154
|
+
'S1_0_c8_c7_3':
|
|
155
|
+
- name: 'TLBI VAAE1'
|
|
157
156
|
description: 'TLB Invalidate by VA, All ASID, EL1'
|
|
158
|
-
S1_0_c8_c7_5:
|
|
159
|
-
|
|
157
|
+
'S1_0_c8_c7_5':
|
|
158
|
+
- name: 'TLBI VALE1'
|
|
160
159
|
description: 'TLB Invalidate by VA, Last level, EL1'
|
|
161
|
-
S1_0_c8_c7_7:
|
|
162
|
-
|
|
160
|
+
'S1_0_c8_c7_7':
|
|
161
|
+
- name: 'TLBI VAALE1'
|
|
163
162
|
description: 'TLB Invalidate by VA, All ASID, Last level, EL1'
|
|
164
|
-
S1_3_c7_c3_4:
|
|
165
|
-
|
|
163
|
+
'S1_3_c7_c3_4':
|
|
164
|
+
- name: 'CFP RCTX'
|
|
166
165
|
description: 'Control Flow Prediction Restriction by Context'
|
|
167
|
-
S1_3_c7_c3_5:
|
|
168
|
-
|
|
166
|
+
'S1_3_c7_c3_5':
|
|
167
|
+
- name: 'DVP RCTX'
|
|
169
168
|
description: 'Data Value Prediction Restriction by Context'
|
|
170
|
-
S1_3_c7_c3_7:
|
|
171
|
-
|
|
169
|
+
'S1_3_c7_c3_7':
|
|
170
|
+
- name: 'CPP RCTX'
|
|
172
171
|
description: 'Cache Prefetch Prediction Restriction by Context'
|
|
173
|
-
S1_3_c7_c4_1:
|
|
174
|
-
|
|
172
|
+
'S1_3_c7_c4_1':
|
|
173
|
+
- name: 'DC ZVA'
|
|
175
174
|
description: 'Data Cache Zero by VA'
|
|
176
|
-
S1_3_c7_c4_3:
|
|
177
|
-
|
|
175
|
+
'S1_3_c7_c4_3':
|
|
176
|
+
- name: 'DC GVA'
|
|
178
177
|
description: 'Data Cache set Allocation Tag by VA'
|
|
179
|
-
S1_3_c7_c4_4:
|
|
180
|
-
|
|
178
|
+
'S1_3_c7_c4_4':
|
|
179
|
+
- name: 'DC GZVA'
|
|
181
180
|
description: 'Data Cache set Allocation Tags and Zero by VA'
|
|
182
|
-
S1_3_c7_c5_1:
|
|
183
|
-
|
|
181
|
+
'S1_3_c7_c5_1':
|
|
182
|
+
- name: 'IC IVAU'
|
|
184
183
|
description: 'Instruction Cache line Invalidate by VA to PoU'
|
|
185
|
-
S1_3_c7_c10_1:
|
|
186
|
-
|
|
184
|
+
'S1_3_c7_c10_1':
|
|
185
|
+
- name: 'DC CVAC'
|
|
187
186
|
description: 'Data or unified Cache line Clean by VA to PoC'
|
|
188
|
-
S1_3_c7_c10_3:
|
|
189
|
-
|
|
187
|
+
'S1_3_c7_c10_3':
|
|
188
|
+
- name: 'DC CGVAC'
|
|
190
189
|
description: 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC'
|
|
191
|
-
S1_3_c7_c10_5:
|
|
192
|
-
|
|
190
|
+
'S1_3_c7_c10_5':
|
|
191
|
+
- name: 'DC CGDVAC'
|
|
193
192
|
description: 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC'
|
|
194
|
-
S1_3_c7_c11_1:
|
|
195
|
-
|
|
193
|
+
'S1_3_c7_c11_1':
|
|
194
|
+
- name: 'DC CVAU'
|
|
196
195
|
description: 'Data or unified Cache line Clean by VA to PoU'
|
|
197
|
-
S1_3_c7_c12_1:
|
|
198
|
-
|
|
196
|
+
'S1_3_c7_c12_1':
|
|
197
|
+
- name: 'DC CVAP'
|
|
199
198
|
description: 'Data or unified Cache line Clean by VA to PoP'
|
|
200
|
-
S1_3_c7_c12_3:
|
|
201
|
-
|
|
199
|
+
'S1_3_c7_c12_3':
|
|
200
|
+
- name: 'DC CGVAP'
|
|
202
201
|
description: 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoP'
|
|
203
|
-
S1_3_c7_c12_5:
|
|
204
|
-
|
|
202
|
+
'S1_3_c7_c12_5':
|
|
203
|
+
- name: 'DC CGDVAP'
|
|
205
204
|
description: 'Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by VA to PoP'
|
|
206
|
-
S1_3_c7_c13_1:
|
|
207
|
-
|
|
205
|
+
'S1_3_c7_c13_1':
|
|
206
|
+
- name: 'DC CVADP'
|
|
208
207
|
description: 'Data or unified Cache line Clean by VA to PoDP'
|
|
209
|
-
S1_3_c7_c13_3:
|
|
210
|
-
|
|
208
|
+
'S1_3_c7_c13_3':
|
|
209
|
+
- name: 'DC CGVADP'
|
|
211
210
|
description: 'Clean of Allocation Tags by VA to PoDP'
|
|
212
|
-
S1_3_c7_c13_5:
|
|
213
|
-
|
|
211
|
+
'S1_3_c7_c13_5':
|
|
212
|
+
- name: 'DC CGDVADP'
|
|
214
213
|
description: 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoDP'
|
|
215
|
-
S1_3_c7_c14_1:
|
|
216
|
-
|
|
214
|
+
'S1_3_c7_c14_1':
|
|
215
|
+
- name: 'DC CIVAC'
|
|
217
216
|
description: 'Data or unified Cache line Clean and Invalidate by VA to PoC'
|
|
218
|
-
S1_3_c7_c14_3:
|
|
219
|
-
|
|
217
|
+
'S1_3_c7_c14_3':
|
|
218
|
+
- name: 'DC CIGVAC'
|
|
220
219
|
description: 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by VA to PoC'
|
|
221
|
-
S1_3_c7_c14_5:
|
|
222
|
-
|
|
220
|
+
'S1_3_c7_c14_5':
|
|
221
|
+
- name: 'DC CIGDVAC'
|
|
223
222
|
description: 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by VA to PoC'
|
|
224
|
-
S1_4_c7_c8_0:
|
|
225
|
-
|
|
223
|
+
'S1_4_c7_c8_0':
|
|
224
|
+
- name: 'AT S1E2R'
|
|
226
225
|
description: 'Address Translate Stage 1 EL2 Read'
|
|
227
|
-
S1_4_c7_c8_1:
|
|
228
|
-
|
|
226
|
+
'S1_4_c7_c8_1':
|
|
227
|
+
- name: 'AT S1E2W'
|
|
229
228
|
description: 'Address Translate Stage 1 EL2 Write'
|
|
230
|
-
S1_4_c7_c8_4:
|
|
231
|
-
|
|
229
|
+
'S1_4_c7_c8_4':
|
|
230
|
+
- name: 'AT S12E1R'
|
|
232
231
|
description: 'Address Translate Stages 1 and 2 EL1 Read'
|
|
233
|
-
S1_4_c7_c8_5:
|
|
234
|
-
|
|
232
|
+
'S1_4_c7_c8_5':
|
|
233
|
+
- name: 'AT S12E1W'
|
|
235
234
|
description: 'Address Translate Stages 1 and 2 EL1 Write'
|
|
236
|
-
S1_4_c7_c8_6:
|
|
237
|
-
|
|
235
|
+
'S1_4_c7_c8_6':
|
|
236
|
+
- name: 'AT S12E0R'
|
|
238
237
|
description: 'Address Translate Stages 1 and 2 EL0 Read'
|
|
239
|
-
S1_4_c7_c8_7:
|
|
240
|
-
|
|
238
|
+
'S1_4_c7_c8_7':
|
|
239
|
+
- name: 'AT S12E0W'
|
|
241
240
|
description: 'Address Translate Stages 1 and 2 EL0 Write'
|
|
242
|
-
S1_4_c8_c0_1:
|
|
243
|
-
|
|
241
|
+
'S1_4_c8_c0_1':
|
|
242
|
+
- name: 'TLBI IPAS2E1IS'
|
|
244
243
|
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable'
|
|
245
|
-
S1_4_c8_c0_2:
|
|
246
|
-
|
|
244
|
+
'S1_4_c8_c0_2':
|
|
245
|
+
- name: 'TLBI RIPAS2E1IS'
|
|
247
246
|
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable'
|
|
248
|
-
S1_4_c8_c0_5:
|
|
249
|
-
|
|
247
|
+
'S1_4_c8_c0_5':
|
|
248
|
+
- name: 'TLBI IPAS2LE1IS'
|
|
250
249
|
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable'
|
|
251
|
-
S1_4_c8_c0_6:
|
|
252
|
-
|
|
250
|
+
'S1_4_c8_c0_6':
|
|
251
|
+
- name: 'TLBI RIPAS2LE1IS'
|
|
253
252
|
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable'
|
|
254
|
-
S1_4_c8_c1_0:
|
|
255
|
-
|
|
253
|
+
'S1_4_c8_c1_0':
|
|
254
|
+
- name: 'TLBI ALLE2OS'
|
|
256
255
|
description: 'TLB Invalidate All, EL2, Outer Shareable'
|
|
257
|
-
S1_4_c8_c1_1:
|
|
258
|
-
|
|
256
|
+
'S1_4_c8_c1_1':
|
|
257
|
+
- name: 'TLBI VAE2OS'
|
|
259
258
|
description: 'TLB Invalidate by VA, EL2, Outer Shareable'
|
|
260
|
-
S1_4_c8_c1_4:
|
|
261
|
-
|
|
259
|
+
'S1_4_c8_c1_4':
|
|
260
|
+
- name: 'TLBI ALLE1OS'
|
|
262
261
|
description: 'TLB Invalidate All, EL1, Outer Shareable'
|
|
263
|
-
S1_4_c8_c1_5:
|
|
264
|
-
|
|
262
|
+
'S1_4_c8_c1_5':
|
|
263
|
+
- name: 'TLBI VALE2OS'
|
|
265
264
|
description: 'TLB Invalidate by VA, Last level, EL2, Outer Shareable'
|
|
266
|
-
S1_4_c8_c1_6:
|
|
267
|
-
|
|
265
|
+
'S1_4_c8_c1_6':
|
|
266
|
+
- name: 'TLBI VMALLS12E1OS'
|
|
268
267
|
description: 'TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Outer Shareable'
|
|
269
|
-
S1_4_c8_c2_1:
|
|
270
|
-
|
|
268
|
+
'S1_4_c8_c2_1':
|
|
269
|
+
- name: 'TLBI RVAE2IS'
|
|
271
270
|
description: 'TLB Range Invalidate by VA, EL2, Inner Shareable'
|
|
272
|
-
S1_4_c8_c2_5:
|
|
273
|
-
|
|
271
|
+
'S1_4_c8_c2_5':
|
|
272
|
+
- name: 'TLBI RVALE2IS'
|
|
274
273
|
description: 'TLB Range Invalidate by VA, Last level, EL2, Inner Shareable'
|
|
275
|
-
S1_4_c8_c3_0:
|
|
276
|
-
|
|
274
|
+
'S1_4_c8_c3_0':
|
|
275
|
+
- name: 'TLBI ALLE2IS'
|
|
277
276
|
description: 'TLB Invalidate All, EL2, Inner Shareable'
|
|
278
|
-
S1_4_c8_c3_1:
|
|
279
|
-
|
|
277
|
+
'S1_4_c8_c3_1':
|
|
278
|
+
- name: 'TLBI VAE2IS'
|
|
280
279
|
description: 'TLB Invalidate by VA, EL2, Inner Shareable'
|
|
281
|
-
S1_4_c8_c3_4:
|
|
282
|
-
|
|
280
|
+
'S1_4_c8_c3_4':
|
|
281
|
+
- name: 'TLBI ALLE1IS'
|
|
283
282
|
description: 'TLB Invalidate All, EL1, Inner Shareable'
|
|
284
|
-
S1_4_c8_c3_5:
|
|
285
|
-
|
|
283
|
+
'S1_4_c8_c3_5':
|
|
284
|
+
- name: 'TLBI VALE2IS'
|
|
286
285
|
description: 'TLB Invalidate by VA, Last level, EL2, Inner Shareable'
|
|
287
|
-
S1_4_c8_c3_6:
|
|
288
|
-
|
|
286
|
+
'S1_4_c8_c3_6':
|
|
287
|
+
- name: 'TLBI VMALLS12E1IS'
|
|
289
288
|
description: 'TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable'
|
|
290
|
-
S1_4_c8_c4_0:
|
|
291
|
-
|
|
289
|
+
'S1_4_c8_c4_0':
|
|
290
|
+
- name: 'TLBI IPAS2E1OS'
|
|
292
291
|
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable'
|
|
293
|
-
S1_4_c8_c4_1:
|
|
294
|
-
|
|
292
|
+
'S1_4_c8_c4_1':
|
|
293
|
+
- name: 'TLBI IPAS2E1'
|
|
295
294
|
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, EL1'
|
|
296
|
-
S1_4_c8_c4_2:
|
|
297
|
-
|
|
295
|
+
'S1_4_c8_c4_2':
|
|
296
|
+
- name: 'TLBI RIPAS2E1'
|
|
298
297
|
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1'
|
|
299
|
-
S1_4_c8_c4_3:
|
|
300
|
-
|
|
298
|
+
'S1_4_c8_c4_3':
|
|
299
|
+
- name: 'TLBI RIPAS2E1OS'
|
|
301
300
|
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable'
|
|
302
|
-
S1_4_c8_c4_4:
|
|
303
|
-
|
|
301
|
+
'S1_4_c8_c4_4':
|
|
302
|
+
- name: 'TLBI IPAS2LE1OS'
|
|
304
303
|
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable'
|
|
305
|
-
S1_4_c8_c4_5:
|
|
306
|
-
|
|
304
|
+
'S1_4_c8_c4_5':
|
|
305
|
+
- name: 'TLBI IPAS2LE1'
|
|
307
306
|
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1'
|
|
308
|
-
S1_4_c8_c4_6:
|
|
309
|
-
|
|
307
|
+
'S1_4_c8_c4_6':
|
|
308
|
+
- name: 'TLBI RIPAS2LE1'
|
|
310
309
|
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1'
|
|
311
|
-
S1_4_c8_c4_7:
|
|
312
|
-
|
|
310
|
+
'S1_4_c8_c4_7':
|
|
311
|
+
- name: 'TLBI RIPAS2LE1OS'
|
|
313
312
|
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable'
|
|
314
|
-
S1_4_c8_c5_1:
|
|
315
|
-
|
|
313
|
+
'S1_4_c8_c5_1':
|
|
314
|
+
- name: 'TLBI RVAE2OS'
|
|
316
315
|
description: 'TLB Range Invalidate by VA, EL2, Outer Shareable'
|
|
317
|
-
S1_4_c8_c5_5:
|
|
318
|
-
|
|
316
|
+
'S1_4_c8_c5_5':
|
|
317
|
+
- name: 'TLBI RVALE2OS'
|
|
319
318
|
description: 'TLB Range Invalidate by VA, Last level, EL2, Outer Shareable'
|
|
320
|
-
S1_4_c8_c6_1:
|
|
321
|
-
|
|
319
|
+
'S1_4_c8_c6_1':
|
|
320
|
+
- name: 'TLBI RVAE2'
|
|
322
321
|
description: 'TLB Range Invalidate by VA, EL2'
|
|
323
|
-
S1_4_c8_c6_5:
|
|
324
|
-
|
|
322
|
+
'S1_4_c8_c6_5':
|
|
323
|
+
- name: 'TLBI RVALE2'
|
|
325
324
|
description: 'TLB Range Invalidate by VA, Last level, EL2'
|
|
326
|
-
S1_4_c8_c7_0:
|
|
327
|
-
|
|
325
|
+
'S1_4_c8_c7_0':
|
|
326
|
+
- name: 'TLBI ALLE2'
|
|
328
327
|
description: 'TLB Invalidate All, EL2'
|
|
329
|
-
S1_4_c8_c7_1:
|
|
330
|
-
|
|
328
|
+
'S1_4_c8_c7_1':
|
|
329
|
+
- name: 'TLBI VAE2'
|
|
331
330
|
description: 'TLB Invalidate by VA, EL2'
|
|
332
|
-
S1_4_c8_c7_4:
|
|
333
|
-
|
|
331
|
+
'S1_4_c8_c7_4':
|
|
332
|
+
- name: 'TLBI ALLE1'
|
|
334
333
|
description: 'TLB Invalidate All, EL1'
|
|
335
|
-
S1_4_c8_c7_5:
|
|
336
|
-
|
|
334
|
+
'S1_4_c8_c7_5':
|
|
335
|
+
- name: 'TLBI VALE2'
|
|
337
336
|
description: 'TLB Invalidate by VA, Last level, EL2'
|
|
338
|
-
S1_4_c8_c7_6:
|
|
339
|
-
|
|
337
|
+
'S1_4_c8_c7_6':
|
|
338
|
+
- name: 'TLBI VMALLS12E1'
|
|
340
339
|
description: 'TLB Invalidate by VMID, All at Stage 1 and 2, EL1'
|
|
341
|
-
S1_6_c7_c8_0:
|
|
342
|
-
|
|
340
|
+
'S1_6_c7_c8_0':
|
|
341
|
+
- name: 'AT S1E3R'
|
|
343
342
|
description: 'Address Translate Stage 1 EL3 Read'
|
|
344
|
-
S1_6_c7_c8_1:
|
|
345
|
-
|
|
343
|
+
'S1_6_c7_c8_1':
|
|
344
|
+
- name: 'AT S1E3W'
|
|
346
345
|
description: 'Address Translate Stage 1 EL3 Write'
|
|
347
|
-
S1_6_c8_c1_0:
|
|
348
|
-
|
|
346
|
+
'S1_6_c8_c1_0':
|
|
347
|
+
- name: 'TLBI ALLE3OS'
|
|
349
348
|
description: 'TLB Invalidate All, EL3, Outer Shareable'
|
|
350
|
-
S1_6_c8_c1_1:
|
|
351
|
-
|
|
349
|
+
'S1_6_c8_c1_1':
|
|
350
|
+
- name: 'TLBI VAE3OS'
|
|
352
351
|
description: 'TLB Invalidate by VA, EL3, Outer Shareable'
|
|
353
|
-
S1_6_c8_c1_5:
|
|
354
|
-
|
|
352
|
+
'S1_6_c8_c1_5':
|
|
353
|
+
- name: 'TLBI VALE3OS'
|
|
355
354
|
description: 'TLB Invalidate by VA, Last level, EL3, Outer Shareable'
|
|
356
|
-
S1_6_c8_c2_1:
|
|
357
|
-
|
|
355
|
+
'S1_6_c8_c2_1':
|
|
356
|
+
- name: 'TLBI RVAE3IS'
|
|
358
357
|
description: 'TLB Range Invalidate by VA, EL3, Inner Shareable'
|
|
359
|
-
S1_6_c8_c2_5:
|
|
360
|
-
|
|
358
|
+
'S1_6_c8_c2_5':
|
|
359
|
+
- name: 'TLBI RVALE3IS'
|
|
361
360
|
description: 'TLB Range Invalidate by VA, Last level, EL3, Inner Shareable'
|
|
362
|
-
S1_6_c8_c3_0:
|
|
363
|
-
|
|
361
|
+
'S1_6_c8_c3_0':
|
|
362
|
+
- name: 'TLBI ALLE3IS'
|
|
364
363
|
description: 'TLB Invalidate All, EL3, Inner Shareable'
|
|
365
|
-
S1_6_c8_c3_1:
|
|
366
|
-
|
|
364
|
+
'S1_6_c8_c3_1':
|
|
365
|
+
- name: 'TLBI VAE3IS'
|
|
367
366
|
description: 'TLB Invalidate by VA, EL3, Inner Shareable'
|
|
368
|
-
S1_6_c8_c3_5:
|
|
369
|
-
|
|
367
|
+
'S1_6_c8_c3_5':
|
|
368
|
+
- name: 'TLBI VALE3IS'
|
|
370
369
|
description: 'TLB Invalidate by VA, Last level, EL3, Inner Shareable'
|
|
371
|
-
S1_6_c8_c5_1:
|
|
372
|
-
|
|
370
|
+
'S1_6_c8_c5_1':
|
|
371
|
+
- name: 'TLBI RVAE3OS'
|
|
373
372
|
description: 'TLB Range Invalidate by VA, EL3, Outer Shareable'
|
|
374
|
-
S1_6_c8_c5_5:
|
|
375
|
-
|
|
373
|
+
'S1_6_c8_c5_5':
|
|
374
|
+
- name: 'TLBI RVALE3OS'
|
|
376
375
|
description: 'TLB Range Invalidate by VA, Last level, EL3, Outer Shareable'
|
|
377
|
-
S1_6_c8_c6_1:
|
|
378
|
-
|
|
376
|
+
'S1_6_c8_c6_1':
|
|
377
|
+
- name: 'TLBI RVAE3'
|
|
379
378
|
description: 'TLB Range Invalidate by VA, EL3'
|
|
380
|
-
S1_6_c8_c6_5:
|
|
381
|
-
|
|
379
|
+
'S1_6_c8_c6_5':
|
|
380
|
+
- name: 'TLBI RVALE3'
|
|
382
381
|
description: 'TLB Range Invalidate by VA, Last level, EL3'
|
|
383
|
-
S1_6_c8_c7_0:
|
|
384
|
-
|
|
382
|
+
'S1_6_c8_c7_0':
|
|
383
|
+
- name: 'TLBI ALLE3'
|
|
385
384
|
description: 'TLB Invalidate All, EL3'
|
|
386
|
-
S1_6_c8_c7_1:
|
|
387
|
-
|
|
385
|
+
'S1_6_c8_c7_1':
|
|
386
|
+
- name: 'TLBI VAE3'
|
|
388
387
|
description: 'TLB Invalidate by VA, EL3'
|
|
389
|
-
S1_6_c8_c7_5:
|
|
390
|
-
|
|
388
|
+
'S1_6_c8_c7_5':
|
|
389
|
+
- name: 'TLBI VALE3'
|
|
391
390
|
description: 'TLB Invalidate by VA, Last level, EL3'
|
|
392
|
-
S2_0_c0_c0_2:
|
|
393
|
-
|
|
391
|
+
'S2_0_c0_c0_2':
|
|
392
|
+
- name: 'OSDTRRX_EL1'
|
|
394
393
|
description: 'OS Lock Data Transfer Register, Receive'
|
|
395
|
-
S2_0_c0_c0_4:
|
|
396
|
-
|
|
394
|
+
'S2_0_c0_c0_4':
|
|
395
|
+
- name: 'DBGBVR0_EL1'
|
|
397
396
|
description: 'Debug Breakpoint Value Register 0'
|
|
398
|
-
S2_0_c0_c0_5:
|
|
399
|
-
|
|
397
|
+
'S2_0_c0_c0_5':
|
|
398
|
+
- name: 'DBGBCR0_EL1'
|
|
400
399
|
description: 'Debug Breakpoint Control Register 0'
|
|
401
|
-
S2_0_c0_c0_6:
|
|
402
|
-
|
|
400
|
+
'S2_0_c0_c0_6':
|
|
401
|
+
- name: 'DBGWVR0_EL1'
|
|
403
402
|
description: 'Debug Watchpoint Value Register 0'
|
|
404
|
-
S2_0_c0_c0_7:
|
|
405
|
-
|
|
403
|
+
'S2_0_c0_c0_7':
|
|
404
|
+
- name: 'DBGWCR0_EL1'
|
|
406
405
|
description: 'Debug Watchpoint Control Register 0'
|
|
407
|
-
S2_0_c0_c1_4:
|
|
408
|
-
|
|
406
|
+
'S2_0_c0_c1_4':
|
|
407
|
+
- name: 'DBGBVR1_EL1'
|
|
409
408
|
description: 'Debug Breakpoint Value Register 1'
|
|
410
|
-
S2_0_c0_c1_5:
|
|
411
|
-
|
|
409
|
+
'S2_0_c0_c1_5':
|
|
410
|
+
- name: 'DBGBCR1_EL1'
|
|
412
411
|
description: 'Debug Breakpoint Control Register 1'
|
|
413
|
-
S2_0_c0_c1_6:
|
|
414
|
-
|
|
412
|
+
'S2_0_c0_c1_6':
|
|
413
|
+
- name: 'DBGWVR1_EL1'
|
|
415
414
|
description: 'Debug Watchpoint Value Register 1'
|
|
416
|
-
S2_0_c0_c1_7:
|
|
417
|
-
|
|
415
|
+
'S2_0_c0_c1_7':
|
|
416
|
+
- name: 'DBGWCR1_EL1'
|
|
418
417
|
description: 'Debug Watchpoint Control Register 1'
|
|
419
|
-
S2_0_c0_c2_0:
|
|
420
|
-
|
|
418
|
+
'S2_0_c0_c2_0':
|
|
419
|
+
- name: 'MDCCINT_EL1'
|
|
421
420
|
description: 'Monitor DCC Interrupt Enable Register'
|
|
422
|
-
S2_0_c0_c2_2:
|
|
423
|
-
|
|
421
|
+
'S2_0_c0_c2_2':
|
|
422
|
+
- name: 'MDSCR_EL1'
|
|
424
423
|
description: 'Monitor Debug System Control Register'
|
|
425
|
-
S2_0_c0_c2_4:
|
|
426
|
-
|
|
424
|
+
'S2_0_c0_c2_4':
|
|
425
|
+
- name: 'DBGBVR2_EL1'
|
|
427
426
|
description: 'Debug Breakpoint Value Register 2'
|
|
428
|
-
S2_0_c0_c2_5:
|
|
429
|
-
|
|
427
|
+
'S2_0_c0_c2_5':
|
|
428
|
+
- name: 'DBGBCR2_EL1'
|
|
430
429
|
description: 'Debug Breakpoint Control Register 2'
|
|
431
|
-
S2_0_c0_c2_6:
|
|
432
|
-
|
|
430
|
+
'S2_0_c0_c2_6':
|
|
431
|
+
- name: 'DBGWVR2_EL1'
|
|
433
432
|
description: 'Debug Watchpoint Value Register 2'
|
|
434
|
-
S2_0_c0_c2_7:
|
|
435
|
-
|
|
433
|
+
'S2_0_c0_c2_7':
|
|
434
|
+
- name: 'DBGWCR2_EL1'
|
|
436
435
|
description: 'Debug Watchpoint Control Register 2'
|
|
437
|
-
S2_0_c0_c3_2:
|
|
438
|
-
|
|
436
|
+
'S2_0_c0_c3_2':
|
|
437
|
+
- name: 'OSDTRTX_EL1'
|
|
439
438
|
description: 'OS Lock Data Transfer Register, Transmit'
|
|
440
|
-
S2_0_c0_c3_4:
|
|
441
|
-
|
|
439
|
+
'S2_0_c0_c3_4':
|
|
440
|
+
- name: 'DBGBVR3_EL1'
|
|
442
441
|
description: 'Debug Breakpoint Value Register 3'
|
|
443
|
-
S2_0_c0_c3_5:
|
|
444
|
-
|
|
442
|
+
'S2_0_c0_c3_5':
|
|
443
|
+
- name: 'DBGBCR3_EL1'
|
|
445
444
|
description: 'Debug Breakpoint Control Register 3'
|
|
446
|
-
S2_0_c0_c3_6:
|
|
447
|
-
|
|
445
|
+
'S2_0_c0_c3_6':
|
|
446
|
+
- name: 'DBGWVR3_EL1'
|
|
448
447
|
description: 'Debug Watchpoint Value Register 3'
|
|
449
|
-
S2_0_c0_c3_7:
|
|
450
|
-
|
|
448
|
+
'S2_0_c0_c3_7':
|
|
449
|
+
- name: 'DBGWCR3_EL1'
|
|
451
450
|
description: 'Debug Watchpoint Control Register 3'
|
|
452
|
-
S2_0_c0_c4_4:
|
|
453
|
-
|
|
451
|
+
'S2_0_c0_c4_4':
|
|
452
|
+
- name: 'DBGBVR4_EL1'
|
|
454
453
|
description: 'Debug Breakpoint Value Register 4'
|
|
455
|
-
S2_0_c0_c4_5:
|
|
456
|
-
|
|
454
|
+
'S2_0_c0_c4_5':
|
|
455
|
+
- name: 'DBGBCR4_EL1'
|
|
457
456
|
description: 'Debug Breakpoint Control Register 4'
|
|
458
|
-
S2_0_c0_c4_6:
|
|
459
|
-
|
|
457
|
+
'S2_0_c0_c4_6':
|
|
458
|
+
- name: 'DBGWVR4_EL1'
|
|
460
459
|
description: 'Debug Watchpoint Value Register 4'
|
|
461
|
-
S2_0_c0_c4_7:
|
|
462
|
-
|
|
460
|
+
'S2_0_c0_c4_7':
|
|
461
|
+
- name: 'DBGWCR4_EL1'
|
|
463
462
|
description: 'Debug Watchpoint Control Register 4'
|
|
464
|
-
S2_0_c0_c5_4:
|
|
465
|
-
|
|
463
|
+
'S2_0_c0_c5_4':
|
|
464
|
+
- name: 'DBGBVR5_EL1'
|
|
466
465
|
description: 'Debug Breakpoint Value Register 5'
|
|
467
|
-
S2_0_c0_c5_5:
|
|
468
|
-
|
|
466
|
+
'S2_0_c0_c5_5':
|
|
467
|
+
- name: 'DBGBCR5_EL1'
|
|
469
468
|
description: 'Debug Breakpoint Control Register 5'
|
|
470
|
-
S2_0_c0_c5_6:
|
|
471
|
-
|
|
469
|
+
'S2_0_c0_c5_6':
|
|
470
|
+
- name: 'DBGWVR5_EL1'
|
|
472
471
|
description: 'Debug Watchpoint Value Register 5'
|
|
473
|
-
S2_0_c0_c5_7:
|
|
474
|
-
|
|
472
|
+
'S2_0_c0_c5_7':
|
|
473
|
+
- name: 'DBGWCR5_EL1'
|
|
475
474
|
description: 'Debug Watchpoint Control Register 5'
|
|
476
|
-
S2_0_c0_c6_2:
|
|
477
|
-
|
|
475
|
+
'S2_0_c0_c6_2':
|
|
476
|
+
- name: 'OSECCR_EL1'
|
|
478
477
|
description: 'OS Lock Exception Catch Control Register'
|
|
479
|
-
S2_0_c0_c6_4:
|
|
480
|
-
|
|
478
|
+
'S2_0_c0_c6_4':
|
|
479
|
+
- name: 'DBGBVR6_EL1'
|
|
481
480
|
description: 'Debug Breakpoint Value Register 6'
|
|
482
|
-
S2_0_c0_c6_5:
|
|
483
|
-
|
|
481
|
+
'S2_0_c0_c6_5':
|
|
482
|
+
- name: 'DBGBCR6_EL1'
|
|
484
483
|
description: 'Debug Breakpoint Control Register 6'
|
|
485
|
-
S2_0_c0_c6_6:
|
|
486
|
-
|
|
484
|
+
'S2_0_c0_c6_6':
|
|
485
|
+
- name: 'DBGWVR6_EL1'
|
|
487
486
|
description: 'Debug Watchpoint Value Register 6'
|
|
488
|
-
S2_0_c0_c6_7:
|
|
489
|
-
|
|
487
|
+
'S2_0_c0_c6_7':
|
|
488
|
+
- name: 'DBGWCR6_EL1'
|
|
490
489
|
description: 'Debug Watchpoint Control Register 6'
|
|
491
|
-
S2_0_c0_c7_4:
|
|
492
|
-
|
|
490
|
+
'S2_0_c0_c7_4':
|
|
491
|
+
- name: 'DBGBVR7_EL1'
|
|
493
492
|
description: 'Debug Breakpoint Value Register 7'
|
|
494
|
-
S2_0_c0_c7_5:
|
|
495
|
-
|
|
493
|
+
'S2_0_c0_c7_5':
|
|
494
|
+
- name: 'DBGBCR7_EL1'
|
|
496
495
|
description: 'Debug Breakpoint Control Register 7'
|
|
497
|
-
S2_0_c0_c7_6:
|
|
498
|
-
|
|
496
|
+
'S2_0_c0_c7_6':
|
|
497
|
+
- name: 'DBGWVR7_EL1'
|
|
499
498
|
description: 'Debug Watchpoint Value Register 7'
|
|
500
|
-
S2_0_c0_c7_7:
|
|
501
|
-
|
|
499
|
+
'S2_0_c0_c7_7':
|
|
500
|
+
- name: 'DBGWCR7_EL1'
|
|
502
501
|
description: 'Debug Watchpoint Control Register 7'
|
|
503
|
-
S2_0_c0_c8_4:
|
|
504
|
-
|
|
502
|
+
'S2_0_c0_c8_4':
|
|
503
|
+
- name: 'DBGBVR8_EL1'
|
|
505
504
|
description: 'Debug Breakpoint Value Register 8'
|
|
506
|
-
S2_0_c0_c8_5:
|
|
507
|
-
|
|
505
|
+
'S2_0_c0_c8_5':
|
|
506
|
+
- name: 'DBGBCR8_EL1'
|
|
508
507
|
description: 'Debug Breakpoint Control Register 8'
|
|
509
|
-
S2_0_c0_c8_6:
|
|
510
|
-
|
|
508
|
+
'S2_0_c0_c8_6':
|
|
509
|
+
- name: 'DBGWVR8_EL1'
|
|
511
510
|
description: 'Debug Watchpoint Value Register 8'
|
|
512
|
-
S2_0_c0_c8_7:
|
|
513
|
-
|
|
511
|
+
'S2_0_c0_c8_7':
|
|
512
|
+
- name: 'DBGWCR8_EL1'
|
|
514
513
|
description: 'Debug Watchpoint Control Register 8'
|
|
515
|
-
S2_0_c0_c9_4:
|
|
516
|
-
|
|
514
|
+
'S2_0_c0_c9_4':
|
|
515
|
+
- name: 'DBGBVR9_EL1'
|
|
517
516
|
description: 'Debug Breakpoint Value Register 9'
|
|
518
|
-
S2_0_c0_c9_5:
|
|
519
|
-
|
|
517
|
+
'S2_0_c0_c9_5':
|
|
518
|
+
- name: 'DBGBCR9_EL1'
|
|
520
519
|
description: 'Debug Breakpoint Control Register 9'
|
|
521
|
-
S2_0_c0_c9_6:
|
|
522
|
-
|
|
520
|
+
'S2_0_c0_c9_6':
|
|
521
|
+
- name: 'DBGWVR9_EL1'
|
|
523
522
|
description: 'Debug Watchpoint Value Register 9'
|
|
524
|
-
S2_0_c0_c9_7:
|
|
525
|
-
|
|
523
|
+
'S2_0_c0_c9_7':
|
|
524
|
+
- name: 'DBGWCR9_EL1'
|
|
526
525
|
description: 'Debug Watchpoint Control Register 9'
|
|
527
|
-
S2_0_c0_c10_4:
|
|
528
|
-
|
|
526
|
+
'S2_0_c0_c10_4':
|
|
527
|
+
- name: 'DBGBVR10_EL1'
|
|
529
528
|
description: 'Debug Breakpoint Value Register 10'
|
|
530
|
-
S2_0_c0_c10_5:
|
|
531
|
-
|
|
529
|
+
'S2_0_c0_c10_5':
|
|
530
|
+
- name: 'DBGBCR10_EL1'
|
|
532
531
|
description: 'Debug Breakpoint Control Register 10'
|
|
533
|
-
S2_0_c0_c10_6:
|
|
534
|
-
|
|
532
|
+
'S2_0_c0_c10_6':
|
|
533
|
+
- name: 'DBGWVR10_EL1'
|
|
535
534
|
description: 'Debug Watchpoint Value Register 10'
|
|
536
|
-
S2_0_c0_c10_7:
|
|
537
|
-
|
|
535
|
+
'S2_0_c0_c10_7':
|
|
536
|
+
- name: 'DBGWCR10_EL1'
|
|
538
537
|
description: 'Debug Watchpoint Control Register 10'
|
|
539
|
-
S2_0_c0_c11_4:
|
|
540
|
-
|
|
538
|
+
'S2_0_c0_c11_4':
|
|
539
|
+
- name: 'DBGBVR11_EL1'
|
|
541
540
|
description: 'Debug Breakpoint Value Register 11'
|
|
542
|
-
S2_0_c0_c11_5:
|
|
543
|
-
|
|
541
|
+
'S2_0_c0_c11_5':
|
|
542
|
+
- name: 'DBGBCR11_EL1'
|
|
544
543
|
description: 'Debug Breakpoint Control Register 11'
|
|
545
|
-
S2_0_c0_c11_6:
|
|
546
|
-
|
|
544
|
+
'S2_0_c0_c11_6':
|
|
545
|
+
- name: 'DBGWVR11_EL1'
|
|
547
546
|
description: 'Debug Watchpoint Value Register 11'
|
|
548
|
-
S2_0_c0_c11_7:
|
|
549
|
-
|
|
547
|
+
'S2_0_c0_c11_7':
|
|
548
|
+
- name: 'DBGWCR11_EL1'
|
|
550
549
|
description: 'Debug Watchpoint Control Register 11'
|
|
551
|
-
S2_0_c0_c12_4:
|
|
552
|
-
|
|
550
|
+
'S2_0_c0_c12_4':
|
|
551
|
+
- name: 'DBGBVR12_EL1'
|
|
553
552
|
description: 'Debug Breakpoint Value Register 12'
|
|
554
|
-
S2_0_c0_c12_5:
|
|
555
|
-
|
|
553
|
+
'S2_0_c0_c12_5':
|
|
554
|
+
- name: 'DBGBCR12_EL1'
|
|
556
555
|
description: 'Debug Breakpoint Control Register 12'
|
|
557
|
-
S2_0_c0_c12_6:
|
|
558
|
-
|
|
556
|
+
'S2_0_c0_c12_6':
|
|
557
|
+
- name: 'DBGWVR12_EL1'
|
|
559
558
|
description: 'Debug Watchpoint Value Register 12'
|
|
560
|
-
S2_0_c0_c12_7:
|
|
561
|
-
|
|
559
|
+
'S2_0_c0_c12_7':
|
|
560
|
+
- name: 'DBGWCR12_EL1'
|
|
562
561
|
description: 'Debug Watchpoint Control Register 12'
|
|
563
|
-
S2_0_c0_c13_4:
|
|
564
|
-
|
|
562
|
+
'S2_0_c0_c13_4':
|
|
563
|
+
- name: 'DBGBVR13_EL1'
|
|
565
564
|
description: 'Debug Breakpoint Value Register 13'
|
|
566
|
-
S2_0_c0_c13_5:
|
|
567
|
-
|
|
565
|
+
'S2_0_c0_c13_5':
|
|
566
|
+
- name: 'DBGBCR13_EL1'
|
|
568
567
|
description: 'Debug Breakpoint Control Register 13'
|
|
569
|
-
S2_0_c0_c13_6:
|
|
570
|
-
|
|
568
|
+
'S2_0_c0_c13_6':
|
|
569
|
+
- name: 'DBGWVR13_EL1'
|
|
571
570
|
description: 'Debug Watchpoint Value Register 13'
|
|
572
|
-
S2_0_c0_c13_7:
|
|
573
|
-
|
|
571
|
+
'S2_0_c0_c13_7':
|
|
572
|
+
- name: 'DBGWCR13_EL1'
|
|
574
573
|
description: 'Debug Watchpoint Control Register 13'
|
|
575
|
-
S2_0_c0_c14_4:
|
|
576
|
-
|
|
574
|
+
'S2_0_c0_c14_4':
|
|
575
|
+
- name: 'DBGBVR14_EL1'
|
|
577
576
|
description: 'Debug Breakpoint Value Register 14'
|
|
578
|
-
S2_0_c0_c14_5:
|
|
579
|
-
|
|
577
|
+
'S2_0_c0_c14_5':
|
|
578
|
+
- name: 'DBGBCR14_EL1'
|
|
580
579
|
description: 'Debug Breakpoint Control Register 14'
|
|
581
|
-
S2_0_c0_c14_6:
|
|
582
|
-
|
|
580
|
+
'S2_0_c0_c14_6':
|
|
581
|
+
- name: 'DBGWVR14_EL1'
|
|
583
582
|
description: 'Debug Watchpoint Value Register 14'
|
|
584
|
-
S2_0_c0_c14_7:
|
|
585
|
-
|
|
583
|
+
'S2_0_c0_c14_7':
|
|
584
|
+
- name: 'DBGWCR14_EL1'
|
|
586
585
|
description: 'Debug Watchpoint Control Register 14'
|
|
587
|
-
S2_0_c0_c15_4:
|
|
588
|
-
|
|
586
|
+
'S2_0_c0_c15_4':
|
|
587
|
+
- name: 'DBGBVR15_EL1'
|
|
589
588
|
description: 'Debug Breakpoint Value Register 15'
|
|
590
|
-
S2_0_c0_c15_5:
|
|
591
|
-
|
|
589
|
+
'S2_0_c0_c15_5':
|
|
590
|
+
- name: 'DBGBCR15_EL1'
|
|
592
591
|
description: 'Debug Breakpoint Control Register 15'
|
|
593
|
-
S2_0_c0_c15_6:
|
|
594
|
-
|
|
592
|
+
'S2_0_c0_c15_6':
|
|
593
|
+
- name: 'DBGWVR15_EL1'
|
|
595
594
|
description: 'Debug Watchpoint Value Register 15'
|
|
596
|
-
S2_0_c0_c15_7:
|
|
597
|
-
|
|
595
|
+
'S2_0_c0_c15_7':
|
|
596
|
+
- name: 'DBGWCR15_EL1'
|
|
598
597
|
description: 'Debug Watchpoint Control Register 15'
|
|
599
|
-
S2_0_c1_c0_0:
|
|
600
|
-
|
|
598
|
+
'S2_0_c1_c0_0':
|
|
599
|
+
- name: 'MDRAR_EL1'
|
|
601
600
|
description: 'Monitor Debug ROM Address Register'
|
|
602
|
-
S2_0_c1_c0_4:
|
|
603
|
-
|
|
601
|
+
'S2_0_c1_c0_4':
|
|
602
|
+
- name: 'OSLAR_EL1'
|
|
604
603
|
description: 'OS Lock Access Register'
|
|
605
|
-
S2_0_c1_c1_4:
|
|
606
|
-
|
|
604
|
+
'S2_0_c1_c1_4':
|
|
605
|
+
- name: 'OSLSR_EL1'
|
|
607
606
|
description: 'OS Lock Status Register'
|
|
608
|
-
S2_0_c1_c3_4:
|
|
609
|
-
|
|
607
|
+
'S2_0_c1_c3_4':
|
|
608
|
+
- name: 'OSDLR_EL1'
|
|
610
609
|
description: 'OS Double Lock Register'
|
|
611
|
-
S2_0_c1_c4_4:
|
|
612
|
-
|
|
610
|
+
'S2_0_c1_c4_4':
|
|
611
|
+
- name: 'DBGPRCR_EL1'
|
|
613
612
|
description: 'Debug Power Control Register'
|
|
614
|
-
S2_0_c7_c8_6:
|
|
615
|
-
|
|
613
|
+
'S2_0_c7_c8_6':
|
|
614
|
+
- name: 'DBGCLAIMSET_EL1'
|
|
616
615
|
description: 'Debug CLAIM Tag Set register'
|
|
617
|
-
S2_0_c7_c9_6:
|
|
618
|
-
|
|
616
|
+
'S2_0_c7_c9_6':
|
|
617
|
+
- name: 'DBGCLAIMCLR_EL1'
|
|
619
618
|
description: 'Debug CLAIM Tag Clear register'
|
|
620
|
-
S2_0_c7_c14_6:
|
|
621
|
-
|
|
619
|
+
'S2_0_c7_c14_6':
|
|
620
|
+
- name: 'DBGAUTHSTATUS_EL1'
|
|
622
621
|
description: 'Debug Authentication Status register'
|
|
623
|
-
S2_3_c0_c1_0:
|
|
624
|
-
|
|
622
|
+
'S2_3_c0_c1_0':
|
|
623
|
+
- name: 'MDCCSR_EL0'
|
|
625
624
|
description: 'Monitor DCC Status Register'
|
|
626
|
-
S2_3_c0_c4_0:
|
|
627
|
-
|
|
625
|
+
'S2_3_c0_c4_0':
|
|
626
|
+
- name: 'DBGDTR_EL0'
|
|
628
627
|
description: 'Debug Data Transfer Register, half-duplex'
|
|
629
|
-
S2_3_c0_c5_0:
|
|
630
|
-
|
|
631
|
-
description: 'Debug Data Transfer Register'
|
|
632
|
-
|
|
633
|
-
|
|
628
|
+
'S2_3_c0_c5_0':
|
|
629
|
+
- name: 'DBGDTRRX_EL0'
|
|
630
|
+
description: 'Debug Data Transfer Register, Receive'
|
|
631
|
+
- name: 'DBGDTRTX_EL0'
|
|
632
|
+
description: 'Debug Data Transfer Register, Transmit'
|
|
633
|
+
'S2_4_c0_c7_0':
|
|
634
|
+
- name: 'DBGVCR32_EL2'
|
|
634
635
|
description: 'Debug Vector Catch Register'
|
|
635
|
-
S3_0_c0_c0_0:
|
|
636
|
-
|
|
636
|
+
'S3_0_c0_c0_0':
|
|
637
|
+
- name: 'MIDR_EL1'
|
|
637
638
|
description: 'Main ID Register'
|
|
638
|
-
S3_0_c0_c0_5:
|
|
639
|
-
|
|
639
|
+
'S3_0_c0_c0_5':
|
|
640
|
+
- name: 'MPIDR_EL1'
|
|
640
641
|
description: 'Multiprocessor Affinity Register'
|
|
641
|
-
S3_0_c0_c0_6:
|
|
642
|
-
|
|
642
|
+
'S3_0_c0_c0_6':
|
|
643
|
+
- name: 'REVIDR_EL1'
|
|
643
644
|
description: 'Revision ID Register'
|
|
644
|
-
S3_0_c0_c1_0:
|
|
645
|
-
|
|
645
|
+
'S3_0_c0_c1_0':
|
|
646
|
+
- name: 'ID_PFR0_EL1'
|
|
646
647
|
description: 'AArch32 Processor Feature Register 0'
|
|
647
|
-
S3_0_c0_c1_1:
|
|
648
|
-
|
|
648
|
+
'S3_0_c0_c1_1':
|
|
649
|
+
- name: 'ID_PFR1_EL1'
|
|
649
650
|
description: 'AArch32 Processor Feature Register 1'
|
|
650
|
-
S3_0_c0_c1_2:
|
|
651
|
-
|
|
651
|
+
'S3_0_c0_c1_2':
|
|
652
|
+
- name: 'ID_DFR0_EL1'
|
|
652
653
|
description: 'AArch32 Debug Feature Register 0'
|
|
653
|
-
S3_0_c0_c1_3:
|
|
654
|
-
|
|
654
|
+
'S3_0_c0_c1_3':
|
|
655
|
+
- name: 'ID_AFR0_EL1'
|
|
655
656
|
description: 'AArch32 Auxiliary Feature Register 0'
|
|
656
|
-
S3_0_c0_c1_4:
|
|
657
|
-
|
|
657
|
+
'S3_0_c0_c1_4':
|
|
658
|
+
- name: 'ID_MMFR0_EL1'
|
|
658
659
|
description: 'AArch32 Memory Model Feature Register 0'
|
|
659
|
-
S3_0_c0_c1_5:
|
|
660
|
-
|
|
660
|
+
'S3_0_c0_c1_5':
|
|
661
|
+
- name: 'ID_MMFR1_EL1'
|
|
661
662
|
description: 'AArch32 Memory Model Feature Register 1'
|
|
662
|
-
S3_0_c0_c1_6:
|
|
663
|
-
|
|
663
|
+
'S3_0_c0_c1_6':
|
|
664
|
+
- name: 'ID_MMFR2_EL1'
|
|
664
665
|
description: 'AArch32 Memory Model Feature Register 2'
|
|
665
|
-
S3_0_c0_c1_7:
|
|
666
|
-
|
|
666
|
+
'S3_0_c0_c1_7':
|
|
667
|
+
- name: 'ID_MMFR3_EL1'
|
|
667
668
|
description: 'AArch32 Memory Model Feature Register 3'
|
|
668
|
-
S3_0_c0_c2_0:
|
|
669
|
-
|
|
669
|
+
'S3_0_c0_c2_0':
|
|
670
|
+
- name: 'ID_ISAR0_EL1'
|
|
670
671
|
description: 'AArch32 Instruction Set Attribute Register 0'
|
|
671
|
-
S3_0_c0_c2_1:
|
|
672
|
-
|
|
672
|
+
'S3_0_c0_c2_1':
|
|
673
|
+
- name: 'ID_ISAR1_EL1'
|
|
673
674
|
description: 'AArch32 Instruction Set Attribute Register 1'
|
|
674
|
-
S3_0_c0_c2_2:
|
|
675
|
-
|
|
675
|
+
'S3_0_c0_c2_2':
|
|
676
|
+
- name: 'ID_ISAR2_EL1'
|
|
676
677
|
description: 'AArch32 Instruction Set Attribute Register 2'
|
|
677
|
-
S3_0_c0_c2_3:
|
|
678
|
-
|
|
678
|
+
'S3_0_c0_c2_3':
|
|
679
|
+
- name: 'ID_ISAR3_EL1'
|
|
679
680
|
description: 'AArch32 Instruction Set Attribute Register 3'
|
|
680
|
-
S3_0_c0_c2_4:
|
|
681
|
-
|
|
681
|
+
'S3_0_c0_c2_4':
|
|
682
|
+
- name: 'ID_ISAR4_EL1'
|
|
682
683
|
description: 'AArch32 Instruction Set Attribute Register 4'
|
|
683
|
-
S3_0_c0_c2_5:
|
|
684
|
-
|
|
684
|
+
'S3_0_c0_c2_5':
|
|
685
|
+
- name: 'ID_ISAR5_EL1'
|
|
685
686
|
description: 'AArch32 Instruction Set Attribute Register 5'
|
|
686
|
-
S3_0_c0_c2_6:
|
|
687
|
-
|
|
687
|
+
'S3_0_c0_c2_6':
|
|
688
|
+
- name: 'ID_MMFR4_EL1'
|
|
688
689
|
description: 'AArch32 Memory Model Feature Register 4'
|
|
689
|
-
S3_0_c0_c2_7:
|
|
690
|
-
|
|
690
|
+
'S3_0_c0_c2_7':
|
|
691
|
+
- name: 'ID_ISAR6_EL1'
|
|
691
692
|
description: 'AArch32 Instruction Set Attribute Register 6'
|
|
692
|
-
S3_0_c0_c3_0:
|
|
693
|
-
|
|
693
|
+
'S3_0_c0_c3_0':
|
|
694
|
+
- name: 'MVFR0_EL1'
|
|
694
695
|
description: 'AArch32 Media and VFP Feature Register 0'
|
|
695
|
-
S3_0_c0_c3_1:
|
|
696
|
-
|
|
696
|
+
'S3_0_c0_c3_1':
|
|
697
|
+
- name: 'MVFR1_EL1'
|
|
697
698
|
description: 'AArch32 Media and VFP Feature Register 1'
|
|
698
|
-
S3_0_c0_c3_2:
|
|
699
|
-
|
|
699
|
+
'S3_0_c0_c3_2':
|
|
700
|
+
- name: 'MVFR2_EL1'
|
|
700
701
|
description: 'AArch32 Media and VFP Feature Register 2'
|
|
701
|
-
S3_0_c0_c3_4:
|
|
702
|
-
|
|
702
|
+
'S3_0_c0_c3_4':
|
|
703
|
+
- name: 'ID_PFR2_EL1'
|
|
703
704
|
description: 'AArch32 Processor Feature Register 2'
|
|
704
|
-
S3_0_c0_c3_5:
|
|
705
|
-
|
|
705
|
+
'S3_0_c0_c3_5':
|
|
706
|
+
- name: 'ID_DFR1_EL1'
|
|
706
707
|
description: 'Debug Feature Register 1'
|
|
707
|
-
S3_0_c0_c3_6:
|
|
708
|
-
|
|
708
|
+
'S3_0_c0_c3_6':
|
|
709
|
+
- name: 'ID_MMFR5_EL1'
|
|
709
710
|
description: 'AArch32 Memory Model Feature Register 5'
|
|
710
|
-
S3_0_c0_c4_0:
|
|
711
|
-
|
|
711
|
+
'S3_0_c0_c4_0':
|
|
712
|
+
- name: 'ID_AA64PFR0_EL1'
|
|
712
713
|
description: 'AArch64 Processor Feature Register 0'
|
|
713
|
-
S3_0_c0_c4_1:
|
|
714
|
-
|
|
714
|
+
'S3_0_c0_c4_1':
|
|
715
|
+
- name: 'ID_AA64PFR1_EL1'
|
|
715
716
|
description: 'AArch64 Processor Feature Register 1'
|
|
716
|
-
S3_0_c0_c4_4:
|
|
717
|
-
|
|
717
|
+
'S3_0_c0_c4_4':
|
|
718
|
+
- name: 'ID_AA64ZFR0_EL1'
|
|
718
719
|
description: 'SVE Feature ID register 0'
|
|
719
|
-
S3_0_c0_c5_0:
|
|
720
|
-
|
|
720
|
+
'S3_0_c0_c5_0':
|
|
721
|
+
- name: 'ID_AA64DFR0_EL1'
|
|
721
722
|
description: 'AArch64 Debug Feature Register 0'
|
|
722
|
-
S3_0_c0_c5_1:
|
|
723
|
-
|
|
723
|
+
'S3_0_c0_c5_1':
|
|
724
|
+
- name: 'ID_AA64DFR1_EL1'
|
|
724
725
|
description: 'AArch64 Debug Feature Register 1'
|
|
725
|
-
S3_0_c0_c5_4:
|
|
726
|
-
|
|
726
|
+
'S3_0_c0_c5_4':
|
|
727
|
+
- name: 'ID_AA64AFR0_EL1'
|
|
727
728
|
description: 'AArch64 Auxiliary Feature Register 0'
|
|
728
|
-
S3_0_c0_c5_5:
|
|
729
|
-
|
|
729
|
+
'S3_0_c0_c5_5':
|
|
730
|
+
- name: 'ID_AA64AFR1_EL1'
|
|
730
731
|
description: 'AArch64 Auxiliary Feature Register 1'
|
|
731
|
-
S3_0_c0_c6_0:
|
|
732
|
-
|
|
732
|
+
'S3_0_c0_c6_0':
|
|
733
|
+
- name: 'ID_AA64ISAR0_EL1'
|
|
733
734
|
description: 'AArch64 Instruction Set Attribute Register 0'
|
|
734
|
-
S3_0_c0_c6_1:
|
|
735
|
-
|
|
735
|
+
'S3_0_c0_c6_1':
|
|
736
|
+
- name: 'ID_AA64ISAR1_EL1'
|
|
736
737
|
description: 'AArch64 Instruction Set Attribute Register 1'
|
|
737
|
-
S3_0_c0_c7_0:
|
|
738
|
-
|
|
738
|
+
'S3_0_c0_c7_0':
|
|
739
|
+
- name: 'ID_AA64MMFR0_EL1'
|
|
739
740
|
description: 'AArch64 Memory Model Feature Register 0'
|
|
740
|
-
S3_0_c0_c7_1:
|
|
741
|
-
|
|
741
|
+
'S3_0_c0_c7_1':
|
|
742
|
+
- name: 'ID_AA64MMFR1_EL1'
|
|
742
743
|
description: 'AArch64 Memory Model Feature Register 1'
|
|
743
|
-
S3_0_c0_c7_2:
|
|
744
|
-
|
|
744
|
+
'S3_0_c0_c7_2':
|
|
745
|
+
- name: 'ID_AA64MMFR2_EL1'
|
|
745
746
|
description: 'AArch64 Memory Model Feature Register 2'
|
|
746
|
-
S3_0_c1_c0_0:
|
|
747
|
-
|
|
747
|
+
'S3_0_c1_c0_0':
|
|
748
|
+
- name: 'SCTLR_EL1'
|
|
748
749
|
description: 'System Control Register (EL1)'
|
|
749
|
-
S3_0_c1_c0_1:
|
|
750
|
-
|
|
750
|
+
'S3_0_c1_c0_1':
|
|
751
|
+
- name: 'ACTLR_EL1'
|
|
751
752
|
description: 'Auxiliary Control Register (EL1)'
|
|
752
|
-
S3_0_c1_c0_2:
|
|
753
|
-
|
|
753
|
+
'S3_0_c1_c0_2':
|
|
754
|
+
- name: 'CPACR_EL1'
|
|
754
755
|
description: 'Architectural Feature Access Control Register'
|
|
755
|
-
S3_0_c1_c0_5:
|
|
756
|
-
|
|
756
|
+
'S3_0_c1_c0_5':
|
|
757
|
+
- name: 'RGSR_EL1'
|
|
757
758
|
description: 'Random Allocation Tag Seed Register.'
|
|
758
|
-
S3_0_c1_c0_6:
|
|
759
|
-
|
|
759
|
+
'S3_0_c1_c0_6':
|
|
760
|
+
- name: 'GCR_EL1'
|
|
760
761
|
description: 'Tag Control Register.'
|
|
761
|
-
S3_0_c1_c2_0:
|
|
762
|
-
|
|
762
|
+
'S3_0_c1_c2_0':
|
|
763
|
+
- name: 'ZCR_EL1'
|
|
763
764
|
description: 'SVE Control Register for EL1'
|
|
764
|
-
S3_0_c1_c2_1:
|
|
765
|
-
|
|
765
|
+
'S3_0_c1_c2_1':
|
|
766
|
+
- name: 'TRFCR_EL1'
|
|
766
767
|
description: 'Trace Filter Control Register (EL1)'
|
|
767
|
-
S3_0_c2_c0_0:
|
|
768
|
-
|
|
768
|
+
'S3_0_c2_c0_0':
|
|
769
|
+
- name: 'TTBR0_EL1'
|
|
769
770
|
description: 'Translation Table Base Register 0 (EL1)'
|
|
770
|
-
S3_0_c2_c0_1:
|
|
771
|
-
|
|
771
|
+
'S3_0_c2_c0_1':
|
|
772
|
+
- name: 'TTBR1_EL1'
|
|
772
773
|
description: 'Translation Table Base Register 1 (EL1)'
|
|
773
|
-
S3_0_c2_c0_2:
|
|
774
|
-
|
|
774
|
+
'S3_0_c2_c0_2':
|
|
775
|
+
- name: 'TCR_EL1'
|
|
775
776
|
description: 'Translation Control Register (EL1)'
|
|
776
|
-
S3_0_c2_c1_0:
|
|
777
|
-
|
|
777
|
+
'S3_0_c2_c1_0':
|
|
778
|
+
- name: 'APIAKeyLo_EL1'
|
|
778
779
|
description: 'Pointer Authentication Key A for Instruction (bits[63:0]) '
|
|
779
|
-
S3_0_c2_c1_1:
|
|
780
|
-
|
|
780
|
+
'S3_0_c2_c1_1':
|
|
781
|
+
- name: 'APIAKeyHi_EL1'
|
|
781
782
|
description: 'Pointer Authentication Key A for Instruction (bits[127:64]) '
|
|
782
|
-
S3_0_c2_c1_2:
|
|
783
|
-
|
|
783
|
+
'S3_0_c2_c1_2':
|
|
784
|
+
- name: 'APIBKeyLo_EL1'
|
|
784
785
|
description: 'Pointer Authentication Key B for Instruction (bits[63:0]) '
|
|
785
|
-
S3_0_c2_c1_3:
|
|
786
|
-
|
|
786
|
+
'S3_0_c2_c1_3':
|
|
787
|
+
- name: 'APIBKeyHi_EL1'
|
|
787
788
|
description: 'Pointer Authentication Key B for Instruction (bits[127:64]) '
|
|
788
|
-
S3_0_c2_c2_0:
|
|
789
|
-
|
|
789
|
+
'S3_0_c2_c2_0':
|
|
790
|
+
- name: 'APDAKeyLo_EL1'
|
|
790
791
|
description: 'Pointer Authentication Key A for Data (bits[63:0]) '
|
|
791
|
-
S3_0_c2_c2_1:
|
|
792
|
-
|
|
792
|
+
'S3_0_c2_c2_1':
|
|
793
|
+
- name: 'APDAKeyHi_EL1'
|
|
793
794
|
description: 'Pointer Authentication Key A for Data (bits[127:64]) '
|
|
794
|
-
S3_0_c2_c2_2:
|
|
795
|
-
|
|
795
|
+
'S3_0_c2_c2_2':
|
|
796
|
+
- name: 'APDBKeyLo_EL1'
|
|
796
797
|
description: 'Pointer Authentication Key B for Data (bits[63:0]) '
|
|
797
|
-
S3_0_c2_c2_3:
|
|
798
|
-
|
|
798
|
+
'S3_0_c2_c2_3':
|
|
799
|
+
- name: 'APDBKeyHi_EL1'
|
|
799
800
|
description: 'Pointer Authentication Key B for Data (bits[127:64]) '
|
|
800
|
-
S3_0_c2_c3_0:
|
|
801
|
-
|
|
801
|
+
'S3_0_c2_c3_0':
|
|
802
|
+
- name: 'APGAKeyLo_EL1'
|
|
802
803
|
description: 'Pointer Authentication Key A for Code (bits[63:0]) '
|
|
803
|
-
S3_0_c2_c3_1:
|
|
804
|
-
|
|
804
|
+
'S3_0_c2_c3_1':
|
|
805
|
+
- name: 'APGAKeyHi_EL1'
|
|
805
806
|
description: 'Pointer Authentication Key A for Code (bits[127:64]) '
|
|
806
|
-
S3_0_c4_c0_0:
|
|
807
|
-
|
|
807
|
+
'S3_0_c4_c0_0':
|
|
808
|
+
- name: 'SPSR_EL1'
|
|
808
809
|
description: 'Saved Program Status Register (EL1)'
|
|
809
|
-
S3_0_c4_c0_1:
|
|
810
|
-
|
|
810
|
+
'S3_0_c4_c0_1':
|
|
811
|
+
- name: 'ELR_EL1'
|
|
811
812
|
description: 'Exception Link Register (EL1)'
|
|
812
|
-
S3_0_c4_c1_0:
|
|
813
|
-
|
|
813
|
+
'S3_0_c4_c1_0':
|
|
814
|
+
- name: 'SP_EL0'
|
|
814
815
|
description: 'Stack Pointer (EL0)'
|
|
815
|
-
S3_0_c4_c2_0:
|
|
816
|
-
|
|
816
|
+
'S3_0_c4_c2_0':
|
|
817
|
+
- name: 'SPSel'
|
|
817
818
|
description: 'Stack Pointer Select'
|
|
818
|
-
S3_0_c4_c2_2:
|
|
819
|
-
|
|
819
|
+
'S3_0_c4_c2_2':
|
|
820
|
+
- name: 'CurrentEL'
|
|
820
821
|
description: 'Current Exception Level'
|
|
821
|
-
S3_0_c4_c2_3:
|
|
822
|
-
|
|
822
|
+
'S3_0_c4_c2_3':
|
|
823
|
+
- name: 'PAN'
|
|
823
824
|
description: 'Privileged Access Never'
|
|
824
|
-
S3_0_c4_c2_4:
|
|
825
|
-
|
|
825
|
+
'S3_0_c4_c2_4':
|
|
826
|
+
- name: 'UAO'
|
|
826
827
|
description: 'User Access Override'
|
|
827
|
-
S3_0_c4_c6_0:
|
|
828
|
-
|
|
829
|
-
description: Interrupt Controller Interrupt Priority Mask Register
|
|
830
|
-
|
|
831
|
-
|
|
832
|
-
|
|
828
|
+
'S3_0_c4_c6_0':
|
|
829
|
+
- name: 'ICC_PMR_EL1'
|
|
830
|
+
description: 'Interrupt Controller Interrupt Priority Mask Register'
|
|
831
|
+
- name: 'ICV_PMR_EL1'
|
|
832
|
+
description: 'Interrupt Controller Virtual Interrupt Priority Mask Register'
|
|
833
|
+
'S3_0_c5_c1_0':
|
|
834
|
+
- name: 'AFSR0_EL1'
|
|
833
835
|
description: 'Auxiliary Fault Status Register 0 (EL1)'
|
|
834
|
-
S3_0_c5_c1_1:
|
|
835
|
-
|
|
836
|
+
'S3_0_c5_c1_1':
|
|
837
|
+
- name: 'AFSR1_EL1'
|
|
836
838
|
description: 'Auxiliary Fault Status Register 1 (EL1)'
|
|
837
|
-
S3_0_c5_c2_0:
|
|
838
|
-
|
|
839
|
+
'S3_0_c5_c2_0':
|
|
840
|
+
- name: 'ESR_EL1'
|
|
839
841
|
description: 'Exception Syndrome Register (EL1)'
|
|
840
|
-
S3_0_c5_c3_0:
|
|
841
|
-
|
|
842
|
+
'S3_0_c5_c3_0':
|
|
843
|
+
- name: 'ERRIDR_EL1'
|
|
842
844
|
description: 'Error Record ID Register'
|
|
843
|
-
S3_0_c5_c3_1:
|
|
844
|
-
|
|
845
|
+
'S3_0_c5_c3_1':
|
|
846
|
+
- name: 'ERRSELR_EL1'
|
|
845
847
|
description: 'Error Record Select Register'
|
|
846
|
-
S3_0_c5_c4_0:
|
|
847
|
-
|
|
848
|
+
'S3_0_c5_c4_0':
|
|
849
|
+
- name: 'ERXFR_EL1'
|
|
848
850
|
description: 'Selected Error Record Feature Register'
|
|
849
|
-
S3_0_c5_c4_1:
|
|
850
|
-
|
|
851
|
+
'S3_0_c5_c4_1':
|
|
852
|
+
- name: 'ERXCTLR_EL1'
|
|
851
853
|
description: 'Selected Error Record Control Register'
|
|
852
|
-
S3_0_c5_c4_2:
|
|
853
|
-
|
|
854
|
+
'S3_0_c5_c4_2':
|
|
855
|
+
- name: 'ERXSTATUS_EL1'
|
|
854
856
|
description: 'Selected Error Record Primary Status Register'
|
|
855
|
-
S3_0_c5_c4_3:
|
|
856
|
-
|
|
857
|
+
'S3_0_c5_c4_3':
|
|
858
|
+
- name: 'ERXADDR_EL1'
|
|
857
859
|
description: 'Selected Error Record Address Register'
|
|
858
|
-
S3_0_c5_c4_4:
|
|
859
|
-
|
|
860
|
+
'S3_0_c5_c4_4':
|
|
861
|
+
- name: 'ERXPFGF_EL1'
|
|
860
862
|
description: 'Selected Pseudo-fault Generation Feature register'
|
|
861
|
-
S3_0_c5_c4_5:
|
|
862
|
-
|
|
863
|
+
'S3_0_c5_c4_5':
|
|
864
|
+
- name: 'ERXPFGCTL_EL1'
|
|
863
865
|
description: 'Selected Pseudo-fault Generation Control register'
|
|
864
|
-
S3_0_c5_c4_6:
|
|
865
|
-
|
|
866
|
+
'S3_0_c5_c4_6':
|
|
867
|
+
- name: 'ERXPFGCDN_EL1'
|
|
866
868
|
description: 'Selected Pseudo-fault Generation Countdown register'
|
|
867
|
-
S3_0_c5_c5_0:
|
|
868
|
-
|
|
869
|
+
'S3_0_c5_c5_0':
|
|
870
|
+
- name: 'ERXMISC0_EL1'
|
|
869
871
|
description: 'Selected Error Record Miscellaneous Register 0'
|
|
870
|
-
S3_0_c5_c5_1:
|
|
871
|
-
|
|
872
|
+
'S3_0_c5_c5_1':
|
|
873
|
+
- name: 'ERXMISC1_EL1'
|
|
872
874
|
description: 'Selected Error Record Miscellaneous Register 1'
|
|
873
|
-
S3_0_c5_c5_2:
|
|
874
|
-
|
|
875
|
+
'S3_0_c5_c5_2':
|
|
876
|
+
- name: 'ERXMISC2_EL1'
|
|
875
877
|
description: 'Selected Error Record Miscellaneous Register 2'
|
|
876
|
-
S3_0_c5_c5_3:
|
|
877
|
-
|
|
878
|
+
'S3_0_c5_c5_3':
|
|
879
|
+
- name: 'ERXMISC3_EL1'
|
|
878
880
|
description: 'Selected Error Record Miscellaneous Register 3'
|
|
879
|
-
S3_0_c5_c6_0:
|
|
880
|
-
|
|
881
|
+
'S3_0_c5_c6_0':
|
|
882
|
+
- name: 'TFSR_EL1'
|
|
881
883
|
description: 'Tag Fault Status Register (EL1)'
|
|
882
|
-
S3_0_c5_c6_1:
|
|
883
|
-
|
|
884
|
+
'S3_0_c5_c6_1':
|
|
885
|
+
- name: 'TFSRE0_EL1'
|
|
884
886
|
description: 'Tag Fault Status Register (EL0).'
|
|
885
|
-
S3_0_c6_c0_0:
|
|
886
|
-
|
|
887
|
+
'S3_0_c6_c0_0':
|
|
888
|
+
- name: 'FAR_EL1'
|
|
887
889
|
description: 'Fault Address Register (EL1)'
|
|
888
|
-
S3_0_c7_c4_0:
|
|
889
|
-
|
|
890
|
+
'S3_0_c7_c4_0':
|
|
891
|
+
- name: 'PAR_EL1'
|
|
890
892
|
description: 'Physical Address Register'
|
|
891
|
-
S3_0_c9_c9_0:
|
|
892
|
-
|
|
893
|
+
'S3_0_c9_c9_0':
|
|
894
|
+
- name: 'PMSCR_EL1'
|
|
893
895
|
description: 'Statistical Profiling Control Register (EL1)'
|
|
894
|
-
S3_0_c9_c9_2:
|
|
895
|
-
|
|
896
|
+
'S3_0_c9_c9_2':
|
|
897
|
+
- name: 'PMSICR_EL1'
|
|
896
898
|
description: 'Sampling Interval Counter Register'
|
|
897
|
-
S3_0_c9_c9_3:
|
|
898
|
-
|
|
899
|
+
'S3_0_c9_c9_3':
|
|
900
|
+
- name: 'PMSIRR_EL1'
|
|
899
901
|
description: 'Sampling Interval Reload Register'
|
|
900
|
-
S3_0_c9_c9_4:
|
|
901
|
-
|
|
902
|
+
'S3_0_c9_c9_4':
|
|
903
|
+
- name: 'PMSFCR_EL1'
|
|
902
904
|
description: 'Sampling Filter Control Register'
|
|
903
|
-
S3_0_c9_c9_5:
|
|
904
|
-
|
|
905
|
+
'S3_0_c9_c9_5':
|
|
906
|
+
- name: 'PMSEVFR_EL1'
|
|
905
907
|
description: 'Sampling Event Filter Register'
|
|
906
|
-
S3_0_c9_c9_6:
|
|
907
|
-
|
|
908
|
+
'S3_0_c9_c9_6':
|
|
909
|
+
- name: 'PMSLATFR_EL1'
|
|
908
910
|
description: 'Sampling Latency Filter Register'
|
|
909
|
-
S3_0_c9_c9_7:
|
|
910
|
-
|
|
911
|
+
'S3_0_c9_c9_7':
|
|
912
|
+
- name: 'PMSIDR_EL1'
|
|
911
913
|
description: 'Sampling Profiling ID Register'
|
|
912
|
-
S3_0_c9_c10_0:
|
|
913
|
-
|
|
914
|
+
'S3_0_c9_c10_0':
|
|
915
|
+
- name: 'PMBLIMITR_EL1'
|
|
914
916
|
description: 'Profiling Buffer Limit Address Register'
|
|
915
|
-
S3_0_c9_c10_1:
|
|
916
|
-
|
|
917
|
+
'S3_0_c9_c10_1':
|
|
918
|
+
- name: 'PMBPTR_EL1'
|
|
917
919
|
description: 'Profiling Buffer Write Pointer Register'
|
|
918
|
-
S3_0_c9_c10_3:
|
|
919
|
-
|
|
920
|
+
'S3_0_c9_c10_3':
|
|
921
|
+
- name: 'PMBSR_EL1'
|
|
920
922
|
description: 'Profiling Buffer Status/syndrome Register'
|
|
921
|
-
S3_0_c9_c10_7:
|
|
922
|
-
|
|
923
|
+
'S3_0_c9_c10_7':
|
|
924
|
+
- name: 'PMBIDR_EL1'
|
|
923
925
|
description: 'Profiling Buffer ID Register'
|
|
924
|
-
S3_0_c9_c14_1:
|
|
925
|
-
|
|
926
|
+
'S3_0_c9_c14_1':
|
|
927
|
+
- name: 'PMINTENSET_EL1'
|
|
926
928
|
description: 'Performance Monitors Interrupt Enable Set register'
|
|
927
|
-
S3_0_c9_c14_2:
|
|
928
|
-
|
|
929
|
+
'S3_0_c9_c14_2':
|
|
930
|
+
- name: 'PMINTENCLR_EL1'
|
|
929
931
|
description: 'Performance Monitors Interrupt Enable Clear register'
|
|
930
|
-
S3_0_c9_c14_6:
|
|
931
|
-
|
|
932
|
+
'S3_0_c9_c14_6':
|
|
933
|
+
- name: 'PMMIR_EL1'
|
|
932
934
|
description: 'Performance Monitors Machine Identification Register'
|
|
933
|
-
S3_0_c10_c2_0:
|
|
934
|
-
|
|
935
|
+
'S3_0_c10_c2_0':
|
|
936
|
+
- name: 'MAIR_EL1'
|
|
935
937
|
description: 'Memory Attribute Indirection Register (EL1)'
|
|
936
|
-
S3_0_c10_c3_0:
|
|
937
|
-
|
|
938
|
+
'S3_0_c10_c3_0':
|
|
939
|
+
- name: 'AMAIR_EL1'
|
|
938
940
|
description: 'Auxiliary Memory Attribute Indirection Register (EL1)'
|
|
939
|
-
S3_0_c10_c4_0:
|
|
940
|
-
|
|
941
|
+
'S3_0_c10_c4_0':
|
|
942
|
+
- name: 'LORSA_EL1'
|
|
941
943
|
description: 'LORegion Start Address (EL1)'
|
|
942
|
-
S3_0_c10_c4_1:
|
|
943
|
-
|
|
944
|
+
'S3_0_c10_c4_1':
|
|
945
|
+
- name: 'LOREA_EL1'
|
|
944
946
|
description: 'LORegion End Address (EL1)'
|
|
945
|
-
S3_0_c10_c4_2:
|
|
946
|
-
|
|
947
|
+
'S3_0_c10_c4_2':
|
|
948
|
+
- name: 'LORN_EL1'
|
|
947
949
|
description: 'LORegion Number (EL1)'
|
|
948
|
-
S3_0_c10_c4_3:
|
|
949
|
-
|
|
950
|
+
'S3_0_c10_c4_3':
|
|
951
|
+
- name: 'LORC_EL1'
|
|
950
952
|
description: 'LORegion Control (EL1)'
|
|
951
|
-
S3_0_c10_c4_4:
|
|
952
|
-
|
|
953
|
+
'S3_0_c10_c4_4':
|
|
954
|
+
- name: 'MPAMIDR_EL1'
|
|
953
955
|
description: 'MPAM ID Register (EL1)'
|
|
954
|
-
S3_0_c10_c4_7:
|
|
955
|
-
|
|
956
|
+
'S3_0_c10_c4_7':
|
|
957
|
+
- name: 'LORID_EL1'
|
|
956
958
|
description: 'LORegionID (EL1)'
|
|
957
|
-
S3_0_c10_c5_0:
|
|
958
|
-
|
|
959
|
+
'S3_0_c10_c5_0':
|
|
960
|
+
- name: 'MPAM1_EL1'
|
|
959
961
|
description: 'MPAM1 Register (EL1)'
|
|
960
|
-
S3_0_c10_c5_1:
|
|
961
|
-
|
|
962
|
+
'S3_0_c10_c5_1':
|
|
963
|
+
- name: 'MPAM0_EL1'
|
|
962
964
|
description: 'MPAM0 Register (EL1)'
|
|
963
|
-
S3_0_c12_c0_0:
|
|
964
|
-
|
|
965
|
+
'S3_0_c12_c0_0':
|
|
966
|
+
- name: 'VBAR_EL1'
|
|
965
967
|
description: 'Vector Base Address Register (EL1)'
|
|
966
|
-
S3_0_c12_c0_1:
|
|
967
|
-
|
|
968
|
+
'S3_0_c12_c0_1':
|
|
969
|
+
- name: 'RVBAR_EL1'
|
|
968
970
|
description: 'Reset Vector Base Address Register (if EL2 and EL3 not implemented)'
|
|
969
|
-
S3_0_c12_c0_2:
|
|
970
|
-
|
|
971
|
+
'S3_0_c12_c0_2':
|
|
972
|
+
- name: 'RMR_EL1'
|
|
971
973
|
description: 'Reset Management Register (EL1)'
|
|
972
|
-
S3_0_c12_c1_0:
|
|
973
|
-
|
|
974
|
+
'S3_0_c12_c1_0':
|
|
975
|
+
- name: 'ISR_EL1'
|
|
974
976
|
description: 'Interrupt Status Register'
|
|
975
|
-
S3_0_c12_c1_1:
|
|
976
|
-
|
|
977
|
+
'S3_0_c12_c1_1':
|
|
978
|
+
- name: 'DISR_EL1'
|
|
977
979
|
description: 'Deferred Interrupt Status Register'
|
|
978
|
-
S3_0_c12_c8_0:
|
|
979
|
-
|
|
980
|
-
description: Interrupt Controller Interrupt Acknowledge Register 0
|
|
981
|
-
|
|
982
|
-
|
|
983
|
-
|
|
984
|
-
|
|
985
|
-
|
|
986
|
-
|
|
987
|
-
|
|
988
|
-
|
|
989
|
-
|
|
990
|
-
|
|
991
|
-
|
|
992
|
-
description: Interrupt Controller
|
|
993
|
-
|
|
994
|
-
|
|
995
|
-
|
|
996
|
-
|
|
997
|
-
|
|
998
|
-
|
|
999
|
-
|
|
1000
|
-
description: Interrupt Controller Active Priorities Group 0 Register
|
|
1001
|
-
|
|
1002
|
-
|
|
1003
|
-
|
|
1004
|
-
|
|
1005
|
-
|
|
1006
|
-
|
|
1007
|
-
|
|
1008
|
-
|
|
1009
|
-
|
|
1010
|
-
|
|
1011
|
-
|
|
1012
|
-
description: Interrupt Controller Active Priorities Group
|
|
1013
|
-
|
|
1014
|
-
|
|
1015
|
-
|
|
1016
|
-
|
|
1017
|
-
|
|
1018
|
-
|
|
1019
|
-
|
|
1020
|
-
description: Interrupt Controller Active Priorities Group 1 Register
|
|
1021
|
-
|
|
1022
|
-
|
|
1023
|
-
|
|
1024
|
-
|
|
1025
|
-
|
|
1026
|
-
|
|
1027
|
-
|
|
1028
|
-
|
|
1029
|
-
|
|
1030
|
-
|
|
1031
|
-
|
|
1032
|
-
description: Interrupt Controller
|
|
1033
|
-
|
|
1034
|
-
|
|
1035
|
-
|
|
980
|
+
'S3_0_c12_c8_0':
|
|
981
|
+
- name: 'ICC_IAR0_EL1'
|
|
982
|
+
description: 'Interrupt Controller Interrupt Acknowledge Register 0'
|
|
983
|
+
- name: 'ICV_IAR0_EL1'
|
|
984
|
+
description: 'Interrupt Controller Virtual Interrupt Acknowledge Register 0'
|
|
985
|
+
'S3_0_c12_c8_1':
|
|
986
|
+
- name: 'ICC_EOIR0_EL1'
|
|
987
|
+
description: 'Interrupt Controller End Of Interrupt Register 0'
|
|
988
|
+
- name: 'ICV_EOIR0_EL1'
|
|
989
|
+
description: 'Interrupt Controller Virtual End Of Interrupt Register 0'
|
|
990
|
+
'S3_0_c12_c8_2':
|
|
991
|
+
- name: 'ICC_HPPIR0_EL1'
|
|
992
|
+
description: 'Interrupt Controller Highest Priority Pending Interrupt Register 0'
|
|
993
|
+
- name: 'ICV_HPPIR0_EL1'
|
|
994
|
+
description: 'Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0'
|
|
995
|
+
'S3_0_c12_c8_3':
|
|
996
|
+
- name: 'ICC_BPR0_EL1'
|
|
997
|
+
description: 'Interrupt Controller Binary Point Register 0'
|
|
998
|
+
- name: 'ICV_BPR0_EL1'
|
|
999
|
+
description: 'Interrupt Controller Virtual Binary Point Register 0'
|
|
1000
|
+
'S3_0_c12_c8_4':
|
|
1001
|
+
- name: 'ICC_AP0R0_EL1'
|
|
1002
|
+
description: 'Interrupt Controller Active Priorities Group 0 Register 0'
|
|
1003
|
+
- name: 'ICV_AP0R0_EL1'
|
|
1004
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 0 Register 0'
|
|
1005
|
+
'S3_0_c12_c8_5':
|
|
1006
|
+
- name: 'ICC_AP0R1_EL1'
|
|
1007
|
+
description: 'Interrupt Controller Active Priorities Group 0 Register 1'
|
|
1008
|
+
- name: 'ICV_AP0R1_EL1'
|
|
1009
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 0 Register 1'
|
|
1010
|
+
'S3_0_c12_c8_6':
|
|
1011
|
+
- name: 'ICC_AP0R2_EL1'
|
|
1012
|
+
description: 'Interrupt Controller Active Priorities Group 0 Register 2'
|
|
1013
|
+
- name: 'ICV_AP0R2_EL1'
|
|
1014
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 0 Register 2'
|
|
1015
|
+
'S3_0_c12_c8_7':
|
|
1016
|
+
- name: 'ICC_AP0R3_EL1'
|
|
1017
|
+
description: 'Interrupt Controller Active Priorities Group 0 Register 3'
|
|
1018
|
+
- name: 'ICV_AP0R3_EL1'
|
|
1019
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 0 Register 3'
|
|
1020
|
+
'S3_0_c12_c9_0':
|
|
1021
|
+
- name: 'ICC_AP1R0_EL1'
|
|
1022
|
+
description: 'Interrupt Controller Active Priorities Group 1 Register 0'
|
|
1023
|
+
- name: 'ICV_AP1R0_EL1'
|
|
1024
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 1 Register 0'
|
|
1025
|
+
'S3_0_c12_c9_1':
|
|
1026
|
+
- name: 'ICC_AP1R1_EL1'
|
|
1027
|
+
description: 'Interrupt Controller Active Priorities Group 1 Register 1'
|
|
1028
|
+
- name: 'ICV_AP1R1_EL1'
|
|
1029
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 1 Register 1'
|
|
1030
|
+
'S3_0_c12_c9_2':
|
|
1031
|
+
- name: 'ICC_AP1R2_EL1'
|
|
1032
|
+
description: 'Interrupt Controller Active Priorities Group 1 Register 2'
|
|
1033
|
+
- name: 'ICV_AP1R2_EL1'
|
|
1034
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 1 Register 2'
|
|
1035
|
+
'S3_0_c12_c9_3':
|
|
1036
|
+
- name: 'ICC_AP1R3_EL1'
|
|
1037
|
+
description: 'Interrupt Controller Active Priorities Group 1 Register 3'
|
|
1038
|
+
- name: 'ICV_AP1R3_EL1'
|
|
1039
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 1 Register 3'
|
|
1040
|
+
'S3_0_c12_c11_1':
|
|
1041
|
+
- name: 'ICC_DIR_EL1'
|
|
1042
|
+
description: 'Interrupt Controller Deactivate Interrupt Register'
|
|
1043
|
+
- name: 'ICV_DIR_EL1'
|
|
1044
|
+
description: 'Interrupt Controller Deactivate Virtual Interrupt Register'
|
|
1045
|
+
'S3_0_c12_c11_3':
|
|
1046
|
+
- name: 'ICC_RPR_EL1'
|
|
1047
|
+
description: 'Interrupt Controller Running Priority Register'
|
|
1048
|
+
- name: 'ICV_RPR_EL1'
|
|
1049
|
+
description: 'Interrupt Controller Virtual Running Priority Register'
|
|
1050
|
+
'S3_0_c12_c11_5':
|
|
1051
|
+
- name: 'ICC_SGI1R_EL1'
|
|
1036
1052
|
description: 'Interrupt Controller Software Generated Interrupt Group 1 Register'
|
|
1037
|
-
S3_0_c12_c11_6:
|
|
1038
|
-
|
|
1053
|
+
'S3_0_c12_c11_6':
|
|
1054
|
+
- name: 'ICC_ASGI1R_EL1'
|
|
1039
1055
|
description: 'Interrupt Controller Alias Software Generated Interrupt Group 1 Register'
|
|
1040
|
-
S3_0_c12_c11_7:
|
|
1041
|
-
|
|
1056
|
+
'S3_0_c12_c11_7':
|
|
1057
|
+
- name: 'ICC_SGI0R_EL1'
|
|
1042
1058
|
description: 'Interrupt Controller Software Generated Interrupt Group 0 Register'
|
|
1043
|
-
S3_0_c12_c12_0:
|
|
1044
|
-
|
|
1045
|
-
description: Interrupt Controller Interrupt Acknowledge Register 1
|
|
1046
|
-
|
|
1047
|
-
|
|
1048
|
-
|
|
1049
|
-
|
|
1050
|
-
|
|
1051
|
-
|
|
1052
|
-
|
|
1053
|
-
|
|
1054
|
-
|
|
1055
|
-
|
|
1056
|
-
|
|
1057
|
-
description: Interrupt Controller
|
|
1058
|
-
|
|
1059
|
-
|
|
1060
|
-
|
|
1061
|
-
|
|
1062
|
-
|
|
1063
|
-
|
|
1064
|
-
|
|
1059
|
+
'S3_0_c12_c12_0':
|
|
1060
|
+
- name: 'ICC_IAR1_EL1'
|
|
1061
|
+
description: 'Interrupt Controller Interrupt Acknowledge Register 1'
|
|
1062
|
+
- name: 'ICV_IAR1_EL1'
|
|
1063
|
+
description: 'Interrupt Controller Virtual Interrupt Acknowledge Register 1'
|
|
1064
|
+
'S3_0_c12_c12_1':
|
|
1065
|
+
- name: 'ICC_EOIR1_EL1'
|
|
1066
|
+
description: 'Interrupt Controller End Of Interrupt Register 1'
|
|
1067
|
+
- name: 'ICV_EOIR1_EL1'
|
|
1068
|
+
description: 'Interrupt Controller Virtual End Of Interrupt Register 1'
|
|
1069
|
+
'S3_0_c12_c12_2':
|
|
1070
|
+
- name: 'ICC_HPPIR1_EL1'
|
|
1071
|
+
description: 'Interrupt Controller Highest Priority Pending Interrupt Register 1'
|
|
1072
|
+
- name: 'ICV_HPPIR1_EL1'
|
|
1073
|
+
description: 'Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1'
|
|
1074
|
+
'S3_0_c12_c12_3':
|
|
1075
|
+
- name: 'ICC_BPR1_EL1'
|
|
1076
|
+
description: 'Interrupt Controller Binary Point Register 1'
|
|
1077
|
+
- name: 'ICV_BPR1_EL1'
|
|
1078
|
+
description: 'Interrupt Controller Virtual Binary Point Register 1'
|
|
1079
|
+
'S3_0_c12_c12_4':
|
|
1080
|
+
- name: 'ICC_CTLR_EL1'
|
|
1081
|
+
description: 'Interrupt Controller Control Register (EL1)'
|
|
1082
|
+
- name: 'ICV_CTLR_EL1'
|
|
1083
|
+
description: 'Interrupt Controller Virtual Control Register'
|
|
1084
|
+
'S3_0_c12_c12_5':
|
|
1085
|
+
- name: 'ICC_SRE_EL1'
|
|
1065
1086
|
description: 'Interrupt Controller System Register Enable register (EL1)'
|
|
1066
|
-
S3_0_c12_c12_6:
|
|
1067
|
-
|
|
1068
|
-
description: Interrupt Controller Interrupt Group 0 Enable register
|
|
1069
|
-
|
|
1070
|
-
|
|
1071
|
-
|
|
1072
|
-
|
|
1073
|
-
|
|
1074
|
-
|
|
1075
|
-
|
|
1087
|
+
'S3_0_c12_c12_6':
|
|
1088
|
+
- name: 'ICC_IGRPEN0_EL1'
|
|
1089
|
+
description: 'Interrupt Controller Interrupt Group 0 Enable register'
|
|
1090
|
+
- name: 'ICV_IGRPEN0_EL1'
|
|
1091
|
+
description: 'Interrupt Controller Virtual Interrupt Group 0 Enable register'
|
|
1092
|
+
'S3_0_c12_c12_7':
|
|
1093
|
+
- name: 'ICC_IGRPEN1_EL1'
|
|
1094
|
+
description: 'Interrupt Controller Interrupt Group 1 Enable register'
|
|
1095
|
+
- name: 'ICV_IGRPEN1_EL1'
|
|
1096
|
+
description: 'Interrupt Controller Virtual Interrupt Group 1 Enable register'
|
|
1097
|
+
'S3_0_c13_c0_1':
|
|
1098
|
+
- name: 'CONTEXTIDR_EL1'
|
|
1076
1099
|
description: 'Context ID Register (EL1)'
|
|
1077
|
-
S3_0_c13_c0_4:
|
|
1078
|
-
|
|
1100
|
+
'S3_0_c13_c0_4':
|
|
1101
|
+
- name: 'TPIDR_EL1'
|
|
1079
1102
|
description: 'EL1 Software Thread ID Register'
|
|
1080
|
-
S3_0_c13_c0_7:
|
|
1081
|
-
|
|
1103
|
+
'S3_0_c13_c0_7':
|
|
1104
|
+
- name: 'SCXTNUM_EL1'
|
|
1082
1105
|
description: 'EL1 Read/Write Software Context Number'
|
|
1083
|
-
S3_0_c14_c1_0:
|
|
1084
|
-
|
|
1106
|
+
'S3_0_c14_c1_0':
|
|
1107
|
+
- name: 'CNTKCTL_EL1'
|
|
1085
1108
|
description: 'Counter-timer Kernel Control register'
|
|
1086
|
-
S3_1_c0_c0_0:
|
|
1087
|
-
|
|
1109
|
+
'S3_1_c0_c0_0':
|
|
1110
|
+
- name: 'CCSIDR_EL1'
|
|
1088
1111
|
description: 'Current Cache Size ID Register'
|
|
1089
|
-
S3_1_c0_c0_1:
|
|
1090
|
-
|
|
1112
|
+
'S3_1_c0_c0_1':
|
|
1113
|
+
- name: 'CLIDR_EL1'
|
|
1091
1114
|
description: 'Cache Level ID Register'
|
|
1092
|
-
S3_1_c0_c0_2:
|
|
1093
|
-
|
|
1115
|
+
'S3_1_c0_c0_2':
|
|
1116
|
+
- name: 'CCSIDR2_EL1'
|
|
1094
1117
|
description: 'Current Cache Size ID Register 2'
|
|
1095
|
-
S3_1_c0_c0_4:
|
|
1096
|
-
|
|
1118
|
+
'S3_1_c0_c0_4':
|
|
1119
|
+
- name: 'GMID_EL1'
|
|
1097
1120
|
description: ' Multiple tag transfer ID register'
|
|
1098
|
-
S3_1_c0_c0_7:
|
|
1099
|
-
|
|
1121
|
+
'S3_1_c0_c0_7':
|
|
1122
|
+
- name: 'AIDR_EL1'
|
|
1100
1123
|
description: 'Auxiliary ID Register'
|
|
1101
|
-
S3_2_c0_c0_0:
|
|
1102
|
-
|
|
1124
|
+
'S3_2_c0_c0_0':
|
|
1125
|
+
- name: 'CSSELR_EL1'
|
|
1103
1126
|
description: 'Cache Size Selection Register'
|
|
1104
|
-
S3_3_c0_c0_1:
|
|
1105
|
-
|
|
1127
|
+
'S3_3_c0_c0_1':
|
|
1128
|
+
- name: 'CTR_EL0'
|
|
1106
1129
|
description: 'Cache Type Register'
|
|
1107
|
-
S3_3_c0_c0_7:
|
|
1108
|
-
|
|
1130
|
+
'S3_3_c0_c0_7':
|
|
1131
|
+
- name: 'DCZID_EL0'
|
|
1109
1132
|
description: 'Data Cache Zero ID register'
|
|
1110
|
-
S3_3_c2_c4_0:
|
|
1111
|
-
|
|
1133
|
+
'S3_3_c2_c4_0':
|
|
1134
|
+
- name: 'RNDR'
|
|
1112
1135
|
description: 'Random Number'
|
|
1113
|
-
S3_3_c2_c4_1:
|
|
1114
|
-
|
|
1136
|
+
'S3_3_c2_c4_1':
|
|
1137
|
+
- name: 'RNDRRS'
|
|
1115
1138
|
description: 'Reseeded Random Number'
|
|
1116
|
-
S3_3_c4_c2_0:
|
|
1117
|
-
|
|
1139
|
+
'S3_3_c4_c2_0':
|
|
1140
|
+
- name: 'NZCV'
|
|
1118
1141
|
description: 'Condition Flags'
|
|
1119
|
-
S3_3_c4_c2_1:
|
|
1120
|
-
|
|
1142
|
+
'S3_3_c4_c2_1':
|
|
1143
|
+
- name: 'DAIF'
|
|
1121
1144
|
description: 'Interrupt Mask Bits'
|
|
1122
|
-
S3_3_c4_c2_5:
|
|
1123
|
-
|
|
1145
|
+
'S3_3_c4_c2_5':
|
|
1146
|
+
- name: 'DIT'
|
|
1124
1147
|
description: 'Data Independent Timing'
|
|
1125
|
-
S3_3_c4_c2_6:
|
|
1126
|
-
|
|
1148
|
+
'S3_3_c4_c2_6':
|
|
1149
|
+
- name: 'SSBS'
|
|
1127
1150
|
description: 'Speculative Store Bypass Safe'
|
|
1128
|
-
S3_3_c4_c2_7:
|
|
1129
|
-
|
|
1151
|
+
'S3_3_c4_c2_7':
|
|
1152
|
+
- name: 'TCO'
|
|
1130
1153
|
description: 'Tag Check Override'
|
|
1131
|
-
S3_3_c4_c4_0:
|
|
1132
|
-
|
|
1154
|
+
'S3_3_c4_c4_0':
|
|
1155
|
+
- name: 'FPCR'
|
|
1133
1156
|
description: 'Floating-point Control Register'
|
|
1134
|
-
S3_3_c4_c4_1:
|
|
1135
|
-
|
|
1157
|
+
'S3_3_c4_c4_1':
|
|
1158
|
+
- name: 'FPSR'
|
|
1136
1159
|
description: 'Floating-point Status Register'
|
|
1137
|
-
S3_3_c4_c5_0:
|
|
1138
|
-
|
|
1160
|
+
'S3_3_c4_c5_0':
|
|
1161
|
+
- name: 'DSPSR_EL0'
|
|
1139
1162
|
description: 'Debug Saved Program Status Register'
|
|
1140
|
-
S3_3_c4_c5_1:
|
|
1141
|
-
|
|
1163
|
+
'S3_3_c4_c5_1':
|
|
1164
|
+
- name: 'DLR_EL0'
|
|
1142
1165
|
description: 'Debug Link Register'
|
|
1143
|
-
S3_3_c9_c12_0:
|
|
1144
|
-
|
|
1166
|
+
'S3_3_c9_c12_0':
|
|
1167
|
+
- name: 'PMCR_EL0'
|
|
1145
1168
|
description: 'Performance Monitors Control Register'
|
|
1146
|
-
S3_3_c9_c12_1:
|
|
1147
|
-
|
|
1169
|
+
'S3_3_c9_c12_1':
|
|
1170
|
+
- name: 'PMCNTENSET_EL0'
|
|
1148
1171
|
description: 'Performance Monitors Count Enable Set register'
|
|
1149
|
-
S3_3_c9_c12_2:
|
|
1150
|
-
|
|
1172
|
+
'S3_3_c9_c12_2':
|
|
1173
|
+
- name: 'PMCNTENCLR_EL0'
|
|
1151
1174
|
description: 'Performance Monitors Count Enable Clear register'
|
|
1152
|
-
S3_3_c9_c12_3:
|
|
1153
|
-
|
|
1175
|
+
'S3_3_c9_c12_3':
|
|
1176
|
+
- name: 'PMOVSCLR_EL0'
|
|
1154
1177
|
description: 'Performance Monitors Overflow Flag Status Clear Register'
|
|
1155
|
-
S3_3_c9_c12_4:
|
|
1156
|
-
|
|
1178
|
+
'S3_3_c9_c12_4':
|
|
1179
|
+
- name: 'PMSWINC_EL0'
|
|
1157
1180
|
description: 'Performance Monitors Software Increment register'
|
|
1158
|
-
S3_3_c9_c12_5:
|
|
1159
|
-
|
|
1181
|
+
'S3_3_c9_c12_5':
|
|
1182
|
+
- name: 'PMSELR_EL0'
|
|
1160
1183
|
description: 'Performance Monitors Event Counter Selection Register'
|
|
1161
|
-
S3_3_c9_c12_6:
|
|
1162
|
-
|
|
1184
|
+
'S3_3_c9_c12_6':
|
|
1185
|
+
- name: 'PMCEID0_EL0'
|
|
1163
1186
|
description: 'Performance Monitors Common Event Identification register 0'
|
|
1164
|
-
S3_3_c9_c12_7:
|
|
1165
|
-
|
|
1187
|
+
'S3_3_c9_c12_7':
|
|
1188
|
+
- name: 'PMCEID1_EL0'
|
|
1166
1189
|
description: 'Performance Monitors Common Event Identification register 1'
|
|
1167
|
-
S3_3_c9_c13_0:
|
|
1168
|
-
|
|
1190
|
+
'S3_3_c9_c13_0':
|
|
1191
|
+
- name: 'PMCCNTR_EL0'
|
|
1169
1192
|
description: 'Performance Monitors Cycle Count Register'
|
|
1170
|
-
S3_3_c9_c13_1:
|
|
1171
|
-
|
|
1193
|
+
'S3_3_c9_c13_1':
|
|
1194
|
+
- name: 'PMXEVTYPER_EL0'
|
|
1172
1195
|
description: 'Performance Monitors Selected Event Type Register'
|
|
1173
|
-
S3_3_c9_c13_2:
|
|
1174
|
-
|
|
1196
|
+
'S3_3_c9_c13_2':
|
|
1197
|
+
- name: 'PMXEVCNTR_EL0'
|
|
1175
1198
|
description: 'Performance Monitors Selected Event Count Register'
|
|
1176
|
-
S3_3_c9_c14_0:
|
|
1177
|
-
|
|
1199
|
+
'S3_3_c9_c14_0':
|
|
1200
|
+
- name: 'PMUSERENR_EL0'
|
|
1178
1201
|
description: 'Performance Monitors User Enable Register'
|
|
1179
|
-
S3_3_c9_c14_3:
|
|
1180
|
-
|
|
1202
|
+
'S3_3_c9_c14_3':
|
|
1203
|
+
- name: 'PMOVSSET_EL0'
|
|
1181
1204
|
description: 'Performance Monitors Overflow Flag Status Set register'
|
|
1182
|
-
S3_3_c13_c0_2:
|
|
1183
|
-
|
|
1205
|
+
'S3_3_c13_c0_2':
|
|
1206
|
+
- name: 'TPIDR_EL0'
|
|
1184
1207
|
description: 'EL0 Read/Write Software Thread ID Register'
|
|
1185
|
-
S3_3_c13_c0_3:
|
|
1186
|
-
|
|
1208
|
+
'S3_3_c13_c0_3':
|
|
1209
|
+
- name: 'TPIDRRO_EL0'
|
|
1187
1210
|
description: 'EL0 Read-Only Software Thread ID Register'
|
|
1188
|
-
S3_3_c13_c0_7:
|
|
1189
|
-
|
|
1211
|
+
'S3_3_c13_c0_7':
|
|
1212
|
+
- name: 'SCXTNUM_EL0'
|
|
1190
1213
|
description: 'EL0 Read/Write Software Context Number'
|
|
1191
|
-
S3_3_c13_c2_0:
|
|
1192
|
-
|
|
1214
|
+
'S3_3_c13_c2_0':
|
|
1215
|
+
- name: 'AMCR_EL0'
|
|
1193
1216
|
description: 'Activity Monitors Control Register'
|
|
1194
|
-
S3_3_c13_c2_1:
|
|
1195
|
-
|
|
1217
|
+
'S3_3_c13_c2_1':
|
|
1218
|
+
- name: 'AMCFGR_EL0'
|
|
1196
1219
|
description: 'Activity Monitors Configuration Register'
|
|
1197
|
-
S3_3_c13_c2_2:
|
|
1198
|
-
|
|
1220
|
+
'S3_3_c13_c2_2':
|
|
1221
|
+
- name: 'AMCGCR_EL0'
|
|
1199
1222
|
description: 'Activity Monitors Counter Group Configuration Register'
|
|
1200
|
-
S3_3_c13_c2_3:
|
|
1201
|
-
|
|
1223
|
+
'S3_3_c13_c2_3':
|
|
1224
|
+
- name: 'AMUSERENR_EL0'
|
|
1202
1225
|
description: 'Activity Monitors User Enable Register'
|
|
1203
|
-
S3_3_c13_c2_4:
|
|
1204
|
-
|
|
1226
|
+
'S3_3_c13_c2_4':
|
|
1227
|
+
- name: 'AMCNTENCLR0_EL0'
|
|
1205
1228
|
description: 'Activity Monitors Count Enable Clear Register 0'
|
|
1206
|
-
S3_3_c13_c2_5:
|
|
1207
|
-
|
|
1229
|
+
'S3_3_c13_c2_5':
|
|
1230
|
+
- name: 'AMCNTENSET0_EL0'
|
|
1208
1231
|
description: 'Activity Monitors Count Enable Set Register 0'
|
|
1209
|
-
S3_3_c13_c2_6:
|
|
1210
|
-
|
|
1232
|
+
'S3_3_c13_c2_6':
|
|
1233
|
+
- name: 'AMCG1IDR_EL0'
|
|
1211
1234
|
description: 'Activity Monitors Counter Group 1 Identification Register'
|
|
1212
|
-
S3_3_c13_c3_0:
|
|
1213
|
-
|
|
1235
|
+
'S3_3_c13_c3_0':
|
|
1236
|
+
- name: 'AMCNTENCLR1_EL0'
|
|
1214
1237
|
description: 'Activity Monitors Count Enable Clear Register 1'
|
|
1215
|
-
S3_3_c13_c3_1:
|
|
1216
|
-
|
|
1238
|
+
'S3_3_c13_c3_1':
|
|
1239
|
+
- name: 'AMCNTENSET1_EL0'
|
|
1217
1240
|
description: 'Activity Monitors Count Enable Set Register 1'
|
|
1218
|
-
S3_3_c13_c4_0:
|
|
1219
|
-
|
|
1241
|
+
'S3_3_c13_c4_0':
|
|
1242
|
+
- name: 'AMEVCNTR00_EL0'
|
|
1220
1243
|
description: 'Activity Monitors Event Counter Register 0 0'
|
|
1221
|
-
S3_3_c13_c4_1:
|
|
1222
|
-
|
|
1244
|
+
'S3_3_c13_c4_1':
|
|
1245
|
+
- name: 'AMEVCNTR01_EL0'
|
|
1223
1246
|
description: 'Activity Monitors Event Counter Register 0 1'
|
|
1224
|
-
S3_3_c13_c4_2:
|
|
1225
|
-
|
|
1247
|
+
'S3_3_c13_c4_2':
|
|
1248
|
+
- name: 'AMEVCNTR02_EL0'
|
|
1226
1249
|
description: 'Activity Monitors Event Counter Register 0 2'
|
|
1227
|
-
S3_3_c13_c4_3:
|
|
1228
|
-
|
|
1250
|
+
'S3_3_c13_c4_3':
|
|
1251
|
+
- name: 'AMEVCNTR03_EL0'
|
|
1229
1252
|
description: 'Activity Monitors Event Counter Register 0 3'
|
|
1230
|
-
S3_3_c13_c4_4:
|
|
1231
|
-
|
|
1253
|
+
'S3_3_c13_c4_4':
|
|
1254
|
+
- name: 'AMEVCNTR04_EL0'
|
|
1232
1255
|
description: 'Activity Monitors Event Counter Register 0 4'
|
|
1233
|
-
S3_3_c13_c4_5:
|
|
1234
|
-
|
|
1256
|
+
'S3_3_c13_c4_5':
|
|
1257
|
+
- name: 'AMEVCNTR05_EL0'
|
|
1235
1258
|
description: 'Activity Monitors Event Counter Register 0 5'
|
|
1236
|
-
S3_3_c13_c4_6:
|
|
1237
|
-
|
|
1259
|
+
'S3_3_c13_c4_6':
|
|
1260
|
+
- name: 'AMEVCNTR06_EL0'
|
|
1238
1261
|
description: 'Activity Monitors Event Counter Register 0 6'
|
|
1239
|
-
S3_3_c13_c4_7:
|
|
1240
|
-
|
|
1262
|
+
'S3_3_c13_c4_7':
|
|
1263
|
+
- name: 'AMEVCNTR07_EL0'
|
|
1241
1264
|
description: 'Activity Monitors Event Counter Register 0 7'
|
|
1242
|
-
S3_3_c13_c5_0:
|
|
1243
|
-
|
|
1265
|
+
'S3_3_c13_c5_0':
|
|
1266
|
+
- name: 'AMEVCNTR08_EL0'
|
|
1244
1267
|
description: 'Activity Monitors Event Counter Register 0 8'
|
|
1245
|
-
S3_3_c13_c5_1:
|
|
1246
|
-
|
|
1268
|
+
'S3_3_c13_c5_1':
|
|
1269
|
+
- name: 'AMEVCNTR09_EL0'
|
|
1247
1270
|
description: 'Activity Monitors Event Counter Register 0 9'
|
|
1248
|
-
S3_3_c13_c5_2:
|
|
1249
|
-
|
|
1271
|
+
'S3_3_c13_c5_2':
|
|
1272
|
+
- name: 'AMEVCNTR010_EL0'
|
|
1250
1273
|
description: 'Activity Monitors Event Counter Register 0 10'
|
|
1251
|
-
S3_3_c13_c5_3:
|
|
1252
|
-
|
|
1274
|
+
'S3_3_c13_c5_3':
|
|
1275
|
+
- name: 'AMEVCNTR011_EL0'
|
|
1253
1276
|
description: 'Activity Monitors Event Counter Register 0 11'
|
|
1254
|
-
S3_3_c13_c5_4:
|
|
1255
|
-
|
|
1277
|
+
'S3_3_c13_c5_4':
|
|
1278
|
+
- name: 'AMEVCNTR012_EL0'
|
|
1256
1279
|
description: 'Activity Monitors Event Counter Register 0 12'
|
|
1257
|
-
S3_3_c13_c5_5:
|
|
1258
|
-
|
|
1280
|
+
'S3_3_c13_c5_5':
|
|
1281
|
+
- name: 'AMEVCNTR013_EL0'
|
|
1259
1282
|
description: 'Activity Monitors Event Counter Register 0 13'
|
|
1260
|
-
S3_3_c13_c5_6:
|
|
1261
|
-
|
|
1283
|
+
'S3_3_c13_c5_6':
|
|
1284
|
+
- name: 'AMEVCNTR014_EL0'
|
|
1262
1285
|
description: 'Activity Monitors Event Counter Register 0 14'
|
|
1263
|
-
S3_3_c13_c5_7:
|
|
1264
|
-
|
|
1286
|
+
'S3_3_c13_c5_7':
|
|
1287
|
+
- name: 'AMEVCNTR015_EL0'
|
|
1265
1288
|
description: 'Activity Monitors Event Counter Register 0 15'
|
|
1266
|
-
S3_3_c13_c6_0:
|
|
1267
|
-
|
|
1289
|
+
'S3_3_c13_c6_0':
|
|
1290
|
+
- name: 'AMEVTYPER00_EL0'
|
|
1268
1291
|
description: 'Activity Monitors Event Type Register 0 0'
|
|
1269
|
-
S3_3_c13_c6_1:
|
|
1270
|
-
|
|
1292
|
+
'S3_3_c13_c6_1':
|
|
1293
|
+
- name: 'AMEVTYPER01_EL0'
|
|
1271
1294
|
description: 'Activity Monitors Event Type Register 0 1'
|
|
1272
|
-
S3_3_c13_c6_2:
|
|
1273
|
-
|
|
1295
|
+
'S3_3_c13_c6_2':
|
|
1296
|
+
- name: 'AMEVTYPER02_EL0'
|
|
1274
1297
|
description: 'Activity Monitors Event Type Register 0 2'
|
|
1275
|
-
S3_3_c13_c6_3:
|
|
1276
|
-
|
|
1298
|
+
'S3_3_c13_c6_3':
|
|
1299
|
+
- name: 'AMEVTYPER03_EL0'
|
|
1277
1300
|
description: 'Activity Monitors Event Type Register 0 3'
|
|
1278
|
-
S3_3_c13_c6_4:
|
|
1279
|
-
|
|
1301
|
+
'S3_3_c13_c6_4':
|
|
1302
|
+
- name: 'AMEVTYPER04_EL0'
|
|
1280
1303
|
description: 'Activity Monitors Event Type Register 0 4'
|
|
1281
|
-
S3_3_c13_c6_5:
|
|
1282
|
-
|
|
1304
|
+
'S3_3_c13_c6_5':
|
|
1305
|
+
- name: 'AMEVTYPER05_EL0'
|
|
1283
1306
|
description: 'Activity Monitors Event Type Register 0 5'
|
|
1284
|
-
S3_3_c13_c6_6:
|
|
1285
|
-
|
|
1307
|
+
'S3_3_c13_c6_6':
|
|
1308
|
+
- name: 'AMEVTYPER06_EL0'
|
|
1286
1309
|
description: 'Activity Monitors Event Type Register 0 6'
|
|
1287
|
-
S3_3_c13_c6_7:
|
|
1288
|
-
|
|
1310
|
+
'S3_3_c13_c6_7':
|
|
1311
|
+
- name: 'AMEVTYPER07_EL0'
|
|
1289
1312
|
description: 'Activity Monitors Event Type Register 0 7'
|
|
1290
|
-
S3_3_c13_c7_0:
|
|
1291
|
-
|
|
1313
|
+
'S3_3_c13_c7_0':
|
|
1314
|
+
- name: 'AMEVTYPER08_EL0'
|
|
1292
1315
|
description: 'Activity Monitors Event Type Register 0 8'
|
|
1293
|
-
S3_3_c13_c7_1:
|
|
1294
|
-
|
|
1316
|
+
'S3_3_c13_c7_1':
|
|
1317
|
+
- name: 'AMEVTYPER09_EL0'
|
|
1295
1318
|
description: 'Activity Monitors Event Type Register 0 9'
|
|
1296
|
-
S3_3_c13_c7_2:
|
|
1297
|
-
|
|
1319
|
+
'S3_3_c13_c7_2':
|
|
1320
|
+
- name: 'AMEVTYPER010_EL0'
|
|
1298
1321
|
description: 'Activity Monitors Event Type Register 0 10'
|
|
1299
|
-
S3_3_c13_c7_3:
|
|
1300
|
-
|
|
1322
|
+
'S3_3_c13_c7_3':
|
|
1323
|
+
- name: 'AMEVTYPER011_EL0'
|
|
1301
1324
|
description: 'Activity Monitors Event Type Register 0 11'
|
|
1302
|
-
S3_3_c13_c7_4:
|
|
1303
|
-
|
|
1325
|
+
'S3_3_c13_c7_4':
|
|
1326
|
+
- name: 'AMEVTYPER012_EL0'
|
|
1304
1327
|
description: 'Activity Monitors Event Type Register 0 12'
|
|
1305
|
-
S3_3_c13_c7_5:
|
|
1306
|
-
|
|
1328
|
+
'S3_3_c13_c7_5':
|
|
1329
|
+
- name: 'AMEVTYPER013_EL0'
|
|
1307
1330
|
description: 'Activity Monitors Event Type Register 0 13'
|
|
1308
|
-
S3_3_c13_c7_6:
|
|
1309
|
-
|
|
1331
|
+
'S3_3_c13_c7_6':
|
|
1332
|
+
- name: 'AMEVTYPER014_EL0'
|
|
1310
1333
|
description: 'Activity Monitors Event Type Register 0 14'
|
|
1311
|
-
S3_3_c13_c7_7:
|
|
1312
|
-
|
|
1334
|
+
'S3_3_c13_c7_7':
|
|
1335
|
+
- name: 'AMEVTYPER015_EL0'
|
|
1313
1336
|
description: 'Activity Monitors Event Type Register 0 15'
|
|
1314
|
-
S3_3_c13_c12_0:
|
|
1315
|
-
|
|
1337
|
+
'S3_3_c13_c12_0':
|
|
1338
|
+
- name: 'AMEVCNTR10_EL0'
|
|
1316
1339
|
description: 'Activity Monitors Event Counter Register 1 0'
|
|
1317
|
-
S3_3_c13_c12_1:
|
|
1318
|
-
|
|
1340
|
+
'S3_3_c13_c12_1':
|
|
1341
|
+
- name: 'AMEVCNTR11_EL0'
|
|
1319
1342
|
description: 'Activity Monitors Event Counter Register 1 1'
|
|
1320
|
-
S3_3_c13_c12_2:
|
|
1321
|
-
|
|
1343
|
+
'S3_3_c13_c12_2':
|
|
1344
|
+
- name: 'AMEVCNTR12_EL0'
|
|
1322
1345
|
description: 'Activity Monitors Event Counter Register 1 2'
|
|
1323
|
-
S3_3_c13_c12_3:
|
|
1324
|
-
|
|
1346
|
+
'S3_3_c13_c12_3':
|
|
1347
|
+
- name: 'AMEVCNTR13_EL0'
|
|
1325
1348
|
description: 'Activity Monitors Event Counter Register 1 3'
|
|
1326
|
-
S3_3_c13_c12_4:
|
|
1327
|
-
|
|
1349
|
+
'S3_3_c13_c12_4':
|
|
1350
|
+
- name: 'AMEVCNTR14_EL0'
|
|
1328
1351
|
description: 'Activity Monitors Event Counter Register 1 4'
|
|
1329
|
-
S3_3_c13_c12_5:
|
|
1330
|
-
|
|
1352
|
+
'S3_3_c13_c12_5':
|
|
1353
|
+
- name: 'AMEVCNTR15_EL0'
|
|
1331
1354
|
description: 'Activity Monitors Event Counter Register 1 5'
|
|
1332
|
-
S3_3_c13_c12_6:
|
|
1333
|
-
|
|
1355
|
+
'S3_3_c13_c12_6':
|
|
1356
|
+
- name: 'AMEVCNTR16_EL0'
|
|
1334
1357
|
description: 'Activity Monitors Event Counter Register 1 6'
|
|
1335
|
-
S3_3_c13_c12_7:
|
|
1336
|
-
|
|
1358
|
+
'S3_3_c13_c12_7':
|
|
1359
|
+
- name: 'AMEVCNTR17_EL0'
|
|
1337
1360
|
description: 'Activity Monitors Event Counter Register 1 7'
|
|
1338
|
-
S3_3_c13_c13_0:
|
|
1339
|
-
|
|
1361
|
+
'S3_3_c13_c13_0':
|
|
1362
|
+
- name: 'AMEVCNTR18_EL0'
|
|
1340
1363
|
description: 'Activity Monitors Event Counter Register 1 8'
|
|
1341
|
-
S3_3_c13_c13_1:
|
|
1342
|
-
|
|
1364
|
+
'S3_3_c13_c13_1':
|
|
1365
|
+
- name: 'AMEVCNTR19_EL0'
|
|
1343
1366
|
description: 'Activity Monitors Event Counter Register 1 9'
|
|
1344
|
-
S3_3_c13_c13_2:
|
|
1345
|
-
|
|
1367
|
+
'S3_3_c13_c13_2':
|
|
1368
|
+
- name: 'AMEVCNTR110_EL0'
|
|
1346
1369
|
description: 'Activity Monitors Event Counter Register 1 10'
|
|
1347
|
-
S3_3_c13_c13_3:
|
|
1348
|
-
|
|
1370
|
+
'S3_3_c13_c13_3':
|
|
1371
|
+
- name: 'AMEVCNTR111_EL0'
|
|
1349
1372
|
description: 'Activity Monitors Event Counter Register 1 11'
|
|
1350
|
-
S3_3_c13_c13_4:
|
|
1351
|
-
|
|
1373
|
+
'S3_3_c13_c13_4':
|
|
1374
|
+
- name: 'AMEVCNTR112_EL0'
|
|
1352
1375
|
description: 'Activity Monitors Event Counter Register 1 12'
|
|
1353
|
-
S3_3_c13_c13_5:
|
|
1354
|
-
|
|
1376
|
+
'S3_3_c13_c13_5':
|
|
1377
|
+
- name: 'AMEVCNTR113_EL0'
|
|
1355
1378
|
description: 'Activity Monitors Event Counter Register 1 13'
|
|
1356
|
-
S3_3_c13_c13_6:
|
|
1357
|
-
|
|
1379
|
+
'S3_3_c13_c13_6':
|
|
1380
|
+
- name: 'AMEVCNTR114_EL0'
|
|
1358
1381
|
description: 'Activity Monitors Event Counter Register 1 14'
|
|
1359
|
-
S3_3_c13_c13_7:
|
|
1360
|
-
|
|
1382
|
+
'S3_3_c13_c13_7':
|
|
1383
|
+
- name: 'AMEVCNTR115_EL0'
|
|
1361
1384
|
description: 'Activity Monitors Event Counter Register 1 15'
|
|
1362
|
-
S3_3_c13_c14_0:
|
|
1363
|
-
|
|
1385
|
+
'S3_3_c13_c14_0':
|
|
1386
|
+
- name: 'AMEVTYPER10_EL0'
|
|
1364
1387
|
description: 'Activity Monitors Event Type Register 1 0'
|
|
1365
|
-
S3_3_c13_c14_1:
|
|
1366
|
-
|
|
1388
|
+
'S3_3_c13_c14_1':
|
|
1389
|
+
- name: 'AMEVTYPER11_EL0'
|
|
1367
1390
|
description: 'Activity Monitors Event Type Register 1 1'
|
|
1368
|
-
S3_3_c13_c14_2:
|
|
1369
|
-
|
|
1391
|
+
'S3_3_c13_c14_2':
|
|
1392
|
+
- name: 'AMEVTYPER12_EL0'
|
|
1370
1393
|
description: 'Activity Monitors Event Type Register 1 2'
|
|
1371
|
-
S3_3_c13_c14_3:
|
|
1372
|
-
|
|
1394
|
+
'S3_3_c13_c14_3':
|
|
1395
|
+
- name: 'AMEVTYPER13_EL0'
|
|
1373
1396
|
description: 'Activity Monitors Event Type Register 1 3'
|
|
1374
|
-
S3_3_c13_c14_4:
|
|
1375
|
-
|
|
1397
|
+
'S3_3_c13_c14_4':
|
|
1398
|
+
- name: 'AMEVTYPER14_EL0'
|
|
1376
1399
|
description: 'Activity Monitors Event Type Register 1 4'
|
|
1377
|
-
S3_3_c13_c14_5:
|
|
1378
|
-
|
|
1400
|
+
'S3_3_c13_c14_5':
|
|
1401
|
+
- name: 'AMEVTYPER15_EL0'
|
|
1379
1402
|
description: 'Activity Monitors Event Type Register 1 5'
|
|
1380
|
-
S3_3_c13_c14_6:
|
|
1381
|
-
|
|
1403
|
+
'S3_3_c13_c14_6':
|
|
1404
|
+
- name: 'AMEVTYPER16_EL0'
|
|
1382
1405
|
description: 'Activity Monitors Event Type Register 1 6'
|
|
1383
|
-
S3_3_c13_c14_7:
|
|
1384
|
-
|
|
1406
|
+
'S3_3_c13_c14_7':
|
|
1407
|
+
- name: 'AMEVTYPER17_EL0'
|
|
1385
1408
|
description: 'Activity Monitors Event Type Register 1 7'
|
|
1386
|
-
S3_3_c13_c15_0:
|
|
1387
|
-
|
|
1409
|
+
'S3_3_c13_c15_0':
|
|
1410
|
+
- name: 'AMEVTYPER18_EL0'
|
|
1388
1411
|
description: 'Activity Monitors Event Type Register 1 8'
|
|
1389
|
-
S3_3_c13_c15_1:
|
|
1390
|
-
|
|
1412
|
+
'S3_3_c13_c15_1':
|
|
1413
|
+
- name: 'AMEVTYPER19_EL0'
|
|
1391
1414
|
description: 'Activity Monitors Event Type Register 1 9'
|
|
1392
|
-
S3_3_c13_c15_2:
|
|
1393
|
-
|
|
1415
|
+
'S3_3_c13_c15_2':
|
|
1416
|
+
- name: 'AMEVTYPER110_EL0'
|
|
1394
1417
|
description: 'Activity Monitors Event Type Register 1 10'
|
|
1395
|
-
S3_3_c13_c15_3:
|
|
1396
|
-
|
|
1418
|
+
'S3_3_c13_c15_3':
|
|
1419
|
+
- name: 'AMEVTYPER111_EL0'
|
|
1397
1420
|
description: 'Activity Monitors Event Type Register 1 11'
|
|
1398
|
-
S3_3_c13_c15_4:
|
|
1399
|
-
|
|
1421
|
+
'S3_3_c13_c15_4':
|
|
1422
|
+
- name: 'AMEVTYPER112_EL0'
|
|
1400
1423
|
description: 'Activity Monitors Event Type Register 1 12'
|
|
1401
|
-
S3_3_c13_c15_5:
|
|
1402
|
-
|
|
1424
|
+
'S3_3_c13_c15_5':
|
|
1425
|
+
- name: 'AMEVTYPER113_EL0'
|
|
1403
1426
|
description: 'Activity Monitors Event Type Register 1 13'
|
|
1404
|
-
S3_3_c13_c15_6:
|
|
1405
|
-
|
|
1427
|
+
'S3_3_c13_c15_6':
|
|
1428
|
+
- name: 'AMEVTYPER114_EL0'
|
|
1406
1429
|
description: 'Activity Monitors Event Type Register 1 14'
|
|
1407
|
-
S3_3_c13_c15_7:
|
|
1408
|
-
|
|
1430
|
+
'S3_3_c13_c15_7':
|
|
1431
|
+
- name: 'AMEVTYPER115_EL0'
|
|
1409
1432
|
description: 'Activity Monitors Event Type Register 1 15'
|
|
1410
|
-
S3_3_c14_c0_0:
|
|
1411
|
-
|
|
1433
|
+
'S3_3_c14_c0_0':
|
|
1434
|
+
- name: 'CNTFRQ_EL0'
|
|
1412
1435
|
description: 'Counter-timer Frequency register'
|
|
1413
|
-
S3_3_c14_c0_1:
|
|
1414
|
-
|
|
1436
|
+
'S3_3_c14_c0_1':
|
|
1437
|
+
- name: 'CNTPCT_EL0'
|
|
1415
1438
|
description: 'Counter-timer Physical Count register'
|
|
1416
|
-
S3_3_c14_c0_2:
|
|
1417
|
-
|
|
1439
|
+
'S3_3_c14_c0_2':
|
|
1440
|
+
- name: 'CNTVCT_EL0'
|
|
1418
1441
|
description: 'Counter-timer Virtual Count register'
|
|
1419
|
-
S3_3_c14_c0_5:
|
|
1420
|
-
|
|
1442
|
+
'S3_3_c14_c0_5':
|
|
1443
|
+
- name: 'CNTPCTSS_EL0'
|
|
1421
1444
|
description: 'Counter-timer Self-Synchronized Physical Count register'
|
|
1422
|
-
S3_3_c14_c0_6:
|
|
1423
|
-
|
|
1445
|
+
'S3_3_c14_c0_6':
|
|
1446
|
+
- name: 'CNTVCTSS_EL0'
|
|
1424
1447
|
description: 'Counter-timer Self-Synchronized Virtual Count register'
|
|
1425
|
-
S3_3_c14_c2_0:
|
|
1426
|
-
|
|
1448
|
+
'S3_3_c14_c2_0':
|
|
1449
|
+
- name: 'CNTP_TVAL_EL0'
|
|
1427
1450
|
description: 'Counter-timer Physical Timer TimerValue register'
|
|
1428
|
-
S3_3_c14_c2_1:
|
|
1429
|
-
|
|
1451
|
+
'S3_3_c14_c2_1':
|
|
1452
|
+
- name: 'CNTP_CTL_EL0'
|
|
1430
1453
|
description: 'Counter-timer Physical Timer Control register'
|
|
1431
|
-
S3_3_c14_c2_2:
|
|
1432
|
-
|
|
1454
|
+
'S3_3_c14_c2_2':
|
|
1455
|
+
- name: 'CNTP_CVAL_EL0'
|
|
1433
1456
|
description: 'Counter-timer Physical Timer CompareValue register'
|
|
1434
|
-
S3_3_c14_c3_0:
|
|
1435
|
-
|
|
1457
|
+
'S3_3_c14_c3_0':
|
|
1458
|
+
- name: 'CNTV_TVAL_EL0'
|
|
1436
1459
|
description: 'Counter-timer Virtual Timer TimerValue register'
|
|
1437
|
-
S3_3_c14_c3_1:
|
|
1438
|
-
|
|
1460
|
+
'S3_3_c14_c3_1':
|
|
1461
|
+
- name: 'CNTV_CTL_EL0'
|
|
1439
1462
|
description: 'Counter-timer Virtual Timer Control register'
|
|
1440
|
-
S3_3_c14_c3_2:
|
|
1441
|
-
|
|
1463
|
+
'S3_3_c14_c3_2':
|
|
1464
|
+
- name: 'CNTV_CVAL_EL0'
|
|
1442
1465
|
description: 'Counter-timer Virtual Timer CompareValue register'
|
|
1443
|
-
S3_3_c14_c8_0:
|
|
1444
|
-
|
|
1466
|
+
'S3_3_c14_c8_0':
|
|
1467
|
+
- name: 'PMEVCNTR0_EL0'
|
|
1445
1468
|
description: 'Performance Monitors Event Count Register 0'
|
|
1446
|
-
S3_3_c14_c8_1:
|
|
1447
|
-
|
|
1469
|
+
'S3_3_c14_c8_1':
|
|
1470
|
+
- name: 'PMEVCNTR1_EL0'
|
|
1448
1471
|
description: 'Performance Monitors Event Count Register 1'
|
|
1449
|
-
S3_3_c14_c8_2:
|
|
1450
|
-
|
|
1472
|
+
'S3_3_c14_c8_2':
|
|
1473
|
+
- name: 'PMEVCNTR2_EL0'
|
|
1451
1474
|
description: 'Performance Monitors Event Count Register 2'
|
|
1452
|
-
S3_3_c14_c8_3:
|
|
1453
|
-
|
|
1475
|
+
'S3_3_c14_c8_3':
|
|
1476
|
+
- name: 'PMEVCNTR3_EL0'
|
|
1454
1477
|
description: 'Performance Monitors Event Count Register 3'
|
|
1455
|
-
S3_3_c14_c8_4:
|
|
1456
|
-
|
|
1478
|
+
'S3_3_c14_c8_4':
|
|
1479
|
+
- name: 'PMEVCNTR4_EL0'
|
|
1457
1480
|
description: 'Performance Monitors Event Count Register 4'
|
|
1458
|
-
S3_3_c14_c8_5:
|
|
1459
|
-
|
|
1481
|
+
'S3_3_c14_c8_5':
|
|
1482
|
+
- name: 'PMEVCNTR5_EL0'
|
|
1460
1483
|
description: 'Performance Monitors Event Count Register 5'
|
|
1461
|
-
S3_3_c14_c8_6:
|
|
1462
|
-
|
|
1484
|
+
'S3_3_c14_c8_6':
|
|
1485
|
+
- name: 'PMEVCNTR6_EL0'
|
|
1463
1486
|
description: 'Performance Monitors Event Count Register 6'
|
|
1464
|
-
S3_3_c14_c8_7:
|
|
1465
|
-
|
|
1487
|
+
'S3_3_c14_c8_7':
|
|
1488
|
+
- name: 'PMEVCNTR7_EL0'
|
|
1466
1489
|
description: 'Performance Monitors Event Count Register 7'
|
|
1467
|
-
S3_3_c14_c9_0:
|
|
1468
|
-
|
|
1490
|
+
'S3_3_c14_c9_0':
|
|
1491
|
+
- name: 'PMEVCNTR8_EL0'
|
|
1469
1492
|
description: 'Performance Monitors Event Count Register 8'
|
|
1470
|
-
S3_3_c14_c9_1:
|
|
1471
|
-
|
|
1493
|
+
'S3_3_c14_c9_1':
|
|
1494
|
+
- name: 'PMEVCNTR9_EL0'
|
|
1472
1495
|
description: 'Performance Monitors Event Count Register 9'
|
|
1473
|
-
S3_3_c14_c9_2:
|
|
1474
|
-
|
|
1496
|
+
'S3_3_c14_c9_2':
|
|
1497
|
+
- name: 'PMEVCNTR10_EL0'
|
|
1475
1498
|
description: 'Performance Monitors Event Count Register 10'
|
|
1476
|
-
S3_3_c14_c9_3:
|
|
1477
|
-
|
|
1499
|
+
'S3_3_c14_c9_3':
|
|
1500
|
+
- name: 'PMEVCNTR11_EL0'
|
|
1478
1501
|
description: 'Performance Monitors Event Count Register 11'
|
|
1479
|
-
S3_3_c14_c9_4:
|
|
1480
|
-
|
|
1502
|
+
'S3_3_c14_c9_4':
|
|
1503
|
+
- name: 'PMEVCNTR12_EL0'
|
|
1481
1504
|
description: 'Performance Monitors Event Count Register 12'
|
|
1482
|
-
S3_3_c14_c9_5:
|
|
1483
|
-
|
|
1505
|
+
'S3_3_c14_c9_5':
|
|
1506
|
+
- name: 'PMEVCNTR13_EL0'
|
|
1484
1507
|
description: 'Performance Monitors Event Count Register 13'
|
|
1485
|
-
S3_3_c14_c9_6:
|
|
1486
|
-
|
|
1508
|
+
'S3_3_c14_c9_6':
|
|
1509
|
+
- name: 'PMEVCNTR14_EL0'
|
|
1487
1510
|
description: 'Performance Monitors Event Count Register 14'
|
|
1488
|
-
S3_3_c14_c9_7:
|
|
1489
|
-
|
|
1511
|
+
'S3_3_c14_c9_7':
|
|
1512
|
+
- name: 'PMEVCNTR15_EL0'
|
|
1490
1513
|
description: 'Performance Monitors Event Count Register 15'
|
|
1491
|
-
S3_3_c14_c10_0:
|
|
1492
|
-
|
|
1514
|
+
'S3_3_c14_c10_0':
|
|
1515
|
+
- name: 'PMEVCNTR16_EL0'
|
|
1493
1516
|
description: 'Performance Monitors Event Count Register 16'
|
|
1494
|
-
S3_3_c14_c10_1:
|
|
1495
|
-
|
|
1517
|
+
'S3_3_c14_c10_1':
|
|
1518
|
+
- name: 'PMEVCNTR17_EL0'
|
|
1496
1519
|
description: 'Performance Monitors Event Count Register 17'
|
|
1497
|
-
S3_3_c14_c10_2:
|
|
1498
|
-
|
|
1520
|
+
'S3_3_c14_c10_2':
|
|
1521
|
+
- name: 'PMEVCNTR18_EL0'
|
|
1499
1522
|
description: 'Performance Monitors Event Count Register 18'
|
|
1500
|
-
S3_3_c14_c10_3:
|
|
1501
|
-
|
|
1523
|
+
'S3_3_c14_c10_3':
|
|
1524
|
+
- name: 'PMEVCNTR19_EL0'
|
|
1502
1525
|
description: 'Performance Monitors Event Count Register 19'
|
|
1503
|
-
S3_3_c14_c10_4:
|
|
1504
|
-
|
|
1526
|
+
'S3_3_c14_c10_4':
|
|
1527
|
+
- name: 'PMEVCNTR20_EL0'
|
|
1505
1528
|
description: 'Performance Monitors Event Count Register 20'
|
|
1506
|
-
S3_3_c14_c10_5:
|
|
1507
|
-
|
|
1529
|
+
'S3_3_c14_c10_5':
|
|
1530
|
+
- name: 'PMEVCNTR21_EL0'
|
|
1508
1531
|
description: 'Performance Monitors Event Count Register 21'
|
|
1509
|
-
S3_3_c14_c10_6:
|
|
1510
|
-
|
|
1532
|
+
'S3_3_c14_c10_6':
|
|
1533
|
+
- name: 'PMEVCNTR22_EL0'
|
|
1511
1534
|
description: 'Performance Monitors Event Count Register 22'
|
|
1512
|
-
S3_3_c14_c10_7:
|
|
1513
|
-
|
|
1535
|
+
'S3_3_c14_c10_7':
|
|
1536
|
+
- name: 'PMEVCNTR23_EL0'
|
|
1514
1537
|
description: 'Performance Monitors Event Count Register 23'
|
|
1515
|
-
S3_3_c14_c11_0:
|
|
1516
|
-
|
|
1538
|
+
'S3_3_c14_c11_0':
|
|
1539
|
+
- name: 'PMEVCNTR24_EL0'
|
|
1517
1540
|
description: 'Performance Monitors Event Count Register 24'
|
|
1518
|
-
S3_3_c14_c11_1:
|
|
1519
|
-
|
|
1541
|
+
'S3_3_c14_c11_1':
|
|
1542
|
+
- name: 'PMEVCNTR25_EL0'
|
|
1520
1543
|
description: 'Performance Monitors Event Count Register 25'
|
|
1521
|
-
S3_3_c14_c11_2:
|
|
1522
|
-
|
|
1544
|
+
'S3_3_c14_c11_2':
|
|
1545
|
+
- name: 'PMEVCNTR26_EL0'
|
|
1523
1546
|
description: 'Performance Monitors Event Count Register 26'
|
|
1524
|
-
S3_3_c14_c11_3:
|
|
1525
|
-
|
|
1547
|
+
'S3_3_c14_c11_3':
|
|
1548
|
+
- name: 'PMEVCNTR27_EL0'
|
|
1526
1549
|
description: 'Performance Monitors Event Count Register 27'
|
|
1527
|
-
S3_3_c14_c11_4:
|
|
1528
|
-
|
|
1550
|
+
'S3_3_c14_c11_4':
|
|
1551
|
+
- name: 'PMEVCNTR28_EL0'
|
|
1529
1552
|
description: 'Performance Monitors Event Count Register 28'
|
|
1530
|
-
S3_3_c14_c11_5:
|
|
1531
|
-
|
|
1553
|
+
'S3_3_c14_c11_5':
|
|
1554
|
+
- name: 'PMEVCNTR29_EL0'
|
|
1532
1555
|
description: 'Performance Monitors Event Count Register 29'
|
|
1533
|
-
S3_3_c14_c11_6:
|
|
1534
|
-
|
|
1556
|
+
'S3_3_c14_c11_6':
|
|
1557
|
+
- name: 'PMEVCNTR30_EL0'
|
|
1535
1558
|
description: 'Performance Monitors Event Count Register 30'
|
|
1536
|
-
S3_3_c14_c11_7:
|
|
1537
|
-
|
|
1559
|
+
'S3_3_c14_c11_7':
|
|
1560
|
+
- name: 'PMEVCNTR31_EL0'
|
|
1538
1561
|
description: 'Performance Monitors Event Count Register 31'
|
|
1539
|
-
S3_3_c14_c12_0:
|
|
1540
|
-
|
|
1562
|
+
'S3_3_c14_c12_0':
|
|
1563
|
+
- name: 'PMEVTYPER0_EL0'
|
|
1541
1564
|
description: 'Performance Monitors Event Type Register 0'
|
|
1542
|
-
S3_3_c14_c12_1:
|
|
1543
|
-
|
|
1565
|
+
'S3_3_c14_c12_1':
|
|
1566
|
+
- name: 'PMEVTYPER1_EL0'
|
|
1544
1567
|
description: 'Performance Monitors Event Type Register 1'
|
|
1545
|
-
S3_3_c14_c12_2:
|
|
1546
|
-
|
|
1568
|
+
'S3_3_c14_c12_2':
|
|
1569
|
+
- name: 'PMEVTYPER2_EL0'
|
|
1547
1570
|
description: 'Performance Monitors Event Type Register 2'
|
|
1548
|
-
S3_3_c14_c12_3:
|
|
1549
|
-
|
|
1571
|
+
'S3_3_c14_c12_3':
|
|
1572
|
+
- name: 'PMEVTYPER3_EL0'
|
|
1550
1573
|
description: 'Performance Monitors Event Type Register 3'
|
|
1551
|
-
S3_3_c14_c12_4:
|
|
1552
|
-
|
|
1574
|
+
'S3_3_c14_c12_4':
|
|
1575
|
+
- name: 'PMEVTYPER4_EL0'
|
|
1553
1576
|
description: 'Performance Monitors Event Type Register 4'
|
|
1554
|
-
S3_3_c14_c12_5:
|
|
1555
|
-
|
|
1577
|
+
'S3_3_c14_c12_5':
|
|
1578
|
+
- name: 'PMEVTYPER5_EL0'
|
|
1556
1579
|
description: 'Performance Monitors Event Type Register 5'
|
|
1557
|
-
S3_3_c14_c12_6:
|
|
1558
|
-
|
|
1580
|
+
'S3_3_c14_c12_6':
|
|
1581
|
+
- name: 'PMEVTYPER6_EL0'
|
|
1559
1582
|
description: 'Performance Monitors Event Type Register 6'
|
|
1560
|
-
S3_3_c14_c12_7:
|
|
1561
|
-
|
|
1583
|
+
'S3_3_c14_c12_7':
|
|
1584
|
+
- name: 'PMEVTYPER7_EL0'
|
|
1562
1585
|
description: 'Performance Monitors Event Type Register 7'
|
|
1563
|
-
S3_3_c14_c13_0:
|
|
1564
|
-
|
|
1586
|
+
'S3_3_c14_c13_0':
|
|
1587
|
+
- name: 'PMEVTYPER8_EL0'
|
|
1565
1588
|
description: 'Performance Monitors Event Type Register 8'
|
|
1566
|
-
S3_3_c14_c13_1:
|
|
1567
|
-
|
|
1589
|
+
'S3_3_c14_c13_1':
|
|
1590
|
+
- name: 'PMEVTYPER9_EL0'
|
|
1568
1591
|
description: 'Performance Monitors Event Type Register 9'
|
|
1569
|
-
S3_3_c14_c13_2:
|
|
1570
|
-
|
|
1592
|
+
'S3_3_c14_c13_2':
|
|
1593
|
+
- name: 'PMEVTYPER10_EL0'
|
|
1571
1594
|
description: 'Performance Monitors Event Type Register 10'
|
|
1572
|
-
S3_3_c14_c13_3:
|
|
1573
|
-
|
|
1595
|
+
'S3_3_c14_c13_3':
|
|
1596
|
+
- name: 'PMEVTYPER11_EL0'
|
|
1574
1597
|
description: 'Performance Monitors Event Type Register 11'
|
|
1575
|
-
S3_3_c14_c13_4:
|
|
1576
|
-
|
|
1598
|
+
'S3_3_c14_c13_4':
|
|
1599
|
+
- name: 'PMEVTYPER12_EL0'
|
|
1577
1600
|
description: 'Performance Monitors Event Type Register 12'
|
|
1578
|
-
S3_3_c14_c13_5:
|
|
1579
|
-
|
|
1601
|
+
'S3_3_c14_c13_5':
|
|
1602
|
+
- name: 'PMEVTYPER13_EL0'
|
|
1580
1603
|
description: 'Performance Monitors Event Type Register 13'
|
|
1581
|
-
S3_3_c14_c13_6:
|
|
1582
|
-
|
|
1604
|
+
'S3_3_c14_c13_6':
|
|
1605
|
+
- name: 'PMEVTYPER14_EL0'
|
|
1583
1606
|
description: 'Performance Monitors Event Type Register 14'
|
|
1584
|
-
S3_3_c14_c13_7:
|
|
1585
|
-
|
|
1607
|
+
'S3_3_c14_c13_7':
|
|
1608
|
+
- name: 'PMEVTYPER15_EL0'
|
|
1586
1609
|
description: 'Performance Monitors Event Type Register 15'
|
|
1587
|
-
S3_3_c14_c14_0:
|
|
1588
|
-
|
|
1610
|
+
'S3_3_c14_c14_0':
|
|
1611
|
+
- name: 'PMEVTYPER16_EL0'
|
|
1589
1612
|
description: 'Performance Monitors Event Type Register 16'
|
|
1590
|
-
S3_3_c14_c14_1:
|
|
1591
|
-
|
|
1613
|
+
'S3_3_c14_c14_1':
|
|
1614
|
+
- name: 'PMEVTYPER17_EL0'
|
|
1592
1615
|
description: 'Performance Monitors Event Type Register 17'
|
|
1593
|
-
S3_3_c14_c14_2:
|
|
1594
|
-
|
|
1616
|
+
'S3_3_c14_c14_2':
|
|
1617
|
+
- name: 'PMEVTYPER18_EL0'
|
|
1595
1618
|
description: 'Performance Monitors Event Type Register 18'
|
|
1596
|
-
S3_3_c14_c14_3:
|
|
1597
|
-
|
|
1619
|
+
'S3_3_c14_c14_3':
|
|
1620
|
+
- name: 'PMEVTYPER19_EL0'
|
|
1598
1621
|
description: 'Performance Monitors Event Type Register 19'
|
|
1599
|
-
S3_3_c14_c14_4:
|
|
1600
|
-
|
|
1622
|
+
'S3_3_c14_c14_4':
|
|
1623
|
+
- name: 'PMEVTYPER20_EL0'
|
|
1601
1624
|
description: 'Performance Monitors Event Type Register 20'
|
|
1602
|
-
S3_3_c14_c14_5:
|
|
1603
|
-
|
|
1625
|
+
'S3_3_c14_c14_5':
|
|
1626
|
+
- name: 'PMEVTYPER21_EL0'
|
|
1604
1627
|
description: 'Performance Monitors Event Type Register 21'
|
|
1605
|
-
S3_3_c14_c14_6:
|
|
1606
|
-
|
|
1628
|
+
'S3_3_c14_c14_6':
|
|
1629
|
+
- name: 'PMEVTYPER22_EL0'
|
|
1607
1630
|
description: 'Performance Monitors Event Type Register 22'
|
|
1608
|
-
S3_3_c14_c14_7:
|
|
1609
|
-
|
|
1631
|
+
'S3_3_c14_c14_7':
|
|
1632
|
+
- name: 'PMEVTYPER23_EL0'
|
|
1610
1633
|
description: 'Performance Monitors Event Type Register 23'
|
|
1611
|
-
S3_3_c14_c15_0:
|
|
1612
|
-
|
|
1634
|
+
'S3_3_c14_c15_0':
|
|
1635
|
+
- name: 'PMEVTYPER24_EL0'
|
|
1613
1636
|
description: 'Performance Monitors Event Type Register 24'
|
|
1614
|
-
S3_3_c14_c15_1:
|
|
1615
|
-
|
|
1637
|
+
'S3_3_c14_c15_1':
|
|
1638
|
+
- name: 'PMEVTYPER25_EL0'
|
|
1616
1639
|
description: 'Performance Monitors Event Type Register 25'
|
|
1617
|
-
S3_3_c14_c15_2:
|
|
1618
|
-
|
|
1640
|
+
'S3_3_c14_c15_2':
|
|
1641
|
+
- name: 'PMEVTYPER26_EL0'
|
|
1619
1642
|
description: 'Performance Monitors Event Type Register 26'
|
|
1620
|
-
S3_3_c14_c15_3:
|
|
1621
|
-
|
|
1643
|
+
'S3_3_c14_c15_3':
|
|
1644
|
+
- name: 'PMEVTYPER27_EL0'
|
|
1622
1645
|
description: 'Performance Monitors Event Type Register 27'
|
|
1623
|
-
S3_3_c14_c15_4:
|
|
1624
|
-
|
|
1646
|
+
'S3_3_c14_c15_4':
|
|
1647
|
+
- name: 'PMEVTYPER28_EL0'
|
|
1625
1648
|
description: 'Performance Monitors Event Type Register 28'
|
|
1626
|
-
S3_3_c14_c15_5:
|
|
1627
|
-
|
|
1649
|
+
'S3_3_c14_c15_5':
|
|
1650
|
+
- name: 'PMEVTYPER29_EL0'
|
|
1628
1651
|
description: 'Performance Monitors Event Type Register 29'
|
|
1629
|
-
S3_3_c14_c15_6:
|
|
1630
|
-
|
|
1652
|
+
'S3_3_c14_c15_6':
|
|
1653
|
+
- name: 'PMEVTYPER30_EL0'
|
|
1631
1654
|
description: 'Performance Monitors Event Type Register 30'
|
|
1632
|
-
S3_3_c14_c15_7:
|
|
1633
|
-
|
|
1634
|
-
description: Performance Monitors Cycle Count Filter Register
|
|
1635
|
-
|
|
1636
|
-
|
|
1637
|
-
|
|
1655
|
+
'S3_3_c14_c15_7':
|
|
1656
|
+
- name: 'PMCCFILTR_EL0'
|
|
1657
|
+
description: 'Performance Monitors Cycle Count Filter Register'
|
|
1658
|
+
- name: 'PMEVTYPER31_EL0'
|
|
1659
|
+
description: 'Performance Monitors Event Type Register 31'
|
|
1660
|
+
'S3_4_c0_c0_0':
|
|
1661
|
+
- name: 'VPIDR_EL2'
|
|
1638
1662
|
description: 'Virtualization Processor ID Register'
|
|
1639
|
-
S3_4_c0_c0_5:
|
|
1640
|
-
|
|
1663
|
+
'S3_4_c0_c0_5':
|
|
1664
|
+
- name: 'VMPIDR_EL2'
|
|
1641
1665
|
description: 'Virtualization Multiprocessor ID Register'
|
|
1642
|
-
S3_4_c1_c0_0:
|
|
1643
|
-
|
|
1666
|
+
'S3_4_c1_c0_0':
|
|
1667
|
+
- name: 'SCTLR_EL2'
|
|
1644
1668
|
description: 'System Control Register (EL2)'
|
|
1645
|
-
S3_4_c1_c0_1:
|
|
1646
|
-
|
|
1669
|
+
'S3_4_c1_c0_1':
|
|
1670
|
+
- name: 'ACTLR_EL2'
|
|
1647
1671
|
description: 'Auxiliary Control Register (EL2)'
|
|
1648
|
-
S3_4_c1_c1_0:
|
|
1649
|
-
|
|
1672
|
+
'S3_4_c1_c1_0':
|
|
1673
|
+
- name: 'HCR_EL2'
|
|
1650
1674
|
description: 'Hypervisor Configuration Register'
|
|
1651
|
-
S3_4_c1_c1_1:
|
|
1652
|
-
|
|
1675
|
+
'S3_4_c1_c1_1':
|
|
1676
|
+
- name: 'MDCR_EL2'
|
|
1653
1677
|
description: 'Monitor Debug Configuration Register (EL2)'
|
|
1654
|
-
S3_4_c1_c1_2:
|
|
1655
|
-
|
|
1678
|
+
'S3_4_c1_c1_2':
|
|
1679
|
+
- name: 'CPTR_EL2'
|
|
1656
1680
|
description: 'Architectural Feature Trap Register (EL2)'
|
|
1657
|
-
S3_4_c1_c1_3:
|
|
1658
|
-
|
|
1681
|
+
'S3_4_c1_c1_3':
|
|
1682
|
+
- name: 'HSTR_EL2'
|
|
1659
1683
|
description: 'Hypervisor System Trap Register'
|
|
1660
|
-
S3_4_c1_c1_4:
|
|
1661
|
-
|
|
1684
|
+
'S3_4_c1_c1_4':
|
|
1685
|
+
- name: 'HFGRTR_EL2'
|
|
1662
1686
|
description: 'Hypervisor Fine-Grained Read Trap Register'
|
|
1663
|
-
S3_4_c1_c1_5:
|
|
1664
|
-
|
|
1687
|
+
'S3_4_c1_c1_5':
|
|
1688
|
+
- name: 'HFGWTR_EL2'
|
|
1665
1689
|
description: 'Hypervisor Fine-Grained Write Trap Register'
|
|
1666
|
-
S3_4_c1_c1_6:
|
|
1667
|
-
|
|
1690
|
+
'S3_4_c1_c1_6':
|
|
1691
|
+
- name: 'HFGITR_EL2'
|
|
1668
1692
|
description: 'Hypervisor Fine-Grained Instruction Trap Register'
|
|
1669
|
-
S3_4_c1_c1_7:
|
|
1670
|
-
|
|
1693
|
+
'S3_4_c1_c1_7':
|
|
1694
|
+
- name: 'HACR_EL2'
|
|
1671
1695
|
description: 'Hypervisor Auxiliary Control Register'
|
|
1672
|
-
S3_4_c1_c2_0:
|
|
1673
|
-
|
|
1696
|
+
'S3_4_c1_c2_0':
|
|
1697
|
+
- name: 'ZCR_EL2'
|
|
1674
1698
|
description: 'SVE Control Register for EL2'
|
|
1675
|
-
S3_4_c1_c2_1:
|
|
1676
|
-
|
|
1699
|
+
'S3_4_c1_c2_1':
|
|
1700
|
+
- name: 'TRFCR_EL2'
|
|
1677
1701
|
description: 'Trace Filter Control Register (EL2)'
|
|
1678
|
-
S3_4_c1_c3_1:
|
|
1679
|
-
|
|
1702
|
+
'S3_4_c1_c3_1':
|
|
1703
|
+
- name: 'SDER32_EL2'
|
|
1680
1704
|
description: 'AArch32 Secure Debug Enable Register'
|
|
1681
|
-
S3_4_c2_c0_0:
|
|
1682
|
-
|
|
1705
|
+
'S3_4_c2_c0_0':
|
|
1706
|
+
- name: 'TTBR0_EL2'
|
|
1683
1707
|
description: 'Translation Table Base Register 0 (EL2)'
|
|
1684
|
-
S3_4_c2_c0_1:
|
|
1685
|
-
|
|
1708
|
+
'S3_4_c2_c0_1':
|
|
1709
|
+
- name: 'TTBR1_EL2'
|
|
1686
1710
|
description: 'Translation Table Base Register 1 (EL2)'
|
|
1687
|
-
S3_4_c2_c0_2:
|
|
1688
|
-
|
|
1711
|
+
'S3_4_c2_c0_2':
|
|
1712
|
+
- name: 'TCR_EL2'
|
|
1689
1713
|
description: 'Translation Control Register (EL2)'
|
|
1690
|
-
S3_4_c2_c1_0:
|
|
1691
|
-
|
|
1714
|
+
'S3_4_c2_c1_0':
|
|
1715
|
+
- name: 'VTTBR_EL2'
|
|
1692
1716
|
description: 'Virtualization Translation Table Base Register'
|
|
1693
|
-
S3_4_c2_c1_2:
|
|
1694
|
-
|
|
1717
|
+
'S3_4_c2_c1_2':
|
|
1718
|
+
- name: 'VTCR_EL2'
|
|
1695
1719
|
description: 'Virtualization Translation Control Register'
|
|
1696
|
-
S3_4_c2_c2_0:
|
|
1697
|
-
|
|
1720
|
+
'S3_4_c2_c2_0':
|
|
1721
|
+
- name: 'VNCR_EL2'
|
|
1698
1722
|
description: 'Virtual Nested Control Register'
|
|
1699
|
-
S3_4_c2_c6_0:
|
|
1700
|
-
|
|
1723
|
+
'S3_4_c2_c6_0':
|
|
1724
|
+
- name: 'VSTTBR_EL2'
|
|
1701
1725
|
description: 'Virtualization Secure Translation Table Base Register'
|
|
1702
|
-
S3_4_c2_c6_2:
|
|
1703
|
-
|
|
1726
|
+
'S3_4_c2_c6_2':
|
|
1727
|
+
- name: 'VSTCR_EL2'
|
|
1704
1728
|
description: 'Virtualization Secure Translation Control Register'
|
|
1705
|
-
S3_4_c3_c0_0:
|
|
1706
|
-
|
|
1729
|
+
'S3_4_c3_c0_0':
|
|
1730
|
+
- name: 'DACR32_EL2'
|
|
1707
1731
|
description: 'Domain Access Control Register'
|
|
1708
|
-
S3_4_c3_c1_4:
|
|
1709
|
-
|
|
1732
|
+
'S3_4_c3_c1_4':
|
|
1733
|
+
- name: 'HDFGRTR_EL2'
|
|
1710
1734
|
description: 'Hypervisor Debug Fine-Grained Read Trap Register'
|
|
1711
|
-
S3_4_c3_c1_5:
|
|
1712
|
-
|
|
1735
|
+
'S3_4_c3_c1_5':
|
|
1736
|
+
- name: 'HDFGWTR_EL2'
|
|
1713
1737
|
description: 'Hypervisor Debug Fine-Grained Write Trap Register'
|
|
1714
|
-
S3_4_c3_c1_6:
|
|
1715
|
-
|
|
1738
|
+
'S3_4_c3_c1_6':
|
|
1739
|
+
- name: 'HAFGRTR_EL2'
|
|
1716
1740
|
description: 'Hypervisor Activity Monitors Fine-Grained Read Trap Register'
|
|
1717
|
-
S3_4_c4_c0_0:
|
|
1718
|
-
|
|
1741
|
+
'S3_4_c4_c0_0':
|
|
1742
|
+
- name: 'SPSR_EL2'
|
|
1719
1743
|
description: 'Saved Program Status Register (EL2)'
|
|
1720
|
-
S3_4_c4_c0_1:
|
|
1721
|
-
|
|
1744
|
+
'S3_4_c4_c0_1':
|
|
1745
|
+
- name: 'ELR_EL2'
|
|
1722
1746
|
description: 'Exception Link Register (EL2)'
|
|
1723
|
-
S3_4_c4_c1_0:
|
|
1724
|
-
|
|
1747
|
+
'S3_4_c4_c1_0':
|
|
1748
|
+
- name: 'SP_EL1'
|
|
1725
1749
|
description: 'Stack Pointer (EL1)'
|
|
1726
|
-
S3_4_c4_c3_0:
|
|
1727
|
-
|
|
1750
|
+
'S3_4_c4_c3_0':
|
|
1751
|
+
- name: 'SPSR_irq'
|
|
1728
1752
|
description: 'Saved Program Status Register (IRQ mode)'
|
|
1729
|
-
S3_4_c4_c3_1:
|
|
1730
|
-
|
|
1753
|
+
'S3_4_c4_c3_1':
|
|
1754
|
+
- name: 'SPSR_abt'
|
|
1731
1755
|
description: 'Saved Program Status Register (Abort mode)'
|
|
1732
|
-
S3_4_c4_c3_2:
|
|
1733
|
-
|
|
1756
|
+
'S3_4_c4_c3_2':
|
|
1757
|
+
- name: 'SPSR_und'
|
|
1734
1758
|
description: 'Saved Program Status Register (Undefined mode)'
|
|
1735
|
-
S3_4_c4_c3_3:
|
|
1736
|
-
|
|
1759
|
+
'S3_4_c4_c3_3':
|
|
1760
|
+
- name: 'SPSR_fiq'
|
|
1737
1761
|
description: 'Saved Program Status Register (FIQ mode)'
|
|
1738
|
-
S3_4_c5_c0_1:
|
|
1739
|
-
|
|
1762
|
+
'S3_4_c5_c0_1':
|
|
1763
|
+
- name: 'IFSR32_EL2'
|
|
1740
1764
|
description: 'Instruction Fault Status Register (EL2)'
|
|
1741
|
-
S3_4_c5_c1_0:
|
|
1742
|
-
|
|
1765
|
+
'S3_4_c5_c1_0':
|
|
1766
|
+
- name: 'AFSR0_EL2'
|
|
1743
1767
|
description: 'Auxiliary Fault Status Register 0 (EL2)'
|
|
1744
|
-
S3_4_c5_c1_1:
|
|
1745
|
-
|
|
1768
|
+
'S3_4_c5_c1_1':
|
|
1769
|
+
- name: 'AFSR1_EL2'
|
|
1746
1770
|
description: 'Auxiliary Fault Status Register 1 (EL2)'
|
|
1747
|
-
S3_4_c5_c2_0:
|
|
1748
|
-
|
|
1771
|
+
'S3_4_c5_c2_0':
|
|
1772
|
+
- name: 'ESR_EL2'
|
|
1749
1773
|
description: 'Exception Syndrome Register (EL2)'
|
|
1750
|
-
S3_4_c5_c2_3:
|
|
1751
|
-
|
|
1774
|
+
'S3_4_c5_c2_3':
|
|
1775
|
+
- name: 'VSESR_EL2'
|
|
1752
1776
|
description: 'Virtual SError Exception Syndrome Register'
|
|
1753
|
-
S3_4_c5_c3_0:
|
|
1754
|
-
|
|
1777
|
+
'S3_4_c5_c3_0':
|
|
1778
|
+
- name: 'FPEXC32_EL2'
|
|
1755
1779
|
description: 'Floating-Point Exception Control register'
|
|
1756
|
-
S3_4_c5_c6_0:
|
|
1757
|
-
|
|
1780
|
+
'S3_4_c5_c6_0':
|
|
1781
|
+
- name: 'TFSR_EL2'
|
|
1758
1782
|
description: 'Tag Fault Status Register (EL2)'
|
|
1759
|
-
S3_4_c6_c0_0:
|
|
1760
|
-
|
|
1783
|
+
'S3_4_c6_c0_0':
|
|
1784
|
+
- name: 'FAR_EL2'
|
|
1761
1785
|
description: 'Fault Address Register (EL2)'
|
|
1762
|
-
S3_4_c6_c0_4:
|
|
1763
|
-
|
|
1786
|
+
'S3_4_c6_c0_4':
|
|
1787
|
+
- name: 'HPFAR_EL2'
|
|
1764
1788
|
description: 'Hypervisor IPA Fault Address Register'
|
|
1765
|
-
S3_4_c9_c9_0:
|
|
1766
|
-
|
|
1789
|
+
'S3_4_c9_c9_0':
|
|
1790
|
+
- name: 'PMSCR_EL2'
|
|
1767
1791
|
description: 'Statistical Profiling Control Register (EL2)'
|
|
1768
|
-
S3_4_c10_c2_0:
|
|
1769
|
-
|
|
1792
|
+
'S3_4_c10_c2_0':
|
|
1793
|
+
- name: 'MAIR_EL2'
|
|
1770
1794
|
description: 'Memory Attribute Indirection Register (EL2)'
|
|
1771
|
-
S3_4_c10_c3_0:
|
|
1772
|
-
|
|
1795
|
+
'S3_4_c10_c3_0':
|
|
1796
|
+
- name: 'AMAIR_EL2'
|
|
1773
1797
|
description: 'Auxiliary Memory Attribute Indirection Register (EL2)'
|
|
1774
|
-
S3_4_c10_c4_0:
|
|
1775
|
-
|
|
1798
|
+
'S3_4_c10_c4_0':
|
|
1799
|
+
- name: 'MPAMHCR_EL2'
|
|
1776
1800
|
description: 'MPAM Hypervisor Control Register (EL2)'
|
|
1777
|
-
S3_4_c10_c4_1:
|
|
1778
|
-
|
|
1801
|
+
'S3_4_c10_c4_1':
|
|
1802
|
+
- name: 'MPAMVPMV_EL2'
|
|
1779
1803
|
description: 'MPAM Virtual Partition Mapping Valid Register'
|
|
1780
|
-
S3_4_c10_c5_0:
|
|
1781
|
-
|
|
1804
|
+
'S3_4_c10_c5_0':
|
|
1805
|
+
- name: 'MPAM2_EL2'
|
|
1782
1806
|
description: 'MPAM2 Register (EL2)'
|
|
1783
|
-
S3_4_c10_c6_0:
|
|
1784
|
-
|
|
1807
|
+
'S3_4_c10_c6_0':
|
|
1808
|
+
- name: 'MPAMVPM0_EL2'
|
|
1785
1809
|
description: 'MPAM Virtual PARTID Mapping Register 0'
|
|
1786
|
-
S3_4_c10_c6_1:
|
|
1787
|
-
|
|
1810
|
+
'S3_4_c10_c6_1':
|
|
1811
|
+
- name: 'MPAMVPM1_EL2'
|
|
1788
1812
|
description: 'MPAM Virtual PARTID Mapping Register 1'
|
|
1789
|
-
S3_4_c10_c6_2:
|
|
1790
|
-
|
|
1813
|
+
'S3_4_c10_c6_2':
|
|
1814
|
+
- name: 'MPAMVPM2_EL2'
|
|
1791
1815
|
description: 'MPAM Virtual PARTID Mapping Register 2'
|
|
1792
|
-
S3_4_c10_c6_3:
|
|
1793
|
-
|
|
1816
|
+
'S3_4_c10_c6_3':
|
|
1817
|
+
- name: 'MPAMVPM3_EL2'
|
|
1794
1818
|
description: 'MPAM Virtual PARTID Mapping Register 3'
|
|
1795
|
-
S3_4_c10_c6_4:
|
|
1796
|
-
|
|
1819
|
+
'S3_4_c10_c6_4':
|
|
1820
|
+
- name: 'MPAMVPM4_EL2'
|
|
1797
1821
|
description: 'MPAM Virtual PARTID Mapping Register 4'
|
|
1798
|
-
S3_4_c10_c6_5:
|
|
1799
|
-
|
|
1822
|
+
'S3_4_c10_c6_5':
|
|
1823
|
+
- name: 'MPAMVPM5_EL2'
|
|
1800
1824
|
description: 'MPAM Virtual PARTID Mapping Register 5'
|
|
1801
|
-
S3_4_c10_c6_6:
|
|
1802
|
-
|
|
1825
|
+
'S3_4_c10_c6_6':
|
|
1826
|
+
- name: 'MPAMVPM6_EL2'
|
|
1803
1827
|
description: 'MPAM Virtual PARTID Mapping Register 6'
|
|
1804
|
-
S3_4_c10_c6_7:
|
|
1805
|
-
|
|
1828
|
+
'S3_4_c10_c6_7':
|
|
1829
|
+
- name: 'MPAMVPM7_EL2'
|
|
1806
1830
|
description: 'MPAM Virtual PARTID Mapping Register 7'
|
|
1807
|
-
S3_4_c12_c0_0:
|
|
1808
|
-
|
|
1831
|
+
'S3_4_c12_c0_0':
|
|
1832
|
+
- name: 'VBAR_EL2'
|
|
1809
1833
|
description: 'Vector Base Address Register (EL2)'
|
|
1810
|
-
S3_4_c12_c0_1:
|
|
1811
|
-
|
|
1834
|
+
'S3_4_c12_c0_1':
|
|
1835
|
+
- name: 'RVBAR_EL2'
|
|
1812
1836
|
description: 'Reset Vector Base Address Register (if EL3 not implemented)'
|
|
1813
|
-
S3_4_c12_c0_2:
|
|
1814
|
-
|
|
1837
|
+
'S3_4_c12_c0_2':
|
|
1838
|
+
- name: 'RMR_EL2'
|
|
1815
1839
|
description: 'Reset Management Register (EL2)'
|
|
1816
|
-
S3_4_c12_c1_1:
|
|
1817
|
-
|
|
1840
|
+
'S3_4_c12_c1_1':
|
|
1841
|
+
- name: 'VDISR_EL2'
|
|
1818
1842
|
description: 'Virtual Deferred Interrupt Status Register'
|
|
1819
|
-
S3_4_c12_c8_0:
|
|
1820
|
-
|
|
1843
|
+
'S3_4_c12_c8_0':
|
|
1844
|
+
- name: 'ICH_AP0R0_EL2'
|
|
1821
1845
|
description: 'Interrupt Controller Hyp Active Priorities Group 0 Register 0'
|
|
1822
|
-
S3_4_c12_c8_1:
|
|
1823
|
-
|
|
1846
|
+
'S3_4_c12_c8_1':
|
|
1847
|
+
- name: 'ICH_AP0R1_EL2'
|
|
1824
1848
|
description: 'Interrupt Controller Hyp Active Priorities Group 0 Register 1'
|
|
1825
|
-
S3_4_c12_c8_2:
|
|
1826
|
-
|
|
1849
|
+
'S3_4_c12_c8_2':
|
|
1850
|
+
- name: 'ICH_AP0R2_EL2'
|
|
1827
1851
|
description: 'Interrupt Controller Hyp Active Priorities Group 0 Register 2'
|
|
1828
|
-
S3_4_c12_c8_3:
|
|
1829
|
-
|
|
1852
|
+
'S3_4_c12_c8_3':
|
|
1853
|
+
- name: 'ICH_AP0R3_EL2'
|
|
1830
1854
|
description: 'Interrupt Controller Hyp Active Priorities Group 0 Register 3'
|
|
1831
|
-
S3_4_c12_c9_0:
|
|
1832
|
-
|
|
1855
|
+
'S3_4_c12_c9_0':
|
|
1856
|
+
- name: 'ICH_AP1R0_EL2'
|
|
1833
1857
|
description: 'Interrupt Controller Hyp Active Priorities Group 1 Register 0'
|
|
1834
|
-
S3_4_c12_c9_1:
|
|
1835
|
-
|
|
1858
|
+
'S3_4_c12_c9_1':
|
|
1859
|
+
- name: 'ICH_AP1R1_EL2'
|
|
1836
1860
|
description: 'Interrupt Controller Hyp Active Priorities Group 1 Register 1'
|
|
1837
|
-
S3_4_c12_c9_2:
|
|
1838
|
-
|
|
1861
|
+
'S3_4_c12_c9_2':
|
|
1862
|
+
- name: 'ICH_AP1R2_EL2'
|
|
1839
1863
|
description: 'Interrupt Controller Hyp Active Priorities Group 1 Register 2'
|
|
1840
|
-
S3_4_c12_c9_3:
|
|
1841
|
-
|
|
1864
|
+
'S3_4_c12_c9_3':
|
|
1865
|
+
- name: 'ICH_AP1R3_EL2'
|
|
1842
1866
|
description: 'Interrupt Controller Hyp Active Priorities Group 1 Register 3'
|
|
1843
|
-
S3_4_c12_c9_5:
|
|
1844
|
-
|
|
1867
|
+
'S3_4_c12_c9_5':
|
|
1868
|
+
- name: 'ICC_SRE_EL2'
|
|
1845
1869
|
description: 'Interrupt Controller System Register Enable register (EL2)'
|
|
1846
|
-
S3_4_c12_c11_0:
|
|
1847
|
-
|
|
1870
|
+
'S3_4_c12_c11_0':
|
|
1871
|
+
- name: 'ICH_HCR_EL2'
|
|
1848
1872
|
description: 'Interrupt Controller Hyp Control Register'
|
|
1849
|
-
S3_4_c12_c11_1:
|
|
1850
|
-
|
|
1873
|
+
'S3_4_c12_c11_1':
|
|
1874
|
+
- name: 'ICH_VTR_EL2'
|
|
1851
1875
|
description: 'Interrupt Controller VGIC Type Register'
|
|
1852
|
-
S3_4_c12_c11_2:
|
|
1853
|
-
|
|
1876
|
+
'S3_4_c12_c11_2':
|
|
1877
|
+
- name: 'ICH_MISR_EL2'
|
|
1854
1878
|
description: 'Interrupt Controller Maintenance Interrupt State Register'
|
|
1855
|
-
S3_4_c12_c11_3:
|
|
1856
|
-
|
|
1879
|
+
'S3_4_c12_c11_3':
|
|
1880
|
+
- name: 'ICH_EISR_EL2'
|
|
1857
1881
|
description: 'Interrupt Controller End of Interrupt Status Register'
|
|
1858
|
-
S3_4_c12_c11_5:
|
|
1859
|
-
|
|
1882
|
+
'S3_4_c12_c11_5':
|
|
1883
|
+
- name: 'ICH_ELRSR_EL2'
|
|
1860
1884
|
description: 'Interrupt Controller Empty List Register Status Register'
|
|
1861
|
-
S3_4_c12_c11_7:
|
|
1862
|
-
|
|
1885
|
+
'S3_4_c12_c11_7':
|
|
1886
|
+
- name: 'ICH_VMCR_EL2'
|
|
1863
1887
|
description: 'Interrupt Controller Virtual Machine Control Register'
|
|
1864
|
-
S3_4_c12_c12_0:
|
|
1865
|
-
|
|
1888
|
+
'S3_4_c12_c12_0':
|
|
1889
|
+
- name: 'ICH_LR0_EL2'
|
|
1866
1890
|
description: 'Interrupt Controller List Register 0'
|
|
1867
|
-
S3_4_c12_c12_1:
|
|
1868
|
-
|
|
1891
|
+
'S3_4_c12_c12_1':
|
|
1892
|
+
- name: 'ICH_LR1_EL2'
|
|
1869
1893
|
description: 'Interrupt Controller List Register 1'
|
|
1870
|
-
S3_4_c12_c12_2:
|
|
1871
|
-
|
|
1894
|
+
'S3_4_c12_c12_2':
|
|
1895
|
+
- name: 'ICH_LR2_EL2'
|
|
1872
1896
|
description: 'Interrupt Controller List Register 2'
|
|
1873
|
-
S3_4_c12_c12_3:
|
|
1874
|
-
|
|
1897
|
+
'S3_4_c12_c12_3':
|
|
1898
|
+
- name: 'ICH_LR3_EL2'
|
|
1875
1899
|
description: 'Interrupt Controller List Register 3'
|
|
1876
|
-
S3_4_c12_c12_4:
|
|
1877
|
-
|
|
1900
|
+
'S3_4_c12_c12_4':
|
|
1901
|
+
- name: 'ICH_LR4_EL2'
|
|
1878
1902
|
description: 'Interrupt Controller List Register 4'
|
|
1879
|
-
S3_4_c12_c12_5:
|
|
1880
|
-
|
|
1903
|
+
'S3_4_c12_c12_5':
|
|
1904
|
+
- name: 'ICH_LR5_EL2'
|
|
1881
1905
|
description: 'Interrupt Controller List Register 5'
|
|
1882
|
-
S3_4_c12_c12_6:
|
|
1883
|
-
|
|
1906
|
+
'S3_4_c12_c12_6':
|
|
1907
|
+
- name: 'ICH_LR6_EL2'
|
|
1884
1908
|
description: 'Interrupt Controller List Register 6'
|
|
1885
|
-
S3_4_c12_c12_7:
|
|
1886
|
-
|
|
1909
|
+
'S3_4_c12_c12_7':
|
|
1910
|
+
- name: 'ICH_LR7_EL2'
|
|
1887
1911
|
description: 'Interrupt Controller List Register 7'
|
|
1888
|
-
S3_4_c12_c13_0:
|
|
1889
|
-
|
|
1912
|
+
'S3_4_c12_c13_0':
|
|
1913
|
+
- name: 'ICH_LR8_EL2'
|
|
1890
1914
|
description: 'Interrupt Controller List Register 8'
|
|
1891
|
-
S3_4_c12_c13_1:
|
|
1892
|
-
|
|
1915
|
+
'S3_4_c12_c13_1':
|
|
1916
|
+
- name: 'ICH_LR9_EL2'
|
|
1893
1917
|
description: 'Interrupt Controller List Register 9'
|
|
1894
|
-
S3_4_c12_c13_2:
|
|
1895
|
-
|
|
1918
|
+
'S3_4_c12_c13_2':
|
|
1919
|
+
- name: 'ICH_LR10_EL2'
|
|
1896
1920
|
description: 'Interrupt Controller List Register 10'
|
|
1897
|
-
S3_4_c12_c13_3:
|
|
1898
|
-
|
|
1921
|
+
'S3_4_c12_c13_3':
|
|
1922
|
+
- name: 'ICH_LR11_EL2'
|
|
1899
1923
|
description: 'Interrupt Controller List Register 11'
|
|
1900
|
-
S3_4_c12_c13_4:
|
|
1901
|
-
|
|
1924
|
+
'S3_4_c12_c13_4':
|
|
1925
|
+
- name: 'ICH_LR12_EL2'
|
|
1902
1926
|
description: 'Interrupt Controller List Register 12'
|
|
1903
|
-
S3_4_c12_c13_5:
|
|
1904
|
-
|
|
1927
|
+
'S3_4_c12_c13_5':
|
|
1928
|
+
- name: 'ICH_LR13_EL2'
|
|
1905
1929
|
description: 'Interrupt Controller List Register 13'
|
|
1906
|
-
S3_4_c12_c13_6:
|
|
1907
|
-
|
|
1930
|
+
'S3_4_c12_c13_6':
|
|
1931
|
+
- name: 'ICH_LR14_EL2'
|
|
1908
1932
|
description: 'Interrupt Controller List Register 14'
|
|
1909
|
-
S3_4_c12_c13_7:
|
|
1910
|
-
|
|
1933
|
+
'S3_4_c12_c13_7':
|
|
1934
|
+
- name: 'ICH_LR15_EL2'
|
|
1911
1935
|
description: 'Interrupt Controller List Register 15'
|
|
1912
|
-
S3_4_c13_c0_1:
|
|
1913
|
-
|
|
1936
|
+
'S3_4_c13_c0_1':
|
|
1937
|
+
- name: 'CONTEXTIDR_EL2'
|
|
1914
1938
|
description: 'Context ID Register (EL2)'
|
|
1915
|
-
S3_4_c13_c0_2:
|
|
1916
|
-
|
|
1939
|
+
'S3_4_c13_c0_2':
|
|
1940
|
+
- name: 'TPIDR_EL2'
|
|
1917
1941
|
description: 'EL2 Software Thread ID Register'
|
|
1918
|
-
S3_4_c13_c0_7:
|
|
1919
|
-
|
|
1942
|
+
'S3_4_c13_c0_7':
|
|
1943
|
+
- name: 'SCXTNUM_EL2'
|
|
1920
1944
|
description: 'EL2 Read/Write Software Context Number'
|
|
1921
|
-
S3_4_c13_c8_0:
|
|
1922
|
-
|
|
1945
|
+
'S3_4_c13_c8_0':
|
|
1946
|
+
- name: 'AMEVCNTVOFF00_EL2'
|
|
1923
1947
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 0'
|
|
1924
|
-
S3_4_c13_c8_1:
|
|
1925
|
-
|
|
1948
|
+
'S3_4_c13_c8_1':
|
|
1949
|
+
- name: 'AMEVCNTVOFF01_EL2'
|
|
1926
1950
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 1'
|
|
1927
|
-
S3_4_c13_c8_2:
|
|
1928
|
-
|
|
1951
|
+
'S3_4_c13_c8_2':
|
|
1952
|
+
- name: 'AMEVCNTVOFF02_EL2'
|
|
1929
1953
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 2'
|
|
1930
|
-
S3_4_c13_c8_3:
|
|
1931
|
-
|
|
1954
|
+
'S3_4_c13_c8_3':
|
|
1955
|
+
- name: 'AMEVCNTVOFF03_EL2'
|
|
1932
1956
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 3'
|
|
1933
|
-
S3_4_c13_c8_4:
|
|
1934
|
-
|
|
1957
|
+
'S3_4_c13_c8_4':
|
|
1958
|
+
- name: 'AMEVCNTVOFF04_EL2'
|
|
1935
1959
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 4'
|
|
1936
|
-
S3_4_c13_c8_5:
|
|
1937
|
-
|
|
1960
|
+
'S3_4_c13_c8_5':
|
|
1961
|
+
- name: 'AMEVCNTVOFF05_EL2'
|
|
1938
1962
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 5'
|
|
1939
|
-
S3_4_c13_c8_6:
|
|
1940
|
-
|
|
1963
|
+
'S3_4_c13_c8_6':
|
|
1964
|
+
- name: 'AMEVCNTVOFF06_EL2'
|
|
1941
1965
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 6'
|
|
1942
|
-
S3_4_c13_c8_7:
|
|
1943
|
-
|
|
1966
|
+
'S3_4_c13_c8_7':
|
|
1967
|
+
- name: 'AMEVCNTVOFF07_EL2'
|
|
1944
1968
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 7'
|
|
1945
|
-
S3_4_c13_c9_0:
|
|
1946
|
-
|
|
1969
|
+
'S3_4_c13_c9_0':
|
|
1970
|
+
- name: 'AMEVCNTVOFF08_EL2'
|
|
1947
1971
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 8'
|
|
1948
|
-
S3_4_c13_c9_1:
|
|
1949
|
-
|
|
1972
|
+
'S3_4_c13_c9_1':
|
|
1973
|
+
- name: 'AMEVCNTVOFF09_EL2'
|
|
1950
1974
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 9'
|
|
1951
|
-
S3_4_c13_c9_2:
|
|
1952
|
-
|
|
1975
|
+
'S3_4_c13_c9_2':
|
|
1976
|
+
- name: 'AMEVCNTVOFF010_EL2'
|
|
1953
1977
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 10'
|
|
1954
|
-
S3_4_c13_c9_3:
|
|
1955
|
-
|
|
1978
|
+
'S3_4_c13_c9_3':
|
|
1979
|
+
- name: 'AMEVCNTVOFF011_EL2'
|
|
1956
1980
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 11'
|
|
1957
|
-
S3_4_c13_c9_4:
|
|
1958
|
-
|
|
1981
|
+
'S3_4_c13_c9_4':
|
|
1982
|
+
- name: 'AMEVCNTVOFF012_EL2'
|
|
1959
1983
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 12'
|
|
1960
|
-
S3_4_c13_c9_5:
|
|
1961
|
-
|
|
1984
|
+
'S3_4_c13_c9_5':
|
|
1985
|
+
- name: 'AMEVCNTVOFF013_EL2'
|
|
1962
1986
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 13'
|
|
1963
|
-
S3_4_c13_c9_6:
|
|
1964
|
-
|
|
1987
|
+
'S3_4_c13_c9_6':
|
|
1988
|
+
- name: 'AMEVCNTVOFF014_EL2'
|
|
1965
1989
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 14'
|
|
1966
|
-
S3_4_c13_c9_7:
|
|
1967
|
-
|
|
1990
|
+
'S3_4_c13_c9_7':
|
|
1991
|
+
- name: 'AMEVCNTVOFF015_EL2'
|
|
1968
1992
|
description: 'Activity Monitors Event Counter Virtual Offset Register 0 15'
|
|
1969
|
-
S3_4_c13_c10_0:
|
|
1970
|
-
|
|
1993
|
+
'S3_4_c13_c10_0':
|
|
1994
|
+
- name: 'AMEVCNTVOFF10_EL2'
|
|
1971
1995
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 0'
|
|
1972
|
-
S3_4_c13_c10_1:
|
|
1973
|
-
|
|
1996
|
+
'S3_4_c13_c10_1':
|
|
1997
|
+
- name: 'AMEVCNTVOFF11_EL2'
|
|
1974
1998
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 1'
|
|
1975
|
-
S3_4_c13_c10_2:
|
|
1976
|
-
|
|
1999
|
+
'S3_4_c13_c10_2':
|
|
2000
|
+
- name: 'AMEVCNTVOFF12_EL2'
|
|
1977
2001
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 2'
|
|
1978
|
-
S3_4_c13_c10_3:
|
|
1979
|
-
|
|
2002
|
+
'S3_4_c13_c10_3':
|
|
2003
|
+
- name: 'AMEVCNTVOFF13_EL2'
|
|
1980
2004
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 3'
|
|
1981
|
-
S3_4_c13_c10_4:
|
|
1982
|
-
|
|
2005
|
+
'S3_4_c13_c10_4':
|
|
2006
|
+
- name: 'AMEVCNTVOFF14_EL2'
|
|
1983
2007
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 4'
|
|
1984
|
-
S3_4_c13_c10_5:
|
|
1985
|
-
|
|
2008
|
+
'S3_4_c13_c10_5':
|
|
2009
|
+
- name: 'AMEVCNTVOFF15_EL2'
|
|
1986
2010
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 5'
|
|
1987
|
-
S3_4_c13_c10_6:
|
|
1988
|
-
|
|
2011
|
+
'S3_4_c13_c10_6':
|
|
2012
|
+
- name: 'AMEVCNTVOFF16_EL2'
|
|
1989
2013
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 6'
|
|
1990
|
-
S3_4_c13_c10_7:
|
|
1991
|
-
|
|
2014
|
+
'S3_4_c13_c10_7':
|
|
2015
|
+
- name: 'AMEVCNTVOFF17_EL2'
|
|
1992
2016
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 7'
|
|
1993
|
-
S3_4_c13_c11_0:
|
|
1994
|
-
|
|
2017
|
+
'S3_4_c13_c11_0':
|
|
2018
|
+
- name: 'AMEVCNTVOFF18_EL2'
|
|
1995
2019
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 8'
|
|
1996
|
-
S3_4_c13_c11_1:
|
|
1997
|
-
|
|
2020
|
+
'S3_4_c13_c11_1':
|
|
2021
|
+
- name: 'AMEVCNTVOFF19_EL2'
|
|
1998
2022
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 9'
|
|
1999
|
-
S3_4_c13_c11_2:
|
|
2000
|
-
|
|
2023
|
+
'S3_4_c13_c11_2':
|
|
2024
|
+
- name: 'AMEVCNTVOFF110_EL2'
|
|
2001
2025
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 10'
|
|
2002
|
-
S3_4_c13_c11_3:
|
|
2003
|
-
|
|
2026
|
+
'S3_4_c13_c11_3':
|
|
2027
|
+
- name: 'AMEVCNTVOFF111_EL2'
|
|
2004
2028
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 11'
|
|
2005
|
-
S3_4_c13_c11_4:
|
|
2006
|
-
|
|
2029
|
+
'S3_4_c13_c11_4':
|
|
2030
|
+
- name: 'AMEVCNTVOFF112_EL2'
|
|
2007
2031
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 12'
|
|
2008
|
-
S3_4_c13_c11_5:
|
|
2009
|
-
|
|
2032
|
+
'S3_4_c13_c11_5':
|
|
2033
|
+
- name: 'AMEVCNTVOFF113_EL2'
|
|
2010
2034
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 13'
|
|
2011
|
-
S3_4_c13_c11_6:
|
|
2012
|
-
|
|
2035
|
+
'S3_4_c13_c11_6':
|
|
2036
|
+
- name: 'AMEVCNTVOFF114_EL2'
|
|
2013
2037
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 14'
|
|
2014
|
-
S3_4_c13_c11_7:
|
|
2015
|
-
|
|
2038
|
+
'S3_4_c13_c11_7':
|
|
2039
|
+
- name: 'AMEVCNTVOFF115_EL2'
|
|
2016
2040
|
description: 'Activity Monitors Event Counter Virtual Offset Register 1 15'
|
|
2017
|
-
S3_4_c14_c0_3:
|
|
2018
|
-
|
|
2041
|
+
'S3_4_c14_c0_3':
|
|
2042
|
+
- name: 'CNTVOFF_EL2'
|
|
2019
2043
|
description: 'Counter-timer Virtual Offset register'
|
|
2020
|
-
S3_4_c14_c0_6:
|
|
2021
|
-
|
|
2044
|
+
'S3_4_c14_c0_6':
|
|
2045
|
+
- name: 'CNTPOFF_EL2'
|
|
2022
2046
|
description: 'Counter-timer Physical Offset register'
|
|
2023
|
-
S3_4_c14_c1_0:
|
|
2024
|
-
|
|
2047
|
+
'S3_4_c14_c1_0':
|
|
2048
|
+
- name: 'CNTHCTL_EL2'
|
|
2025
2049
|
description: 'Counter-timer Hypervisor Control register'
|
|
2026
|
-
S3_4_c14_c2_0:
|
|
2027
|
-
|
|
2050
|
+
'S3_4_c14_c2_0':
|
|
2051
|
+
- name: 'CNTHP_TVAL_EL2'
|
|
2028
2052
|
description: 'Counter-timer Physical Timer TimerValue register (EL2)'
|
|
2029
|
-
S3_4_c14_c2_1:
|
|
2030
|
-
|
|
2053
|
+
'S3_4_c14_c2_1':
|
|
2054
|
+
- name: 'CNTHP_CTL_EL2'
|
|
2031
2055
|
description: 'Counter-timer Hypervisor Physical Timer Control register'
|
|
2032
|
-
S3_4_c14_c2_2:
|
|
2033
|
-
|
|
2056
|
+
'S3_4_c14_c2_2':
|
|
2057
|
+
- name: 'CNTHP_CVAL_EL2'
|
|
2034
2058
|
description: 'Counter-timer Physical Timer CompareValue register (EL2)'
|
|
2035
|
-
S3_4_c14_c3_0:
|
|
2036
|
-
|
|
2059
|
+
'S3_4_c14_c3_0':
|
|
2060
|
+
- name: 'CNTHV_TVAL_EL2'
|
|
2037
2061
|
description: 'Counter-timer Virtual Timer TimerValue Register (EL2)'
|
|
2038
|
-
S3_4_c14_c3_1:
|
|
2039
|
-
|
|
2062
|
+
'S3_4_c14_c3_1':
|
|
2063
|
+
- name: 'CNTHV_CTL_EL2'
|
|
2040
2064
|
description: 'Counter-timer Virtual Timer Control register (EL2)'
|
|
2041
|
-
S3_4_c14_c3_2:
|
|
2042
|
-
|
|
2065
|
+
'S3_4_c14_c3_2':
|
|
2066
|
+
- name: 'CNTHV_CVAL_EL2'
|
|
2043
2067
|
description: 'Counter-timer Virtual Timer CompareValue register (EL2)'
|
|
2044
|
-
S3_4_c14_c4_0:
|
|
2045
|
-
|
|
2068
|
+
'S3_4_c14_c4_0':
|
|
2069
|
+
- name: 'CNTHVS_TVAL_EL2'
|
|
2046
2070
|
description: 'Counter-timer Secure Virtual Timer TimerValue register (EL2)'
|
|
2047
|
-
S3_4_c14_c4_1:
|
|
2048
|
-
|
|
2071
|
+
'S3_4_c14_c4_1':
|
|
2072
|
+
- name: 'CNTHVS_CTL_EL2'
|
|
2049
2073
|
description: 'Counter-timer Secure Virtual Timer Control register (EL2)'
|
|
2050
|
-
S3_4_c14_c4_2:
|
|
2051
|
-
|
|
2074
|
+
'S3_4_c14_c4_2':
|
|
2075
|
+
- name: 'CNTHVS_CVAL_EL2'
|
|
2052
2076
|
description: 'Counter-timer Secure Virtual Timer CompareValue register (EL2)'
|
|
2053
|
-
S3_4_c14_c5_0:
|
|
2054
|
-
|
|
2077
|
+
'S3_4_c14_c5_0':
|
|
2078
|
+
- name: 'CNTHPS_TVAL_EL2'
|
|
2055
2079
|
description: 'Counter-timer Secure Physical Timer TimerValue register (EL2)'
|
|
2056
|
-
S3_4_c14_c5_1:
|
|
2057
|
-
|
|
2080
|
+
'S3_4_c14_c5_1':
|
|
2081
|
+
- name: 'CNTHPS_CTL_EL2'
|
|
2058
2082
|
description: 'Counter-timer Secure Physical Timer Control register (EL2)'
|
|
2059
|
-
S3_4_c14_c5_2:
|
|
2060
|
-
|
|
2083
|
+
'S3_4_c14_c5_2':
|
|
2084
|
+
- name: 'CNTHPS_CVAL_EL2'
|
|
2061
2085
|
description: 'Counter-timer Secure Physical Timer CompareValue register (EL2)'
|
|
2062
|
-
S3_6_c1_c0_0:
|
|
2063
|
-
|
|
2086
|
+
'S3_6_c1_c0_0':
|
|
2087
|
+
- name: 'SCTLR_EL3'
|
|
2064
2088
|
description: 'System Control Register (EL3)'
|
|
2065
|
-
S3_6_c1_c0_1:
|
|
2066
|
-
|
|
2089
|
+
'S3_6_c1_c0_1':
|
|
2090
|
+
- name: 'ACTLR_EL3'
|
|
2067
2091
|
description: 'Auxiliary Control Register (EL3)'
|
|
2068
|
-
S3_6_c1_c1_0:
|
|
2069
|
-
|
|
2092
|
+
'S3_6_c1_c1_0':
|
|
2093
|
+
- name: 'SCR_EL3'
|
|
2070
2094
|
description: 'Secure Configuration Register'
|
|
2071
|
-
S3_6_c1_c1_1:
|
|
2072
|
-
|
|
2095
|
+
'S3_6_c1_c1_1':
|
|
2096
|
+
- name: 'SDER32_EL3'
|
|
2073
2097
|
description: 'AArch32 Secure Debug Enable Register'
|
|
2074
|
-
S3_6_c1_c1_2:
|
|
2075
|
-
|
|
2098
|
+
'S3_6_c1_c1_2':
|
|
2099
|
+
- name: 'CPTR_EL3'
|
|
2076
2100
|
description: 'Architectural Feature Trap Register (EL3)'
|
|
2077
|
-
S3_6_c1_c2_0:
|
|
2078
|
-
|
|
2101
|
+
'S3_6_c1_c2_0':
|
|
2102
|
+
- name: 'ZCR_EL3'
|
|
2079
2103
|
description: 'SVE Control Register for EL3'
|
|
2080
|
-
S3_6_c1_c3_1:
|
|
2081
|
-
|
|
2104
|
+
'S3_6_c1_c3_1':
|
|
2105
|
+
- name: 'MDCR_EL3'
|
|
2082
2106
|
description: 'Monitor Debug Configuration Register (EL3)'
|
|
2083
|
-
S3_6_c2_c0_0:
|
|
2084
|
-
|
|
2107
|
+
'S3_6_c2_c0_0':
|
|
2108
|
+
- name: 'TTBR0_EL3'
|
|
2085
2109
|
description: 'Translation Table Base Register 0 (EL3)'
|
|
2086
|
-
S3_6_c2_c0_2:
|
|
2087
|
-
|
|
2110
|
+
'S3_6_c2_c0_2':
|
|
2111
|
+
- name: 'TCR_EL3'
|
|
2088
2112
|
description: 'Translation Control Register (EL3)'
|
|
2089
|
-
S3_6_c4_c0_0:
|
|
2090
|
-
|
|
2113
|
+
'S3_6_c4_c0_0':
|
|
2114
|
+
- name: 'SPSR_EL3'
|
|
2091
2115
|
description: 'Saved Program Status Register (EL3)'
|
|
2092
|
-
S3_6_c4_c0_1:
|
|
2093
|
-
|
|
2116
|
+
'S3_6_c4_c0_1':
|
|
2117
|
+
- name: 'ELR_EL3'
|
|
2094
2118
|
description: 'Exception Link Register (EL3)'
|
|
2095
|
-
S3_6_c4_c1_0:
|
|
2096
|
-
|
|
2119
|
+
'S3_6_c4_c1_0':
|
|
2120
|
+
- name: 'SP_EL2'
|
|
2097
2121
|
description: 'Stack Pointer (EL2)'
|
|
2098
|
-
S3_6_c5_c1_0:
|
|
2099
|
-
|
|
2122
|
+
'S3_6_c5_c1_0':
|
|
2123
|
+
- name: 'AFSR0_EL3'
|
|
2100
2124
|
description: 'Auxiliary Fault Status Register 0 (EL3)'
|
|
2101
|
-
S3_6_c5_c1_1:
|
|
2102
|
-
|
|
2125
|
+
'S3_6_c5_c1_1':
|
|
2126
|
+
- name: 'AFSR1_EL3'
|
|
2103
2127
|
description: 'Auxiliary Fault Status Register 1 (EL3)'
|
|
2104
|
-
S3_6_c5_c2_0:
|
|
2105
|
-
|
|
2128
|
+
'S3_6_c5_c2_0':
|
|
2129
|
+
- name: 'ESR_EL3'
|
|
2106
2130
|
description: 'Exception Syndrome Register (EL3)'
|
|
2107
|
-
S3_6_c5_c6_0:
|
|
2108
|
-
|
|
2131
|
+
'S3_6_c5_c6_0':
|
|
2132
|
+
- name: 'TFSR_EL3'
|
|
2109
2133
|
description: 'Tag Fault Status Register (EL3)'
|
|
2110
|
-
S3_6_c6_c0_0:
|
|
2111
|
-
|
|
2134
|
+
'S3_6_c6_c0_0':
|
|
2135
|
+
- name: 'FAR_EL3'
|
|
2112
2136
|
description: 'Fault Address Register (EL3)'
|
|
2113
|
-
S3_6_c10_c2_0:
|
|
2114
|
-
|
|
2137
|
+
'S3_6_c10_c2_0':
|
|
2138
|
+
- name: 'MAIR_EL3'
|
|
2115
2139
|
description: 'Memory Attribute Indirection Register (EL3)'
|
|
2116
|
-
S3_6_c10_c3_0:
|
|
2117
|
-
|
|
2140
|
+
'S3_6_c10_c3_0':
|
|
2141
|
+
- name: 'AMAIR_EL3'
|
|
2118
2142
|
description: 'Auxiliary Memory Attribute Indirection Register (EL3)'
|
|
2119
|
-
S3_6_c10_c5_0:
|
|
2120
|
-
|
|
2143
|
+
'S3_6_c10_c5_0':
|
|
2144
|
+
- name: 'MPAM3_EL3'
|
|
2121
2145
|
description: 'MPAM3 Register (EL3)'
|
|
2122
|
-
S3_6_c12_c0_0:
|
|
2123
|
-
|
|
2146
|
+
'S3_6_c12_c0_0':
|
|
2147
|
+
- name: 'VBAR_EL3'
|
|
2124
2148
|
description: 'Vector Base Address Register (EL3)'
|
|
2125
|
-
S3_6_c12_c0_1:
|
|
2126
|
-
|
|
2149
|
+
'S3_6_c12_c0_1':
|
|
2150
|
+
- name: 'RVBAR_EL3'
|
|
2127
2151
|
description: 'Reset Vector Base Address Register (if EL3 implemented)'
|
|
2128
|
-
S3_6_c12_c0_2:
|
|
2129
|
-
|
|
2152
|
+
'S3_6_c12_c0_2':
|
|
2153
|
+
- name: 'RMR_EL3'
|
|
2130
2154
|
description: 'Reset Management Register (EL3)'
|
|
2131
|
-
S3_6_c12_c12_4:
|
|
2132
|
-
|
|
2155
|
+
'S3_6_c12_c12_4':
|
|
2156
|
+
- name: 'ICC_CTLR_EL3'
|
|
2133
2157
|
description: 'Interrupt Controller Control Register (EL3)'
|
|
2134
|
-
S3_6_c12_c12_5:
|
|
2135
|
-
|
|
2158
|
+
'S3_6_c12_c12_5':
|
|
2159
|
+
- name: 'ICC_SRE_EL3'
|
|
2136
2160
|
description: 'Interrupt Controller System Register Enable register (EL3)'
|
|
2137
|
-
S3_6_c12_c12_7:
|
|
2138
|
-
|
|
2161
|
+
'S3_6_c12_c12_7':
|
|
2162
|
+
- name: 'ICC_IGRPEN1_EL3'
|
|
2139
2163
|
description: 'Interrupt Controller Interrupt Group 1 Enable register (EL3)'
|
|
2140
|
-
S3_6_c13_c0_2:
|
|
2141
|
-
|
|
2164
|
+
'S3_6_c13_c0_2':
|
|
2165
|
+
- name: 'TPIDR_EL3'
|
|
2142
2166
|
description: 'EL3 Software Thread ID Register'
|
|
2143
|
-
S3_6_c13_c0_7:
|
|
2144
|
-
|
|
2167
|
+
'S3_6_c13_c0_7':
|
|
2168
|
+
- name: 'SCXTNUM_EL3'
|
|
2145
2169
|
description: 'EL3 Read/Write Software Context Number'
|
|
2146
|
-
S3_7_c14_c2_0:
|
|
2147
|
-
|
|
2170
|
+
'S3_7_c14_c2_0':
|
|
2171
|
+
- name: 'CNTPS_TVAL_EL1'
|
|
2148
2172
|
description: 'Counter-timer Physical Secure Timer TimerValue register'
|
|
2149
|
-
S3_7_c14_c2_1:
|
|
2150
|
-
|
|
2173
|
+
'S3_7_c14_c2_1':
|
|
2174
|
+
- name: 'CNTPS_CTL_EL1'
|
|
2151
2175
|
description: 'Counter-timer Physical Secure Timer Control register'
|
|
2152
|
-
S3_7_c14_c2_2:
|
|
2153
|
-
|
|
2176
|
+
'S3_7_c14_c2_2':
|
|
2177
|
+
- name: 'CNTPS_CVAL_EL1'
|
|
2154
2178
|
description: 'Counter-timer Physical Secure Timer CompareValue register'
|
|
2155
2179
|
apple_system_registers:
|
|
2156
|
-
S3_0_c15_c0_0:
|
|
2180
|
+
- 'S3_0_c15_c0_0':
|
|
2157
2181
|
name: 'HID0'
|
|
2158
2182
|
description: ''
|
|
2159
|
-
S3_0_c15_c0_1:
|
|
2183
|
+
- 'S3_0_c15_c0_1':
|
|
2160
2184
|
name: 'EHID0'
|
|
2161
2185
|
description: ''
|
|
2162
|
-
S3_0_c15_c1_0:
|
|
2186
|
+
- 'S3_0_c15_c1_0':
|
|
2163
2187
|
name: 'HID1'
|
|
2164
2188
|
description: ''
|
|
2165
|
-
S3_0_c15_c1_1:
|
|
2189
|
+
- 'S3_0_c15_c1_1':
|
|
2166
2190
|
name: 'EHID1'
|
|
2167
2191
|
description: ''
|
|
2168
|
-
S3_0_c15_c2_0:
|
|
2192
|
+
- 'S3_0_c15_c2_0':
|
|
2169
2193
|
name: 'HID2'
|
|
2170
2194
|
description: ''
|
|
2171
|
-
S3_0_c15_c2_1:
|
|
2195
|
+
- 'S3_0_c15_c2_1':
|
|
2172
2196
|
name: 'EHID2'
|
|
2173
2197
|
description: ''
|
|
2174
|
-
S3_0_c15_c3_0:
|
|
2198
|
+
- 'S3_0_c15_c3_0':
|
|
2175
2199
|
name: 'HID3'
|
|
2176
2200
|
description: ''
|
|
2177
|
-
S3_0_c15_c3_1:
|
|
2201
|
+
- 'S3_0_c15_c3_1':
|
|
2178
2202
|
name: 'EHID3'
|
|
2179
2203
|
description: ''
|
|
2180
|
-
S3_0_c15_c4_0:
|
|
2204
|
+
- 'S3_0_c15_c4_0':
|
|
2181
2205
|
name: 'HID4'
|
|
2182
2206
|
description: ''
|
|
2183
|
-
S3_0_c15_c4_1:
|
|
2207
|
+
- 'S3_0_c15_c4_1':
|
|
2184
2208
|
name: 'EHID4'
|
|
2185
2209
|
description: ''
|
|
2186
|
-
S3_0_c15_c5_0:
|
|
2210
|
+
- 'S3_0_c15_c5_0':
|
|
2187
2211
|
name: 'HID5'
|
|
2188
2212
|
description: 'L2 cache load/store prefetcher'
|
|
2189
|
-
S3_0_c15_c5_1:
|
|
2213
|
+
- 'S3_0_c15_c5_1':
|
|
2190
2214
|
name: 'EHID5'
|
|
2191
2215
|
description: ''
|
|
2192
|
-
S3_0_c15_c6_0:
|
|
2216
|
+
- 'S3_0_c15_c6_0':
|
|
2193
2217
|
name: 'HID6'
|
|
2194
2218
|
description: ''
|
|
2195
|
-
S3_0_c15_c7_0:
|
|
2219
|
+
- 'S3_0_c15_c7_0':
|
|
2196
2220
|
name: 'L2_CRAMCONFIG'
|
|
2197
2221
|
description: ''
|
|
2198
|
-
S3_0_c15_c8_0:
|
|
2222
|
+
- 'S3_0_c15_c8_0':
|
|
2199
2223
|
name: 'HID8'
|
|
2200
2224
|
description: ''
|
|
2201
|
-
S3_0_c15_c9_0:
|
|
2225
|
+
- 'S3_0_c15_c9_0':
|
|
2202
2226
|
name: 'HID9'
|
|
2203
2227
|
description: ''
|
|
2204
|
-
S3_0_c15_c10_0:
|
|
2228
|
+
- 'S3_0_c15_c10_0':
|
|
2205
2229
|
name: 'HID10'
|
|
2206
2230
|
description: ''
|
|
2207
|
-
S3_0_c15_c10_1:
|
|
2231
|
+
- 'S3_0_c15_c10_1':
|
|
2208
2232
|
name: 'EHID10'
|
|
2209
2233
|
description: ''
|
|
2210
|
-
S3_0_c15_c11_0:
|
|
2234
|
+
- 'S3_0_c15_c11_0':
|
|
2211
2235
|
name: 'HID11'
|
|
2212
2236
|
description: ''
|
|
2213
|
-
S3_0_c15_c11_1:
|
|
2237
|
+
- 'S3_0_c15_c11_1':
|
|
2214
2238
|
name: 'EHID11'
|
|
2215
2239
|
description: ''
|
|
2216
|
-
S3_0_c15_c14_0:
|
|
2240
|
+
- 'S3_0_c15_c14_0':
|
|
2217
2241
|
name: 'HID13'
|
|
2218
2242
|
description: ''
|
|
2219
|
-
S3_0_c15_c15_0:
|
|
2243
|
+
- 'S3_0_c15_c15_0':
|
|
2220
2244
|
name: 'HID14'
|
|
2221
2245
|
description: ''
|
|
2222
|
-
S3_0_c15_c15_2:
|
|
2246
|
+
- 'S3_0_c15_c15_2':
|
|
2223
2247
|
name: 'HID16'
|
|
2224
2248
|
description: ''
|
|
2225
|
-
S3_1_c15_c0_0:
|
|
2249
|
+
- 'S3_1_c15_c0_0':
|
|
2226
2250
|
name: 'PMCR0'
|
|
2227
2251
|
description: 'Apple Performance Monitor Control Register 0'
|
|
2228
|
-
S3_1_c15_c1_0:
|
|
2252
|
+
- 'S3_1_c15_c1_0':
|
|
2229
2253
|
name: 'PMCR1'
|
|
2230
2254
|
description: 'Controls which execution modes count events'
|
|
2231
|
-
S3_1_c15_c2_0:
|
|
2255
|
+
- 'S3_1_c15_c2_0':
|
|
2232
2256
|
name: 'PMCR2'
|
|
2233
2257
|
description: 'Controls watchpoint registers'
|
|
2234
|
-
S3_1_c15_c3_0:
|
|
2258
|
+
- 'S3_1_c15_c3_0':
|
|
2235
2259
|
name: 'PMCR3'
|
|
2236
2260
|
description: 'Controls breakpoints and address matching'
|
|
2237
|
-
S3_1_c15_c4_0:
|
|
2261
|
+
- 'S3_1_c15_c4_0':
|
|
2238
2262
|
name: 'PMCR4'
|
|
2239
2263
|
description: 'Controls opcode matching'
|
|
2240
|
-
S3_1_c15_c5_0:
|
|
2264
|
+
- 'S3_1_c15_c5_0':
|
|
2241
2265
|
name: 'PMESR0'
|
|
2242
2266
|
description: ''
|
|
2243
|
-
S3_1_c15_c6_0:
|
|
2267
|
+
- 'S3_1_c15_c6_0':
|
|
2244
2268
|
name: 'PMESR1'
|
|
2245
2269
|
description: ''
|
|
2246
|
-
S3_1_c15_c7_0:
|
|
2270
|
+
- 'S3_1_c15_c7_0':
|
|
2247
2271
|
name: 'OPMAT0'
|
|
2248
2272
|
description: ''
|
|
2249
|
-
S3_1_c15_c8_0:
|
|
2273
|
+
- 'S3_1_c15_c8_0':
|
|
2250
2274
|
name: 'OPMAT1'
|
|
2251
2275
|
description: ''
|
|
2252
|
-
S3_1_c15_c9_0:
|
|
2276
|
+
- 'S3_1_c15_c9_0':
|
|
2253
2277
|
name: 'OPMSK0'
|
|
2254
2278
|
description: ''
|
|
2255
|
-
S3_1_c15_c10_0:
|
|
2279
|
+
- 'S3_1_c15_c10_0':
|
|
2256
2280
|
name: 'OPMSK1'
|
|
2257
2281
|
description: ''
|
|
2258
|
-
S3_1_c15_c13_0:
|
|
2282
|
+
- 'S3_1_c15_c13_0':
|
|
2259
2283
|
name: 'PMSR'
|
|
2260
2284
|
description: ''
|
|
2261
|
-
S3_2_c15_c0_0:
|
|
2285
|
+
- 'S3_2_c15_c0_0':
|
|
2262
2286
|
name: 'PMC0'
|
|
2263
2287
|
description: '48-bit cycles counter'
|
|
2264
|
-
S3_2_c15_c1_0:
|
|
2288
|
+
- 'S3_2_c15_c1_0':
|
|
2265
2289
|
name: 'PMC1'
|
|
2266
2290
|
description: '48-bit instructions counter'
|
|
2267
|
-
S3_2_c15_c2_0:
|
|
2291
|
+
- 'S3_2_c15_c2_0':
|
|
2268
2292
|
name: 'PMC2'
|
|
2269
2293
|
description: ''
|
|
2270
|
-
S3_2_c15_c3_0:
|
|
2294
|
+
- 'S3_2_c15_c3_0':
|
|
2271
2295
|
name: 'PMC3'
|
|
2272
2296
|
description: ''
|
|
2273
|
-
S3_2_c15_c4_0:
|
|
2297
|
+
- 'S3_2_c15_c4_0':
|
|
2274
2298
|
name: 'PMC4'
|
|
2275
2299
|
description: ''
|
|
2276
|
-
S3_2_c15_c5_0:
|
|
2300
|
+
- 'S3_2_c15_c5_0':
|
|
2277
2301
|
name: 'PMC5'
|
|
2278
2302
|
description: ''
|
|
2279
|
-
S3_2_c15_c6_0:
|
|
2303
|
+
- 'S3_2_c15_c6_0':
|
|
2280
2304
|
name: 'PMC6'
|
|
2281
2305
|
description: ''
|
|
2282
|
-
S3_2_c15_c7_0:
|
|
2306
|
+
- 'S3_2_c15_c7_0':
|
|
2283
2307
|
name: 'PMC7'
|
|
2284
2308
|
description: ''
|
|
2285
|
-
S3_2_c15_c9_0:
|
|
2309
|
+
- 'S3_2_c15_c9_0':
|
|
2286
2310
|
name: 'PMC8'
|
|
2287
2311
|
description: ''
|
|
2288
|
-
S3_2_c15_c10_0:
|
|
2312
|
+
- 'S3_2_c15_c10_0':
|
|
2289
2313
|
name: 'PMC9'
|
|
2290
2314
|
description: ''
|
|
2291
|
-
S3_2_c15_c12_0:
|
|
2315
|
+
- 'S3_2_c15_c12_0':
|
|
2292
2316
|
name: 'PMTRHLD6'
|
|
2293
2317
|
description: ''
|
|
2294
|
-
S3_2_c15_c13_0:
|
|
2318
|
+
- 'S3_2_c15_c13_0':
|
|
2295
2319
|
name: 'PMTRHLD4'
|
|
2296
2320
|
description: ''
|
|
2297
|
-
S3_2_c15_c14_0:
|
|
2321
|
+
- 'S3_2_c15_c14_0':
|
|
2298
2322
|
name: 'PMTRHLD2'
|
|
2299
2323
|
description: ''
|
|
2300
|
-
S3_2_c15_c15_0:
|
|
2324
|
+
- 'S3_2_c15_c15_0':
|
|
2301
2325
|
name: 'PMMMAP'
|
|
2302
2326
|
description: ''
|
|
2303
|
-
S3_3_c15_c0_0:
|
|
2327
|
+
- 'S3_3_c15_c0_0':
|
|
2304
2328
|
name: 'LSU_ERR_STS'
|
|
2305
2329
|
description: 'LSU Error Status'
|
|
2306
|
-
S3_3_c15_c1_0:
|
|
2330
|
+
- 'S3_3_c15_c1_0':
|
|
2307
2331
|
name: 'LSU_ERR_CTL'
|
|
2308
2332
|
description: 'LSU Error Control'
|
|
2309
|
-
S3_3_c15_c2_0:
|
|
2333
|
+
- 'S3_3_c15_c2_0':
|
|
2310
2334
|
name: 'E_LSU_ERR_STS'
|
|
2311
2335
|
description: 'LSU Error Status'
|
|
2312
|
-
S3_3_c15_c7_0:
|
|
2336
|
+
- 'S3_3_c15_c7_0':
|
|
2313
2337
|
name: 'L2_CRAMCONFIG'
|
|
2314
2338
|
description: 'LSU Error Status'
|
|
2315
|
-
S3_3_c15_c8_0:
|
|
2339
|
+
- 'S3_3_c15_c8_0':
|
|
2316
2340
|
name: 'LLC_ERR_STS'
|
|
2317
2341
|
description: 'LLC Error Status'
|
|
2318
|
-
S3_3_c15_c8_1:
|
|
2342
|
+
- 'S3_3_c15_c8_1':
|
|
2319
2343
|
name: 'L2E_ERR_STS'
|
|
2320
2344
|
description: ''
|
|
2321
|
-
S3_3_c15_c9_0:
|
|
2345
|
+
- 'S3_3_c15_c9_0':
|
|
2322
2346
|
name: 'LLC_ERR_ADR'
|
|
2323
2347
|
description: 'LLC Error Address'
|
|
2324
|
-
S3_3_c15_c9_1:
|
|
2348
|
+
- 'S3_3_c15_c9_1':
|
|
2325
2349
|
name: 'L2E_ERR_ADR'
|
|
2326
2350
|
description: ''
|
|
2327
|
-
S3_3_c15_c10_0:
|
|
2351
|
+
- 'S3_3_c15_c10_0':
|
|
2328
2352
|
name: 'LLC_ERR_INF'
|
|
2329
2353
|
description: 'LLC Error Information'
|
|
2330
|
-
S3_3_c15_c10_1:
|
|
2354
|
+
- 'S3_3_c15_c10_1':
|
|
2331
2355
|
name: 'L2E_ERR_INF'
|
|
2332
2356
|
description: ''
|
|
2333
|
-
S3_4_c15_c0_0:
|
|
2357
|
+
- 'S3_4_c15_c0_0':
|
|
2334
2358
|
name: 'FED_ERR_STS'
|
|
2335
2359
|
description: 'FED Error Status'
|
|
2336
|
-
S3_4_c15_c0_2:
|
|
2360
|
+
- 'S3_4_c15_c0_2':
|
|
2337
2361
|
name: 'E_FED_ERR_STS'
|
|
2338
2362
|
description: 'FED Error Status'
|
|
2339
|
-
S3_4_c15_c0_4:
|
|
2363
|
+
- 'S3_4_c15_c0_4':
|
|
2340
2364
|
name: 'APCTL_EL1/MIGSTS'
|
|
2341
2365
|
description: ''
|
|
2342
|
-
S3_4_c15_c1_0:
|
|
2366
|
+
- 'S3_4_c15_c1_0':
|
|
2343
2367
|
name: 'KERNELKEYLO_EL1'
|
|
2344
2368
|
description: 'PAC Kernel Key (bits[63:0])'
|
|
2345
|
-
S3_4_c15_c1_1:
|
|
2369
|
+
- 'S3_4_c15_c1_1':
|
|
2346
2370
|
name: 'KERNELKEYHI_EL1'
|
|
2347
2371
|
description: 'PAC Kernel Key (bits[127:64])'
|
|
2348
|
-
S3_4_c15_c1_2:
|
|
2372
|
+
- 'S3_4_c15_c1_2':
|
|
2349
2373
|
name: 'VMSA_LOCK_EL1'
|
|
2350
2374
|
description: 'VMSA Lock'
|
|
2351
|
-
S3_4_c15_c1_6:
|
|
2375
|
+
- 'S3_4_c15_c1_6':
|
|
2352
2376
|
name: 'CTRR_B_UPR_EL1'
|
|
2353
2377
|
description: 'CTRR Upper Range B'
|
|
2354
|
-
S3_4_c15_c1_7:
|
|
2378
|
+
- 'S3_4_c15_c1_7':
|
|
2355
2379
|
name: 'CTRR_B_LWR_EL1'
|
|
2356
2380
|
description: 'CTRR Lower Range B'
|
|
2357
|
-
S3_4_c15_c2_0:
|
|
2381
|
+
- 'S3_4_c15_c2_0':
|
|
2358
2382
|
name: 'APRR_0'
|
|
2359
2383
|
description: 'APRR Register 0'
|
|
2360
|
-
S3_4_c15_c2_1:
|
|
2384
|
+
- 'S3_4_c15_c2_1':
|
|
2361
2385
|
name: 'APRR_1'
|
|
2362
2386
|
description: 'APRR Register 1'
|
|
2363
|
-
S3_4_c15_c2_2:
|
|
2387
|
+
- 'S3_4_c15_c2_2':
|
|
2364
2388
|
name: 'CTRR_LOCK'
|
|
2365
2389
|
description: 'CTRR Lockdown'
|
|
2366
|
-
S3_4_c15_c2_3:
|
|
2390
|
+
- 'S3_4_c15_c2_3':
|
|
2367
2391
|
name: 'CTRR_A_LWR_EL1'
|
|
2368
2392
|
description: 'CTRR Lower Range'
|
|
2369
|
-
S3_4_c15_c2_4:
|
|
2393
|
+
- 'S3_4_c15_c2_4':
|
|
2370
2394
|
name: 'CTRR_A_UPR_EL1'
|
|
2371
2395
|
description: 'CTRR Upper Range'
|
|
2372
|
-
S3_4_c15_c2_5:
|
|
2396
|
+
- 'S3_4_c15_c2_5':
|
|
2373
2397
|
name: 'CTRR_CTL_EL1'
|
|
2374
2398
|
description: 'CTRR Control Register'
|
|
2375
|
-
S3_4_c15_c2_6:
|
|
2399
|
+
- 'S3_4_c15_c2_6':
|
|
2376
2400
|
name: 'APRR_6'
|
|
2377
2401
|
description: 'APRR Register 6'
|
|
2378
|
-
S3_4_c15_c2_7:
|
|
2402
|
+
- 'S3_4_c15_c2_7':
|
|
2379
2403
|
name: 'APRR_7'
|
|
2380
2404
|
description: 'APRR Register 7'
|
|
2381
|
-
S3_4_c15_c11_0:
|
|
2405
|
+
- 'S3_4_c15_c11_0':
|
|
2382
2406
|
name: 'ACC_CTRR_A_LWR_EL2'
|
|
2383
2407
|
description: ''
|
|
2384
|
-
S3_4_c15_c11_1:
|
|
2408
|
+
- 'S3_4_c15_c11_1':
|
|
2385
2409
|
name: 'ACC_CTRR_A_UPR_EL2'
|
|
2386
2410
|
description: ''
|
|
2387
|
-
S3_4_c15_c11_4:
|
|
2411
|
+
- 'S3_4_c15_c11_4':
|
|
2388
2412
|
name: 'ACC_CTRR_CTL_EL2'
|
|
2389
2413
|
description: ''
|
|
2390
|
-
S3_4_c15_c11_5:
|
|
2414
|
+
- 'S3_4_c15_c11_5':
|
|
2391
2415
|
name: 'ACC_CTRR_LOCK_EL2'
|
|
2392
2416
|
description: ''
|
|
2393
|
-
S3_5_c15_c0_0:
|
|
2417
|
+
- 'S3_5_c15_c0_0':
|
|
2394
2418
|
name: 'IPI_RR_LOCAL'
|
|
2395
2419
|
description: ''
|
|
2396
|
-
S3_5_c15_c0_1:
|
|
2420
|
+
- 'S3_5_c15_c0_1':
|
|
2397
2421
|
name: 'IPI_RR_GLOBAL'
|
|
2398
2422
|
description: ''
|
|
2399
|
-
S3_5_c15_c0_5:
|
|
2423
|
+
- 'S3_5_c15_c0_5':
|
|
2400
2424
|
name: 'DPC_ERR_STS'
|
|
2401
2425
|
description: ''
|
|
2402
|
-
S3_5_c15_c1_1:
|
|
2426
|
+
- 'S3_5_c15_c1_1':
|
|
2403
2427
|
name: 'IPI_SR'
|
|
2404
2428
|
description: ''
|
|
2405
|
-
S3_5_c15_c3_1:
|
|
2429
|
+
- 'S3_5_c15_c3_1':
|
|
2406
2430
|
name: 'IPI_CR'
|
|
2407
2431
|
description: ''
|
|
2408
|
-
S3_5_c15_c4_0:
|
|
2432
|
+
- 'S3_5_c15_c4_0':
|
|
2409
2433
|
name: 'ACC_CFG/CYC_CFG'
|
|
2410
2434
|
description: ''
|
|
2411
|
-
S3_5_c15_c5_0:
|
|
2435
|
+
- 'S3_5_c15_c5_0':
|
|
2412
2436
|
name: 'CYC_OVRD'
|
|
2413
2437
|
description: ''
|
|
2414
|
-
S3_5_c15_c6_0:
|
|
2438
|
+
- 'S3_5_c15_c6_0':
|
|
2415
2439
|
name: 'ACC_OVRD'
|
|
2416
2440
|
description: ''
|
|
2417
|
-
S3_5_c15_c6_1:
|
|
2441
|
+
- 'S3_5_c15_c6_1':
|
|
2418
2442
|
name: 'ACC_EBLK_OVRD'
|
|
2419
2443
|
description: ''
|
|
2420
|
-
S3_6_c15_c0_0:
|
|
2444
|
+
- 'S3_6_c15_c0_0':
|
|
2421
2445
|
name: 'MMU_ERR_STS'
|
|
2422
2446
|
description: 'MMU Error Status'
|
|
2423
|
-
S3_6_c15_c2_0:
|
|
2447
|
+
- 'S3_6_c15_c2_0':
|
|
2424
2448
|
name: 'E_MMU_ERR_STS'
|
|
2425
2449
|
description: 'MMU Error Status'
|
|
2426
|
-
S3_6_c15_c12_4:
|
|
2450
|
+
- 'S3_6_c15_c12_4':
|
|
2427
2451
|
name: 'APSTS_EL1'
|
|
2428
2452
|
description: ''
|
|
2429
|
-
S3_7_c15_c0_4:
|
|
2453
|
+
- 'S3_7_c15_c0_4':
|
|
2430
2454
|
name: 'UPMCR0'
|
|
2431
2455
|
description: 'Controls which counters are enabled and how interrupts are generated for overflows'
|
|
2432
|
-
S3_7_c15_c0_5:
|
|
2456
|
+
- 'S3_7_c15_c0_5':
|
|
2433
2457
|
name: 'UPMC8'
|
|
2434
2458
|
description: ''
|
|
2435
|
-
S3_7_c15_c1_4:
|
|
2459
|
+
- 'S3_7_c15_c1_4':
|
|
2436
2460
|
name: 'UPMESR0'
|
|
2437
2461
|
description: 'Event selection register for counters 0-7'
|
|
2438
|
-
S3_7_c15_c1_5:
|
|
2462
|
+
- 'S3_7_c15_c1_5':
|
|
2439
2463
|
name: 'UPMC9'
|
|
2440
2464
|
description: ''
|
|
2441
|
-
S3_7_c15_c2_5:
|
|
2465
|
+
- 'S3_7_c15_c2_5':
|
|
2442
2466
|
name: 'UPMC10'
|
|
2443
2467
|
description: ''
|
|
2444
|
-
S3_7_c15_c3_4:
|
|
2468
|
+
- 'S3_7_c15_c3_4':
|
|
2445
2469
|
name: 'UPMECM0'
|
|
2446
2470
|
description: 'Event core masks for counters 0-3'
|
|
2447
|
-
S3_7_c15_c3_5:
|
|
2471
|
+
- 'S3_7_c15_c3_5':
|
|
2448
2472
|
name: 'UPMC11'
|
|
2449
2473
|
description: ''
|
|
2450
|
-
S3_7_c15_c4_4:
|
|
2474
|
+
- 'S3_7_c15_c4_4':
|
|
2451
2475
|
name: 'UPMECM1'
|
|
2452
2476
|
description: 'Event core masks for counters 4-7'
|
|
2453
|
-
S3_7_c15_c4_5:
|
|
2477
|
+
- 'S3_7_c15_c4_5':
|
|
2454
2478
|
name: 'UPMC12'
|
|
2455
2479
|
description: ''
|
|
2456
|
-
S3_7_c15_c5_4:
|
|
2480
|
+
- 'S3_7_c15_c5_4':
|
|
2457
2481
|
name: 'UPMPCM'
|
|
2458
2482
|
description: ''
|
|
2459
|
-
S3_7_c15_c5_5:
|
|
2483
|
+
- 'S3_7_c15_c5_5':
|
|
2460
2484
|
name: 'UPMC13'
|
|
2461
2485
|
description: ''
|
|
2462
|
-
S3_7_c15_c6_4:
|
|
2486
|
+
- 'S3_7_c15_c6_4':
|
|
2463
2487
|
name: 'UPMSR'
|
|
2464
2488
|
description: ''
|
|
2465
|
-
S3_7_c15_c6_5:
|
|
2489
|
+
- 'S3_7_c15_c6_5':
|
|
2466
2490
|
name: 'UPMC14'
|
|
2467
2491
|
description: ''
|
|
2468
|
-
S3_7_c15_c7_4:
|
|
2492
|
+
- 'S3_7_c15_c7_4':
|
|
2469
2493
|
name: 'UPMC0'
|
|
2470
2494
|
description: ''
|
|
2471
|
-
S3_7_c15_c7_5:
|
|
2495
|
+
- 'S3_7_c15_c7_5':
|
|
2472
2496
|
name: 'UPMC15'
|
|
2473
2497
|
description: ''
|
|
2474
|
-
S3_7_c15_c8_4:
|
|
2498
|
+
- 'S3_7_c15_c8_4':
|
|
2475
2499
|
name: 'UPMC1'
|
|
2476
2500
|
description: ''
|
|
2477
|
-
S3_7_c15_c8_5:
|
|
2501
|
+
- 'S3_7_c15_c8_5':
|
|
2478
2502
|
name: 'UPMECM2'
|
|
2479
2503
|
description: 'Event core masks for counters 8-11'
|
|
2480
|
-
S3_7_c15_c9_4:
|
|
2504
|
+
- 'S3_7_c15_c9_4':
|
|
2481
2505
|
name: 'UPMC2'
|
|
2482
2506
|
description: ''
|
|
2483
|
-
S3_7_c15_c9_5:
|
|
2507
|
+
- 'S3_7_c15_c9_5':
|
|
2484
2508
|
name: 'UPMECM3'
|
|
2485
2509
|
description: 'Event core masks for counters 12-15'
|
|
2486
|
-
S3_7_c15_c10_4:
|
|
2510
|
+
- 'S3_7_c15_c10_4':
|
|
2487
2511
|
name: 'UPMC3'
|
|
2488
2512
|
description: ''
|
|
2489
|
-
S3_7_c15_c11_4:
|
|
2513
|
+
- 'S3_7_c15_c11_4':
|
|
2490
2514
|
name: 'UPMC4'
|
|
2491
2515
|
description: ''
|
|
2492
|
-
S3_7_c15_c11_5:
|
|
2516
|
+
- 'S3_7_c15_c11_5':
|
|
2493
2517
|
name: 'UPMESR1'
|
|
2494
2518
|
description: 'Event selection register for counters 8-15'
|
|
2495
|
-
S3_7_c15_c12_4:
|
|
2519
|
+
- 'S3_7_c15_c12_4':
|
|
2496
2520
|
name: 'UPMC5'
|
|
2497
2521
|
description: ''
|
|
2498
|
-
S3_7_c15_c13_4:
|
|
2522
|
+
- 'S3_7_c15_c13_4':
|
|
2499
2523
|
name: 'UPMC6'
|
|
2500
2524
|
description: ''
|
|
2501
|
-
S3_7_c15_c14_4:
|
|
2525
|
+
- 'S3_7_c15_c14_4':
|
|
2502
2526
|
name: 'UPMC7'
|
|
2503
2527
|
description: ''
|