apple-data 0.1.0
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +7 -0
- data/share/4cc.yaml +295 -0
- data/share/apns.yaml +386 -0
- data/share/backup.yaml +45 -0
- data/share/baseband.yaml +4 -0
- data/share/bluetooth.yaml +76 -0
- data/share/boot_args.yaml +856 -0
- data/share/bridgeos.yaml +165 -0
- data/share/bundles.yaml +61 -0
- data/share/cores.yaml +1738 -0
- data/share/credits.yaml +6222 -0
- data/share/dnssd.yaml +289 -0
- data/share/fdr.yaml +171 -0
- data/share/homekit.yaml +15 -0
- data/share/icloud.yaml +9 -0
- data/share/img4.yaml +456 -0
- data/share/ioreg.yaml +5643 -0
- data/share/ipsw.yaml +1101 -0
- data/share/kext.yaml +1719 -0
- data/share/launchd/services_bridgeOS_6.1.yaml +1323 -0
- data/share/lightning.yaml +35 -0
- data/share/lockdownd.yaml +79 -0
- data/share/mach_o.yaml +428 -0
- data/share/mobile_assets.yaml +964 -0
- data/share/mobile_gestalt.yaml +2446 -0
- data/share/nvram.yaml +442 -0
- data/share/ota.yaml +9 -0
- data/share/pki.yaml +170 -0
- data/share/platforms.yaml +32 -0
- data/share/pmu.yaml +30 -0
- data/share/registers.yaml +2527 -0
- data/share/resources.yaml +199 -0
- data/share/sep.yaml +210 -0
- data/share/services.yaml +638 -0
- data/share/syscfg.yaml +1 -0
- metadata +78 -0
|
@@ -0,0 +1,2527 @@
|
|
|
1
|
+
---
|
|
2
|
+
description: Representations of registers and instructions for various CPU elements
|
|
3
|
+
credits:
|
|
4
|
+
- https://gist.github.com/bazad/42054285391c6e0dcd0ede4b5f969ad2
|
|
5
|
+
aarch64:
|
|
6
|
+
pstate:
|
|
7
|
+
0b011: 'UAO'
|
|
8
|
+
0b100: 'PAN'
|
|
9
|
+
0b101: 'SPSel'
|
|
10
|
+
0b110: 'DAIFSet'
|
|
11
|
+
0b111: 'DAIFClr'
|
|
12
|
+
msr:
|
|
13
|
+
'S1_0_c7_c1_0':
|
|
14
|
+
- name: 'IC IALLUIS'
|
|
15
|
+
description: 'Instruction Cache Invalidate All to PoU, Inner Shareable'
|
|
16
|
+
'S1_0_c7_c5_0':
|
|
17
|
+
- name: 'IC IALLU'
|
|
18
|
+
description: 'Instruction Cache Invalidate All to PoU'
|
|
19
|
+
'S1_0_c7_c6_1':
|
|
20
|
+
- name: 'DC IVAC'
|
|
21
|
+
description: 'Data or unified Cache line Invalidate by VA to PoC'
|
|
22
|
+
'S1_0_c7_c6_2':
|
|
23
|
+
- name: 'DC ISW'
|
|
24
|
+
description: 'Data or unified Cache line Invalidate by Set/Way'
|
|
25
|
+
'S1_0_c7_c6_3':
|
|
26
|
+
- name: 'DC IGVAC'
|
|
27
|
+
description: 'Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC'
|
|
28
|
+
'S1_0_c7_c6_4':
|
|
29
|
+
- name: 'DC IGSW'
|
|
30
|
+
description: 'Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by Set/Way'
|
|
31
|
+
'S1_0_c7_c6_5':
|
|
32
|
+
- name: 'DC IGDVAC'
|
|
33
|
+
description: 'Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC'
|
|
34
|
+
'S1_0_c7_c6_6':
|
|
35
|
+
- name: 'DC IGDSW'
|
|
36
|
+
description: 'Data, Allocation Tag or unified Cache line Invalidate of Data and Allocation Tags by Set/Way'
|
|
37
|
+
'S1_0_c7_c8_0':
|
|
38
|
+
- name: 'AT S1E1R'
|
|
39
|
+
description: 'Address Translate Stage 1 EL1 Read'
|
|
40
|
+
'S1_0_c7_c8_1':
|
|
41
|
+
- name: 'AT S1E1W'
|
|
42
|
+
description: 'Address Translate Stage 1 EL1 Write'
|
|
43
|
+
'S1_0_c7_c8_2':
|
|
44
|
+
- name: 'AT S1E0R'
|
|
45
|
+
description: 'Address Translate Stage 1 EL0 Read'
|
|
46
|
+
'S1_0_c7_c8_3':
|
|
47
|
+
- name: 'AT S1E0W'
|
|
48
|
+
description: 'Address Translate Stage 1 EL0 Write'
|
|
49
|
+
'S1_0_c7_c9_0':
|
|
50
|
+
- name: 'AT S1E1RP'
|
|
51
|
+
description: 'Address Translate Stage 1 EL1 Read PAN'
|
|
52
|
+
'S1_0_c7_c9_1':
|
|
53
|
+
- name: 'AT S1E1WP'
|
|
54
|
+
description: 'Address Translate Stage 1 EL1 Write PAN'
|
|
55
|
+
'S1_0_c7_c10_2':
|
|
56
|
+
- name: 'DC CSW'
|
|
57
|
+
description: 'Data or unified Cache line Clean by Set/Way'
|
|
58
|
+
'S1_0_c7_c10_4':
|
|
59
|
+
- name: 'DC CGSW'
|
|
60
|
+
description: 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by Set/Way'
|
|
61
|
+
'S1_0_c7_c10_6':
|
|
62
|
+
- name: 'DC CGDSW'
|
|
63
|
+
description: 'Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by Set/Way'
|
|
64
|
+
'S1_0_c7_c14_2':
|
|
65
|
+
- name: 'DC CISW'
|
|
66
|
+
description: 'Data or unified Cache line Clean and Invalidate by Set/Way'
|
|
67
|
+
'S1_0_c7_c14_4':
|
|
68
|
+
- name: 'DC CIGSW'
|
|
69
|
+
description: 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by Set/Way'
|
|
70
|
+
'S1_0_c7_c14_6':
|
|
71
|
+
- name: 'DC CIGDSW'
|
|
72
|
+
description: 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by Set/Way'
|
|
73
|
+
'S1_0_c8_c1_0':
|
|
74
|
+
- name: 'TLBI VMALLE1OS'
|
|
75
|
+
description: 'TLB Invalidate by VMID, All at stage 1, EL1, Outer Shareable'
|
|
76
|
+
'S1_0_c8_c1_1':
|
|
77
|
+
- name: 'TLBI VAE1OS'
|
|
78
|
+
description: 'TLB Invalidate by VA, EL1, Outer Shareable'
|
|
79
|
+
'S1_0_c8_c1_2':
|
|
80
|
+
- name: 'TLBI ASIDE1OS'
|
|
81
|
+
description: 'TLB Invalidate by ASID, EL1, Outer Shareable'
|
|
82
|
+
'S1_0_c8_c1_3':
|
|
83
|
+
- name: 'TLBI VAAE1OS'
|
|
84
|
+
description: 'TLB Invalidate by VA, All ASID, EL1, Outer Shareable'
|
|
85
|
+
'S1_0_c8_c1_5':
|
|
86
|
+
- name: 'TLBI VALE1OS'
|
|
87
|
+
description: 'TLB Invalidate by VA, Last level, EL1, Outer Shareable'
|
|
88
|
+
'S1_0_c8_c1_7':
|
|
89
|
+
- name: 'TLBI VAALE1OS'
|
|
90
|
+
description: 'TLB Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable'
|
|
91
|
+
'S1_0_c8_c2_1':
|
|
92
|
+
- name: 'TLBI RVAE1IS'
|
|
93
|
+
description: 'TLB Range Invalidate by VA, EL1, Inner Shareable'
|
|
94
|
+
'S1_0_c8_c2_3':
|
|
95
|
+
- name: 'TLBI RVAAE1IS'
|
|
96
|
+
description: 'TLB Range Invalidate by VA, All ASID, EL1, Inner Shareable'
|
|
97
|
+
'S1_0_c8_c2_5':
|
|
98
|
+
- name: 'TLBI RVALE1IS'
|
|
99
|
+
description: 'TLB Range Invalidate by VA, Last level, EL1, Inner Shareable'
|
|
100
|
+
'S1_0_c8_c2_7':
|
|
101
|
+
- name: 'TLBI RVAALE1IS'
|
|
102
|
+
description: 'TLB Range Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable'
|
|
103
|
+
'S1_0_c8_c3_0':
|
|
104
|
+
- name: 'TLBI VMALLE1IS'
|
|
105
|
+
description: 'TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable'
|
|
106
|
+
'S1_0_c8_c3_1':
|
|
107
|
+
- name: 'TLBI VAE1IS'
|
|
108
|
+
description: 'TLB Invalidate by VA, EL1, Inner Shareable'
|
|
109
|
+
'S1_0_c8_c3_2':
|
|
110
|
+
- name: 'TLBI ASIDE1IS'
|
|
111
|
+
description: 'TLB Invalidate by ASID, EL1, Inner Shareable'
|
|
112
|
+
'S1_0_c8_c3_3':
|
|
113
|
+
- name: 'TLBI VAAE1IS'
|
|
114
|
+
description: 'TLB Invalidate by VA, All ASID, EL1, Inner Shareable'
|
|
115
|
+
'S1_0_c8_c3_5':
|
|
116
|
+
- name: 'TLBI VALE1IS'
|
|
117
|
+
description: 'TLB Invalidate by VA, Last level, EL1, Inner Shareable'
|
|
118
|
+
'S1_0_c8_c3_7':
|
|
119
|
+
- name: 'TLBI VAALE1IS'
|
|
120
|
+
description: 'TLB Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable'
|
|
121
|
+
'S1_0_c8_c5_1':
|
|
122
|
+
- name: 'TLBI RVAE1OS'
|
|
123
|
+
description: 'TLB Range Invalidate by VA, EL1, Outer Shareable'
|
|
124
|
+
'S1_0_c8_c5_3':
|
|
125
|
+
- name: 'TLBI RVAAE1OS'
|
|
126
|
+
description: 'TLB Range Invalidate by VA, All ASID, EL1, Outer Shareable'
|
|
127
|
+
'S1_0_c8_c5_5':
|
|
128
|
+
- name: 'TLBI RVALE1OS'
|
|
129
|
+
description: 'TLB Range Invalidate by VA, Last level, EL1, Outer Shareable'
|
|
130
|
+
'S1_0_c8_c5_7':
|
|
131
|
+
- name: 'TLBI RVAALE1OS'
|
|
132
|
+
description: 'TLB Range Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable'
|
|
133
|
+
'S1_0_c8_c6_1':
|
|
134
|
+
- name: 'TLBI RVAE1'
|
|
135
|
+
description: 'TLB Range Invalidate by VA, EL1'
|
|
136
|
+
'S1_0_c8_c6_3':
|
|
137
|
+
- name: 'TLBI RVAAE1'
|
|
138
|
+
description: 'TLB Range Invalidate by VA, All ASID, EL1'
|
|
139
|
+
'S1_0_c8_c6_5':
|
|
140
|
+
- name: 'TLBI RVALE1'
|
|
141
|
+
description: 'TLB Range Invalidate by VA, Last level, EL1'
|
|
142
|
+
'S1_0_c8_c6_7':
|
|
143
|
+
- name: 'TLBI RVAALE1'
|
|
144
|
+
description: 'TLB Range Invalidate by VA, All ASID, Last level, EL1'
|
|
145
|
+
'S1_0_c8_c7_0':
|
|
146
|
+
- name: 'TLBI VMALLE1'
|
|
147
|
+
description: 'TLB Invalidate by VMID, All at stage 1, EL1'
|
|
148
|
+
'S1_0_c8_c7_1':
|
|
149
|
+
- name: 'TLBI VAE1'
|
|
150
|
+
description: 'TLB Invalidate by VA, EL1'
|
|
151
|
+
'S1_0_c8_c7_2':
|
|
152
|
+
- name: 'TLBI ASIDE1'
|
|
153
|
+
description: 'TLB Invalidate by ASID, EL1'
|
|
154
|
+
'S1_0_c8_c7_3':
|
|
155
|
+
- name: 'TLBI VAAE1'
|
|
156
|
+
description: 'TLB Invalidate by VA, All ASID, EL1'
|
|
157
|
+
'S1_0_c8_c7_5':
|
|
158
|
+
- name: 'TLBI VALE1'
|
|
159
|
+
description: 'TLB Invalidate by VA, Last level, EL1'
|
|
160
|
+
'S1_0_c8_c7_7':
|
|
161
|
+
- name: 'TLBI VAALE1'
|
|
162
|
+
description: 'TLB Invalidate by VA, All ASID, Last level, EL1'
|
|
163
|
+
'S1_3_c7_c3_4':
|
|
164
|
+
- name: 'CFP RCTX'
|
|
165
|
+
description: 'Control Flow Prediction Restriction by Context'
|
|
166
|
+
'S1_3_c7_c3_5':
|
|
167
|
+
- name: 'DVP RCTX'
|
|
168
|
+
description: 'Data Value Prediction Restriction by Context'
|
|
169
|
+
'S1_3_c7_c3_7':
|
|
170
|
+
- name: 'CPP RCTX'
|
|
171
|
+
description: 'Cache Prefetch Prediction Restriction by Context'
|
|
172
|
+
'S1_3_c7_c4_1':
|
|
173
|
+
- name: 'DC ZVA'
|
|
174
|
+
description: 'Data Cache Zero by VA'
|
|
175
|
+
'S1_3_c7_c4_3':
|
|
176
|
+
- name: 'DC GVA'
|
|
177
|
+
description: 'Data Cache set Allocation Tag by VA'
|
|
178
|
+
'S1_3_c7_c4_4':
|
|
179
|
+
- name: 'DC GZVA'
|
|
180
|
+
description: 'Data Cache set Allocation Tags and Zero by VA'
|
|
181
|
+
'S1_3_c7_c5_1':
|
|
182
|
+
- name: 'IC IVAU'
|
|
183
|
+
description: 'Instruction Cache line Invalidate by VA to PoU'
|
|
184
|
+
'S1_3_c7_c10_1':
|
|
185
|
+
- name: 'DC CVAC'
|
|
186
|
+
description: 'Data or unified Cache line Clean by VA to PoC'
|
|
187
|
+
'S1_3_c7_c10_3':
|
|
188
|
+
- name: 'DC CGVAC'
|
|
189
|
+
description: 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC'
|
|
190
|
+
'S1_3_c7_c10_5':
|
|
191
|
+
- name: 'DC CGDVAC'
|
|
192
|
+
description: 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC'
|
|
193
|
+
'S1_3_c7_c11_1':
|
|
194
|
+
- name: 'DC CVAU'
|
|
195
|
+
description: 'Data or unified Cache line Clean by VA to PoU'
|
|
196
|
+
'S1_3_c7_c12_1':
|
|
197
|
+
- name: 'DC CVAP'
|
|
198
|
+
description: 'Data or unified Cache line Clean by VA to PoP'
|
|
199
|
+
'S1_3_c7_c12_3':
|
|
200
|
+
- name: 'DC CGVAP'
|
|
201
|
+
description: 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoP'
|
|
202
|
+
'S1_3_c7_c12_5':
|
|
203
|
+
- name: 'DC CGDVAP'
|
|
204
|
+
description: 'Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by VA to PoP'
|
|
205
|
+
'S1_3_c7_c13_1':
|
|
206
|
+
- name: 'DC CVADP'
|
|
207
|
+
description: 'Data or unified Cache line Clean by VA to PoDP'
|
|
208
|
+
'S1_3_c7_c13_3':
|
|
209
|
+
- name: 'DC CGVADP'
|
|
210
|
+
description: 'Clean of Allocation Tags by VA to PoDP'
|
|
211
|
+
'S1_3_c7_c13_5':
|
|
212
|
+
- name: 'DC CGDVADP'
|
|
213
|
+
description: 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoDP'
|
|
214
|
+
'S1_3_c7_c14_1':
|
|
215
|
+
- name: 'DC CIVAC'
|
|
216
|
+
description: 'Data or unified Cache line Clean and Invalidate by VA to PoC'
|
|
217
|
+
'S1_3_c7_c14_3':
|
|
218
|
+
- name: 'DC CIGVAC'
|
|
219
|
+
description: 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by VA to PoC'
|
|
220
|
+
'S1_3_c7_c14_5':
|
|
221
|
+
- name: 'DC CIGDVAC'
|
|
222
|
+
description: 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by VA to PoC'
|
|
223
|
+
'S1_4_c7_c8_0':
|
|
224
|
+
- name: 'AT S1E2R'
|
|
225
|
+
description: 'Address Translate Stage 1 EL2 Read'
|
|
226
|
+
'S1_4_c7_c8_1':
|
|
227
|
+
- name: 'AT S1E2W'
|
|
228
|
+
description: 'Address Translate Stage 1 EL2 Write'
|
|
229
|
+
'S1_4_c7_c8_4':
|
|
230
|
+
- name: 'AT S12E1R'
|
|
231
|
+
description: 'Address Translate Stages 1 and 2 EL1 Read'
|
|
232
|
+
'S1_4_c7_c8_5':
|
|
233
|
+
- name: 'AT S12E1W'
|
|
234
|
+
description: 'Address Translate Stages 1 and 2 EL1 Write'
|
|
235
|
+
'S1_4_c7_c8_6':
|
|
236
|
+
- name: 'AT S12E0R'
|
|
237
|
+
description: 'Address Translate Stages 1 and 2 EL0 Read'
|
|
238
|
+
'S1_4_c7_c8_7':
|
|
239
|
+
- name: 'AT S12E0W'
|
|
240
|
+
description: 'Address Translate Stages 1 and 2 EL0 Write'
|
|
241
|
+
'S1_4_c8_c0_1':
|
|
242
|
+
- name: 'TLBI IPAS2E1IS'
|
|
243
|
+
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable'
|
|
244
|
+
'S1_4_c8_c0_2':
|
|
245
|
+
- name: 'TLBI RIPAS2E1IS'
|
|
246
|
+
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable'
|
|
247
|
+
'S1_4_c8_c0_5':
|
|
248
|
+
- name: 'TLBI IPAS2LE1IS'
|
|
249
|
+
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable'
|
|
250
|
+
'S1_4_c8_c0_6':
|
|
251
|
+
- name: 'TLBI RIPAS2LE1IS'
|
|
252
|
+
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable'
|
|
253
|
+
'S1_4_c8_c1_0':
|
|
254
|
+
- name: 'TLBI ALLE2OS'
|
|
255
|
+
description: 'TLB Invalidate All, EL2, Outer Shareable'
|
|
256
|
+
'S1_4_c8_c1_1':
|
|
257
|
+
- name: 'TLBI VAE2OS'
|
|
258
|
+
description: 'TLB Invalidate by VA, EL2, Outer Shareable'
|
|
259
|
+
'S1_4_c8_c1_4':
|
|
260
|
+
- name: 'TLBI ALLE1OS'
|
|
261
|
+
description: 'TLB Invalidate All, EL1, Outer Shareable'
|
|
262
|
+
'S1_4_c8_c1_5':
|
|
263
|
+
- name: 'TLBI VALE2OS'
|
|
264
|
+
description: 'TLB Invalidate by VA, Last level, EL2, Outer Shareable'
|
|
265
|
+
'S1_4_c8_c1_6':
|
|
266
|
+
- name: 'TLBI VMALLS12E1OS'
|
|
267
|
+
description: 'TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Outer Shareable'
|
|
268
|
+
'S1_4_c8_c2_1':
|
|
269
|
+
- name: 'TLBI RVAE2IS'
|
|
270
|
+
description: 'TLB Range Invalidate by VA, EL2, Inner Shareable'
|
|
271
|
+
'S1_4_c8_c2_5':
|
|
272
|
+
- name: 'TLBI RVALE2IS'
|
|
273
|
+
description: 'TLB Range Invalidate by VA, Last level, EL2, Inner Shareable'
|
|
274
|
+
'S1_4_c8_c3_0':
|
|
275
|
+
- name: 'TLBI ALLE2IS'
|
|
276
|
+
description: 'TLB Invalidate All, EL2, Inner Shareable'
|
|
277
|
+
'S1_4_c8_c3_1':
|
|
278
|
+
- name: 'TLBI VAE2IS'
|
|
279
|
+
description: 'TLB Invalidate by VA, EL2, Inner Shareable'
|
|
280
|
+
'S1_4_c8_c3_4':
|
|
281
|
+
- name: 'TLBI ALLE1IS'
|
|
282
|
+
description: 'TLB Invalidate All, EL1, Inner Shareable'
|
|
283
|
+
'S1_4_c8_c3_5':
|
|
284
|
+
- name: 'TLBI VALE2IS'
|
|
285
|
+
description: 'TLB Invalidate by VA, Last level, EL2, Inner Shareable'
|
|
286
|
+
'S1_4_c8_c3_6':
|
|
287
|
+
- name: 'TLBI VMALLS12E1IS'
|
|
288
|
+
description: 'TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable'
|
|
289
|
+
'S1_4_c8_c4_0':
|
|
290
|
+
- name: 'TLBI IPAS2E1OS'
|
|
291
|
+
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable'
|
|
292
|
+
'S1_4_c8_c4_1':
|
|
293
|
+
- name: 'TLBI IPAS2E1'
|
|
294
|
+
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, EL1'
|
|
295
|
+
'S1_4_c8_c4_2':
|
|
296
|
+
- name: 'TLBI RIPAS2E1'
|
|
297
|
+
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1'
|
|
298
|
+
'S1_4_c8_c4_3':
|
|
299
|
+
- name: 'TLBI RIPAS2E1OS'
|
|
300
|
+
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable'
|
|
301
|
+
'S1_4_c8_c4_4':
|
|
302
|
+
- name: 'TLBI IPAS2LE1OS'
|
|
303
|
+
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable'
|
|
304
|
+
'S1_4_c8_c4_5':
|
|
305
|
+
- name: 'TLBI IPAS2LE1'
|
|
306
|
+
description: 'TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1'
|
|
307
|
+
'S1_4_c8_c4_6':
|
|
308
|
+
- name: 'TLBI RIPAS2LE1'
|
|
309
|
+
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1'
|
|
310
|
+
'S1_4_c8_c4_7':
|
|
311
|
+
- name: 'TLBI RIPAS2LE1OS'
|
|
312
|
+
description: 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable'
|
|
313
|
+
'S1_4_c8_c5_1':
|
|
314
|
+
- name: 'TLBI RVAE2OS'
|
|
315
|
+
description: 'TLB Range Invalidate by VA, EL2, Outer Shareable'
|
|
316
|
+
'S1_4_c8_c5_5':
|
|
317
|
+
- name: 'TLBI RVALE2OS'
|
|
318
|
+
description: 'TLB Range Invalidate by VA, Last level, EL2, Outer Shareable'
|
|
319
|
+
'S1_4_c8_c6_1':
|
|
320
|
+
- name: 'TLBI RVAE2'
|
|
321
|
+
description: 'TLB Range Invalidate by VA, EL2'
|
|
322
|
+
'S1_4_c8_c6_5':
|
|
323
|
+
- name: 'TLBI RVALE2'
|
|
324
|
+
description: 'TLB Range Invalidate by VA, Last level, EL2'
|
|
325
|
+
'S1_4_c8_c7_0':
|
|
326
|
+
- name: 'TLBI ALLE2'
|
|
327
|
+
description: 'TLB Invalidate All, EL2'
|
|
328
|
+
'S1_4_c8_c7_1':
|
|
329
|
+
- name: 'TLBI VAE2'
|
|
330
|
+
description: 'TLB Invalidate by VA, EL2'
|
|
331
|
+
'S1_4_c8_c7_4':
|
|
332
|
+
- name: 'TLBI ALLE1'
|
|
333
|
+
description: 'TLB Invalidate All, EL1'
|
|
334
|
+
'S1_4_c8_c7_5':
|
|
335
|
+
- name: 'TLBI VALE2'
|
|
336
|
+
description: 'TLB Invalidate by VA, Last level, EL2'
|
|
337
|
+
'S1_4_c8_c7_6':
|
|
338
|
+
- name: 'TLBI VMALLS12E1'
|
|
339
|
+
description: 'TLB Invalidate by VMID, All at Stage 1 and 2, EL1'
|
|
340
|
+
'S1_6_c7_c8_0':
|
|
341
|
+
- name: 'AT S1E3R'
|
|
342
|
+
description: 'Address Translate Stage 1 EL3 Read'
|
|
343
|
+
'S1_6_c7_c8_1':
|
|
344
|
+
- name: 'AT S1E3W'
|
|
345
|
+
description: 'Address Translate Stage 1 EL3 Write'
|
|
346
|
+
'S1_6_c8_c1_0':
|
|
347
|
+
- name: 'TLBI ALLE3OS'
|
|
348
|
+
description: 'TLB Invalidate All, EL3, Outer Shareable'
|
|
349
|
+
'S1_6_c8_c1_1':
|
|
350
|
+
- name: 'TLBI VAE3OS'
|
|
351
|
+
description: 'TLB Invalidate by VA, EL3, Outer Shareable'
|
|
352
|
+
'S1_6_c8_c1_5':
|
|
353
|
+
- name: 'TLBI VALE3OS'
|
|
354
|
+
description: 'TLB Invalidate by VA, Last level, EL3, Outer Shareable'
|
|
355
|
+
'S1_6_c8_c2_1':
|
|
356
|
+
- name: 'TLBI RVAE3IS'
|
|
357
|
+
description: 'TLB Range Invalidate by VA, EL3, Inner Shareable'
|
|
358
|
+
'S1_6_c8_c2_5':
|
|
359
|
+
- name: 'TLBI RVALE3IS'
|
|
360
|
+
description: 'TLB Range Invalidate by VA, Last level, EL3, Inner Shareable'
|
|
361
|
+
'S1_6_c8_c3_0':
|
|
362
|
+
- name: 'TLBI ALLE3IS'
|
|
363
|
+
description: 'TLB Invalidate All, EL3, Inner Shareable'
|
|
364
|
+
'S1_6_c8_c3_1':
|
|
365
|
+
- name: 'TLBI VAE3IS'
|
|
366
|
+
description: 'TLB Invalidate by VA, EL3, Inner Shareable'
|
|
367
|
+
'S1_6_c8_c3_5':
|
|
368
|
+
- name: 'TLBI VALE3IS'
|
|
369
|
+
description: 'TLB Invalidate by VA, Last level, EL3, Inner Shareable'
|
|
370
|
+
'S1_6_c8_c5_1':
|
|
371
|
+
- name: 'TLBI RVAE3OS'
|
|
372
|
+
description: 'TLB Range Invalidate by VA, EL3, Outer Shareable'
|
|
373
|
+
'S1_6_c8_c5_5':
|
|
374
|
+
- name: 'TLBI RVALE3OS'
|
|
375
|
+
description: 'TLB Range Invalidate by VA, Last level, EL3, Outer Shareable'
|
|
376
|
+
'S1_6_c8_c6_1':
|
|
377
|
+
- name: 'TLBI RVAE3'
|
|
378
|
+
description: 'TLB Range Invalidate by VA, EL3'
|
|
379
|
+
'S1_6_c8_c6_5':
|
|
380
|
+
- name: 'TLBI RVALE3'
|
|
381
|
+
description: 'TLB Range Invalidate by VA, Last level, EL3'
|
|
382
|
+
'S1_6_c8_c7_0':
|
|
383
|
+
- name: 'TLBI ALLE3'
|
|
384
|
+
description: 'TLB Invalidate All, EL3'
|
|
385
|
+
'S1_6_c8_c7_1':
|
|
386
|
+
- name: 'TLBI VAE3'
|
|
387
|
+
description: 'TLB Invalidate by VA, EL3'
|
|
388
|
+
'S1_6_c8_c7_5':
|
|
389
|
+
- name: 'TLBI VALE3'
|
|
390
|
+
description: 'TLB Invalidate by VA, Last level, EL3'
|
|
391
|
+
'S2_0_c0_c0_2':
|
|
392
|
+
- name: 'OSDTRRX_EL1'
|
|
393
|
+
description: 'OS Lock Data Transfer Register, Receive'
|
|
394
|
+
'S2_0_c0_c0_4':
|
|
395
|
+
- name: 'DBGBVR0_EL1'
|
|
396
|
+
description: 'Debug Breakpoint Value Register 0'
|
|
397
|
+
'S2_0_c0_c0_5':
|
|
398
|
+
- name: 'DBGBCR0_EL1'
|
|
399
|
+
description: 'Debug Breakpoint Control Register 0'
|
|
400
|
+
'S2_0_c0_c0_6':
|
|
401
|
+
- name: 'DBGWVR0_EL1'
|
|
402
|
+
description: 'Debug Watchpoint Value Register 0'
|
|
403
|
+
'S2_0_c0_c0_7':
|
|
404
|
+
- name: 'DBGWCR0_EL1'
|
|
405
|
+
description: 'Debug Watchpoint Control Register 0'
|
|
406
|
+
'S2_0_c0_c1_4':
|
|
407
|
+
- name: 'DBGBVR1_EL1'
|
|
408
|
+
description: 'Debug Breakpoint Value Register 1'
|
|
409
|
+
'S2_0_c0_c1_5':
|
|
410
|
+
- name: 'DBGBCR1_EL1'
|
|
411
|
+
description: 'Debug Breakpoint Control Register 1'
|
|
412
|
+
'S2_0_c0_c1_6':
|
|
413
|
+
- name: 'DBGWVR1_EL1'
|
|
414
|
+
description: 'Debug Watchpoint Value Register 1'
|
|
415
|
+
'S2_0_c0_c1_7':
|
|
416
|
+
- name: 'DBGWCR1_EL1'
|
|
417
|
+
description: 'Debug Watchpoint Control Register 1'
|
|
418
|
+
'S2_0_c0_c2_0':
|
|
419
|
+
- name: 'MDCCINT_EL1'
|
|
420
|
+
description: 'Monitor DCC Interrupt Enable Register'
|
|
421
|
+
'S2_0_c0_c2_2':
|
|
422
|
+
- name: 'MDSCR_EL1'
|
|
423
|
+
description: 'Monitor Debug System Control Register'
|
|
424
|
+
'S2_0_c0_c2_4':
|
|
425
|
+
- name: 'DBGBVR2_EL1'
|
|
426
|
+
description: 'Debug Breakpoint Value Register 2'
|
|
427
|
+
'S2_0_c0_c2_5':
|
|
428
|
+
- name: 'DBGBCR2_EL1'
|
|
429
|
+
description: 'Debug Breakpoint Control Register 2'
|
|
430
|
+
'S2_0_c0_c2_6':
|
|
431
|
+
- name: 'DBGWVR2_EL1'
|
|
432
|
+
description: 'Debug Watchpoint Value Register 2'
|
|
433
|
+
'S2_0_c0_c2_7':
|
|
434
|
+
- name: 'DBGWCR2_EL1'
|
|
435
|
+
description: 'Debug Watchpoint Control Register 2'
|
|
436
|
+
'S2_0_c0_c3_2':
|
|
437
|
+
- name: 'OSDTRTX_EL1'
|
|
438
|
+
description: 'OS Lock Data Transfer Register, Transmit'
|
|
439
|
+
'S2_0_c0_c3_4':
|
|
440
|
+
- name: 'DBGBVR3_EL1'
|
|
441
|
+
description: 'Debug Breakpoint Value Register 3'
|
|
442
|
+
'S2_0_c0_c3_5':
|
|
443
|
+
- name: 'DBGBCR3_EL1'
|
|
444
|
+
description: 'Debug Breakpoint Control Register 3'
|
|
445
|
+
'S2_0_c0_c3_6':
|
|
446
|
+
- name: 'DBGWVR3_EL1'
|
|
447
|
+
description: 'Debug Watchpoint Value Register 3'
|
|
448
|
+
'S2_0_c0_c3_7':
|
|
449
|
+
- name: 'DBGWCR3_EL1'
|
|
450
|
+
description: 'Debug Watchpoint Control Register 3'
|
|
451
|
+
'S2_0_c0_c4_4':
|
|
452
|
+
- name: 'DBGBVR4_EL1'
|
|
453
|
+
description: 'Debug Breakpoint Value Register 4'
|
|
454
|
+
'S2_0_c0_c4_5':
|
|
455
|
+
- name: 'DBGBCR4_EL1'
|
|
456
|
+
description: 'Debug Breakpoint Control Register 4'
|
|
457
|
+
'S2_0_c0_c4_6':
|
|
458
|
+
- name: 'DBGWVR4_EL1'
|
|
459
|
+
description: 'Debug Watchpoint Value Register 4'
|
|
460
|
+
'S2_0_c0_c4_7':
|
|
461
|
+
- name: 'DBGWCR4_EL1'
|
|
462
|
+
description: 'Debug Watchpoint Control Register 4'
|
|
463
|
+
'S2_0_c0_c5_4':
|
|
464
|
+
- name: 'DBGBVR5_EL1'
|
|
465
|
+
description: 'Debug Breakpoint Value Register 5'
|
|
466
|
+
'S2_0_c0_c5_5':
|
|
467
|
+
- name: 'DBGBCR5_EL1'
|
|
468
|
+
description: 'Debug Breakpoint Control Register 5'
|
|
469
|
+
'S2_0_c0_c5_6':
|
|
470
|
+
- name: 'DBGWVR5_EL1'
|
|
471
|
+
description: 'Debug Watchpoint Value Register 5'
|
|
472
|
+
'S2_0_c0_c5_7':
|
|
473
|
+
- name: 'DBGWCR5_EL1'
|
|
474
|
+
description: 'Debug Watchpoint Control Register 5'
|
|
475
|
+
'S2_0_c0_c6_2':
|
|
476
|
+
- name: 'OSECCR_EL1'
|
|
477
|
+
description: 'OS Lock Exception Catch Control Register'
|
|
478
|
+
'S2_0_c0_c6_4':
|
|
479
|
+
- name: 'DBGBVR6_EL1'
|
|
480
|
+
description: 'Debug Breakpoint Value Register 6'
|
|
481
|
+
'S2_0_c0_c6_5':
|
|
482
|
+
- name: 'DBGBCR6_EL1'
|
|
483
|
+
description: 'Debug Breakpoint Control Register 6'
|
|
484
|
+
'S2_0_c0_c6_6':
|
|
485
|
+
- name: 'DBGWVR6_EL1'
|
|
486
|
+
description: 'Debug Watchpoint Value Register 6'
|
|
487
|
+
'S2_0_c0_c6_7':
|
|
488
|
+
- name: 'DBGWCR6_EL1'
|
|
489
|
+
description: 'Debug Watchpoint Control Register 6'
|
|
490
|
+
'S2_0_c0_c7_4':
|
|
491
|
+
- name: 'DBGBVR7_EL1'
|
|
492
|
+
description: 'Debug Breakpoint Value Register 7'
|
|
493
|
+
'S2_0_c0_c7_5':
|
|
494
|
+
- name: 'DBGBCR7_EL1'
|
|
495
|
+
description: 'Debug Breakpoint Control Register 7'
|
|
496
|
+
'S2_0_c0_c7_6':
|
|
497
|
+
- name: 'DBGWVR7_EL1'
|
|
498
|
+
description: 'Debug Watchpoint Value Register 7'
|
|
499
|
+
'S2_0_c0_c7_7':
|
|
500
|
+
- name: 'DBGWCR7_EL1'
|
|
501
|
+
description: 'Debug Watchpoint Control Register 7'
|
|
502
|
+
'S2_0_c0_c8_4':
|
|
503
|
+
- name: 'DBGBVR8_EL1'
|
|
504
|
+
description: 'Debug Breakpoint Value Register 8'
|
|
505
|
+
'S2_0_c0_c8_5':
|
|
506
|
+
- name: 'DBGBCR8_EL1'
|
|
507
|
+
description: 'Debug Breakpoint Control Register 8'
|
|
508
|
+
'S2_0_c0_c8_6':
|
|
509
|
+
- name: 'DBGWVR8_EL1'
|
|
510
|
+
description: 'Debug Watchpoint Value Register 8'
|
|
511
|
+
'S2_0_c0_c8_7':
|
|
512
|
+
- name: 'DBGWCR8_EL1'
|
|
513
|
+
description: 'Debug Watchpoint Control Register 8'
|
|
514
|
+
'S2_0_c0_c9_4':
|
|
515
|
+
- name: 'DBGBVR9_EL1'
|
|
516
|
+
description: 'Debug Breakpoint Value Register 9'
|
|
517
|
+
'S2_0_c0_c9_5':
|
|
518
|
+
- name: 'DBGBCR9_EL1'
|
|
519
|
+
description: 'Debug Breakpoint Control Register 9'
|
|
520
|
+
'S2_0_c0_c9_6':
|
|
521
|
+
- name: 'DBGWVR9_EL1'
|
|
522
|
+
description: 'Debug Watchpoint Value Register 9'
|
|
523
|
+
'S2_0_c0_c9_7':
|
|
524
|
+
- name: 'DBGWCR9_EL1'
|
|
525
|
+
description: 'Debug Watchpoint Control Register 9'
|
|
526
|
+
'S2_0_c0_c10_4':
|
|
527
|
+
- name: 'DBGBVR10_EL1'
|
|
528
|
+
description: 'Debug Breakpoint Value Register 10'
|
|
529
|
+
'S2_0_c0_c10_5':
|
|
530
|
+
- name: 'DBGBCR10_EL1'
|
|
531
|
+
description: 'Debug Breakpoint Control Register 10'
|
|
532
|
+
'S2_0_c0_c10_6':
|
|
533
|
+
- name: 'DBGWVR10_EL1'
|
|
534
|
+
description: 'Debug Watchpoint Value Register 10'
|
|
535
|
+
'S2_0_c0_c10_7':
|
|
536
|
+
- name: 'DBGWCR10_EL1'
|
|
537
|
+
description: 'Debug Watchpoint Control Register 10'
|
|
538
|
+
'S2_0_c0_c11_4':
|
|
539
|
+
- name: 'DBGBVR11_EL1'
|
|
540
|
+
description: 'Debug Breakpoint Value Register 11'
|
|
541
|
+
'S2_0_c0_c11_5':
|
|
542
|
+
- name: 'DBGBCR11_EL1'
|
|
543
|
+
description: 'Debug Breakpoint Control Register 11'
|
|
544
|
+
'S2_0_c0_c11_6':
|
|
545
|
+
- name: 'DBGWVR11_EL1'
|
|
546
|
+
description: 'Debug Watchpoint Value Register 11'
|
|
547
|
+
'S2_0_c0_c11_7':
|
|
548
|
+
- name: 'DBGWCR11_EL1'
|
|
549
|
+
description: 'Debug Watchpoint Control Register 11'
|
|
550
|
+
'S2_0_c0_c12_4':
|
|
551
|
+
- name: 'DBGBVR12_EL1'
|
|
552
|
+
description: 'Debug Breakpoint Value Register 12'
|
|
553
|
+
'S2_0_c0_c12_5':
|
|
554
|
+
- name: 'DBGBCR12_EL1'
|
|
555
|
+
description: 'Debug Breakpoint Control Register 12'
|
|
556
|
+
'S2_0_c0_c12_6':
|
|
557
|
+
- name: 'DBGWVR12_EL1'
|
|
558
|
+
description: 'Debug Watchpoint Value Register 12'
|
|
559
|
+
'S2_0_c0_c12_7':
|
|
560
|
+
- name: 'DBGWCR12_EL1'
|
|
561
|
+
description: 'Debug Watchpoint Control Register 12'
|
|
562
|
+
'S2_0_c0_c13_4':
|
|
563
|
+
- name: 'DBGBVR13_EL1'
|
|
564
|
+
description: 'Debug Breakpoint Value Register 13'
|
|
565
|
+
'S2_0_c0_c13_5':
|
|
566
|
+
- name: 'DBGBCR13_EL1'
|
|
567
|
+
description: 'Debug Breakpoint Control Register 13'
|
|
568
|
+
'S2_0_c0_c13_6':
|
|
569
|
+
- name: 'DBGWVR13_EL1'
|
|
570
|
+
description: 'Debug Watchpoint Value Register 13'
|
|
571
|
+
'S2_0_c0_c13_7':
|
|
572
|
+
- name: 'DBGWCR13_EL1'
|
|
573
|
+
description: 'Debug Watchpoint Control Register 13'
|
|
574
|
+
'S2_0_c0_c14_4':
|
|
575
|
+
- name: 'DBGBVR14_EL1'
|
|
576
|
+
description: 'Debug Breakpoint Value Register 14'
|
|
577
|
+
'S2_0_c0_c14_5':
|
|
578
|
+
- name: 'DBGBCR14_EL1'
|
|
579
|
+
description: 'Debug Breakpoint Control Register 14'
|
|
580
|
+
'S2_0_c0_c14_6':
|
|
581
|
+
- name: 'DBGWVR14_EL1'
|
|
582
|
+
description: 'Debug Watchpoint Value Register 14'
|
|
583
|
+
'S2_0_c0_c14_7':
|
|
584
|
+
- name: 'DBGWCR14_EL1'
|
|
585
|
+
description: 'Debug Watchpoint Control Register 14'
|
|
586
|
+
'S2_0_c0_c15_4':
|
|
587
|
+
- name: 'DBGBVR15_EL1'
|
|
588
|
+
description: 'Debug Breakpoint Value Register 15'
|
|
589
|
+
'S2_0_c0_c15_5':
|
|
590
|
+
- name: 'DBGBCR15_EL1'
|
|
591
|
+
description: 'Debug Breakpoint Control Register 15'
|
|
592
|
+
'S2_0_c0_c15_6':
|
|
593
|
+
- name: 'DBGWVR15_EL1'
|
|
594
|
+
description: 'Debug Watchpoint Value Register 15'
|
|
595
|
+
'S2_0_c0_c15_7':
|
|
596
|
+
- name: 'DBGWCR15_EL1'
|
|
597
|
+
description: 'Debug Watchpoint Control Register 15'
|
|
598
|
+
'S2_0_c1_c0_0':
|
|
599
|
+
- name: 'MDRAR_EL1'
|
|
600
|
+
description: 'Monitor Debug ROM Address Register'
|
|
601
|
+
'S2_0_c1_c0_4':
|
|
602
|
+
- name: 'OSLAR_EL1'
|
|
603
|
+
description: 'OS Lock Access Register'
|
|
604
|
+
'S2_0_c1_c1_4':
|
|
605
|
+
- name: 'OSLSR_EL1'
|
|
606
|
+
description: 'OS Lock Status Register'
|
|
607
|
+
'S2_0_c1_c3_4':
|
|
608
|
+
- name: 'OSDLR_EL1'
|
|
609
|
+
description: 'OS Double Lock Register'
|
|
610
|
+
'S2_0_c1_c4_4':
|
|
611
|
+
- name: 'DBGPRCR_EL1'
|
|
612
|
+
description: 'Debug Power Control Register'
|
|
613
|
+
'S2_0_c7_c8_6':
|
|
614
|
+
- name: 'DBGCLAIMSET_EL1'
|
|
615
|
+
description: 'Debug CLAIM Tag Set register'
|
|
616
|
+
'S2_0_c7_c9_6':
|
|
617
|
+
- name: 'DBGCLAIMCLR_EL1'
|
|
618
|
+
description: 'Debug CLAIM Tag Clear register'
|
|
619
|
+
'S2_0_c7_c14_6':
|
|
620
|
+
- name: 'DBGAUTHSTATUS_EL1'
|
|
621
|
+
description: 'Debug Authentication Status register'
|
|
622
|
+
'S2_3_c0_c1_0':
|
|
623
|
+
- name: 'MDCCSR_EL0'
|
|
624
|
+
description: 'Monitor DCC Status Register'
|
|
625
|
+
'S2_3_c0_c4_0':
|
|
626
|
+
- name: 'DBGDTR_EL0'
|
|
627
|
+
description: 'Debug Data Transfer Register, half-duplex'
|
|
628
|
+
'S2_3_c0_c5_0':
|
|
629
|
+
- name: 'DBGDTRRX_EL0'
|
|
630
|
+
description: 'Debug Data Transfer Register, Receive'
|
|
631
|
+
- name: 'DBGDTRTX_EL0'
|
|
632
|
+
description: 'Debug Data Transfer Register, Transmit'
|
|
633
|
+
'S2_4_c0_c7_0':
|
|
634
|
+
- name: 'DBGVCR32_EL2'
|
|
635
|
+
description: 'Debug Vector Catch Register'
|
|
636
|
+
'S3_0_c0_c0_0':
|
|
637
|
+
- name: 'MIDR_EL1'
|
|
638
|
+
description: 'Main ID Register'
|
|
639
|
+
'S3_0_c0_c0_5':
|
|
640
|
+
- name: 'MPIDR_EL1'
|
|
641
|
+
description: 'Multiprocessor Affinity Register'
|
|
642
|
+
'S3_0_c0_c0_6':
|
|
643
|
+
- name: 'REVIDR_EL1'
|
|
644
|
+
description: 'Revision ID Register'
|
|
645
|
+
'S3_0_c0_c1_0':
|
|
646
|
+
- name: 'ID_PFR0_EL1'
|
|
647
|
+
description: 'AArch32 Processor Feature Register 0'
|
|
648
|
+
'S3_0_c0_c1_1':
|
|
649
|
+
- name: 'ID_PFR1_EL1'
|
|
650
|
+
description: 'AArch32 Processor Feature Register 1'
|
|
651
|
+
'S3_0_c0_c1_2':
|
|
652
|
+
- name: 'ID_DFR0_EL1'
|
|
653
|
+
description: 'AArch32 Debug Feature Register 0'
|
|
654
|
+
'S3_0_c0_c1_3':
|
|
655
|
+
- name: 'ID_AFR0_EL1'
|
|
656
|
+
description: 'AArch32 Auxiliary Feature Register 0'
|
|
657
|
+
'S3_0_c0_c1_4':
|
|
658
|
+
- name: 'ID_MMFR0_EL1'
|
|
659
|
+
description: 'AArch32 Memory Model Feature Register 0'
|
|
660
|
+
'S3_0_c0_c1_5':
|
|
661
|
+
- name: 'ID_MMFR1_EL1'
|
|
662
|
+
description: 'AArch32 Memory Model Feature Register 1'
|
|
663
|
+
'S3_0_c0_c1_6':
|
|
664
|
+
- name: 'ID_MMFR2_EL1'
|
|
665
|
+
description: 'AArch32 Memory Model Feature Register 2'
|
|
666
|
+
'S3_0_c0_c1_7':
|
|
667
|
+
- name: 'ID_MMFR3_EL1'
|
|
668
|
+
description: 'AArch32 Memory Model Feature Register 3'
|
|
669
|
+
'S3_0_c0_c2_0':
|
|
670
|
+
- name: 'ID_ISAR0_EL1'
|
|
671
|
+
description: 'AArch32 Instruction Set Attribute Register 0'
|
|
672
|
+
'S3_0_c0_c2_1':
|
|
673
|
+
- name: 'ID_ISAR1_EL1'
|
|
674
|
+
description: 'AArch32 Instruction Set Attribute Register 1'
|
|
675
|
+
'S3_0_c0_c2_2':
|
|
676
|
+
- name: 'ID_ISAR2_EL1'
|
|
677
|
+
description: 'AArch32 Instruction Set Attribute Register 2'
|
|
678
|
+
'S3_0_c0_c2_3':
|
|
679
|
+
- name: 'ID_ISAR3_EL1'
|
|
680
|
+
description: 'AArch32 Instruction Set Attribute Register 3'
|
|
681
|
+
'S3_0_c0_c2_4':
|
|
682
|
+
- name: 'ID_ISAR4_EL1'
|
|
683
|
+
description: 'AArch32 Instruction Set Attribute Register 4'
|
|
684
|
+
'S3_0_c0_c2_5':
|
|
685
|
+
- name: 'ID_ISAR5_EL1'
|
|
686
|
+
description: 'AArch32 Instruction Set Attribute Register 5'
|
|
687
|
+
'S3_0_c0_c2_6':
|
|
688
|
+
- name: 'ID_MMFR4_EL1'
|
|
689
|
+
description: 'AArch32 Memory Model Feature Register 4'
|
|
690
|
+
'S3_0_c0_c2_7':
|
|
691
|
+
- name: 'ID_ISAR6_EL1'
|
|
692
|
+
description: 'AArch32 Instruction Set Attribute Register 6'
|
|
693
|
+
'S3_0_c0_c3_0':
|
|
694
|
+
- name: 'MVFR0_EL1'
|
|
695
|
+
description: 'AArch32 Media and VFP Feature Register 0'
|
|
696
|
+
'S3_0_c0_c3_1':
|
|
697
|
+
- name: 'MVFR1_EL1'
|
|
698
|
+
description: 'AArch32 Media and VFP Feature Register 1'
|
|
699
|
+
'S3_0_c0_c3_2':
|
|
700
|
+
- name: 'MVFR2_EL1'
|
|
701
|
+
description: 'AArch32 Media and VFP Feature Register 2'
|
|
702
|
+
'S3_0_c0_c3_4':
|
|
703
|
+
- name: 'ID_PFR2_EL1'
|
|
704
|
+
description: 'AArch32 Processor Feature Register 2'
|
|
705
|
+
'S3_0_c0_c3_5':
|
|
706
|
+
- name: 'ID_DFR1_EL1'
|
|
707
|
+
description: 'Debug Feature Register 1'
|
|
708
|
+
'S3_0_c0_c3_6':
|
|
709
|
+
- name: 'ID_MMFR5_EL1'
|
|
710
|
+
description: 'AArch32 Memory Model Feature Register 5'
|
|
711
|
+
'S3_0_c0_c4_0':
|
|
712
|
+
- name: 'ID_AA64PFR0_EL1'
|
|
713
|
+
description: 'AArch64 Processor Feature Register 0'
|
|
714
|
+
'S3_0_c0_c4_1':
|
|
715
|
+
- name: 'ID_AA64PFR1_EL1'
|
|
716
|
+
description: 'AArch64 Processor Feature Register 1'
|
|
717
|
+
'S3_0_c0_c4_4':
|
|
718
|
+
- name: 'ID_AA64ZFR0_EL1'
|
|
719
|
+
description: 'SVE Feature ID register 0'
|
|
720
|
+
'S3_0_c0_c5_0':
|
|
721
|
+
- name: 'ID_AA64DFR0_EL1'
|
|
722
|
+
description: 'AArch64 Debug Feature Register 0'
|
|
723
|
+
'S3_0_c0_c5_1':
|
|
724
|
+
- name: 'ID_AA64DFR1_EL1'
|
|
725
|
+
description: 'AArch64 Debug Feature Register 1'
|
|
726
|
+
'S3_0_c0_c5_4':
|
|
727
|
+
- name: 'ID_AA64AFR0_EL1'
|
|
728
|
+
description: 'AArch64 Auxiliary Feature Register 0'
|
|
729
|
+
'S3_0_c0_c5_5':
|
|
730
|
+
- name: 'ID_AA64AFR1_EL1'
|
|
731
|
+
description: 'AArch64 Auxiliary Feature Register 1'
|
|
732
|
+
'S3_0_c0_c6_0':
|
|
733
|
+
- name: 'ID_AA64ISAR0_EL1'
|
|
734
|
+
description: 'AArch64 Instruction Set Attribute Register 0'
|
|
735
|
+
'S3_0_c0_c6_1':
|
|
736
|
+
- name: 'ID_AA64ISAR1_EL1'
|
|
737
|
+
description: 'AArch64 Instruction Set Attribute Register 1'
|
|
738
|
+
'S3_0_c0_c7_0':
|
|
739
|
+
- name: 'ID_AA64MMFR0_EL1'
|
|
740
|
+
description: 'AArch64 Memory Model Feature Register 0'
|
|
741
|
+
'S3_0_c0_c7_1':
|
|
742
|
+
- name: 'ID_AA64MMFR1_EL1'
|
|
743
|
+
description: 'AArch64 Memory Model Feature Register 1'
|
|
744
|
+
'S3_0_c0_c7_2':
|
|
745
|
+
- name: 'ID_AA64MMFR2_EL1'
|
|
746
|
+
description: 'AArch64 Memory Model Feature Register 2'
|
|
747
|
+
'S3_0_c1_c0_0':
|
|
748
|
+
- name: 'SCTLR_EL1'
|
|
749
|
+
description: 'System Control Register (EL1)'
|
|
750
|
+
'S3_0_c1_c0_1':
|
|
751
|
+
- name: 'ACTLR_EL1'
|
|
752
|
+
description: 'Auxiliary Control Register (EL1)'
|
|
753
|
+
'S3_0_c1_c0_2':
|
|
754
|
+
- name: 'CPACR_EL1'
|
|
755
|
+
description: 'Architectural Feature Access Control Register'
|
|
756
|
+
'S3_0_c1_c0_5':
|
|
757
|
+
- name: 'RGSR_EL1'
|
|
758
|
+
description: 'Random Allocation Tag Seed Register.'
|
|
759
|
+
'S3_0_c1_c0_6':
|
|
760
|
+
- name: 'GCR_EL1'
|
|
761
|
+
description: 'Tag Control Register.'
|
|
762
|
+
'S3_0_c1_c2_0':
|
|
763
|
+
- name: 'ZCR_EL1'
|
|
764
|
+
description: 'SVE Control Register for EL1'
|
|
765
|
+
'S3_0_c1_c2_1':
|
|
766
|
+
- name: 'TRFCR_EL1'
|
|
767
|
+
description: 'Trace Filter Control Register (EL1)'
|
|
768
|
+
'S3_0_c2_c0_0':
|
|
769
|
+
- name: 'TTBR0_EL1'
|
|
770
|
+
description: 'Translation Table Base Register 0 (EL1)'
|
|
771
|
+
'S3_0_c2_c0_1':
|
|
772
|
+
- name: 'TTBR1_EL1'
|
|
773
|
+
description: 'Translation Table Base Register 1 (EL1)'
|
|
774
|
+
'S3_0_c2_c0_2':
|
|
775
|
+
- name: 'TCR_EL1'
|
|
776
|
+
description: 'Translation Control Register (EL1)'
|
|
777
|
+
'S3_0_c2_c1_0':
|
|
778
|
+
- name: 'APIAKeyLo_EL1'
|
|
779
|
+
description: 'Pointer Authentication Key A for Instruction (bits[63:0]) '
|
|
780
|
+
'S3_0_c2_c1_1':
|
|
781
|
+
- name: 'APIAKeyHi_EL1'
|
|
782
|
+
description: 'Pointer Authentication Key A for Instruction (bits[127:64]) '
|
|
783
|
+
'S3_0_c2_c1_2':
|
|
784
|
+
- name: 'APIBKeyLo_EL1'
|
|
785
|
+
description: 'Pointer Authentication Key B for Instruction (bits[63:0]) '
|
|
786
|
+
'S3_0_c2_c1_3':
|
|
787
|
+
- name: 'APIBKeyHi_EL1'
|
|
788
|
+
description: 'Pointer Authentication Key B for Instruction (bits[127:64]) '
|
|
789
|
+
'S3_0_c2_c2_0':
|
|
790
|
+
- name: 'APDAKeyLo_EL1'
|
|
791
|
+
description: 'Pointer Authentication Key A for Data (bits[63:0]) '
|
|
792
|
+
'S3_0_c2_c2_1':
|
|
793
|
+
- name: 'APDAKeyHi_EL1'
|
|
794
|
+
description: 'Pointer Authentication Key A for Data (bits[127:64]) '
|
|
795
|
+
'S3_0_c2_c2_2':
|
|
796
|
+
- name: 'APDBKeyLo_EL1'
|
|
797
|
+
description: 'Pointer Authentication Key B for Data (bits[63:0]) '
|
|
798
|
+
'S3_0_c2_c2_3':
|
|
799
|
+
- name: 'APDBKeyHi_EL1'
|
|
800
|
+
description: 'Pointer Authentication Key B for Data (bits[127:64]) '
|
|
801
|
+
'S3_0_c2_c3_0':
|
|
802
|
+
- name: 'APGAKeyLo_EL1'
|
|
803
|
+
description: 'Pointer Authentication Key A for Code (bits[63:0]) '
|
|
804
|
+
'S3_0_c2_c3_1':
|
|
805
|
+
- name: 'APGAKeyHi_EL1'
|
|
806
|
+
description: 'Pointer Authentication Key A for Code (bits[127:64]) '
|
|
807
|
+
'S3_0_c4_c0_0':
|
|
808
|
+
- name: 'SPSR_EL1'
|
|
809
|
+
description: 'Saved Program Status Register (EL1)'
|
|
810
|
+
'S3_0_c4_c0_1':
|
|
811
|
+
- name: 'ELR_EL1'
|
|
812
|
+
description: 'Exception Link Register (EL1)'
|
|
813
|
+
'S3_0_c4_c1_0':
|
|
814
|
+
- name: 'SP_EL0'
|
|
815
|
+
description: 'Stack Pointer (EL0)'
|
|
816
|
+
'S3_0_c4_c2_0':
|
|
817
|
+
- name: 'SPSel'
|
|
818
|
+
description: 'Stack Pointer Select'
|
|
819
|
+
'S3_0_c4_c2_2':
|
|
820
|
+
- name: 'CurrentEL'
|
|
821
|
+
description: 'Current Exception Level'
|
|
822
|
+
'S3_0_c4_c2_3':
|
|
823
|
+
- name: 'PAN'
|
|
824
|
+
description: 'Privileged Access Never'
|
|
825
|
+
'S3_0_c4_c2_4':
|
|
826
|
+
- name: 'UAO'
|
|
827
|
+
description: 'User Access Override'
|
|
828
|
+
'S3_0_c4_c6_0':
|
|
829
|
+
- name: 'ICC_PMR_EL1'
|
|
830
|
+
description: 'Interrupt Controller Interrupt Priority Mask Register'
|
|
831
|
+
- name: 'ICV_PMR_EL1'
|
|
832
|
+
description: 'Interrupt Controller Virtual Interrupt Priority Mask Register'
|
|
833
|
+
'S3_0_c5_c1_0':
|
|
834
|
+
- name: 'AFSR0_EL1'
|
|
835
|
+
description: 'Auxiliary Fault Status Register 0 (EL1)'
|
|
836
|
+
'S3_0_c5_c1_1':
|
|
837
|
+
- name: 'AFSR1_EL1'
|
|
838
|
+
description: 'Auxiliary Fault Status Register 1 (EL1)'
|
|
839
|
+
'S3_0_c5_c2_0':
|
|
840
|
+
- name: 'ESR_EL1'
|
|
841
|
+
description: 'Exception Syndrome Register (EL1)'
|
|
842
|
+
'S3_0_c5_c3_0':
|
|
843
|
+
- name: 'ERRIDR_EL1'
|
|
844
|
+
description: 'Error Record ID Register'
|
|
845
|
+
'S3_0_c5_c3_1':
|
|
846
|
+
- name: 'ERRSELR_EL1'
|
|
847
|
+
description: 'Error Record Select Register'
|
|
848
|
+
'S3_0_c5_c4_0':
|
|
849
|
+
- name: 'ERXFR_EL1'
|
|
850
|
+
description: 'Selected Error Record Feature Register'
|
|
851
|
+
'S3_0_c5_c4_1':
|
|
852
|
+
- name: 'ERXCTLR_EL1'
|
|
853
|
+
description: 'Selected Error Record Control Register'
|
|
854
|
+
'S3_0_c5_c4_2':
|
|
855
|
+
- name: 'ERXSTATUS_EL1'
|
|
856
|
+
description: 'Selected Error Record Primary Status Register'
|
|
857
|
+
'S3_0_c5_c4_3':
|
|
858
|
+
- name: 'ERXADDR_EL1'
|
|
859
|
+
description: 'Selected Error Record Address Register'
|
|
860
|
+
'S3_0_c5_c4_4':
|
|
861
|
+
- name: 'ERXPFGF_EL1'
|
|
862
|
+
description: 'Selected Pseudo-fault Generation Feature register'
|
|
863
|
+
'S3_0_c5_c4_5':
|
|
864
|
+
- name: 'ERXPFGCTL_EL1'
|
|
865
|
+
description: 'Selected Pseudo-fault Generation Control register'
|
|
866
|
+
'S3_0_c5_c4_6':
|
|
867
|
+
- name: 'ERXPFGCDN_EL1'
|
|
868
|
+
description: 'Selected Pseudo-fault Generation Countdown register'
|
|
869
|
+
'S3_0_c5_c5_0':
|
|
870
|
+
- name: 'ERXMISC0_EL1'
|
|
871
|
+
description: 'Selected Error Record Miscellaneous Register 0'
|
|
872
|
+
'S3_0_c5_c5_1':
|
|
873
|
+
- name: 'ERXMISC1_EL1'
|
|
874
|
+
description: 'Selected Error Record Miscellaneous Register 1'
|
|
875
|
+
'S3_0_c5_c5_2':
|
|
876
|
+
- name: 'ERXMISC2_EL1'
|
|
877
|
+
description: 'Selected Error Record Miscellaneous Register 2'
|
|
878
|
+
'S3_0_c5_c5_3':
|
|
879
|
+
- name: 'ERXMISC3_EL1'
|
|
880
|
+
description: 'Selected Error Record Miscellaneous Register 3'
|
|
881
|
+
'S3_0_c5_c6_0':
|
|
882
|
+
- name: 'TFSR_EL1'
|
|
883
|
+
description: 'Tag Fault Status Register (EL1)'
|
|
884
|
+
'S3_0_c5_c6_1':
|
|
885
|
+
- name: 'TFSRE0_EL1'
|
|
886
|
+
description: 'Tag Fault Status Register (EL0).'
|
|
887
|
+
'S3_0_c6_c0_0':
|
|
888
|
+
- name: 'FAR_EL1'
|
|
889
|
+
description: 'Fault Address Register (EL1)'
|
|
890
|
+
'S3_0_c7_c4_0':
|
|
891
|
+
- name: 'PAR_EL1'
|
|
892
|
+
description: 'Physical Address Register'
|
|
893
|
+
'S3_0_c9_c9_0':
|
|
894
|
+
- name: 'PMSCR_EL1'
|
|
895
|
+
description: 'Statistical Profiling Control Register (EL1)'
|
|
896
|
+
'S3_0_c9_c9_2':
|
|
897
|
+
- name: 'PMSICR_EL1'
|
|
898
|
+
description: 'Sampling Interval Counter Register'
|
|
899
|
+
'S3_0_c9_c9_3':
|
|
900
|
+
- name: 'PMSIRR_EL1'
|
|
901
|
+
description: 'Sampling Interval Reload Register'
|
|
902
|
+
'S3_0_c9_c9_4':
|
|
903
|
+
- name: 'PMSFCR_EL1'
|
|
904
|
+
description: 'Sampling Filter Control Register'
|
|
905
|
+
'S3_0_c9_c9_5':
|
|
906
|
+
- name: 'PMSEVFR_EL1'
|
|
907
|
+
description: 'Sampling Event Filter Register'
|
|
908
|
+
'S3_0_c9_c9_6':
|
|
909
|
+
- name: 'PMSLATFR_EL1'
|
|
910
|
+
description: 'Sampling Latency Filter Register'
|
|
911
|
+
'S3_0_c9_c9_7':
|
|
912
|
+
- name: 'PMSIDR_EL1'
|
|
913
|
+
description: 'Sampling Profiling ID Register'
|
|
914
|
+
'S3_0_c9_c10_0':
|
|
915
|
+
- name: 'PMBLIMITR_EL1'
|
|
916
|
+
description: 'Profiling Buffer Limit Address Register'
|
|
917
|
+
'S3_0_c9_c10_1':
|
|
918
|
+
- name: 'PMBPTR_EL1'
|
|
919
|
+
description: 'Profiling Buffer Write Pointer Register'
|
|
920
|
+
'S3_0_c9_c10_3':
|
|
921
|
+
- name: 'PMBSR_EL1'
|
|
922
|
+
description: 'Profiling Buffer Status/syndrome Register'
|
|
923
|
+
'S3_0_c9_c10_7':
|
|
924
|
+
- name: 'PMBIDR_EL1'
|
|
925
|
+
description: 'Profiling Buffer ID Register'
|
|
926
|
+
'S3_0_c9_c14_1':
|
|
927
|
+
- name: 'PMINTENSET_EL1'
|
|
928
|
+
description: 'Performance Monitors Interrupt Enable Set register'
|
|
929
|
+
'S3_0_c9_c14_2':
|
|
930
|
+
- name: 'PMINTENCLR_EL1'
|
|
931
|
+
description: 'Performance Monitors Interrupt Enable Clear register'
|
|
932
|
+
'S3_0_c9_c14_6':
|
|
933
|
+
- name: 'PMMIR_EL1'
|
|
934
|
+
description: 'Performance Monitors Machine Identification Register'
|
|
935
|
+
'S3_0_c10_c2_0':
|
|
936
|
+
- name: 'MAIR_EL1'
|
|
937
|
+
description: 'Memory Attribute Indirection Register (EL1)'
|
|
938
|
+
'S3_0_c10_c3_0':
|
|
939
|
+
- name: 'AMAIR_EL1'
|
|
940
|
+
description: 'Auxiliary Memory Attribute Indirection Register (EL1)'
|
|
941
|
+
'S3_0_c10_c4_0':
|
|
942
|
+
- name: 'LORSA_EL1'
|
|
943
|
+
description: 'LORegion Start Address (EL1)'
|
|
944
|
+
'S3_0_c10_c4_1':
|
|
945
|
+
- name: 'LOREA_EL1'
|
|
946
|
+
description: 'LORegion End Address (EL1)'
|
|
947
|
+
'S3_0_c10_c4_2':
|
|
948
|
+
- name: 'LORN_EL1'
|
|
949
|
+
description: 'LORegion Number (EL1)'
|
|
950
|
+
'S3_0_c10_c4_3':
|
|
951
|
+
- name: 'LORC_EL1'
|
|
952
|
+
description: 'LORegion Control (EL1)'
|
|
953
|
+
'S3_0_c10_c4_4':
|
|
954
|
+
- name: 'MPAMIDR_EL1'
|
|
955
|
+
description: 'MPAM ID Register (EL1)'
|
|
956
|
+
'S3_0_c10_c4_7':
|
|
957
|
+
- name: 'LORID_EL1'
|
|
958
|
+
description: 'LORegionID (EL1)'
|
|
959
|
+
'S3_0_c10_c5_0':
|
|
960
|
+
- name: 'MPAM1_EL1'
|
|
961
|
+
description: 'MPAM1 Register (EL1)'
|
|
962
|
+
'S3_0_c10_c5_1':
|
|
963
|
+
- name: 'MPAM0_EL1'
|
|
964
|
+
description: 'MPAM0 Register (EL1)'
|
|
965
|
+
'S3_0_c12_c0_0':
|
|
966
|
+
- name: 'VBAR_EL1'
|
|
967
|
+
description: 'Vector Base Address Register (EL1)'
|
|
968
|
+
'S3_0_c12_c0_1':
|
|
969
|
+
- name: 'RVBAR_EL1'
|
|
970
|
+
description: 'Reset Vector Base Address Register (if EL2 and EL3 not implemented)'
|
|
971
|
+
'S3_0_c12_c0_2':
|
|
972
|
+
- name: 'RMR_EL1'
|
|
973
|
+
description: 'Reset Management Register (EL1)'
|
|
974
|
+
'S3_0_c12_c1_0':
|
|
975
|
+
- name: 'ISR_EL1'
|
|
976
|
+
description: 'Interrupt Status Register'
|
|
977
|
+
'S3_0_c12_c1_1':
|
|
978
|
+
- name: 'DISR_EL1'
|
|
979
|
+
description: 'Deferred Interrupt Status Register'
|
|
980
|
+
'S3_0_c12_c8_0':
|
|
981
|
+
- name: 'ICC_IAR0_EL1'
|
|
982
|
+
description: 'Interrupt Controller Interrupt Acknowledge Register 0'
|
|
983
|
+
- name: 'ICV_IAR0_EL1'
|
|
984
|
+
description: 'Interrupt Controller Virtual Interrupt Acknowledge Register 0'
|
|
985
|
+
'S3_0_c12_c8_1':
|
|
986
|
+
- name: 'ICC_EOIR0_EL1'
|
|
987
|
+
description: 'Interrupt Controller End Of Interrupt Register 0'
|
|
988
|
+
- name: 'ICV_EOIR0_EL1'
|
|
989
|
+
description: 'Interrupt Controller Virtual End Of Interrupt Register 0'
|
|
990
|
+
'S3_0_c12_c8_2':
|
|
991
|
+
- name: 'ICC_HPPIR0_EL1'
|
|
992
|
+
description: 'Interrupt Controller Highest Priority Pending Interrupt Register 0'
|
|
993
|
+
- name: 'ICV_HPPIR0_EL1'
|
|
994
|
+
description: 'Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0'
|
|
995
|
+
'S3_0_c12_c8_3':
|
|
996
|
+
- name: 'ICC_BPR0_EL1'
|
|
997
|
+
description: 'Interrupt Controller Binary Point Register 0'
|
|
998
|
+
- name: 'ICV_BPR0_EL1'
|
|
999
|
+
description: 'Interrupt Controller Virtual Binary Point Register 0'
|
|
1000
|
+
'S3_0_c12_c8_4':
|
|
1001
|
+
- name: 'ICC_AP0R0_EL1'
|
|
1002
|
+
description: 'Interrupt Controller Active Priorities Group 0 Register 0'
|
|
1003
|
+
- name: 'ICV_AP0R0_EL1'
|
|
1004
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 0 Register 0'
|
|
1005
|
+
'S3_0_c12_c8_5':
|
|
1006
|
+
- name: 'ICC_AP0R1_EL1'
|
|
1007
|
+
description: 'Interrupt Controller Active Priorities Group 0 Register 1'
|
|
1008
|
+
- name: 'ICV_AP0R1_EL1'
|
|
1009
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 0 Register 1'
|
|
1010
|
+
'S3_0_c12_c8_6':
|
|
1011
|
+
- name: 'ICC_AP0R2_EL1'
|
|
1012
|
+
description: 'Interrupt Controller Active Priorities Group 0 Register 2'
|
|
1013
|
+
- name: 'ICV_AP0R2_EL1'
|
|
1014
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 0 Register 2'
|
|
1015
|
+
'S3_0_c12_c8_7':
|
|
1016
|
+
- name: 'ICC_AP0R3_EL1'
|
|
1017
|
+
description: 'Interrupt Controller Active Priorities Group 0 Register 3'
|
|
1018
|
+
- name: 'ICV_AP0R3_EL1'
|
|
1019
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 0 Register 3'
|
|
1020
|
+
'S3_0_c12_c9_0':
|
|
1021
|
+
- name: 'ICC_AP1R0_EL1'
|
|
1022
|
+
description: 'Interrupt Controller Active Priorities Group 1 Register 0'
|
|
1023
|
+
- name: 'ICV_AP1R0_EL1'
|
|
1024
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 1 Register 0'
|
|
1025
|
+
'S3_0_c12_c9_1':
|
|
1026
|
+
- name: 'ICC_AP1R1_EL1'
|
|
1027
|
+
description: 'Interrupt Controller Active Priorities Group 1 Register 1'
|
|
1028
|
+
- name: 'ICV_AP1R1_EL1'
|
|
1029
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 1 Register 1'
|
|
1030
|
+
'S3_0_c12_c9_2':
|
|
1031
|
+
- name: 'ICC_AP1R2_EL1'
|
|
1032
|
+
description: 'Interrupt Controller Active Priorities Group 1 Register 2'
|
|
1033
|
+
- name: 'ICV_AP1R2_EL1'
|
|
1034
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 1 Register 2'
|
|
1035
|
+
'S3_0_c12_c9_3':
|
|
1036
|
+
- name: 'ICC_AP1R3_EL1'
|
|
1037
|
+
description: 'Interrupt Controller Active Priorities Group 1 Register 3'
|
|
1038
|
+
- name: 'ICV_AP1R3_EL1'
|
|
1039
|
+
description: 'Interrupt Controller Virtual Active Priorities Group 1 Register 3'
|
|
1040
|
+
'S3_0_c12_c11_1':
|
|
1041
|
+
- name: 'ICC_DIR_EL1'
|
|
1042
|
+
description: 'Interrupt Controller Deactivate Interrupt Register'
|
|
1043
|
+
- name: 'ICV_DIR_EL1'
|
|
1044
|
+
description: 'Interrupt Controller Deactivate Virtual Interrupt Register'
|
|
1045
|
+
'S3_0_c12_c11_3':
|
|
1046
|
+
- name: 'ICC_RPR_EL1'
|
|
1047
|
+
description: 'Interrupt Controller Running Priority Register'
|
|
1048
|
+
- name: 'ICV_RPR_EL1'
|
|
1049
|
+
description: 'Interrupt Controller Virtual Running Priority Register'
|
|
1050
|
+
'S3_0_c12_c11_5':
|
|
1051
|
+
- name: 'ICC_SGI1R_EL1'
|
|
1052
|
+
description: 'Interrupt Controller Software Generated Interrupt Group 1 Register'
|
|
1053
|
+
'S3_0_c12_c11_6':
|
|
1054
|
+
- name: 'ICC_ASGI1R_EL1'
|
|
1055
|
+
description: 'Interrupt Controller Alias Software Generated Interrupt Group 1 Register'
|
|
1056
|
+
'S3_0_c12_c11_7':
|
|
1057
|
+
- name: 'ICC_SGI0R_EL1'
|
|
1058
|
+
description: 'Interrupt Controller Software Generated Interrupt Group 0 Register'
|
|
1059
|
+
'S3_0_c12_c12_0':
|
|
1060
|
+
- name: 'ICC_IAR1_EL1'
|
|
1061
|
+
description: 'Interrupt Controller Interrupt Acknowledge Register 1'
|
|
1062
|
+
- name: 'ICV_IAR1_EL1'
|
|
1063
|
+
description: 'Interrupt Controller Virtual Interrupt Acknowledge Register 1'
|
|
1064
|
+
'S3_0_c12_c12_1':
|
|
1065
|
+
- name: 'ICC_EOIR1_EL1'
|
|
1066
|
+
description: 'Interrupt Controller End Of Interrupt Register 1'
|
|
1067
|
+
- name: 'ICV_EOIR1_EL1'
|
|
1068
|
+
description: 'Interrupt Controller Virtual End Of Interrupt Register 1'
|
|
1069
|
+
'S3_0_c12_c12_2':
|
|
1070
|
+
- name: 'ICC_HPPIR1_EL1'
|
|
1071
|
+
description: 'Interrupt Controller Highest Priority Pending Interrupt Register 1'
|
|
1072
|
+
- name: 'ICV_HPPIR1_EL1'
|
|
1073
|
+
description: 'Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1'
|
|
1074
|
+
'S3_0_c12_c12_3':
|
|
1075
|
+
- name: 'ICC_BPR1_EL1'
|
|
1076
|
+
description: 'Interrupt Controller Binary Point Register 1'
|
|
1077
|
+
- name: 'ICV_BPR1_EL1'
|
|
1078
|
+
description: 'Interrupt Controller Virtual Binary Point Register 1'
|
|
1079
|
+
'S3_0_c12_c12_4':
|
|
1080
|
+
- name: 'ICC_CTLR_EL1'
|
|
1081
|
+
description: 'Interrupt Controller Control Register (EL1)'
|
|
1082
|
+
- name: 'ICV_CTLR_EL1'
|
|
1083
|
+
description: 'Interrupt Controller Virtual Control Register'
|
|
1084
|
+
'S3_0_c12_c12_5':
|
|
1085
|
+
- name: 'ICC_SRE_EL1'
|
|
1086
|
+
description: 'Interrupt Controller System Register Enable register (EL1)'
|
|
1087
|
+
'S3_0_c12_c12_6':
|
|
1088
|
+
- name: 'ICC_IGRPEN0_EL1'
|
|
1089
|
+
description: 'Interrupt Controller Interrupt Group 0 Enable register'
|
|
1090
|
+
- name: 'ICV_IGRPEN0_EL1'
|
|
1091
|
+
description: 'Interrupt Controller Virtual Interrupt Group 0 Enable register'
|
|
1092
|
+
'S3_0_c12_c12_7':
|
|
1093
|
+
- name: 'ICC_IGRPEN1_EL1'
|
|
1094
|
+
description: 'Interrupt Controller Interrupt Group 1 Enable register'
|
|
1095
|
+
- name: 'ICV_IGRPEN1_EL1'
|
|
1096
|
+
description: 'Interrupt Controller Virtual Interrupt Group 1 Enable register'
|
|
1097
|
+
'S3_0_c13_c0_1':
|
|
1098
|
+
- name: 'CONTEXTIDR_EL1'
|
|
1099
|
+
description: 'Context ID Register (EL1)'
|
|
1100
|
+
'S3_0_c13_c0_4':
|
|
1101
|
+
- name: 'TPIDR_EL1'
|
|
1102
|
+
description: 'EL1 Software Thread ID Register'
|
|
1103
|
+
'S3_0_c13_c0_7':
|
|
1104
|
+
- name: 'SCXTNUM_EL1'
|
|
1105
|
+
description: 'EL1 Read/Write Software Context Number'
|
|
1106
|
+
'S3_0_c14_c1_0':
|
|
1107
|
+
- name: 'CNTKCTL_EL1'
|
|
1108
|
+
description: 'Counter-timer Kernel Control register'
|
|
1109
|
+
'S3_1_c0_c0_0':
|
|
1110
|
+
- name: 'CCSIDR_EL1'
|
|
1111
|
+
description: 'Current Cache Size ID Register'
|
|
1112
|
+
'S3_1_c0_c0_1':
|
|
1113
|
+
- name: 'CLIDR_EL1'
|
|
1114
|
+
description: 'Cache Level ID Register'
|
|
1115
|
+
'S3_1_c0_c0_2':
|
|
1116
|
+
- name: 'CCSIDR2_EL1'
|
|
1117
|
+
description: 'Current Cache Size ID Register 2'
|
|
1118
|
+
'S3_1_c0_c0_4':
|
|
1119
|
+
- name: 'GMID_EL1'
|
|
1120
|
+
description: ' Multiple tag transfer ID register'
|
|
1121
|
+
'S3_1_c0_c0_7':
|
|
1122
|
+
- name: 'AIDR_EL1'
|
|
1123
|
+
description: 'Auxiliary ID Register'
|
|
1124
|
+
'S3_2_c0_c0_0':
|
|
1125
|
+
- name: 'CSSELR_EL1'
|
|
1126
|
+
description: 'Cache Size Selection Register'
|
|
1127
|
+
'S3_3_c0_c0_1':
|
|
1128
|
+
- name: 'CTR_EL0'
|
|
1129
|
+
description: 'Cache Type Register'
|
|
1130
|
+
'S3_3_c0_c0_7':
|
|
1131
|
+
- name: 'DCZID_EL0'
|
|
1132
|
+
description: 'Data Cache Zero ID register'
|
|
1133
|
+
'S3_3_c2_c4_0':
|
|
1134
|
+
- name: 'RNDR'
|
|
1135
|
+
description: 'Random Number'
|
|
1136
|
+
'S3_3_c2_c4_1':
|
|
1137
|
+
- name: 'RNDRRS'
|
|
1138
|
+
description: 'Reseeded Random Number'
|
|
1139
|
+
'S3_3_c4_c2_0':
|
|
1140
|
+
- name: 'NZCV'
|
|
1141
|
+
description: 'Condition Flags'
|
|
1142
|
+
'S3_3_c4_c2_1':
|
|
1143
|
+
- name: 'DAIF'
|
|
1144
|
+
description: 'Interrupt Mask Bits'
|
|
1145
|
+
'S3_3_c4_c2_5':
|
|
1146
|
+
- name: 'DIT'
|
|
1147
|
+
description: 'Data Independent Timing'
|
|
1148
|
+
'S3_3_c4_c2_6':
|
|
1149
|
+
- name: 'SSBS'
|
|
1150
|
+
description: 'Speculative Store Bypass Safe'
|
|
1151
|
+
'S3_3_c4_c2_7':
|
|
1152
|
+
- name: 'TCO'
|
|
1153
|
+
description: 'Tag Check Override'
|
|
1154
|
+
'S3_3_c4_c4_0':
|
|
1155
|
+
- name: 'FPCR'
|
|
1156
|
+
description: 'Floating-point Control Register'
|
|
1157
|
+
'S3_3_c4_c4_1':
|
|
1158
|
+
- name: 'FPSR'
|
|
1159
|
+
description: 'Floating-point Status Register'
|
|
1160
|
+
'S3_3_c4_c5_0':
|
|
1161
|
+
- name: 'DSPSR_EL0'
|
|
1162
|
+
description: 'Debug Saved Program Status Register'
|
|
1163
|
+
'S3_3_c4_c5_1':
|
|
1164
|
+
- name: 'DLR_EL0'
|
|
1165
|
+
description: 'Debug Link Register'
|
|
1166
|
+
'S3_3_c9_c12_0':
|
|
1167
|
+
- name: 'PMCR_EL0'
|
|
1168
|
+
description: 'Performance Monitors Control Register'
|
|
1169
|
+
'S3_3_c9_c12_1':
|
|
1170
|
+
- name: 'PMCNTENSET_EL0'
|
|
1171
|
+
description: 'Performance Monitors Count Enable Set register'
|
|
1172
|
+
'S3_3_c9_c12_2':
|
|
1173
|
+
- name: 'PMCNTENCLR_EL0'
|
|
1174
|
+
description: 'Performance Monitors Count Enable Clear register'
|
|
1175
|
+
'S3_3_c9_c12_3':
|
|
1176
|
+
- name: 'PMOVSCLR_EL0'
|
|
1177
|
+
description: 'Performance Monitors Overflow Flag Status Clear Register'
|
|
1178
|
+
'S3_3_c9_c12_4':
|
|
1179
|
+
- name: 'PMSWINC_EL0'
|
|
1180
|
+
description: 'Performance Monitors Software Increment register'
|
|
1181
|
+
'S3_3_c9_c12_5':
|
|
1182
|
+
- name: 'PMSELR_EL0'
|
|
1183
|
+
description: 'Performance Monitors Event Counter Selection Register'
|
|
1184
|
+
'S3_3_c9_c12_6':
|
|
1185
|
+
- name: 'PMCEID0_EL0'
|
|
1186
|
+
description: 'Performance Monitors Common Event Identification register 0'
|
|
1187
|
+
'S3_3_c9_c12_7':
|
|
1188
|
+
- name: 'PMCEID1_EL0'
|
|
1189
|
+
description: 'Performance Monitors Common Event Identification register 1'
|
|
1190
|
+
'S3_3_c9_c13_0':
|
|
1191
|
+
- name: 'PMCCNTR_EL0'
|
|
1192
|
+
description: 'Performance Monitors Cycle Count Register'
|
|
1193
|
+
'S3_3_c9_c13_1':
|
|
1194
|
+
- name: 'PMXEVTYPER_EL0'
|
|
1195
|
+
description: 'Performance Monitors Selected Event Type Register'
|
|
1196
|
+
'S3_3_c9_c13_2':
|
|
1197
|
+
- name: 'PMXEVCNTR_EL0'
|
|
1198
|
+
description: 'Performance Monitors Selected Event Count Register'
|
|
1199
|
+
'S3_3_c9_c14_0':
|
|
1200
|
+
- name: 'PMUSERENR_EL0'
|
|
1201
|
+
description: 'Performance Monitors User Enable Register'
|
|
1202
|
+
'S3_3_c9_c14_3':
|
|
1203
|
+
- name: 'PMOVSSET_EL0'
|
|
1204
|
+
description: 'Performance Monitors Overflow Flag Status Set register'
|
|
1205
|
+
'S3_3_c13_c0_2':
|
|
1206
|
+
- name: 'TPIDR_EL0'
|
|
1207
|
+
description: 'EL0 Read/Write Software Thread ID Register'
|
|
1208
|
+
'S3_3_c13_c0_3':
|
|
1209
|
+
- name: 'TPIDRRO_EL0'
|
|
1210
|
+
description: 'EL0 Read-Only Software Thread ID Register'
|
|
1211
|
+
'S3_3_c13_c0_7':
|
|
1212
|
+
- name: 'SCXTNUM_EL0'
|
|
1213
|
+
description: 'EL0 Read/Write Software Context Number'
|
|
1214
|
+
'S3_3_c13_c2_0':
|
|
1215
|
+
- name: 'AMCR_EL0'
|
|
1216
|
+
description: 'Activity Monitors Control Register'
|
|
1217
|
+
'S3_3_c13_c2_1':
|
|
1218
|
+
- name: 'AMCFGR_EL0'
|
|
1219
|
+
description: 'Activity Monitors Configuration Register'
|
|
1220
|
+
'S3_3_c13_c2_2':
|
|
1221
|
+
- name: 'AMCGCR_EL0'
|
|
1222
|
+
description: 'Activity Monitors Counter Group Configuration Register'
|
|
1223
|
+
'S3_3_c13_c2_3':
|
|
1224
|
+
- name: 'AMUSERENR_EL0'
|
|
1225
|
+
description: 'Activity Monitors User Enable Register'
|
|
1226
|
+
'S3_3_c13_c2_4':
|
|
1227
|
+
- name: 'AMCNTENCLR0_EL0'
|
|
1228
|
+
description: 'Activity Monitors Count Enable Clear Register 0'
|
|
1229
|
+
'S3_3_c13_c2_5':
|
|
1230
|
+
- name: 'AMCNTENSET0_EL0'
|
|
1231
|
+
description: 'Activity Monitors Count Enable Set Register 0'
|
|
1232
|
+
'S3_3_c13_c2_6':
|
|
1233
|
+
- name: 'AMCG1IDR_EL0'
|
|
1234
|
+
description: 'Activity Monitors Counter Group 1 Identification Register'
|
|
1235
|
+
'S3_3_c13_c3_0':
|
|
1236
|
+
- name: 'AMCNTENCLR1_EL0'
|
|
1237
|
+
description: 'Activity Monitors Count Enable Clear Register 1'
|
|
1238
|
+
'S3_3_c13_c3_1':
|
|
1239
|
+
- name: 'AMCNTENSET1_EL0'
|
|
1240
|
+
description: 'Activity Monitors Count Enable Set Register 1'
|
|
1241
|
+
'S3_3_c13_c4_0':
|
|
1242
|
+
- name: 'AMEVCNTR00_EL0'
|
|
1243
|
+
description: 'Activity Monitors Event Counter Register 0 0'
|
|
1244
|
+
'S3_3_c13_c4_1':
|
|
1245
|
+
- name: 'AMEVCNTR01_EL0'
|
|
1246
|
+
description: 'Activity Monitors Event Counter Register 0 1'
|
|
1247
|
+
'S3_3_c13_c4_2':
|
|
1248
|
+
- name: 'AMEVCNTR02_EL0'
|
|
1249
|
+
description: 'Activity Monitors Event Counter Register 0 2'
|
|
1250
|
+
'S3_3_c13_c4_3':
|
|
1251
|
+
- name: 'AMEVCNTR03_EL0'
|
|
1252
|
+
description: 'Activity Monitors Event Counter Register 0 3'
|
|
1253
|
+
'S3_3_c13_c4_4':
|
|
1254
|
+
- name: 'AMEVCNTR04_EL0'
|
|
1255
|
+
description: 'Activity Monitors Event Counter Register 0 4'
|
|
1256
|
+
'S3_3_c13_c4_5':
|
|
1257
|
+
- name: 'AMEVCNTR05_EL0'
|
|
1258
|
+
description: 'Activity Monitors Event Counter Register 0 5'
|
|
1259
|
+
'S3_3_c13_c4_6':
|
|
1260
|
+
- name: 'AMEVCNTR06_EL0'
|
|
1261
|
+
description: 'Activity Monitors Event Counter Register 0 6'
|
|
1262
|
+
'S3_3_c13_c4_7':
|
|
1263
|
+
- name: 'AMEVCNTR07_EL0'
|
|
1264
|
+
description: 'Activity Monitors Event Counter Register 0 7'
|
|
1265
|
+
'S3_3_c13_c5_0':
|
|
1266
|
+
- name: 'AMEVCNTR08_EL0'
|
|
1267
|
+
description: 'Activity Monitors Event Counter Register 0 8'
|
|
1268
|
+
'S3_3_c13_c5_1':
|
|
1269
|
+
- name: 'AMEVCNTR09_EL0'
|
|
1270
|
+
description: 'Activity Monitors Event Counter Register 0 9'
|
|
1271
|
+
'S3_3_c13_c5_2':
|
|
1272
|
+
- name: 'AMEVCNTR010_EL0'
|
|
1273
|
+
description: 'Activity Monitors Event Counter Register 0 10'
|
|
1274
|
+
'S3_3_c13_c5_3':
|
|
1275
|
+
- name: 'AMEVCNTR011_EL0'
|
|
1276
|
+
description: 'Activity Monitors Event Counter Register 0 11'
|
|
1277
|
+
'S3_3_c13_c5_4':
|
|
1278
|
+
- name: 'AMEVCNTR012_EL0'
|
|
1279
|
+
description: 'Activity Monitors Event Counter Register 0 12'
|
|
1280
|
+
'S3_3_c13_c5_5':
|
|
1281
|
+
- name: 'AMEVCNTR013_EL0'
|
|
1282
|
+
description: 'Activity Monitors Event Counter Register 0 13'
|
|
1283
|
+
'S3_3_c13_c5_6':
|
|
1284
|
+
- name: 'AMEVCNTR014_EL0'
|
|
1285
|
+
description: 'Activity Monitors Event Counter Register 0 14'
|
|
1286
|
+
'S3_3_c13_c5_7':
|
|
1287
|
+
- name: 'AMEVCNTR015_EL0'
|
|
1288
|
+
description: 'Activity Monitors Event Counter Register 0 15'
|
|
1289
|
+
'S3_3_c13_c6_0':
|
|
1290
|
+
- name: 'AMEVTYPER00_EL0'
|
|
1291
|
+
description: 'Activity Monitors Event Type Register 0 0'
|
|
1292
|
+
'S3_3_c13_c6_1':
|
|
1293
|
+
- name: 'AMEVTYPER01_EL0'
|
|
1294
|
+
description: 'Activity Monitors Event Type Register 0 1'
|
|
1295
|
+
'S3_3_c13_c6_2':
|
|
1296
|
+
- name: 'AMEVTYPER02_EL0'
|
|
1297
|
+
description: 'Activity Monitors Event Type Register 0 2'
|
|
1298
|
+
'S3_3_c13_c6_3':
|
|
1299
|
+
- name: 'AMEVTYPER03_EL0'
|
|
1300
|
+
description: 'Activity Monitors Event Type Register 0 3'
|
|
1301
|
+
'S3_3_c13_c6_4':
|
|
1302
|
+
- name: 'AMEVTYPER04_EL0'
|
|
1303
|
+
description: 'Activity Monitors Event Type Register 0 4'
|
|
1304
|
+
'S3_3_c13_c6_5':
|
|
1305
|
+
- name: 'AMEVTYPER05_EL0'
|
|
1306
|
+
description: 'Activity Monitors Event Type Register 0 5'
|
|
1307
|
+
'S3_3_c13_c6_6':
|
|
1308
|
+
- name: 'AMEVTYPER06_EL0'
|
|
1309
|
+
description: 'Activity Monitors Event Type Register 0 6'
|
|
1310
|
+
'S3_3_c13_c6_7':
|
|
1311
|
+
- name: 'AMEVTYPER07_EL0'
|
|
1312
|
+
description: 'Activity Monitors Event Type Register 0 7'
|
|
1313
|
+
'S3_3_c13_c7_0':
|
|
1314
|
+
- name: 'AMEVTYPER08_EL0'
|
|
1315
|
+
description: 'Activity Monitors Event Type Register 0 8'
|
|
1316
|
+
'S3_3_c13_c7_1':
|
|
1317
|
+
- name: 'AMEVTYPER09_EL0'
|
|
1318
|
+
description: 'Activity Monitors Event Type Register 0 9'
|
|
1319
|
+
'S3_3_c13_c7_2':
|
|
1320
|
+
- name: 'AMEVTYPER010_EL0'
|
|
1321
|
+
description: 'Activity Monitors Event Type Register 0 10'
|
|
1322
|
+
'S3_3_c13_c7_3':
|
|
1323
|
+
- name: 'AMEVTYPER011_EL0'
|
|
1324
|
+
description: 'Activity Monitors Event Type Register 0 11'
|
|
1325
|
+
'S3_3_c13_c7_4':
|
|
1326
|
+
- name: 'AMEVTYPER012_EL0'
|
|
1327
|
+
description: 'Activity Monitors Event Type Register 0 12'
|
|
1328
|
+
'S3_3_c13_c7_5':
|
|
1329
|
+
- name: 'AMEVTYPER013_EL0'
|
|
1330
|
+
description: 'Activity Monitors Event Type Register 0 13'
|
|
1331
|
+
'S3_3_c13_c7_6':
|
|
1332
|
+
- name: 'AMEVTYPER014_EL0'
|
|
1333
|
+
description: 'Activity Monitors Event Type Register 0 14'
|
|
1334
|
+
'S3_3_c13_c7_7':
|
|
1335
|
+
- name: 'AMEVTYPER015_EL0'
|
|
1336
|
+
description: 'Activity Monitors Event Type Register 0 15'
|
|
1337
|
+
'S3_3_c13_c12_0':
|
|
1338
|
+
- name: 'AMEVCNTR10_EL0'
|
|
1339
|
+
description: 'Activity Monitors Event Counter Register 1 0'
|
|
1340
|
+
'S3_3_c13_c12_1':
|
|
1341
|
+
- name: 'AMEVCNTR11_EL0'
|
|
1342
|
+
description: 'Activity Monitors Event Counter Register 1 1'
|
|
1343
|
+
'S3_3_c13_c12_2':
|
|
1344
|
+
- name: 'AMEVCNTR12_EL0'
|
|
1345
|
+
description: 'Activity Monitors Event Counter Register 1 2'
|
|
1346
|
+
'S3_3_c13_c12_3':
|
|
1347
|
+
- name: 'AMEVCNTR13_EL0'
|
|
1348
|
+
description: 'Activity Monitors Event Counter Register 1 3'
|
|
1349
|
+
'S3_3_c13_c12_4':
|
|
1350
|
+
- name: 'AMEVCNTR14_EL0'
|
|
1351
|
+
description: 'Activity Monitors Event Counter Register 1 4'
|
|
1352
|
+
'S3_3_c13_c12_5':
|
|
1353
|
+
- name: 'AMEVCNTR15_EL0'
|
|
1354
|
+
description: 'Activity Monitors Event Counter Register 1 5'
|
|
1355
|
+
'S3_3_c13_c12_6':
|
|
1356
|
+
- name: 'AMEVCNTR16_EL0'
|
|
1357
|
+
description: 'Activity Monitors Event Counter Register 1 6'
|
|
1358
|
+
'S3_3_c13_c12_7':
|
|
1359
|
+
- name: 'AMEVCNTR17_EL0'
|
|
1360
|
+
description: 'Activity Monitors Event Counter Register 1 7'
|
|
1361
|
+
'S3_3_c13_c13_0':
|
|
1362
|
+
- name: 'AMEVCNTR18_EL0'
|
|
1363
|
+
description: 'Activity Monitors Event Counter Register 1 8'
|
|
1364
|
+
'S3_3_c13_c13_1':
|
|
1365
|
+
- name: 'AMEVCNTR19_EL0'
|
|
1366
|
+
description: 'Activity Monitors Event Counter Register 1 9'
|
|
1367
|
+
'S3_3_c13_c13_2':
|
|
1368
|
+
- name: 'AMEVCNTR110_EL0'
|
|
1369
|
+
description: 'Activity Monitors Event Counter Register 1 10'
|
|
1370
|
+
'S3_3_c13_c13_3':
|
|
1371
|
+
- name: 'AMEVCNTR111_EL0'
|
|
1372
|
+
description: 'Activity Monitors Event Counter Register 1 11'
|
|
1373
|
+
'S3_3_c13_c13_4':
|
|
1374
|
+
- name: 'AMEVCNTR112_EL0'
|
|
1375
|
+
description: 'Activity Monitors Event Counter Register 1 12'
|
|
1376
|
+
'S3_3_c13_c13_5':
|
|
1377
|
+
- name: 'AMEVCNTR113_EL0'
|
|
1378
|
+
description: 'Activity Monitors Event Counter Register 1 13'
|
|
1379
|
+
'S3_3_c13_c13_6':
|
|
1380
|
+
- name: 'AMEVCNTR114_EL0'
|
|
1381
|
+
description: 'Activity Monitors Event Counter Register 1 14'
|
|
1382
|
+
'S3_3_c13_c13_7':
|
|
1383
|
+
- name: 'AMEVCNTR115_EL0'
|
|
1384
|
+
description: 'Activity Monitors Event Counter Register 1 15'
|
|
1385
|
+
'S3_3_c13_c14_0':
|
|
1386
|
+
- name: 'AMEVTYPER10_EL0'
|
|
1387
|
+
description: 'Activity Monitors Event Type Register 1 0'
|
|
1388
|
+
'S3_3_c13_c14_1':
|
|
1389
|
+
- name: 'AMEVTYPER11_EL0'
|
|
1390
|
+
description: 'Activity Monitors Event Type Register 1 1'
|
|
1391
|
+
'S3_3_c13_c14_2':
|
|
1392
|
+
- name: 'AMEVTYPER12_EL0'
|
|
1393
|
+
description: 'Activity Monitors Event Type Register 1 2'
|
|
1394
|
+
'S3_3_c13_c14_3':
|
|
1395
|
+
- name: 'AMEVTYPER13_EL0'
|
|
1396
|
+
description: 'Activity Monitors Event Type Register 1 3'
|
|
1397
|
+
'S3_3_c13_c14_4':
|
|
1398
|
+
- name: 'AMEVTYPER14_EL0'
|
|
1399
|
+
description: 'Activity Monitors Event Type Register 1 4'
|
|
1400
|
+
'S3_3_c13_c14_5':
|
|
1401
|
+
- name: 'AMEVTYPER15_EL0'
|
|
1402
|
+
description: 'Activity Monitors Event Type Register 1 5'
|
|
1403
|
+
'S3_3_c13_c14_6':
|
|
1404
|
+
- name: 'AMEVTYPER16_EL0'
|
|
1405
|
+
description: 'Activity Monitors Event Type Register 1 6'
|
|
1406
|
+
'S3_3_c13_c14_7':
|
|
1407
|
+
- name: 'AMEVTYPER17_EL0'
|
|
1408
|
+
description: 'Activity Monitors Event Type Register 1 7'
|
|
1409
|
+
'S3_3_c13_c15_0':
|
|
1410
|
+
- name: 'AMEVTYPER18_EL0'
|
|
1411
|
+
description: 'Activity Monitors Event Type Register 1 8'
|
|
1412
|
+
'S3_3_c13_c15_1':
|
|
1413
|
+
- name: 'AMEVTYPER19_EL0'
|
|
1414
|
+
description: 'Activity Monitors Event Type Register 1 9'
|
|
1415
|
+
'S3_3_c13_c15_2':
|
|
1416
|
+
- name: 'AMEVTYPER110_EL0'
|
|
1417
|
+
description: 'Activity Monitors Event Type Register 1 10'
|
|
1418
|
+
'S3_3_c13_c15_3':
|
|
1419
|
+
- name: 'AMEVTYPER111_EL0'
|
|
1420
|
+
description: 'Activity Monitors Event Type Register 1 11'
|
|
1421
|
+
'S3_3_c13_c15_4':
|
|
1422
|
+
- name: 'AMEVTYPER112_EL0'
|
|
1423
|
+
description: 'Activity Monitors Event Type Register 1 12'
|
|
1424
|
+
'S3_3_c13_c15_5':
|
|
1425
|
+
- name: 'AMEVTYPER113_EL0'
|
|
1426
|
+
description: 'Activity Monitors Event Type Register 1 13'
|
|
1427
|
+
'S3_3_c13_c15_6':
|
|
1428
|
+
- name: 'AMEVTYPER114_EL0'
|
|
1429
|
+
description: 'Activity Monitors Event Type Register 1 14'
|
|
1430
|
+
'S3_3_c13_c15_7':
|
|
1431
|
+
- name: 'AMEVTYPER115_EL0'
|
|
1432
|
+
description: 'Activity Monitors Event Type Register 1 15'
|
|
1433
|
+
'S3_3_c14_c0_0':
|
|
1434
|
+
- name: 'CNTFRQ_EL0'
|
|
1435
|
+
description: 'Counter-timer Frequency register'
|
|
1436
|
+
'S3_3_c14_c0_1':
|
|
1437
|
+
- name: 'CNTPCT_EL0'
|
|
1438
|
+
description: 'Counter-timer Physical Count register'
|
|
1439
|
+
'S3_3_c14_c0_2':
|
|
1440
|
+
- name: 'CNTVCT_EL0'
|
|
1441
|
+
description: 'Counter-timer Virtual Count register'
|
|
1442
|
+
'S3_3_c14_c0_5':
|
|
1443
|
+
- name: 'CNTPCTSS_EL0'
|
|
1444
|
+
description: 'Counter-timer Self-Synchronized Physical Count register'
|
|
1445
|
+
'S3_3_c14_c0_6':
|
|
1446
|
+
- name: 'CNTVCTSS_EL0'
|
|
1447
|
+
description: 'Counter-timer Self-Synchronized Virtual Count register'
|
|
1448
|
+
'S3_3_c14_c2_0':
|
|
1449
|
+
- name: 'CNTP_TVAL_EL0'
|
|
1450
|
+
description: 'Counter-timer Physical Timer TimerValue register'
|
|
1451
|
+
'S3_3_c14_c2_1':
|
|
1452
|
+
- name: 'CNTP_CTL_EL0'
|
|
1453
|
+
description: 'Counter-timer Physical Timer Control register'
|
|
1454
|
+
'S3_3_c14_c2_2':
|
|
1455
|
+
- name: 'CNTP_CVAL_EL0'
|
|
1456
|
+
description: 'Counter-timer Physical Timer CompareValue register'
|
|
1457
|
+
'S3_3_c14_c3_0':
|
|
1458
|
+
- name: 'CNTV_TVAL_EL0'
|
|
1459
|
+
description: 'Counter-timer Virtual Timer TimerValue register'
|
|
1460
|
+
'S3_3_c14_c3_1':
|
|
1461
|
+
- name: 'CNTV_CTL_EL0'
|
|
1462
|
+
description: 'Counter-timer Virtual Timer Control register'
|
|
1463
|
+
'S3_3_c14_c3_2':
|
|
1464
|
+
- name: 'CNTV_CVAL_EL0'
|
|
1465
|
+
description: 'Counter-timer Virtual Timer CompareValue register'
|
|
1466
|
+
'S3_3_c14_c8_0':
|
|
1467
|
+
- name: 'PMEVCNTR0_EL0'
|
|
1468
|
+
description: 'Performance Monitors Event Count Register 0'
|
|
1469
|
+
'S3_3_c14_c8_1':
|
|
1470
|
+
- name: 'PMEVCNTR1_EL0'
|
|
1471
|
+
description: 'Performance Monitors Event Count Register 1'
|
|
1472
|
+
'S3_3_c14_c8_2':
|
|
1473
|
+
- name: 'PMEVCNTR2_EL0'
|
|
1474
|
+
description: 'Performance Monitors Event Count Register 2'
|
|
1475
|
+
'S3_3_c14_c8_3':
|
|
1476
|
+
- name: 'PMEVCNTR3_EL0'
|
|
1477
|
+
description: 'Performance Monitors Event Count Register 3'
|
|
1478
|
+
'S3_3_c14_c8_4':
|
|
1479
|
+
- name: 'PMEVCNTR4_EL0'
|
|
1480
|
+
description: 'Performance Monitors Event Count Register 4'
|
|
1481
|
+
'S3_3_c14_c8_5':
|
|
1482
|
+
- name: 'PMEVCNTR5_EL0'
|
|
1483
|
+
description: 'Performance Monitors Event Count Register 5'
|
|
1484
|
+
'S3_3_c14_c8_6':
|
|
1485
|
+
- name: 'PMEVCNTR6_EL0'
|
|
1486
|
+
description: 'Performance Monitors Event Count Register 6'
|
|
1487
|
+
'S3_3_c14_c8_7':
|
|
1488
|
+
- name: 'PMEVCNTR7_EL0'
|
|
1489
|
+
description: 'Performance Monitors Event Count Register 7'
|
|
1490
|
+
'S3_3_c14_c9_0':
|
|
1491
|
+
- name: 'PMEVCNTR8_EL0'
|
|
1492
|
+
description: 'Performance Monitors Event Count Register 8'
|
|
1493
|
+
'S3_3_c14_c9_1':
|
|
1494
|
+
- name: 'PMEVCNTR9_EL0'
|
|
1495
|
+
description: 'Performance Monitors Event Count Register 9'
|
|
1496
|
+
'S3_3_c14_c9_2':
|
|
1497
|
+
- name: 'PMEVCNTR10_EL0'
|
|
1498
|
+
description: 'Performance Monitors Event Count Register 10'
|
|
1499
|
+
'S3_3_c14_c9_3':
|
|
1500
|
+
- name: 'PMEVCNTR11_EL0'
|
|
1501
|
+
description: 'Performance Monitors Event Count Register 11'
|
|
1502
|
+
'S3_3_c14_c9_4':
|
|
1503
|
+
- name: 'PMEVCNTR12_EL0'
|
|
1504
|
+
description: 'Performance Monitors Event Count Register 12'
|
|
1505
|
+
'S3_3_c14_c9_5':
|
|
1506
|
+
- name: 'PMEVCNTR13_EL0'
|
|
1507
|
+
description: 'Performance Monitors Event Count Register 13'
|
|
1508
|
+
'S3_3_c14_c9_6':
|
|
1509
|
+
- name: 'PMEVCNTR14_EL0'
|
|
1510
|
+
description: 'Performance Monitors Event Count Register 14'
|
|
1511
|
+
'S3_3_c14_c9_7':
|
|
1512
|
+
- name: 'PMEVCNTR15_EL0'
|
|
1513
|
+
description: 'Performance Monitors Event Count Register 15'
|
|
1514
|
+
'S3_3_c14_c10_0':
|
|
1515
|
+
- name: 'PMEVCNTR16_EL0'
|
|
1516
|
+
description: 'Performance Monitors Event Count Register 16'
|
|
1517
|
+
'S3_3_c14_c10_1':
|
|
1518
|
+
- name: 'PMEVCNTR17_EL0'
|
|
1519
|
+
description: 'Performance Monitors Event Count Register 17'
|
|
1520
|
+
'S3_3_c14_c10_2':
|
|
1521
|
+
- name: 'PMEVCNTR18_EL0'
|
|
1522
|
+
description: 'Performance Monitors Event Count Register 18'
|
|
1523
|
+
'S3_3_c14_c10_3':
|
|
1524
|
+
- name: 'PMEVCNTR19_EL0'
|
|
1525
|
+
description: 'Performance Monitors Event Count Register 19'
|
|
1526
|
+
'S3_3_c14_c10_4':
|
|
1527
|
+
- name: 'PMEVCNTR20_EL0'
|
|
1528
|
+
description: 'Performance Monitors Event Count Register 20'
|
|
1529
|
+
'S3_3_c14_c10_5':
|
|
1530
|
+
- name: 'PMEVCNTR21_EL0'
|
|
1531
|
+
description: 'Performance Monitors Event Count Register 21'
|
|
1532
|
+
'S3_3_c14_c10_6':
|
|
1533
|
+
- name: 'PMEVCNTR22_EL0'
|
|
1534
|
+
description: 'Performance Monitors Event Count Register 22'
|
|
1535
|
+
'S3_3_c14_c10_7':
|
|
1536
|
+
- name: 'PMEVCNTR23_EL0'
|
|
1537
|
+
description: 'Performance Monitors Event Count Register 23'
|
|
1538
|
+
'S3_3_c14_c11_0':
|
|
1539
|
+
- name: 'PMEVCNTR24_EL0'
|
|
1540
|
+
description: 'Performance Monitors Event Count Register 24'
|
|
1541
|
+
'S3_3_c14_c11_1':
|
|
1542
|
+
- name: 'PMEVCNTR25_EL0'
|
|
1543
|
+
description: 'Performance Monitors Event Count Register 25'
|
|
1544
|
+
'S3_3_c14_c11_2':
|
|
1545
|
+
- name: 'PMEVCNTR26_EL0'
|
|
1546
|
+
description: 'Performance Monitors Event Count Register 26'
|
|
1547
|
+
'S3_3_c14_c11_3':
|
|
1548
|
+
- name: 'PMEVCNTR27_EL0'
|
|
1549
|
+
description: 'Performance Monitors Event Count Register 27'
|
|
1550
|
+
'S3_3_c14_c11_4':
|
|
1551
|
+
- name: 'PMEVCNTR28_EL0'
|
|
1552
|
+
description: 'Performance Monitors Event Count Register 28'
|
|
1553
|
+
'S3_3_c14_c11_5':
|
|
1554
|
+
- name: 'PMEVCNTR29_EL0'
|
|
1555
|
+
description: 'Performance Monitors Event Count Register 29'
|
|
1556
|
+
'S3_3_c14_c11_6':
|
|
1557
|
+
- name: 'PMEVCNTR30_EL0'
|
|
1558
|
+
description: 'Performance Monitors Event Count Register 30'
|
|
1559
|
+
'S3_3_c14_c11_7':
|
|
1560
|
+
- name: 'PMEVCNTR31_EL0'
|
|
1561
|
+
description: 'Performance Monitors Event Count Register 31'
|
|
1562
|
+
'S3_3_c14_c12_0':
|
|
1563
|
+
- name: 'PMEVTYPER0_EL0'
|
|
1564
|
+
description: 'Performance Monitors Event Type Register 0'
|
|
1565
|
+
'S3_3_c14_c12_1':
|
|
1566
|
+
- name: 'PMEVTYPER1_EL0'
|
|
1567
|
+
description: 'Performance Monitors Event Type Register 1'
|
|
1568
|
+
'S3_3_c14_c12_2':
|
|
1569
|
+
- name: 'PMEVTYPER2_EL0'
|
|
1570
|
+
description: 'Performance Monitors Event Type Register 2'
|
|
1571
|
+
'S3_3_c14_c12_3':
|
|
1572
|
+
- name: 'PMEVTYPER3_EL0'
|
|
1573
|
+
description: 'Performance Monitors Event Type Register 3'
|
|
1574
|
+
'S3_3_c14_c12_4':
|
|
1575
|
+
- name: 'PMEVTYPER4_EL0'
|
|
1576
|
+
description: 'Performance Monitors Event Type Register 4'
|
|
1577
|
+
'S3_3_c14_c12_5':
|
|
1578
|
+
- name: 'PMEVTYPER5_EL0'
|
|
1579
|
+
description: 'Performance Monitors Event Type Register 5'
|
|
1580
|
+
'S3_3_c14_c12_6':
|
|
1581
|
+
- name: 'PMEVTYPER6_EL0'
|
|
1582
|
+
description: 'Performance Monitors Event Type Register 6'
|
|
1583
|
+
'S3_3_c14_c12_7':
|
|
1584
|
+
- name: 'PMEVTYPER7_EL0'
|
|
1585
|
+
description: 'Performance Monitors Event Type Register 7'
|
|
1586
|
+
'S3_3_c14_c13_0':
|
|
1587
|
+
- name: 'PMEVTYPER8_EL0'
|
|
1588
|
+
description: 'Performance Monitors Event Type Register 8'
|
|
1589
|
+
'S3_3_c14_c13_1':
|
|
1590
|
+
- name: 'PMEVTYPER9_EL0'
|
|
1591
|
+
description: 'Performance Monitors Event Type Register 9'
|
|
1592
|
+
'S3_3_c14_c13_2':
|
|
1593
|
+
- name: 'PMEVTYPER10_EL0'
|
|
1594
|
+
description: 'Performance Monitors Event Type Register 10'
|
|
1595
|
+
'S3_3_c14_c13_3':
|
|
1596
|
+
- name: 'PMEVTYPER11_EL0'
|
|
1597
|
+
description: 'Performance Monitors Event Type Register 11'
|
|
1598
|
+
'S3_3_c14_c13_4':
|
|
1599
|
+
- name: 'PMEVTYPER12_EL0'
|
|
1600
|
+
description: 'Performance Monitors Event Type Register 12'
|
|
1601
|
+
'S3_3_c14_c13_5':
|
|
1602
|
+
- name: 'PMEVTYPER13_EL0'
|
|
1603
|
+
description: 'Performance Monitors Event Type Register 13'
|
|
1604
|
+
'S3_3_c14_c13_6':
|
|
1605
|
+
- name: 'PMEVTYPER14_EL0'
|
|
1606
|
+
description: 'Performance Monitors Event Type Register 14'
|
|
1607
|
+
'S3_3_c14_c13_7':
|
|
1608
|
+
- name: 'PMEVTYPER15_EL0'
|
|
1609
|
+
description: 'Performance Monitors Event Type Register 15'
|
|
1610
|
+
'S3_3_c14_c14_0':
|
|
1611
|
+
- name: 'PMEVTYPER16_EL0'
|
|
1612
|
+
description: 'Performance Monitors Event Type Register 16'
|
|
1613
|
+
'S3_3_c14_c14_1':
|
|
1614
|
+
- name: 'PMEVTYPER17_EL0'
|
|
1615
|
+
description: 'Performance Monitors Event Type Register 17'
|
|
1616
|
+
'S3_3_c14_c14_2':
|
|
1617
|
+
- name: 'PMEVTYPER18_EL0'
|
|
1618
|
+
description: 'Performance Monitors Event Type Register 18'
|
|
1619
|
+
'S3_3_c14_c14_3':
|
|
1620
|
+
- name: 'PMEVTYPER19_EL0'
|
|
1621
|
+
description: 'Performance Monitors Event Type Register 19'
|
|
1622
|
+
'S3_3_c14_c14_4':
|
|
1623
|
+
- name: 'PMEVTYPER20_EL0'
|
|
1624
|
+
description: 'Performance Monitors Event Type Register 20'
|
|
1625
|
+
'S3_3_c14_c14_5':
|
|
1626
|
+
- name: 'PMEVTYPER21_EL0'
|
|
1627
|
+
description: 'Performance Monitors Event Type Register 21'
|
|
1628
|
+
'S3_3_c14_c14_6':
|
|
1629
|
+
- name: 'PMEVTYPER22_EL0'
|
|
1630
|
+
description: 'Performance Monitors Event Type Register 22'
|
|
1631
|
+
'S3_3_c14_c14_7':
|
|
1632
|
+
- name: 'PMEVTYPER23_EL0'
|
|
1633
|
+
description: 'Performance Monitors Event Type Register 23'
|
|
1634
|
+
'S3_3_c14_c15_0':
|
|
1635
|
+
- name: 'PMEVTYPER24_EL0'
|
|
1636
|
+
description: 'Performance Monitors Event Type Register 24'
|
|
1637
|
+
'S3_3_c14_c15_1':
|
|
1638
|
+
- name: 'PMEVTYPER25_EL0'
|
|
1639
|
+
description: 'Performance Monitors Event Type Register 25'
|
|
1640
|
+
'S3_3_c14_c15_2':
|
|
1641
|
+
- name: 'PMEVTYPER26_EL0'
|
|
1642
|
+
description: 'Performance Monitors Event Type Register 26'
|
|
1643
|
+
'S3_3_c14_c15_3':
|
|
1644
|
+
- name: 'PMEVTYPER27_EL0'
|
|
1645
|
+
description: 'Performance Monitors Event Type Register 27'
|
|
1646
|
+
'S3_3_c14_c15_4':
|
|
1647
|
+
- name: 'PMEVTYPER28_EL0'
|
|
1648
|
+
description: 'Performance Monitors Event Type Register 28'
|
|
1649
|
+
'S3_3_c14_c15_5':
|
|
1650
|
+
- name: 'PMEVTYPER29_EL0'
|
|
1651
|
+
description: 'Performance Monitors Event Type Register 29'
|
|
1652
|
+
'S3_3_c14_c15_6':
|
|
1653
|
+
- name: 'PMEVTYPER30_EL0'
|
|
1654
|
+
description: 'Performance Monitors Event Type Register 30'
|
|
1655
|
+
'S3_3_c14_c15_7':
|
|
1656
|
+
- name: 'PMCCFILTR_EL0'
|
|
1657
|
+
description: 'Performance Monitors Cycle Count Filter Register'
|
|
1658
|
+
- name: 'PMEVTYPER31_EL0'
|
|
1659
|
+
description: 'Performance Monitors Event Type Register 31'
|
|
1660
|
+
'S3_4_c0_c0_0':
|
|
1661
|
+
- name: 'VPIDR_EL2'
|
|
1662
|
+
description: 'Virtualization Processor ID Register'
|
|
1663
|
+
'S3_4_c0_c0_5':
|
|
1664
|
+
- name: 'VMPIDR_EL2'
|
|
1665
|
+
description: 'Virtualization Multiprocessor ID Register'
|
|
1666
|
+
'S3_4_c1_c0_0':
|
|
1667
|
+
- name: 'SCTLR_EL2'
|
|
1668
|
+
description: 'System Control Register (EL2)'
|
|
1669
|
+
'S3_4_c1_c0_1':
|
|
1670
|
+
- name: 'ACTLR_EL2'
|
|
1671
|
+
description: 'Auxiliary Control Register (EL2)'
|
|
1672
|
+
'S3_4_c1_c1_0':
|
|
1673
|
+
- name: 'HCR_EL2'
|
|
1674
|
+
description: 'Hypervisor Configuration Register'
|
|
1675
|
+
'S3_4_c1_c1_1':
|
|
1676
|
+
- name: 'MDCR_EL2'
|
|
1677
|
+
description: 'Monitor Debug Configuration Register (EL2)'
|
|
1678
|
+
'S3_4_c1_c1_2':
|
|
1679
|
+
- name: 'CPTR_EL2'
|
|
1680
|
+
description: 'Architectural Feature Trap Register (EL2)'
|
|
1681
|
+
'S3_4_c1_c1_3':
|
|
1682
|
+
- name: 'HSTR_EL2'
|
|
1683
|
+
description: 'Hypervisor System Trap Register'
|
|
1684
|
+
'S3_4_c1_c1_4':
|
|
1685
|
+
- name: 'HFGRTR_EL2'
|
|
1686
|
+
description: 'Hypervisor Fine-Grained Read Trap Register'
|
|
1687
|
+
'S3_4_c1_c1_5':
|
|
1688
|
+
- name: 'HFGWTR_EL2'
|
|
1689
|
+
description: 'Hypervisor Fine-Grained Write Trap Register'
|
|
1690
|
+
'S3_4_c1_c1_6':
|
|
1691
|
+
- name: 'HFGITR_EL2'
|
|
1692
|
+
description: 'Hypervisor Fine-Grained Instruction Trap Register'
|
|
1693
|
+
'S3_4_c1_c1_7':
|
|
1694
|
+
- name: 'HACR_EL2'
|
|
1695
|
+
description: 'Hypervisor Auxiliary Control Register'
|
|
1696
|
+
'S3_4_c1_c2_0':
|
|
1697
|
+
- name: 'ZCR_EL2'
|
|
1698
|
+
description: 'SVE Control Register for EL2'
|
|
1699
|
+
'S3_4_c1_c2_1':
|
|
1700
|
+
- name: 'TRFCR_EL2'
|
|
1701
|
+
description: 'Trace Filter Control Register (EL2)'
|
|
1702
|
+
'S3_4_c1_c3_1':
|
|
1703
|
+
- name: 'SDER32_EL2'
|
|
1704
|
+
description: 'AArch32 Secure Debug Enable Register'
|
|
1705
|
+
'S3_4_c2_c0_0':
|
|
1706
|
+
- name: 'TTBR0_EL2'
|
|
1707
|
+
description: 'Translation Table Base Register 0 (EL2)'
|
|
1708
|
+
'S3_4_c2_c0_1':
|
|
1709
|
+
- name: 'TTBR1_EL2'
|
|
1710
|
+
description: 'Translation Table Base Register 1 (EL2)'
|
|
1711
|
+
'S3_4_c2_c0_2':
|
|
1712
|
+
- name: 'TCR_EL2'
|
|
1713
|
+
description: 'Translation Control Register (EL2)'
|
|
1714
|
+
'S3_4_c2_c1_0':
|
|
1715
|
+
- name: 'VTTBR_EL2'
|
|
1716
|
+
description: 'Virtualization Translation Table Base Register'
|
|
1717
|
+
'S3_4_c2_c1_2':
|
|
1718
|
+
- name: 'VTCR_EL2'
|
|
1719
|
+
description: 'Virtualization Translation Control Register'
|
|
1720
|
+
'S3_4_c2_c2_0':
|
|
1721
|
+
- name: 'VNCR_EL2'
|
|
1722
|
+
description: 'Virtual Nested Control Register'
|
|
1723
|
+
'S3_4_c2_c6_0':
|
|
1724
|
+
- name: 'VSTTBR_EL2'
|
|
1725
|
+
description: 'Virtualization Secure Translation Table Base Register'
|
|
1726
|
+
'S3_4_c2_c6_2':
|
|
1727
|
+
- name: 'VSTCR_EL2'
|
|
1728
|
+
description: 'Virtualization Secure Translation Control Register'
|
|
1729
|
+
'S3_4_c3_c0_0':
|
|
1730
|
+
- name: 'DACR32_EL2'
|
|
1731
|
+
description: 'Domain Access Control Register'
|
|
1732
|
+
'S3_4_c3_c1_4':
|
|
1733
|
+
- name: 'HDFGRTR_EL2'
|
|
1734
|
+
description: 'Hypervisor Debug Fine-Grained Read Trap Register'
|
|
1735
|
+
'S3_4_c3_c1_5':
|
|
1736
|
+
- name: 'HDFGWTR_EL2'
|
|
1737
|
+
description: 'Hypervisor Debug Fine-Grained Write Trap Register'
|
|
1738
|
+
'S3_4_c3_c1_6':
|
|
1739
|
+
- name: 'HAFGRTR_EL2'
|
|
1740
|
+
description: 'Hypervisor Activity Monitors Fine-Grained Read Trap Register'
|
|
1741
|
+
'S3_4_c4_c0_0':
|
|
1742
|
+
- name: 'SPSR_EL2'
|
|
1743
|
+
description: 'Saved Program Status Register (EL2)'
|
|
1744
|
+
'S3_4_c4_c0_1':
|
|
1745
|
+
- name: 'ELR_EL2'
|
|
1746
|
+
description: 'Exception Link Register (EL2)'
|
|
1747
|
+
'S3_4_c4_c1_0':
|
|
1748
|
+
- name: 'SP_EL1'
|
|
1749
|
+
description: 'Stack Pointer (EL1)'
|
|
1750
|
+
'S3_4_c4_c3_0':
|
|
1751
|
+
- name: 'SPSR_irq'
|
|
1752
|
+
description: 'Saved Program Status Register (IRQ mode)'
|
|
1753
|
+
'S3_4_c4_c3_1':
|
|
1754
|
+
- name: 'SPSR_abt'
|
|
1755
|
+
description: 'Saved Program Status Register (Abort mode)'
|
|
1756
|
+
'S3_4_c4_c3_2':
|
|
1757
|
+
- name: 'SPSR_und'
|
|
1758
|
+
description: 'Saved Program Status Register (Undefined mode)'
|
|
1759
|
+
'S3_4_c4_c3_3':
|
|
1760
|
+
- name: 'SPSR_fiq'
|
|
1761
|
+
description: 'Saved Program Status Register (FIQ mode)'
|
|
1762
|
+
'S3_4_c5_c0_1':
|
|
1763
|
+
- name: 'IFSR32_EL2'
|
|
1764
|
+
description: 'Instruction Fault Status Register (EL2)'
|
|
1765
|
+
'S3_4_c5_c1_0':
|
|
1766
|
+
- name: 'AFSR0_EL2'
|
|
1767
|
+
description: 'Auxiliary Fault Status Register 0 (EL2)'
|
|
1768
|
+
'S3_4_c5_c1_1':
|
|
1769
|
+
- name: 'AFSR1_EL2'
|
|
1770
|
+
description: 'Auxiliary Fault Status Register 1 (EL2)'
|
|
1771
|
+
'S3_4_c5_c2_0':
|
|
1772
|
+
- name: 'ESR_EL2'
|
|
1773
|
+
description: 'Exception Syndrome Register (EL2)'
|
|
1774
|
+
'S3_4_c5_c2_3':
|
|
1775
|
+
- name: 'VSESR_EL2'
|
|
1776
|
+
description: 'Virtual SError Exception Syndrome Register'
|
|
1777
|
+
'S3_4_c5_c3_0':
|
|
1778
|
+
- name: 'FPEXC32_EL2'
|
|
1779
|
+
description: 'Floating-Point Exception Control register'
|
|
1780
|
+
'S3_4_c5_c6_0':
|
|
1781
|
+
- name: 'TFSR_EL2'
|
|
1782
|
+
description: 'Tag Fault Status Register (EL2)'
|
|
1783
|
+
'S3_4_c6_c0_0':
|
|
1784
|
+
- name: 'FAR_EL2'
|
|
1785
|
+
description: 'Fault Address Register (EL2)'
|
|
1786
|
+
'S3_4_c6_c0_4':
|
|
1787
|
+
- name: 'HPFAR_EL2'
|
|
1788
|
+
description: 'Hypervisor IPA Fault Address Register'
|
|
1789
|
+
'S3_4_c9_c9_0':
|
|
1790
|
+
- name: 'PMSCR_EL2'
|
|
1791
|
+
description: 'Statistical Profiling Control Register (EL2)'
|
|
1792
|
+
'S3_4_c10_c2_0':
|
|
1793
|
+
- name: 'MAIR_EL2'
|
|
1794
|
+
description: 'Memory Attribute Indirection Register (EL2)'
|
|
1795
|
+
'S3_4_c10_c3_0':
|
|
1796
|
+
- name: 'AMAIR_EL2'
|
|
1797
|
+
description: 'Auxiliary Memory Attribute Indirection Register (EL2)'
|
|
1798
|
+
'S3_4_c10_c4_0':
|
|
1799
|
+
- name: 'MPAMHCR_EL2'
|
|
1800
|
+
description: 'MPAM Hypervisor Control Register (EL2)'
|
|
1801
|
+
'S3_4_c10_c4_1':
|
|
1802
|
+
- name: 'MPAMVPMV_EL2'
|
|
1803
|
+
description: 'MPAM Virtual Partition Mapping Valid Register'
|
|
1804
|
+
'S3_4_c10_c5_0':
|
|
1805
|
+
- name: 'MPAM2_EL2'
|
|
1806
|
+
description: 'MPAM2 Register (EL2)'
|
|
1807
|
+
'S3_4_c10_c6_0':
|
|
1808
|
+
- name: 'MPAMVPM0_EL2'
|
|
1809
|
+
description: 'MPAM Virtual PARTID Mapping Register 0'
|
|
1810
|
+
'S3_4_c10_c6_1':
|
|
1811
|
+
- name: 'MPAMVPM1_EL2'
|
|
1812
|
+
description: 'MPAM Virtual PARTID Mapping Register 1'
|
|
1813
|
+
'S3_4_c10_c6_2':
|
|
1814
|
+
- name: 'MPAMVPM2_EL2'
|
|
1815
|
+
description: 'MPAM Virtual PARTID Mapping Register 2'
|
|
1816
|
+
'S3_4_c10_c6_3':
|
|
1817
|
+
- name: 'MPAMVPM3_EL2'
|
|
1818
|
+
description: 'MPAM Virtual PARTID Mapping Register 3'
|
|
1819
|
+
'S3_4_c10_c6_4':
|
|
1820
|
+
- name: 'MPAMVPM4_EL2'
|
|
1821
|
+
description: 'MPAM Virtual PARTID Mapping Register 4'
|
|
1822
|
+
'S3_4_c10_c6_5':
|
|
1823
|
+
- name: 'MPAMVPM5_EL2'
|
|
1824
|
+
description: 'MPAM Virtual PARTID Mapping Register 5'
|
|
1825
|
+
'S3_4_c10_c6_6':
|
|
1826
|
+
- name: 'MPAMVPM6_EL2'
|
|
1827
|
+
description: 'MPAM Virtual PARTID Mapping Register 6'
|
|
1828
|
+
'S3_4_c10_c6_7':
|
|
1829
|
+
- name: 'MPAMVPM7_EL2'
|
|
1830
|
+
description: 'MPAM Virtual PARTID Mapping Register 7'
|
|
1831
|
+
'S3_4_c12_c0_0':
|
|
1832
|
+
- name: 'VBAR_EL2'
|
|
1833
|
+
description: 'Vector Base Address Register (EL2)'
|
|
1834
|
+
'S3_4_c12_c0_1':
|
|
1835
|
+
- name: 'RVBAR_EL2'
|
|
1836
|
+
description: 'Reset Vector Base Address Register (if EL3 not implemented)'
|
|
1837
|
+
'S3_4_c12_c0_2':
|
|
1838
|
+
- name: 'RMR_EL2'
|
|
1839
|
+
description: 'Reset Management Register (EL2)'
|
|
1840
|
+
'S3_4_c12_c1_1':
|
|
1841
|
+
- name: 'VDISR_EL2'
|
|
1842
|
+
description: 'Virtual Deferred Interrupt Status Register'
|
|
1843
|
+
'S3_4_c12_c8_0':
|
|
1844
|
+
- name: 'ICH_AP0R0_EL2'
|
|
1845
|
+
description: 'Interrupt Controller Hyp Active Priorities Group 0 Register 0'
|
|
1846
|
+
'S3_4_c12_c8_1':
|
|
1847
|
+
- name: 'ICH_AP0R1_EL2'
|
|
1848
|
+
description: 'Interrupt Controller Hyp Active Priorities Group 0 Register 1'
|
|
1849
|
+
'S3_4_c12_c8_2':
|
|
1850
|
+
- name: 'ICH_AP0R2_EL2'
|
|
1851
|
+
description: 'Interrupt Controller Hyp Active Priorities Group 0 Register 2'
|
|
1852
|
+
'S3_4_c12_c8_3':
|
|
1853
|
+
- name: 'ICH_AP0R3_EL2'
|
|
1854
|
+
description: 'Interrupt Controller Hyp Active Priorities Group 0 Register 3'
|
|
1855
|
+
'S3_4_c12_c9_0':
|
|
1856
|
+
- name: 'ICH_AP1R0_EL2'
|
|
1857
|
+
description: 'Interrupt Controller Hyp Active Priorities Group 1 Register 0'
|
|
1858
|
+
'S3_4_c12_c9_1':
|
|
1859
|
+
- name: 'ICH_AP1R1_EL2'
|
|
1860
|
+
description: 'Interrupt Controller Hyp Active Priorities Group 1 Register 1'
|
|
1861
|
+
'S3_4_c12_c9_2':
|
|
1862
|
+
- name: 'ICH_AP1R2_EL2'
|
|
1863
|
+
description: 'Interrupt Controller Hyp Active Priorities Group 1 Register 2'
|
|
1864
|
+
'S3_4_c12_c9_3':
|
|
1865
|
+
- name: 'ICH_AP1R3_EL2'
|
|
1866
|
+
description: 'Interrupt Controller Hyp Active Priorities Group 1 Register 3'
|
|
1867
|
+
'S3_4_c12_c9_5':
|
|
1868
|
+
- name: 'ICC_SRE_EL2'
|
|
1869
|
+
description: 'Interrupt Controller System Register Enable register (EL2)'
|
|
1870
|
+
'S3_4_c12_c11_0':
|
|
1871
|
+
- name: 'ICH_HCR_EL2'
|
|
1872
|
+
description: 'Interrupt Controller Hyp Control Register'
|
|
1873
|
+
'S3_4_c12_c11_1':
|
|
1874
|
+
- name: 'ICH_VTR_EL2'
|
|
1875
|
+
description: 'Interrupt Controller VGIC Type Register'
|
|
1876
|
+
'S3_4_c12_c11_2':
|
|
1877
|
+
- name: 'ICH_MISR_EL2'
|
|
1878
|
+
description: 'Interrupt Controller Maintenance Interrupt State Register'
|
|
1879
|
+
'S3_4_c12_c11_3':
|
|
1880
|
+
- name: 'ICH_EISR_EL2'
|
|
1881
|
+
description: 'Interrupt Controller End of Interrupt Status Register'
|
|
1882
|
+
'S3_4_c12_c11_5':
|
|
1883
|
+
- name: 'ICH_ELRSR_EL2'
|
|
1884
|
+
description: 'Interrupt Controller Empty List Register Status Register'
|
|
1885
|
+
'S3_4_c12_c11_7':
|
|
1886
|
+
- name: 'ICH_VMCR_EL2'
|
|
1887
|
+
description: 'Interrupt Controller Virtual Machine Control Register'
|
|
1888
|
+
'S3_4_c12_c12_0':
|
|
1889
|
+
- name: 'ICH_LR0_EL2'
|
|
1890
|
+
description: 'Interrupt Controller List Register 0'
|
|
1891
|
+
'S3_4_c12_c12_1':
|
|
1892
|
+
- name: 'ICH_LR1_EL2'
|
|
1893
|
+
description: 'Interrupt Controller List Register 1'
|
|
1894
|
+
'S3_4_c12_c12_2':
|
|
1895
|
+
- name: 'ICH_LR2_EL2'
|
|
1896
|
+
description: 'Interrupt Controller List Register 2'
|
|
1897
|
+
'S3_4_c12_c12_3':
|
|
1898
|
+
- name: 'ICH_LR3_EL2'
|
|
1899
|
+
description: 'Interrupt Controller List Register 3'
|
|
1900
|
+
'S3_4_c12_c12_4':
|
|
1901
|
+
- name: 'ICH_LR4_EL2'
|
|
1902
|
+
description: 'Interrupt Controller List Register 4'
|
|
1903
|
+
'S3_4_c12_c12_5':
|
|
1904
|
+
- name: 'ICH_LR5_EL2'
|
|
1905
|
+
description: 'Interrupt Controller List Register 5'
|
|
1906
|
+
'S3_4_c12_c12_6':
|
|
1907
|
+
- name: 'ICH_LR6_EL2'
|
|
1908
|
+
description: 'Interrupt Controller List Register 6'
|
|
1909
|
+
'S3_4_c12_c12_7':
|
|
1910
|
+
- name: 'ICH_LR7_EL2'
|
|
1911
|
+
description: 'Interrupt Controller List Register 7'
|
|
1912
|
+
'S3_4_c12_c13_0':
|
|
1913
|
+
- name: 'ICH_LR8_EL2'
|
|
1914
|
+
description: 'Interrupt Controller List Register 8'
|
|
1915
|
+
'S3_4_c12_c13_1':
|
|
1916
|
+
- name: 'ICH_LR9_EL2'
|
|
1917
|
+
description: 'Interrupt Controller List Register 9'
|
|
1918
|
+
'S3_4_c12_c13_2':
|
|
1919
|
+
- name: 'ICH_LR10_EL2'
|
|
1920
|
+
description: 'Interrupt Controller List Register 10'
|
|
1921
|
+
'S3_4_c12_c13_3':
|
|
1922
|
+
- name: 'ICH_LR11_EL2'
|
|
1923
|
+
description: 'Interrupt Controller List Register 11'
|
|
1924
|
+
'S3_4_c12_c13_4':
|
|
1925
|
+
- name: 'ICH_LR12_EL2'
|
|
1926
|
+
description: 'Interrupt Controller List Register 12'
|
|
1927
|
+
'S3_4_c12_c13_5':
|
|
1928
|
+
- name: 'ICH_LR13_EL2'
|
|
1929
|
+
description: 'Interrupt Controller List Register 13'
|
|
1930
|
+
'S3_4_c12_c13_6':
|
|
1931
|
+
- name: 'ICH_LR14_EL2'
|
|
1932
|
+
description: 'Interrupt Controller List Register 14'
|
|
1933
|
+
'S3_4_c12_c13_7':
|
|
1934
|
+
- name: 'ICH_LR15_EL2'
|
|
1935
|
+
description: 'Interrupt Controller List Register 15'
|
|
1936
|
+
'S3_4_c13_c0_1':
|
|
1937
|
+
- name: 'CONTEXTIDR_EL2'
|
|
1938
|
+
description: 'Context ID Register (EL2)'
|
|
1939
|
+
'S3_4_c13_c0_2':
|
|
1940
|
+
- name: 'TPIDR_EL2'
|
|
1941
|
+
description: 'EL2 Software Thread ID Register'
|
|
1942
|
+
'S3_4_c13_c0_7':
|
|
1943
|
+
- name: 'SCXTNUM_EL2'
|
|
1944
|
+
description: 'EL2 Read/Write Software Context Number'
|
|
1945
|
+
'S3_4_c13_c8_0':
|
|
1946
|
+
- name: 'AMEVCNTVOFF00_EL2'
|
|
1947
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 0'
|
|
1948
|
+
'S3_4_c13_c8_1':
|
|
1949
|
+
- name: 'AMEVCNTVOFF01_EL2'
|
|
1950
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 1'
|
|
1951
|
+
'S3_4_c13_c8_2':
|
|
1952
|
+
- name: 'AMEVCNTVOFF02_EL2'
|
|
1953
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 2'
|
|
1954
|
+
'S3_4_c13_c8_3':
|
|
1955
|
+
- name: 'AMEVCNTVOFF03_EL2'
|
|
1956
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 3'
|
|
1957
|
+
'S3_4_c13_c8_4':
|
|
1958
|
+
- name: 'AMEVCNTVOFF04_EL2'
|
|
1959
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 4'
|
|
1960
|
+
'S3_4_c13_c8_5':
|
|
1961
|
+
- name: 'AMEVCNTVOFF05_EL2'
|
|
1962
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 5'
|
|
1963
|
+
'S3_4_c13_c8_6':
|
|
1964
|
+
- name: 'AMEVCNTVOFF06_EL2'
|
|
1965
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 6'
|
|
1966
|
+
'S3_4_c13_c8_7':
|
|
1967
|
+
- name: 'AMEVCNTVOFF07_EL2'
|
|
1968
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 7'
|
|
1969
|
+
'S3_4_c13_c9_0':
|
|
1970
|
+
- name: 'AMEVCNTVOFF08_EL2'
|
|
1971
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 8'
|
|
1972
|
+
'S3_4_c13_c9_1':
|
|
1973
|
+
- name: 'AMEVCNTVOFF09_EL2'
|
|
1974
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 9'
|
|
1975
|
+
'S3_4_c13_c9_2':
|
|
1976
|
+
- name: 'AMEVCNTVOFF010_EL2'
|
|
1977
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 10'
|
|
1978
|
+
'S3_4_c13_c9_3':
|
|
1979
|
+
- name: 'AMEVCNTVOFF011_EL2'
|
|
1980
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 11'
|
|
1981
|
+
'S3_4_c13_c9_4':
|
|
1982
|
+
- name: 'AMEVCNTVOFF012_EL2'
|
|
1983
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 12'
|
|
1984
|
+
'S3_4_c13_c9_5':
|
|
1985
|
+
- name: 'AMEVCNTVOFF013_EL2'
|
|
1986
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 13'
|
|
1987
|
+
'S3_4_c13_c9_6':
|
|
1988
|
+
- name: 'AMEVCNTVOFF014_EL2'
|
|
1989
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 14'
|
|
1990
|
+
'S3_4_c13_c9_7':
|
|
1991
|
+
- name: 'AMEVCNTVOFF015_EL2'
|
|
1992
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 0 15'
|
|
1993
|
+
'S3_4_c13_c10_0':
|
|
1994
|
+
- name: 'AMEVCNTVOFF10_EL2'
|
|
1995
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 0'
|
|
1996
|
+
'S3_4_c13_c10_1':
|
|
1997
|
+
- name: 'AMEVCNTVOFF11_EL2'
|
|
1998
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 1'
|
|
1999
|
+
'S3_4_c13_c10_2':
|
|
2000
|
+
- name: 'AMEVCNTVOFF12_EL2'
|
|
2001
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 2'
|
|
2002
|
+
'S3_4_c13_c10_3':
|
|
2003
|
+
- name: 'AMEVCNTVOFF13_EL2'
|
|
2004
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 3'
|
|
2005
|
+
'S3_4_c13_c10_4':
|
|
2006
|
+
- name: 'AMEVCNTVOFF14_EL2'
|
|
2007
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 4'
|
|
2008
|
+
'S3_4_c13_c10_5':
|
|
2009
|
+
- name: 'AMEVCNTVOFF15_EL2'
|
|
2010
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 5'
|
|
2011
|
+
'S3_4_c13_c10_6':
|
|
2012
|
+
- name: 'AMEVCNTVOFF16_EL2'
|
|
2013
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 6'
|
|
2014
|
+
'S3_4_c13_c10_7':
|
|
2015
|
+
- name: 'AMEVCNTVOFF17_EL2'
|
|
2016
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 7'
|
|
2017
|
+
'S3_4_c13_c11_0':
|
|
2018
|
+
- name: 'AMEVCNTVOFF18_EL2'
|
|
2019
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 8'
|
|
2020
|
+
'S3_4_c13_c11_1':
|
|
2021
|
+
- name: 'AMEVCNTVOFF19_EL2'
|
|
2022
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 9'
|
|
2023
|
+
'S3_4_c13_c11_2':
|
|
2024
|
+
- name: 'AMEVCNTVOFF110_EL2'
|
|
2025
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 10'
|
|
2026
|
+
'S3_4_c13_c11_3':
|
|
2027
|
+
- name: 'AMEVCNTVOFF111_EL2'
|
|
2028
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 11'
|
|
2029
|
+
'S3_4_c13_c11_4':
|
|
2030
|
+
- name: 'AMEVCNTVOFF112_EL2'
|
|
2031
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 12'
|
|
2032
|
+
'S3_4_c13_c11_5':
|
|
2033
|
+
- name: 'AMEVCNTVOFF113_EL2'
|
|
2034
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 13'
|
|
2035
|
+
'S3_4_c13_c11_6':
|
|
2036
|
+
- name: 'AMEVCNTVOFF114_EL2'
|
|
2037
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 14'
|
|
2038
|
+
'S3_4_c13_c11_7':
|
|
2039
|
+
- name: 'AMEVCNTVOFF115_EL2'
|
|
2040
|
+
description: 'Activity Monitors Event Counter Virtual Offset Register 1 15'
|
|
2041
|
+
'S3_4_c14_c0_3':
|
|
2042
|
+
- name: 'CNTVOFF_EL2'
|
|
2043
|
+
description: 'Counter-timer Virtual Offset register'
|
|
2044
|
+
'S3_4_c14_c0_6':
|
|
2045
|
+
- name: 'CNTPOFF_EL2'
|
|
2046
|
+
description: 'Counter-timer Physical Offset register'
|
|
2047
|
+
'S3_4_c14_c1_0':
|
|
2048
|
+
- name: 'CNTHCTL_EL2'
|
|
2049
|
+
description: 'Counter-timer Hypervisor Control register'
|
|
2050
|
+
'S3_4_c14_c2_0':
|
|
2051
|
+
- name: 'CNTHP_TVAL_EL2'
|
|
2052
|
+
description: 'Counter-timer Physical Timer TimerValue register (EL2)'
|
|
2053
|
+
'S3_4_c14_c2_1':
|
|
2054
|
+
- name: 'CNTHP_CTL_EL2'
|
|
2055
|
+
description: 'Counter-timer Hypervisor Physical Timer Control register'
|
|
2056
|
+
'S3_4_c14_c2_2':
|
|
2057
|
+
- name: 'CNTHP_CVAL_EL2'
|
|
2058
|
+
description: 'Counter-timer Physical Timer CompareValue register (EL2)'
|
|
2059
|
+
'S3_4_c14_c3_0':
|
|
2060
|
+
- name: 'CNTHV_TVAL_EL2'
|
|
2061
|
+
description: 'Counter-timer Virtual Timer TimerValue Register (EL2)'
|
|
2062
|
+
'S3_4_c14_c3_1':
|
|
2063
|
+
- name: 'CNTHV_CTL_EL2'
|
|
2064
|
+
description: 'Counter-timer Virtual Timer Control register (EL2)'
|
|
2065
|
+
'S3_4_c14_c3_2':
|
|
2066
|
+
- name: 'CNTHV_CVAL_EL2'
|
|
2067
|
+
description: 'Counter-timer Virtual Timer CompareValue register (EL2)'
|
|
2068
|
+
'S3_4_c14_c4_0':
|
|
2069
|
+
- name: 'CNTHVS_TVAL_EL2'
|
|
2070
|
+
description: 'Counter-timer Secure Virtual Timer TimerValue register (EL2)'
|
|
2071
|
+
'S3_4_c14_c4_1':
|
|
2072
|
+
- name: 'CNTHVS_CTL_EL2'
|
|
2073
|
+
description: 'Counter-timer Secure Virtual Timer Control register (EL2)'
|
|
2074
|
+
'S3_4_c14_c4_2':
|
|
2075
|
+
- name: 'CNTHVS_CVAL_EL2'
|
|
2076
|
+
description: 'Counter-timer Secure Virtual Timer CompareValue register (EL2)'
|
|
2077
|
+
'S3_4_c14_c5_0':
|
|
2078
|
+
- name: 'CNTHPS_TVAL_EL2'
|
|
2079
|
+
description: 'Counter-timer Secure Physical Timer TimerValue register (EL2)'
|
|
2080
|
+
'S3_4_c14_c5_1':
|
|
2081
|
+
- name: 'CNTHPS_CTL_EL2'
|
|
2082
|
+
description: 'Counter-timer Secure Physical Timer Control register (EL2)'
|
|
2083
|
+
'S3_4_c14_c5_2':
|
|
2084
|
+
- name: 'CNTHPS_CVAL_EL2'
|
|
2085
|
+
description: 'Counter-timer Secure Physical Timer CompareValue register (EL2)'
|
|
2086
|
+
'S3_6_c1_c0_0':
|
|
2087
|
+
- name: 'SCTLR_EL3'
|
|
2088
|
+
description: 'System Control Register (EL3)'
|
|
2089
|
+
'S3_6_c1_c0_1':
|
|
2090
|
+
- name: 'ACTLR_EL3'
|
|
2091
|
+
description: 'Auxiliary Control Register (EL3)'
|
|
2092
|
+
'S3_6_c1_c1_0':
|
|
2093
|
+
- name: 'SCR_EL3'
|
|
2094
|
+
description: 'Secure Configuration Register'
|
|
2095
|
+
'S3_6_c1_c1_1':
|
|
2096
|
+
- name: 'SDER32_EL3'
|
|
2097
|
+
description: 'AArch32 Secure Debug Enable Register'
|
|
2098
|
+
'S3_6_c1_c1_2':
|
|
2099
|
+
- name: 'CPTR_EL3'
|
|
2100
|
+
description: 'Architectural Feature Trap Register (EL3)'
|
|
2101
|
+
'S3_6_c1_c2_0':
|
|
2102
|
+
- name: 'ZCR_EL3'
|
|
2103
|
+
description: 'SVE Control Register for EL3'
|
|
2104
|
+
'S3_6_c1_c3_1':
|
|
2105
|
+
- name: 'MDCR_EL3'
|
|
2106
|
+
description: 'Monitor Debug Configuration Register (EL3)'
|
|
2107
|
+
'S3_6_c2_c0_0':
|
|
2108
|
+
- name: 'TTBR0_EL3'
|
|
2109
|
+
description: 'Translation Table Base Register 0 (EL3)'
|
|
2110
|
+
'S3_6_c2_c0_2':
|
|
2111
|
+
- name: 'TCR_EL3'
|
|
2112
|
+
description: 'Translation Control Register (EL3)'
|
|
2113
|
+
'S3_6_c4_c0_0':
|
|
2114
|
+
- name: 'SPSR_EL3'
|
|
2115
|
+
description: 'Saved Program Status Register (EL3)'
|
|
2116
|
+
'S3_6_c4_c0_1':
|
|
2117
|
+
- name: 'ELR_EL3'
|
|
2118
|
+
description: 'Exception Link Register (EL3)'
|
|
2119
|
+
'S3_6_c4_c1_0':
|
|
2120
|
+
- name: 'SP_EL2'
|
|
2121
|
+
description: 'Stack Pointer (EL2)'
|
|
2122
|
+
'S3_6_c5_c1_0':
|
|
2123
|
+
- name: 'AFSR0_EL3'
|
|
2124
|
+
description: 'Auxiliary Fault Status Register 0 (EL3)'
|
|
2125
|
+
'S3_6_c5_c1_1':
|
|
2126
|
+
- name: 'AFSR1_EL3'
|
|
2127
|
+
description: 'Auxiliary Fault Status Register 1 (EL3)'
|
|
2128
|
+
'S3_6_c5_c2_0':
|
|
2129
|
+
- name: 'ESR_EL3'
|
|
2130
|
+
description: 'Exception Syndrome Register (EL3)'
|
|
2131
|
+
'S3_6_c5_c6_0':
|
|
2132
|
+
- name: 'TFSR_EL3'
|
|
2133
|
+
description: 'Tag Fault Status Register (EL3)'
|
|
2134
|
+
'S3_6_c6_c0_0':
|
|
2135
|
+
- name: 'FAR_EL3'
|
|
2136
|
+
description: 'Fault Address Register (EL3)'
|
|
2137
|
+
'S3_6_c10_c2_0':
|
|
2138
|
+
- name: 'MAIR_EL3'
|
|
2139
|
+
description: 'Memory Attribute Indirection Register (EL3)'
|
|
2140
|
+
'S3_6_c10_c3_0':
|
|
2141
|
+
- name: 'AMAIR_EL3'
|
|
2142
|
+
description: 'Auxiliary Memory Attribute Indirection Register (EL3)'
|
|
2143
|
+
'S3_6_c10_c5_0':
|
|
2144
|
+
- name: 'MPAM3_EL3'
|
|
2145
|
+
description: 'MPAM3 Register (EL3)'
|
|
2146
|
+
'S3_6_c12_c0_0':
|
|
2147
|
+
- name: 'VBAR_EL3'
|
|
2148
|
+
description: 'Vector Base Address Register (EL3)'
|
|
2149
|
+
'S3_6_c12_c0_1':
|
|
2150
|
+
- name: 'RVBAR_EL3'
|
|
2151
|
+
description: 'Reset Vector Base Address Register (if EL3 implemented)'
|
|
2152
|
+
'S3_6_c12_c0_2':
|
|
2153
|
+
- name: 'RMR_EL3'
|
|
2154
|
+
description: 'Reset Management Register (EL3)'
|
|
2155
|
+
'S3_6_c12_c12_4':
|
|
2156
|
+
- name: 'ICC_CTLR_EL3'
|
|
2157
|
+
description: 'Interrupt Controller Control Register (EL3)'
|
|
2158
|
+
'S3_6_c12_c12_5':
|
|
2159
|
+
- name: 'ICC_SRE_EL3'
|
|
2160
|
+
description: 'Interrupt Controller System Register Enable register (EL3)'
|
|
2161
|
+
'S3_6_c12_c12_7':
|
|
2162
|
+
- name: 'ICC_IGRPEN1_EL3'
|
|
2163
|
+
description: 'Interrupt Controller Interrupt Group 1 Enable register (EL3)'
|
|
2164
|
+
'S3_6_c13_c0_2':
|
|
2165
|
+
- name: 'TPIDR_EL3'
|
|
2166
|
+
description: 'EL3 Software Thread ID Register'
|
|
2167
|
+
'S3_6_c13_c0_7':
|
|
2168
|
+
- name: 'SCXTNUM_EL3'
|
|
2169
|
+
description: 'EL3 Read/Write Software Context Number'
|
|
2170
|
+
'S3_7_c14_c2_0':
|
|
2171
|
+
- name: 'CNTPS_TVAL_EL1'
|
|
2172
|
+
description: 'Counter-timer Physical Secure Timer TimerValue register'
|
|
2173
|
+
'S3_7_c14_c2_1':
|
|
2174
|
+
- name: 'CNTPS_CTL_EL1'
|
|
2175
|
+
description: 'Counter-timer Physical Secure Timer Control register'
|
|
2176
|
+
'S3_7_c14_c2_2':
|
|
2177
|
+
- name: 'CNTPS_CVAL_EL1'
|
|
2178
|
+
description: 'Counter-timer Physical Secure Timer CompareValue register'
|
|
2179
|
+
apple_system_registers:
|
|
2180
|
+
- 'S3_0_c15_c0_0':
|
|
2181
|
+
name: 'HID0'
|
|
2182
|
+
description: ''
|
|
2183
|
+
- 'S3_0_c15_c0_1':
|
|
2184
|
+
name: 'EHID0'
|
|
2185
|
+
description: ''
|
|
2186
|
+
- 'S3_0_c15_c1_0':
|
|
2187
|
+
name: 'HID1'
|
|
2188
|
+
description: ''
|
|
2189
|
+
- 'S3_0_c15_c1_1':
|
|
2190
|
+
name: 'EHID1'
|
|
2191
|
+
description: ''
|
|
2192
|
+
- 'S3_0_c15_c2_0':
|
|
2193
|
+
name: 'HID2'
|
|
2194
|
+
description: ''
|
|
2195
|
+
- 'S3_0_c15_c2_1':
|
|
2196
|
+
name: 'EHID2'
|
|
2197
|
+
description: ''
|
|
2198
|
+
- 'S3_0_c15_c3_0':
|
|
2199
|
+
name: 'HID3'
|
|
2200
|
+
description: ''
|
|
2201
|
+
- 'S3_0_c15_c3_1':
|
|
2202
|
+
name: 'EHID3'
|
|
2203
|
+
description: ''
|
|
2204
|
+
- 'S3_0_c15_c4_0':
|
|
2205
|
+
name: 'HID4'
|
|
2206
|
+
description: ''
|
|
2207
|
+
- 'S3_0_c15_c4_1':
|
|
2208
|
+
name: 'EHID4'
|
|
2209
|
+
description: ''
|
|
2210
|
+
- 'S3_0_c15_c5_0':
|
|
2211
|
+
name: 'HID5'
|
|
2212
|
+
description: 'L2 cache load/store prefetcher'
|
|
2213
|
+
- 'S3_0_c15_c5_1':
|
|
2214
|
+
name: 'EHID5'
|
|
2215
|
+
description: ''
|
|
2216
|
+
- 'S3_0_c15_c6_0':
|
|
2217
|
+
name: 'HID6'
|
|
2218
|
+
description: ''
|
|
2219
|
+
- 'S3_0_c15_c7_0':
|
|
2220
|
+
name: 'L2_CRAMCONFIG'
|
|
2221
|
+
description: ''
|
|
2222
|
+
- 'S3_0_c15_c8_0':
|
|
2223
|
+
name: 'HID8'
|
|
2224
|
+
description: ''
|
|
2225
|
+
- 'S3_0_c15_c9_0':
|
|
2226
|
+
name: 'HID9'
|
|
2227
|
+
description: ''
|
|
2228
|
+
- 'S3_0_c15_c10_0':
|
|
2229
|
+
name: 'HID10'
|
|
2230
|
+
description: ''
|
|
2231
|
+
- 'S3_0_c15_c10_1':
|
|
2232
|
+
name: 'EHID10'
|
|
2233
|
+
description: ''
|
|
2234
|
+
- 'S3_0_c15_c11_0':
|
|
2235
|
+
name: 'HID11'
|
|
2236
|
+
description: ''
|
|
2237
|
+
- 'S3_0_c15_c11_1':
|
|
2238
|
+
name: 'EHID11'
|
|
2239
|
+
description: ''
|
|
2240
|
+
- 'S3_0_c15_c14_0':
|
|
2241
|
+
name: 'HID13'
|
|
2242
|
+
description: ''
|
|
2243
|
+
- 'S3_0_c15_c15_0':
|
|
2244
|
+
name: 'HID14'
|
|
2245
|
+
description: ''
|
|
2246
|
+
- 'S3_0_c15_c15_2':
|
|
2247
|
+
name: 'HID16'
|
|
2248
|
+
description: ''
|
|
2249
|
+
- 'S3_1_c15_c0_0':
|
|
2250
|
+
name: 'PMCR0'
|
|
2251
|
+
description: 'Apple Performance Monitor Control Register 0'
|
|
2252
|
+
- 'S3_1_c15_c1_0':
|
|
2253
|
+
name: 'PMCR1'
|
|
2254
|
+
description: 'Controls which execution modes count events'
|
|
2255
|
+
- 'S3_1_c15_c2_0':
|
|
2256
|
+
name: 'PMCR2'
|
|
2257
|
+
description: 'Controls watchpoint registers'
|
|
2258
|
+
- 'S3_1_c15_c3_0':
|
|
2259
|
+
name: 'PMCR3'
|
|
2260
|
+
description: 'Controls breakpoints and address matching'
|
|
2261
|
+
- 'S3_1_c15_c4_0':
|
|
2262
|
+
name: 'PMCR4'
|
|
2263
|
+
description: 'Controls opcode matching'
|
|
2264
|
+
- 'S3_1_c15_c5_0':
|
|
2265
|
+
name: 'PMESR0'
|
|
2266
|
+
description: ''
|
|
2267
|
+
- 'S3_1_c15_c6_0':
|
|
2268
|
+
name: 'PMESR1'
|
|
2269
|
+
description: ''
|
|
2270
|
+
- 'S3_1_c15_c7_0':
|
|
2271
|
+
name: 'OPMAT0'
|
|
2272
|
+
description: ''
|
|
2273
|
+
- 'S3_1_c15_c8_0':
|
|
2274
|
+
name: 'OPMAT1'
|
|
2275
|
+
description: ''
|
|
2276
|
+
- 'S3_1_c15_c9_0':
|
|
2277
|
+
name: 'OPMSK0'
|
|
2278
|
+
description: ''
|
|
2279
|
+
- 'S3_1_c15_c10_0':
|
|
2280
|
+
name: 'OPMSK1'
|
|
2281
|
+
description: ''
|
|
2282
|
+
- 'S3_1_c15_c13_0':
|
|
2283
|
+
name: 'PMSR'
|
|
2284
|
+
description: ''
|
|
2285
|
+
- 'S3_2_c15_c0_0':
|
|
2286
|
+
name: 'PMC0'
|
|
2287
|
+
description: '48-bit cycles counter'
|
|
2288
|
+
- 'S3_2_c15_c1_0':
|
|
2289
|
+
name: 'PMC1'
|
|
2290
|
+
description: '48-bit instructions counter'
|
|
2291
|
+
- 'S3_2_c15_c2_0':
|
|
2292
|
+
name: 'PMC2'
|
|
2293
|
+
description: ''
|
|
2294
|
+
- 'S3_2_c15_c3_0':
|
|
2295
|
+
name: 'PMC3'
|
|
2296
|
+
description: ''
|
|
2297
|
+
- 'S3_2_c15_c4_0':
|
|
2298
|
+
name: 'PMC4'
|
|
2299
|
+
description: ''
|
|
2300
|
+
- 'S3_2_c15_c5_0':
|
|
2301
|
+
name: 'PMC5'
|
|
2302
|
+
description: ''
|
|
2303
|
+
- 'S3_2_c15_c6_0':
|
|
2304
|
+
name: 'PMC6'
|
|
2305
|
+
description: ''
|
|
2306
|
+
- 'S3_2_c15_c7_0':
|
|
2307
|
+
name: 'PMC7'
|
|
2308
|
+
description: ''
|
|
2309
|
+
- 'S3_2_c15_c9_0':
|
|
2310
|
+
name: 'PMC8'
|
|
2311
|
+
description: ''
|
|
2312
|
+
- 'S3_2_c15_c10_0':
|
|
2313
|
+
name: 'PMC9'
|
|
2314
|
+
description: ''
|
|
2315
|
+
- 'S3_2_c15_c12_0':
|
|
2316
|
+
name: 'PMTRHLD6'
|
|
2317
|
+
description: ''
|
|
2318
|
+
- 'S3_2_c15_c13_0':
|
|
2319
|
+
name: 'PMTRHLD4'
|
|
2320
|
+
description: ''
|
|
2321
|
+
- 'S3_2_c15_c14_0':
|
|
2322
|
+
name: 'PMTRHLD2'
|
|
2323
|
+
description: ''
|
|
2324
|
+
- 'S3_2_c15_c15_0':
|
|
2325
|
+
name: 'PMMMAP'
|
|
2326
|
+
description: ''
|
|
2327
|
+
- 'S3_3_c15_c0_0':
|
|
2328
|
+
name: 'LSU_ERR_STS'
|
|
2329
|
+
description: 'LSU Error Status'
|
|
2330
|
+
- 'S3_3_c15_c1_0':
|
|
2331
|
+
name: 'LSU_ERR_CTL'
|
|
2332
|
+
description: 'LSU Error Control'
|
|
2333
|
+
- 'S3_3_c15_c2_0':
|
|
2334
|
+
name: 'E_LSU_ERR_STS'
|
|
2335
|
+
description: 'LSU Error Status'
|
|
2336
|
+
- 'S3_3_c15_c7_0':
|
|
2337
|
+
name: 'L2_CRAMCONFIG'
|
|
2338
|
+
description: 'LSU Error Status'
|
|
2339
|
+
- 'S3_3_c15_c8_0':
|
|
2340
|
+
name: 'LLC_ERR_STS'
|
|
2341
|
+
description: 'LLC Error Status'
|
|
2342
|
+
- 'S3_3_c15_c8_1':
|
|
2343
|
+
name: 'L2E_ERR_STS'
|
|
2344
|
+
description: ''
|
|
2345
|
+
- 'S3_3_c15_c9_0':
|
|
2346
|
+
name: 'LLC_ERR_ADR'
|
|
2347
|
+
description: 'LLC Error Address'
|
|
2348
|
+
- 'S3_3_c15_c9_1':
|
|
2349
|
+
name: 'L2E_ERR_ADR'
|
|
2350
|
+
description: ''
|
|
2351
|
+
- 'S3_3_c15_c10_0':
|
|
2352
|
+
name: 'LLC_ERR_INF'
|
|
2353
|
+
description: 'LLC Error Information'
|
|
2354
|
+
- 'S3_3_c15_c10_1':
|
|
2355
|
+
name: 'L2E_ERR_INF'
|
|
2356
|
+
description: ''
|
|
2357
|
+
- 'S3_4_c15_c0_0':
|
|
2358
|
+
name: 'FED_ERR_STS'
|
|
2359
|
+
description: 'FED Error Status'
|
|
2360
|
+
- 'S3_4_c15_c0_2':
|
|
2361
|
+
name: 'E_FED_ERR_STS'
|
|
2362
|
+
description: 'FED Error Status'
|
|
2363
|
+
- 'S3_4_c15_c0_4':
|
|
2364
|
+
name: 'APCTL_EL1/MIGSTS'
|
|
2365
|
+
description: ''
|
|
2366
|
+
- 'S3_4_c15_c1_0':
|
|
2367
|
+
name: 'KERNELKEYLO_EL1'
|
|
2368
|
+
description: 'PAC Kernel Key (bits[63:0])'
|
|
2369
|
+
- 'S3_4_c15_c1_1':
|
|
2370
|
+
name: 'KERNELKEYHI_EL1'
|
|
2371
|
+
description: 'PAC Kernel Key (bits[127:64])'
|
|
2372
|
+
- 'S3_4_c15_c1_2':
|
|
2373
|
+
name: 'VMSA_LOCK_EL1'
|
|
2374
|
+
description: 'VMSA Lock'
|
|
2375
|
+
- 'S3_4_c15_c1_6':
|
|
2376
|
+
name: 'CTRR_B_UPR_EL1'
|
|
2377
|
+
description: 'CTRR Upper Range B'
|
|
2378
|
+
- 'S3_4_c15_c1_7':
|
|
2379
|
+
name: 'CTRR_B_LWR_EL1'
|
|
2380
|
+
description: 'CTRR Lower Range B'
|
|
2381
|
+
- 'S3_4_c15_c2_0':
|
|
2382
|
+
name: 'APRR_0'
|
|
2383
|
+
description: 'APRR Register 0'
|
|
2384
|
+
- 'S3_4_c15_c2_1':
|
|
2385
|
+
name: 'APRR_1'
|
|
2386
|
+
description: 'APRR Register 1'
|
|
2387
|
+
- 'S3_4_c15_c2_2':
|
|
2388
|
+
name: 'CTRR_LOCK'
|
|
2389
|
+
description: 'CTRR Lockdown'
|
|
2390
|
+
- 'S3_4_c15_c2_3':
|
|
2391
|
+
name: 'CTRR_A_LWR_EL1'
|
|
2392
|
+
description: 'CTRR Lower Range'
|
|
2393
|
+
- 'S3_4_c15_c2_4':
|
|
2394
|
+
name: 'CTRR_A_UPR_EL1'
|
|
2395
|
+
description: 'CTRR Upper Range'
|
|
2396
|
+
- 'S3_4_c15_c2_5':
|
|
2397
|
+
name: 'CTRR_CTL_EL1'
|
|
2398
|
+
description: 'CTRR Control Register'
|
|
2399
|
+
- 'S3_4_c15_c2_6':
|
|
2400
|
+
name: 'APRR_6'
|
|
2401
|
+
description: 'APRR Register 6'
|
|
2402
|
+
- 'S3_4_c15_c2_7':
|
|
2403
|
+
name: 'APRR_7'
|
|
2404
|
+
description: 'APRR Register 7'
|
|
2405
|
+
- 'S3_4_c15_c11_0':
|
|
2406
|
+
name: 'ACC_CTRR_A_LWR_EL2'
|
|
2407
|
+
description: ''
|
|
2408
|
+
- 'S3_4_c15_c11_1':
|
|
2409
|
+
name: 'ACC_CTRR_A_UPR_EL2'
|
|
2410
|
+
description: ''
|
|
2411
|
+
- 'S3_4_c15_c11_4':
|
|
2412
|
+
name: 'ACC_CTRR_CTL_EL2'
|
|
2413
|
+
description: ''
|
|
2414
|
+
- 'S3_4_c15_c11_5':
|
|
2415
|
+
name: 'ACC_CTRR_LOCK_EL2'
|
|
2416
|
+
description: ''
|
|
2417
|
+
- 'S3_5_c15_c0_0':
|
|
2418
|
+
name: 'IPI_RR_LOCAL'
|
|
2419
|
+
description: ''
|
|
2420
|
+
- 'S3_5_c15_c0_1':
|
|
2421
|
+
name: 'IPI_RR_GLOBAL'
|
|
2422
|
+
description: ''
|
|
2423
|
+
- 'S3_5_c15_c0_5':
|
|
2424
|
+
name: 'DPC_ERR_STS'
|
|
2425
|
+
description: ''
|
|
2426
|
+
- 'S3_5_c15_c1_1':
|
|
2427
|
+
name: 'IPI_SR'
|
|
2428
|
+
description: ''
|
|
2429
|
+
- 'S3_5_c15_c3_1':
|
|
2430
|
+
name: 'IPI_CR'
|
|
2431
|
+
description: ''
|
|
2432
|
+
- 'S3_5_c15_c4_0':
|
|
2433
|
+
name: 'ACC_CFG/CYC_CFG'
|
|
2434
|
+
description: ''
|
|
2435
|
+
- 'S3_5_c15_c5_0':
|
|
2436
|
+
name: 'CYC_OVRD'
|
|
2437
|
+
description: ''
|
|
2438
|
+
- 'S3_5_c15_c6_0':
|
|
2439
|
+
name: 'ACC_OVRD'
|
|
2440
|
+
description: ''
|
|
2441
|
+
- 'S3_5_c15_c6_1':
|
|
2442
|
+
name: 'ACC_EBLK_OVRD'
|
|
2443
|
+
description: ''
|
|
2444
|
+
- 'S3_6_c15_c0_0':
|
|
2445
|
+
name: 'MMU_ERR_STS'
|
|
2446
|
+
description: 'MMU Error Status'
|
|
2447
|
+
- 'S3_6_c15_c2_0':
|
|
2448
|
+
name: 'E_MMU_ERR_STS'
|
|
2449
|
+
description: 'MMU Error Status'
|
|
2450
|
+
- 'S3_6_c15_c12_4':
|
|
2451
|
+
name: 'APSTS_EL1'
|
|
2452
|
+
description: ''
|
|
2453
|
+
- 'S3_7_c15_c0_4':
|
|
2454
|
+
name: 'UPMCR0'
|
|
2455
|
+
description: 'Controls which counters are enabled and how interrupts are generated for overflows'
|
|
2456
|
+
- 'S3_7_c15_c0_5':
|
|
2457
|
+
name: 'UPMC8'
|
|
2458
|
+
description: ''
|
|
2459
|
+
- 'S3_7_c15_c1_4':
|
|
2460
|
+
name: 'UPMESR0'
|
|
2461
|
+
description: 'Event selection register for counters 0-7'
|
|
2462
|
+
- 'S3_7_c15_c1_5':
|
|
2463
|
+
name: 'UPMC9'
|
|
2464
|
+
description: ''
|
|
2465
|
+
- 'S3_7_c15_c2_5':
|
|
2466
|
+
name: 'UPMC10'
|
|
2467
|
+
description: ''
|
|
2468
|
+
- 'S3_7_c15_c3_4':
|
|
2469
|
+
name: 'UPMECM0'
|
|
2470
|
+
description: 'Event core masks for counters 0-3'
|
|
2471
|
+
- 'S3_7_c15_c3_5':
|
|
2472
|
+
name: 'UPMC11'
|
|
2473
|
+
description: ''
|
|
2474
|
+
- 'S3_7_c15_c4_4':
|
|
2475
|
+
name: 'UPMECM1'
|
|
2476
|
+
description: 'Event core masks for counters 4-7'
|
|
2477
|
+
- 'S3_7_c15_c4_5':
|
|
2478
|
+
name: 'UPMC12'
|
|
2479
|
+
description: ''
|
|
2480
|
+
- 'S3_7_c15_c5_4':
|
|
2481
|
+
name: 'UPMPCM'
|
|
2482
|
+
description: ''
|
|
2483
|
+
- 'S3_7_c15_c5_5':
|
|
2484
|
+
name: 'UPMC13'
|
|
2485
|
+
description: ''
|
|
2486
|
+
- 'S3_7_c15_c6_4':
|
|
2487
|
+
name: 'UPMSR'
|
|
2488
|
+
description: ''
|
|
2489
|
+
- 'S3_7_c15_c6_5':
|
|
2490
|
+
name: 'UPMC14'
|
|
2491
|
+
description: ''
|
|
2492
|
+
- 'S3_7_c15_c7_4':
|
|
2493
|
+
name: 'UPMC0'
|
|
2494
|
+
description: ''
|
|
2495
|
+
- 'S3_7_c15_c7_5':
|
|
2496
|
+
name: 'UPMC15'
|
|
2497
|
+
description: ''
|
|
2498
|
+
- 'S3_7_c15_c8_4':
|
|
2499
|
+
name: 'UPMC1'
|
|
2500
|
+
description: ''
|
|
2501
|
+
- 'S3_7_c15_c8_5':
|
|
2502
|
+
name: 'UPMECM2'
|
|
2503
|
+
description: 'Event core masks for counters 8-11'
|
|
2504
|
+
- 'S3_7_c15_c9_4':
|
|
2505
|
+
name: 'UPMC2'
|
|
2506
|
+
description: ''
|
|
2507
|
+
- 'S3_7_c15_c9_5':
|
|
2508
|
+
name: 'UPMECM3'
|
|
2509
|
+
description: 'Event core masks for counters 12-15'
|
|
2510
|
+
- 'S3_7_c15_c10_4':
|
|
2511
|
+
name: 'UPMC3'
|
|
2512
|
+
description: ''
|
|
2513
|
+
- 'S3_7_c15_c11_4':
|
|
2514
|
+
name: 'UPMC4'
|
|
2515
|
+
description: ''
|
|
2516
|
+
- 'S3_7_c15_c11_5':
|
|
2517
|
+
name: 'UPMESR1'
|
|
2518
|
+
description: 'Event selection register for counters 8-15'
|
|
2519
|
+
- 'S3_7_c15_c12_4':
|
|
2520
|
+
name: 'UPMC5'
|
|
2521
|
+
description: ''
|
|
2522
|
+
- 'S3_7_c15_c13_4':
|
|
2523
|
+
name: 'UPMC6'
|
|
2524
|
+
description: ''
|
|
2525
|
+
- 'S3_7_c15_c14_4':
|
|
2526
|
+
name: 'UPMC7'
|
|
2527
|
+
description: ''
|