aarch64 1.0.0 → 1.0.1

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Files changed (211) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +5 -2
  3. data/Rakefile +2 -0
  4. data/lib/aarch64/instructions/adc.rb +1 -1
  5. data/lib/aarch64/instructions/adcs.rb +1 -1
  6. data/lib/aarch64/instructions/add_addsub_ext.rb +1 -1
  7. data/lib/aarch64/instructions/and_log_imm.rb +1 -1
  8. data/lib/aarch64/instructions/ands_log_imm.rb +1 -1
  9. data/lib/aarch64/instructions/asrv.rb +1 -1
  10. data/lib/aarch64/instructions/axflag.rb +0 -6
  11. data/lib/aarch64/instructions/cfinv.rb +1 -1
  12. data/lib/aarch64/instructions/crc32.rb +1 -1
  13. data/lib/aarch64/instructions/crc32c.rb +1 -1
  14. data/lib/aarch64/instructions/csdb.rb +1 -8
  15. data/lib/aarch64/instructions/csel.rb +1 -1
  16. data/lib/aarch64/instructions/csneg.rb +1 -1
  17. data/lib/aarch64/instructions/dcps.rb +1 -1
  18. data/lib/aarch64/instructions/dgh.rb +1 -8
  19. data/lib/aarch64/instructions/dmb.rb +1 -1
  20. data/lib/aarch64/instructions/drps.rb +1 -1
  21. data/lib/aarch64/instructions/dsb.rb +1 -1
  22. data/lib/aarch64/instructions/eon.rb +1 -1
  23. data/lib/aarch64/instructions/eor_log_imm.rb +1 -1
  24. data/lib/aarch64/instructions/eor_log_shift.rb +1 -1
  25. data/lib/aarch64/instructions/eret.rb +1 -1
  26. data/lib/aarch64/instructions/ereta.rb +1 -1
  27. data/lib/aarch64/instructions/esb.rb +1 -8
  28. data/lib/aarch64/instructions/extr.rb +1 -1
  29. data/lib/aarch64/instructions/gmi.rb +1 -1
  30. data/lib/aarch64/instructions/hlt.rb +1 -1
  31. data/lib/aarch64/instructions/hvc.rb +1 -1
  32. data/lib/aarch64/instructions/irg.rb +1 -1
  33. data/lib/aarch64/instructions/isb.rb +1 -1
  34. data/lib/aarch64/instructions/ld64b.rb +1 -1
  35. data/lib/aarch64/instructions/ldadd.rb +1 -1
  36. data/lib/aarch64/instructions/ldaddb.rb +1 -1
  37. data/lib/aarch64/instructions/ldaddh.rb +1 -1
  38. data/lib/aarch64/instructions/ldapr.rb +1 -1
  39. data/lib/aarch64/instructions/ldaprb.rb +1 -1
  40. data/lib/aarch64/instructions/ldaprh.rb +1 -1
  41. data/lib/aarch64/instructions/ldapur_gen.rb +1 -1
  42. data/lib/aarch64/instructions/ldar.rb +1 -1
  43. data/lib/aarch64/instructions/ldaxp.rb +1 -1
  44. data/lib/aarch64/instructions/ldaxr.rb +1 -1
  45. data/lib/aarch64/instructions/ldclr.rb +1 -1
  46. data/lib/aarch64/instructions/ldclrb.rb +1 -1
  47. data/lib/aarch64/instructions/ldeor.rb +1 -1
  48. data/lib/aarch64/instructions/ldg.rb +1 -1
  49. data/lib/aarch64/instructions/ldgm.rb +1 -1
  50. data/lib/aarch64/instructions/ldlar.rb +1 -1
  51. data/lib/aarch64/instructions/ldnp_gen.rb +1 -1
  52. data/lib/aarch64/instructions/ldp_gen.rb +1 -1
  53. data/lib/aarch64/instructions/ldpsw.rb +1 -1
  54. data/lib/aarch64/instructions/ldr_imm_gen.rb +1 -1
  55. data/lib/aarch64/instructions/ldr_imm_unsigned.rb +1 -1
  56. data/lib/aarch64/instructions/ldr_lit_gen.rb +1 -1
  57. data/lib/aarch64/instructions/ldr_reg_gen.rb +1 -1
  58. data/lib/aarch64/instructions/ldra.rb +1 -1
  59. data/lib/aarch64/instructions/ldrb_imm.rb +1 -1
  60. data/lib/aarch64/instructions/ldrb_reg.rb +1 -1
  61. data/lib/aarch64/instructions/ldrb_unsigned.rb +1 -1
  62. data/lib/aarch64/instructions/ldrh_imm.rb +1 -1
  63. data/lib/aarch64/instructions/ldrh_reg.rb +1 -1
  64. data/lib/aarch64/instructions/ldrh_unsigned.rb +1 -1
  65. data/lib/aarch64/instructions/ldrsb_imm.rb +1 -1
  66. data/lib/aarch64/instructions/ldrsb_reg.rb +1 -1
  67. data/lib/aarch64/instructions/ldrsb_unsigned.rb +1 -1
  68. data/lib/aarch64/instructions/ldrsh_imm.rb +1 -1
  69. data/lib/aarch64/instructions/ldrsh_reg.rb +1 -1
  70. data/lib/aarch64/instructions/ldrsh_unsigned.rb +1 -1
  71. data/lib/aarch64/instructions/ldrsw_imm.rb +1 -1
  72. data/lib/aarch64/instructions/ldrsw_lit.rb +1 -1
  73. data/lib/aarch64/instructions/ldrsw_reg.rb +1 -1
  74. data/lib/aarch64/instructions/ldrsw_unsigned.rb +1 -1
  75. data/lib/aarch64/instructions/ldset.rb +1 -1
  76. data/lib/aarch64/instructions/ldsetb.rb +1 -1
  77. data/lib/aarch64/instructions/ldseth.rb +1 -1
  78. data/lib/aarch64/instructions/ldsmax.rb +1 -1
  79. data/lib/aarch64/instructions/ldsmaxb.rb +1 -1
  80. data/lib/aarch64/instructions/ldsmaxh.rb +1 -1
  81. data/lib/aarch64/instructions/ldsmin.rb +1 -1
  82. data/lib/aarch64/instructions/ldsminb.rb +1 -1
  83. data/lib/aarch64/instructions/ldsminh.rb +1 -1
  84. data/lib/aarch64/instructions/ldtr.rb +1 -1
  85. data/lib/aarch64/instructions/ldtrb.rb +1 -1
  86. data/lib/aarch64/instructions/ldtrh.rb +1 -1
  87. data/lib/aarch64/instructions/ldtrsb.rb +1 -1
  88. data/lib/aarch64/instructions/ldtrsh.rb +1 -1
  89. data/lib/aarch64/instructions/ldtrsw.rb +1 -1
  90. data/lib/aarch64/instructions/ldumax.rb +1 -1
  91. data/lib/aarch64/instructions/ldumaxb.rb +1 -1
  92. data/lib/aarch64/instructions/ldumaxh.rb +1 -1
  93. data/lib/aarch64/instructions/ldumin.rb +1 -1
  94. data/lib/aarch64/instructions/lduminb.rb +1 -1
  95. data/lib/aarch64/instructions/lduminh.rb +1 -1
  96. data/lib/aarch64/instructions/ldur_gen.rb +1 -1
  97. data/lib/aarch64/instructions/ldursb.rb +1 -1
  98. data/lib/aarch64/instructions/ldursh.rb +1 -1
  99. data/lib/aarch64/instructions/ldursw.rb +1 -1
  100. data/lib/aarch64/instructions/ldxp.rb +1 -1
  101. data/lib/aarch64/instructions/ldxr.rb +1 -1
  102. data/lib/aarch64/instructions/lslv.rb +1 -1
  103. data/lib/aarch64/instructions/lsrv.rb +1 -1
  104. data/lib/aarch64/instructions/madd.rb +1 -1
  105. data/lib/aarch64/instructions/movn.rb +1 -1
  106. data/lib/aarch64/instructions/mrs.rb +1 -1
  107. data/lib/aarch64/instructions/msr_imm.rb +1 -1
  108. data/lib/aarch64/instructions/msr_reg.rb +1 -1
  109. data/lib/aarch64/instructions/msub.rb +1 -1
  110. data/lib/aarch64/instructions/nop.rb +1 -8
  111. data/lib/aarch64/instructions/orn_log_shift.rb +1 -1
  112. data/lib/aarch64/instructions/orr_log_imm.rb +1 -1
  113. data/lib/aarch64/instructions/orr_log_shift.rb +1 -1
  114. data/lib/aarch64/instructions/pacda.rb +1 -1
  115. data/lib/aarch64/instructions/pacdb.rb +1 -1
  116. data/lib/aarch64/instructions/pacga.rb +1 -1
  117. data/lib/aarch64/instructions/pacia.rb +1 -1
  118. data/lib/aarch64/instructions/pacia2.rb +1 -1
  119. data/lib/aarch64/instructions/pacib.rb +1 -1
  120. data/lib/aarch64/instructions/prfm_imm.rb +1 -1
  121. data/lib/aarch64/instructions/prfm_lit.rb +1 -1
  122. data/lib/aarch64/instructions/prfm_reg.rb +1 -1
  123. data/lib/aarch64/instructions/prfum.rb +1 -1
  124. data/lib/aarch64/instructions/psb.rb +1 -1
  125. data/lib/aarch64/instructions/rbit_int.rb +1 -1
  126. data/lib/aarch64/instructions/reta.rb +1 -1
  127. data/lib/aarch64/instructions/rev.rb +1 -1
  128. data/lib/aarch64/instructions/rmif.rb +1 -1
  129. data/lib/aarch64/instructions/rorv.rb +1 -1
  130. data/lib/aarch64/instructions/sb.rb +1 -8
  131. data/lib/aarch64/instructions/sbc.rb +1 -1
  132. data/lib/aarch64/instructions/sbcs.rb +1 -1
  133. data/lib/aarch64/instructions/sdiv.rb +1 -1
  134. data/lib/aarch64/instructions/setf.rb +1 -1
  135. data/lib/aarch64/instructions/sev.rb +1 -1
  136. data/lib/aarch64/instructions/sevl.rb +0 -6
  137. data/lib/aarch64/instructions/smaddl.rb +1 -1
  138. data/lib/aarch64/instructions/smc.rb +1 -1
  139. data/lib/aarch64/instructions/smsubl.rb +1 -1
  140. data/lib/aarch64/instructions/smulh.rb +1 -1
  141. data/lib/aarch64/instructions/st2g.rb +1 -1
  142. data/lib/aarch64/instructions/st64b.rb +1 -1
  143. data/lib/aarch64/instructions/st64bv.rb +1 -1
  144. data/lib/aarch64/instructions/st64bv0.rb +1 -1
  145. data/lib/aarch64/instructions/stg.rb +1 -1
  146. data/lib/aarch64/instructions/stgm.rb +1 -1
  147. data/lib/aarch64/instructions/stgp.rb +1 -1
  148. data/lib/aarch64/instructions/stllr.rb +1 -1
  149. data/lib/aarch64/instructions/stllrb.rb +1 -1
  150. data/lib/aarch64/instructions/stllrh.rb +1 -1
  151. data/lib/aarch64/instructions/stlr.rb +1 -1
  152. data/lib/aarch64/instructions/stlrb.rb +1 -1
  153. data/lib/aarch64/instructions/stlrh.rb +1 -1
  154. data/lib/aarch64/instructions/stlur_gen.rb +1 -1
  155. data/lib/aarch64/instructions/stlxp.rb +1 -1
  156. data/lib/aarch64/instructions/stlxr.rb +1 -1
  157. data/lib/aarch64/instructions/stlxrb.rb +1 -1
  158. data/lib/aarch64/instructions/stlxrh.rb +1 -1
  159. data/lib/aarch64/instructions/stnp_gen.rb +1 -1
  160. data/lib/aarch64/instructions/stp_gen.rb +1 -1
  161. data/lib/aarch64/instructions/str_imm_gen.rb +1 -1
  162. data/lib/aarch64/instructions/str_imm_unsigned.rb +1 -1
  163. data/lib/aarch64/instructions/str_reg_gen.rb +1 -1
  164. data/lib/aarch64/instructions/strb_imm.rb +1 -1
  165. data/lib/aarch64/instructions/strb_imm_unsigned.rb +1 -1
  166. data/lib/aarch64/instructions/strb_reg.rb +1 -1
  167. data/lib/aarch64/instructions/strh_imm.rb +1 -1
  168. data/lib/aarch64/instructions/strh_imm_unsigned.rb +1 -1
  169. data/lib/aarch64/instructions/strh_reg.rb +1 -1
  170. data/lib/aarch64/instructions/sttr.rb +1 -1
  171. data/lib/aarch64/instructions/stur_gen.rb +1 -1
  172. data/lib/aarch64/instructions/stxp.rb +1 -1
  173. data/lib/aarch64/instructions/stxr.rb +1 -1
  174. data/lib/aarch64/instructions/stxrb.rb +1 -1
  175. data/lib/aarch64/instructions/stxrh.rb +1 -1
  176. data/lib/aarch64/instructions/stz2g.rb +1 -1
  177. data/lib/aarch64/instructions/stzg.rb +1 -1
  178. data/lib/aarch64/instructions/stzgm.rb +1 -1
  179. data/lib/aarch64/instructions/sub_addsub_ext.rb +1 -1
  180. data/lib/aarch64/instructions/sub_addsub_imm.rb +1 -1
  181. data/lib/aarch64/instructions/sub_addsub_shift.rb +1 -1
  182. data/lib/aarch64/instructions/subg.rb +1 -1
  183. data/lib/aarch64/instructions/subp.rb +1 -1
  184. data/lib/aarch64/instructions/subps.rb +1 -1
  185. data/lib/aarch64/instructions/svc.rb +1 -1
  186. data/lib/aarch64/instructions/swp.rb +1 -1
  187. data/lib/aarch64/instructions/swpb.rb +1 -1
  188. data/lib/aarch64/instructions/swph.rb +1 -1
  189. data/lib/aarch64/instructions/sys.rb +1 -1
  190. data/lib/aarch64/instructions/sysl.rb +1 -1
  191. data/lib/aarch64/instructions/tbnz.rb +1 -1
  192. data/lib/aarch64/instructions/tbz.rb +1 -1
  193. data/lib/aarch64/instructions/tsb.rb +1 -1
  194. data/lib/aarch64/instructions/ubfm.rb +1 -1
  195. data/lib/aarch64/instructions/udf_perm_undef.rb +1 -1
  196. data/lib/aarch64/instructions/udiv.rb +1 -1
  197. data/lib/aarch64/instructions/umaddl.rb +1 -1
  198. data/lib/aarch64/instructions/umsubl.rb +1 -1
  199. data/lib/aarch64/instructions/umulh.rb +1 -1
  200. data/lib/aarch64/instructions/wfe.rb +1 -1
  201. data/lib/aarch64/instructions/wfet.rb +1 -1
  202. data/lib/aarch64/instructions/wfi.rb +1 -8
  203. data/lib/aarch64/instructions/wfit.rb +1 -1
  204. data/lib/aarch64/instructions/xaflag.rb +1 -8
  205. data/lib/aarch64/instructions/xpac.rb +1 -1
  206. data/lib/aarch64/instructions/xpaclri.rb +0 -6
  207. data/lib/aarch64/instructions/yield.rb +1 -1
  208. data/lib/aarch64/version.rb +1 -1
  209. data/lib/aarch64.rb +72 -161
  210. data/test/dsl_test.rb +8 -0
  211. metadata +6 -6
@@ -5,7 +5,7 @@ module AArch64
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  # PSB CSYNC
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  class PSB
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  def encode
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- self.PSB
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+ PSB()
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  end
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  private
@@ -12,7 +12,7 @@ module AArch64
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  end
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  def encode
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- self.RBIT_int(@sf, @rn.to_i, @rd.to_i)
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+ RBIT_int(@sf, @rn.to_i, @rd.to_i)
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  end
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  private
@@ -10,7 +10,7 @@ module AArch64
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  end
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  def encode
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- self.RETA(@m)
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+ RETA(@m)
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  end
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  private
@@ -13,7 +13,7 @@ module AArch64
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  end
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  def encode
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- self.REV(@sf, @rn.to_i, @rd.to_i, @opc)
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+ REV(@sf, @rn.to_i, @rd.to_i, @opc)
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  end
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  private
@@ -11,7 +11,7 @@ module AArch64
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  end
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  def encode
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- self.RMIF(@imm6, @rn.to_i, @mask)
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+ RMIF(@imm6, @rn.to_i, @mask)
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  end
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  private
@@ -13,7 +13,7 @@ module AArch64
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  end
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  def encode
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- self.RORV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
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+ RORV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
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  end
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  private
@@ -5,14 +5,7 @@ module AArch64
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  # SB
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  class SB
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  def encode
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- self.SB
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- end
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-
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- private
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-
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- def SB
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- insn = 0b1101010100_0_00_011_0011_0000_1_11_11111
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- insn
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+ 0b1101010100_0_00_011_0011_0000_1_11_11111
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  end
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  end
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  end
@@ -13,7 +13,7 @@ module AArch64
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  end
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  def encode
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- self.SBC(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
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+ SBC(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
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  end
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  private
@@ -13,7 +13,7 @@ module AArch64
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  end
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  def encode
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- self.SBCS(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
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+ SBCS(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
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  end
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  private
@@ -13,7 +13,7 @@ module AArch64
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  end
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  def encode
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- self.SDIV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
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+ SDIV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
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  end
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  private
@@ -11,7 +11,7 @@ module AArch64
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  end
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  def encode
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- self.SETF(@sz, @rn.to_i)
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+ SETF(@sz, @rn.to_i)
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  end
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  private
@@ -5,7 +5,7 @@ module AArch64
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  # SEV
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  class SEV
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  def encode
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- self.SEV
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+ SEV()
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  end
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  private
@@ -5,12 +5,6 @@ module AArch64
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  # SEVL
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  class SEVL
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  def encode
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- self.SEVL
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- end
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-
11
- private
12
-
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- def SEVL
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  0b1101010100_0_00_011_0010_0000_101_11111
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  end
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  end
@@ -12,7 +12,7 @@ module AArch64
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  end
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  def encode
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- self.SMADDL(@rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
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+ SMADDL(@rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
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  end
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  private
@@ -9,7 +9,7 @@ module AArch64
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  end
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  def encode
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- self.SMC(@imm16)
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+ SMC(@imm16)
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  end
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  private
@@ -12,7 +12,7 @@ module AArch64
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  end
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  def encode
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- self.SMSUBL(@rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
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+ SMSUBL(@rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
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  end
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  private
@@ -11,7 +11,7 @@ module AArch64
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  end
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  def encode
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- self.SMULH(@rm.to_i, @rn.to_i, @rd.to_i)
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+ SMULH(@rm.to_i, @rn.to_i, @rd.to_i)
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  end
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  private
@@ -14,7 +14,7 @@ module AArch64
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  end
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  def encode
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- self.ST2G(@imm9, @option, @xn.to_i, @xt.to_i)
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+ ST2G(@imm9, @option, @xn.to_i, @xt.to_i)
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  end
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  private
@@ -10,7 +10,7 @@ module AArch64
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  end
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  def encode
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- self.ST64B(@rn.to_i, @rt.to_i)
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+ ST64B(@rn.to_i, @rt.to_i)
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  end
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  private
@@ -11,7 +11,7 @@ module AArch64
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  end
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  def encode
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- self.ST64BV(@rs.to_i, @rn.to_i, @rt.to_i)
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+ ST64BV(@rs.to_i, @rn.to_i, @rt.to_i)
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  end
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  private
@@ -11,7 +11,7 @@ module AArch64
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  end
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  def encode
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- self.ST64BV0(@rs.to_i, @rn.to_i, @rt.to_i)
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+ ST64BV0(@rs.to_i, @rn.to_i, @rt.to_i)
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  end
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  private
@@ -14,7 +14,7 @@ module AArch64
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  end
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  def encode
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- self.STG(@imm9, @option, @xn.to_i, @xt.to_i)
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+ STG(@imm9, @option, @xn.to_i, @xt.to_i)
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  end
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  private
@@ -10,7 +10,7 @@ module AArch64
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  end
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  def encode
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- self.STGM(@xn.to_i, @xt.to_i)
13
+ STGM(@xn.to_i, @xt.to_i)
14
14
  end
15
15
 
16
16
  private
@@ -15,7 +15,7 @@ module AArch64
15
15
  end
16
16
 
17
17
  def encode
18
- self.STGP(@option, @simm7, @xt2.to_i, @xn.to_i, @xt.to_i)
18
+ STGP(@option, @simm7, @xt2.to_i, @xn.to_i, @xt.to_i)
19
19
  end
20
20
 
21
21
  private
@@ -12,7 +12,7 @@ module AArch64
12
12
  end
13
13
 
14
14
  def encode
15
- self.STLLR(@size, @rn.to_i, @rt.to_i)
15
+ STLLR(@size, @rn.to_i, @rt.to_i)
16
16
  end
17
17
 
18
18
  private
@@ -10,7 +10,7 @@ module AArch64
10
10
  end
11
11
 
12
12
  def encode
13
- self.STLLRB(@rn.to_i, @rt.to_i)
13
+ STLLRB(@rn.to_i, @rt.to_i)
14
14
  end
15
15
 
16
16
  private
@@ -10,7 +10,7 @@ module AArch64
10
10
  end
11
11
 
12
12
  def encode
13
- self.STLLRH(@rn.to_i, @rt.to_i)
13
+ STLLRH(@rn.to_i, @rt.to_i)
14
14
  end
15
15
 
16
16
  private
@@ -12,7 +12,7 @@ module AArch64
12
12
  end
13
13
 
14
14
  def encode
15
- self.STLR(@size, @rn.to_i, @rt.to_i)
15
+ STLR(@size, @rn.to_i, @rt.to_i)
16
16
  end
17
17
 
18
18
  private
@@ -10,7 +10,7 @@ module AArch64
10
10
  end
11
11
 
12
12
  def encode
13
- self.STLRB(@rn.to_i, @rt.to_i)
13
+ STLRB(@rn.to_i, @rt.to_i)
14
14
  end
15
15
 
16
16
  private
@@ -10,7 +10,7 @@ module AArch64
10
10
  end
11
11
 
12
12
  def encode
13
- self.STLRH(@rn.to_i, @rt.to_i)
13
+ STLRH(@rn.to_i, @rt.to_i)
14
14
  end
15
15
 
16
16
  private
@@ -13,7 +13,7 @@ module AArch64
13
13
  end
14
14
 
15
15
  def encode
16
- self.STLUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
16
+ STLUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
17
17
  end
18
18
 
19
19
  private
@@ -14,7 +14,7 @@ module AArch64
14
14
  end
15
15
 
16
16
  def encode
17
- self.STLXP(@sz, @rs.to_i, @rt2.to_i, @rn.to_i, @rt.to_i)
17
+ STLXP(@sz, @rs.to_i, @rt2.to_i, @rn.to_i, @rt.to_i)
18
18
  end
19
19
 
20
20
  private
@@ -13,7 +13,7 @@ module AArch64
13
13
  end
14
14
 
15
15
  def encode
16
- self.STLXR(@size, @rs.to_i, @rn.to_i, @rt.to_i)
16
+ STLXR(@size, @rs.to_i, @rn.to_i, @rt.to_i)
17
17
  end
18
18
 
19
19
  private
@@ -11,7 +11,7 @@ module AArch64
11
11
  end
12
12
 
13
13
  def encode
14
- self.STLXRB(@rs.to_i, @rn.to_i, @rt.to_i)
14
+ STLXRB(@rs.to_i, @rn.to_i, @rt.to_i)
15
15
  end
16
16
 
17
17
  private
@@ -11,7 +11,7 @@ module AArch64
11
11
  end
12
12
 
13
13
  def encode
14
- self.STLXRH(@rs.to_i, @rn.to_i, @rt.to_i)
14
+ STLXRH(@rs.to_i, @rn.to_i, @rt.to_i)
15
15
  end
16
16
 
17
17
  private
@@ -14,7 +14,7 @@ module AArch64
14
14
  end
15
15
 
16
16
  def encode
17
- self.STNP_gen(@opc, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
17
+ STNP_gen(@opc, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
18
18
  end
19
19
 
20
20
  private
@@ -19,7 +19,7 @@ module AArch64
19
19
  end
20
20
 
21
21
  def encode
22
- self.STP_gen(@opc, @option, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
22
+ STP_gen(@opc, @option, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
23
23
  end
24
24
 
25
25
  private
@@ -18,7 +18,7 @@ module AArch64
18
18
  end
19
19
 
20
20
  def encode
21
- self.STR_imm_gen(@size, @imm9, @opt, @rn.to_i, @rt.to_i)
21
+ STR_imm_gen(@size, @imm9, @opt, @rn.to_i, @rt.to_i)
22
22
  end
23
23
 
24
24
  private
@@ -13,7 +13,7 @@ module AArch64
13
13
  end
14
14
 
15
15
  def encode
16
- self.STR_imm_gen(@size, @imm12, @rn.to_i, @rt.to_i)
16
+ STR_imm_gen(@size, @imm12, @rn.to_i, @rt.to_i)
17
17
  end
18
18
 
19
19
  private
@@ -15,7 +15,7 @@ module AArch64
15
15
  end
16
16
 
17
17
  def encode
18
- self.STR_reg_gen(@size, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
18
+ STR_reg_gen(@size, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
19
19
  end
20
20
 
21
21
  private
@@ -14,7 +14,7 @@ module AArch64
14
14
  end
15
15
 
16
16
  def encode
17
- self.STRB_imm(@imm9, @opt, @rn.to_i, @rt.to_i)
17
+ STRB_imm(@imm9, @opt, @rn.to_i, @rt.to_i)
18
18
  end
19
19
 
20
20
  private
@@ -11,7 +11,7 @@ module AArch64
11
11
  end
12
12
 
13
13
  def encode
14
- self.STRB_imm_unsigned(@imm12, @rn.to_i, @rt.to_i)
14
+ STRB_imm_unsigned(@imm12, @rn.to_i, @rt.to_i)
15
15
  end
16
16
 
17
17
  private
@@ -14,7 +14,7 @@ module AArch64
14
14
  end
15
15
 
16
16
  def encode
17
- self.STRB_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
17
+ STRB_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
18
18
  end
19
19
 
20
20
  private
@@ -14,7 +14,7 @@ module AArch64
14
14
  end
15
15
 
16
16
  def encode
17
- self.STRH_imm(@imm9, @opt, @rn.to_i, @rt.to_i)
17
+ STRH_imm(@imm9, @opt, @rn.to_i, @rt.to_i)
18
18
  end
19
19
 
20
20
  private
@@ -11,7 +11,7 @@ module AArch64
11
11
  end
12
12
 
13
13
  def encode
14
- self.STRH_imm_unsigned(@imm12, @rn.to_i, @rt.to_i)
14
+ STRH_imm_unsigned(@imm12, @rn.to_i, @rt.to_i)
15
15
  end
16
16
 
17
17
  private
@@ -13,7 +13,7 @@ module AArch64
13
13
  end
14
14
 
15
15
  def encode
16
- self.STRH_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
16
+ STRH_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
17
17
  end
18
18
 
19
19
  private
@@ -13,7 +13,7 @@ module AArch64
13
13
  end
14
14
 
15
15
  def encode
16
- self.STTR(@size, @imm9, @rn.to_i, @rt.to_i)
16
+ STTR(@size, @imm9, @rn.to_i, @rt.to_i)
17
17
  end
18
18
 
19
19
  private
@@ -13,7 +13,7 @@ module AArch64
13
13
  end
14
14
 
15
15
  def encode
16
- self.STUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
16
+ STUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
17
17
  end
18
18
 
19
19
  private
@@ -14,7 +14,7 @@ module AArch64
14
14
  end
15
15
 
16
16
  def encode
17
- self.STXP(@sf, @rs.to_i, @rt2.to_i, @rn.to_i, @rt1.to_i)
17
+ STXP(@sf, @rs.to_i, @rt2.to_i, @rn.to_i, @rt1.to_i)
18
18
  end
19
19
 
20
20
  private
@@ -13,7 +13,7 @@ module AArch64
13
13
  end
14
14
 
15
15
  def encode
16
- self.STXR(@size, @rs.to_i, @rn.to_i, @rt.to_i)
16
+ STXR(@size, @rs.to_i, @rn.to_i, @rt.to_i)
17
17
  end
18
18
 
19
19
  private
@@ -11,7 +11,7 @@ module AArch64
11
11
  end
12
12
 
13
13
  def encode
14
- self.STXRB(@rs.to_i, @rn.to_i, @rt.to_i)
14
+ STXRB(@rs.to_i, @rn.to_i, @rt.to_i)
15
15
  end
16
16
 
17
17
  private
@@ -11,7 +11,7 @@ module AArch64
11
11
  end
12
12
 
13
13
  def encode
14
- self.STXRH(@rs.to_i, @rn.to_i, @rt.to_i)
14
+ STXRH(@rs.to_i, @rn.to_i, @rt.to_i)
15
15
  end
16
16
 
17
17
  private
@@ -14,7 +14,7 @@ module AArch64
14
14
  end
15
15
 
16
16
  def encode
17
- self.STZ2G(@imm9, @opt, @xn.to_i, @xt.to_i)
17
+ STZ2G(@imm9, @opt, @xn.to_i, @xt.to_i)
18
18
  end
19
19
 
20
20
  private
@@ -14,7 +14,7 @@ module AArch64
14
14
  end
15
15
 
16
16
  def encode
17
- self.STZG(@imm9, @opt, @xn.to_i, @xt.to_i)
17
+ STZG(@imm9, @opt, @xn.to_i, @xt.to_i)
18
18
  end
19
19
 
20
20
  private
@@ -10,7 +10,7 @@ module AArch64
10
10
  end
11
11
 
12
12
  def encode
13
- self.STZGM(@rn.to_i, @rt.to_i)
13
+ STZGM(@rn.to_i, @rt.to_i)
14
14
  end
15
15
 
16
16
  private
@@ -15,7 +15,7 @@ module AArch64
15
15
  end
16
16
 
17
17
  def encode
18
- self.SUB_addsub_ext(@sf, @rm.to_i, @extend, @amount, @rn.to_i, @rd.to_i)
18
+ SUB_addsub_ext(@sf, @rm.to_i, @extend, @amount, @rn.to_i, @rd.to_i)
19
19
  end
20
20
 
21
21
  private
@@ -14,7 +14,7 @@ module AArch64
14
14
  end
15
15
 
16
16
  def encode
17
- self.SUB_addsub_imm(@sf, @shift, @imm, @rn.to_i, @rd.to_i)
17
+ SUB_addsub_imm(@sf, @shift, @imm, @rn.to_i, @rd.to_i)
18
18
  end
19
19
 
20
20
  private
@@ -15,7 +15,7 @@ module AArch64
15
15
  end
16
16
 
17
17
  def encode
18
- self.SUB_addsub_shift(@sf, @shift, @rm.to_i, @amount, @rn.to_i, @rd.to_i)
18
+ SUB_addsub_shift(@sf, @shift, @rm.to_i, @amount, @rn.to_i, @rd.to_i)
19
19
  end
20
20
 
21
21
  private
@@ -12,7 +12,7 @@ module AArch64
12
12
  end
13
13
 
14
14
  def encode
15
- self.SUBG(@uimm6, @uimm4, @xn.to_i, @xd.to_i)
15
+ SUBG(@uimm6, @uimm4, @xn.to_i, @xd.to_i)
16
16
  end
17
17
 
18
18
  private
@@ -11,7 +11,7 @@ module AArch64
11
11
  end
12
12
 
13
13
  def encode
14
- self.SUBP(@xm.to_i, @xn.to_i, @xm.to_i)
14
+ SUBP(@xm.to_i, @xn.to_i, @xm.to_i)
15
15
  end
16
16
 
17
17
  private
@@ -11,7 +11,7 @@ module AArch64
11
11
  end
12
12
 
13
13
  def encode
14
- self.SUBPS(@xm.to_i, @xn.to_i, @xd.to_i)
14
+ SUBPS(@xm.to_i, @xn.to_i, @xd.to_i)
15
15
  end
16
16
 
17
17
  private
@@ -9,7 +9,7 @@ module AArch64
9
9
  end
10
10
 
11
11
  def encode
12
- self.SVC(@imm)
12
+ SVC(@imm)
13
13
  end
14
14
 
15
15
  private
@@ -21,7 +21,7 @@ module AArch64
21
21
  end
22
22
 
23
23
  def encode
24
- self.SWP(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
24
+ SWP(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
25
25
  end
26
26
 
27
27
  private