Rdcpu16 0.0.1

data/MIT-LICENSE

@@ -0,0 +1,21 @@
+Copyright 2012 Patrick Helm
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be
+included in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+

data/README.rdoc

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+= Rdcpu16
+
+== Ruby port of: http://0x10c.com/doc/dcpu-16.txt
+This is a simple Ruby port of the fictive 16-bit-cpu DCPU16.
+
+== Make sure to checkout these resources:
+
+  * http://0x10c.com/
+  * http://0x10cforum.com/
+

data/Rakefile

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+##!/usr/bin/env rake
+##include Rake::DSL
+
+require "bundler/gem_tasks"
+
+#begin
+#  require 'bundler/setup'
+#rescue LoadError
+#  puts 'You must `gem install bundler` and `bundle install` to run rake tasks'
+#end
+#begin
+#  require 'rdoc/task'
+#rescue LoadError
+#  require 'rdoc/rdoc'
+#  require 'rake/rdoctask'
+#  RDoc::Task = Rake::RDocTask
+#end
+
+#RDoc::Task.new(:rdoc) do |rdoc|
+#  rdoc.rdoc_dir = 'rdoc'
+#  rdoc.title    = 'RubyRescuetime'
+#  rdoc.options << '--line-numbers'
+#  rdoc.rdoc_files.include('README.rdoc')
+#  rdoc.rdoc_files.include('lib/**/*.rb')
+#end
+
+
+
+#Bundler::GemHelper.install_tasks
+
+## require 'rake/testtask'
+
+##Rake::TestTask.new(:test) do |t|
+##  t.libs << 'lib'
+##  t.libs << 'test'
+##  t.pattern = 'test/**/*_test.rb'
+##  t.verbose = true
+##end
+
+
+##task :default => :test
+

data/lib/dcpu16/cpu/instructions.rb

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+module DCPU16
+  module Instructions
+    # sets a to b
+    def set(a, b)
+      @cycle += 1
+      b
+    end
+
+    # sets a to a+b, sets O to 0x0001 if there's an overflow, 0x0 otherwise
+    def add(a, b)
+      @cycle += 2
+      (a + b > 0xFFFF) ? @O.write(0x0001) : @O.write(0x0)
+      a + b
+    end
+
+    # sets a to a-b, sets O to 0xffff if there's an underflow, 0x0 otherwise
+    def sub(a, b)
+      @cycle += 2
+      (b > a) ? @O.write(0xffff) : @O.write(0x0)
+      a - b
+    end
+
+    # sets a to a*b, sets O to
+    def mul(a, b)
+      @cycle += 2
+      @O.write( ( (a * b) >> 16) & 0xffff )
+      a * b
+    end
+
+    # sets a to a/b, sets O to ((a<<16)/b)&0xffff. if b==0, sets a and O to 0 instead.
+    def div(a, b)
+      @cycle += 3
+      if b == 0
+        @O.write(0)
+        return 0
+      else
+        @O.write( ( (a << 16) / b) & 0xffff )
+        return (a / b)
+      end
+    end
+
+    # sets a to a%b. if b==0, sets a to 0 instead.
+    def mod(a, b)
+      @cycle += 3
+      (b == 0) ? 0 : a % b
+    end
+
+    # sets a to a<<b, sets O to ((a<<b)>>16)&0xffff
+    def shl(a, b)
+      @cycle += 2
+      @O.write( ( (a << b) >> 16 ) & 0xffff )
+      a << b
+    end
+
+    # sets a to a>>b, sets O to ((a<<16)>>b)&0xffff
+    def shr(a, b)
+      @cycle += 2
+      @O.write( ( (a << 16) >> b) & 0xffff )
+      a >> b
+    end
+
+    # sets a to a & b
+    def and(a, b)
+      @cycle += 1
+      a & b
+    end
+
+    # sets a to a | b
+    def bor(a, b)
+      @cycle += 1
+      a | b
+    end
+
+    # sets a to a ^ b
+    def xor(a, b)
+      @cycle += 1
+      a ^ b
+    end
+
+    # performs next instruction only if a == b
+    def ife(a, b)
+      @cycle += 2
+      @skip = !(a == b)
+      @cycle += 1 unless a == b
+
+      return nil
+    end
+
+    # performs next instruction only if a != b
+    def ifn(a, b)
+      @cycle += 2
+      @skip = !(a != b)
+      @cycle += 1 unless a != b
+
+      return nil
+    end
+
+    # performs next instruction only if a > b
+    def ifg(a, b)
+      @cycle += 2
+      @skip = !(a > b)
+      @cycle += 1 unless a > b
+
+      return nil
+    end
+
+    # performs next instruction only if (a & b) != 0
+    def ifb(a, b)
+      @cycle += 2
+      @skip = !((a & b) != 0)
+      @cycle += 1 unless (a & b) != 0
+
+      return nil
+    end
+
+
+    class Reserved < StandardError; end
+
+    ### NON - Basic ###
+    def reserved(a)
+      raise Reserved
+    end
+
+    # JSR a - pushes the address of the next instruction to the stack, then sets PC to a
+    def jsr(a)
+      @cycle += 2
+
+      # pushes the address of the next instruction to the stack
+      @SP -= 1
+      @memory.write(@SP, @PC.read)
+
+      @PC.write(a)
+      return nil
+    end
+  end
+end
+

data/lib/dcpu16/cpu.rb

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+require 'dcpu16/support/debug'
+
+require 'dcpu16/cpu/instructions'
+
+require 'dcpu16/instruction'
+require 'dcpu16/literal'
+require 'dcpu16/memory'
+require 'dcpu16/operand'
+require 'dcpu16/register'
+
+require "observer"
+
+module DCPU16
+  class CPU
+    include DCPU16::Debug
+    include DCPU16::Instructions
+    include Observable
+
+    RAM_SIZE  = 0x10000
+    REGISTERS = [:A, :B, :C, :X, :Y, :Z, :I, :J]
+    REGISTERS_COUNT = REGISTERS.length
+    CLOCK_CYCLE = 100000 # cycles per second
+
+    attr_accessor :cycle, :memory, :registers
+
+    # program counter (PC), stack pointer (SP), overflow (O)
+    attr_accessor :PC, :SP, :O
+
+    # HACK: actually used to determine if we need to skip next instruction
+    attr_accessor :skip
+
+    attr_accessor :clock_cycle
+
+    def initialize(memory = [])
+      @cycle      = 0
+      @memory     = DCPU16::Memory.new(memory)
+      @registers  = Array.new(REGISTERS_COUNT) { DCPU16::Register.new }
+      @PC = DCPU16::Register.new(0x0)
+      @SP = DCPU16::Register.new(0xFFFF)
+      @O  = DCPU16::Register.new(0x0)
+
+      @clock_cycle = CLOCK_CYCLE
+      @debug = true
+      @skip  = false
+    end
+
+    # Define alias_methods for Registers: A(), B(), ...
+    REGISTERS.each_with_index { |k, v| define_method(k) { registers[v] } }
+
+    # Run in endless loop
+    def run
+      @started_at = Time.now
+      max_cycles = 1
+
+      while true do
+        if @cycle < max_cycles
+          step
+        else
+          diff = Time.now - @started_at
+          max_cycles = (diff * @clock_cycle)
+        end
+      end
+    end
+
+    # Resets the CPU and its sub-systems (registers, memory, ...)
+    def reset
+      @cycle = 0
+      @memory.reset
+      @registers.each { |r| r.reset }
+      @PC.reset
+      @SP.reset
+      @O.reset
+    end
+
+    # DOC
+    def last_instruction
+      @instruction
+    end
+
+    # Perform a single step
+    # TODO: Refacor if/else/if/else ...
+    def step
+      @instruction = Instruction.new(@memory.read(@PC))
+      @PC += 1
+
+      op  = @instruction.op
+      a   = get_operand(@instruction.a)
+      b   = get_operand(@instruction.b) if @instruction.b
+
+      if @skip
+        @skip = false
+      else
+        if b
+          result = self.send(op, a.value, b.value)
+        else
+          result = self.send(op, a.value)
+        end
+        a.write(result) if result
+      end
+
+      changed
+      notify_observers(self)
+    end
+
+    # TODO: May be removed
+    def get_operand(value)
+      DCPU16::Operand.new(self, value)
+    end
+  end
+end
+

data/lib/dcpu16/instruction.rb

@@ -0,0 +1,57 @@
+# Instructions are 1-3 words long and are fully defined by the first word.
+# In a basic instruction, the lower four bits of the first word of the instruction are the opcode,
+# and the remaining twelve bits are split into two six bit values, called a and b.
+# a is always handled by the processor before b, and is the lower six bits.
+
+# In bits (with the least significant being last),
+# a basic instruction has the format: bbbbbbaaaaaaoooo
+
+# bbbb bbaa aaaa oooo
+# 0000 0000 0000 1111 -> 0x000f
+# 0000 0011 1111 0000 -> 0x03f0
+# 1111 1100 0000 0000 -> 0xfc00
+
+# Non-basic opcodes always have their lower four bits unset, have one value and a six bit opcode.
+# In binary, they have the format: aaaaaaoooooo0000
+
+# aaaa aaoo oooo 0000
+# 0000 0011 1111 0000 -> 0x03f0
+# 1111 1100 0000 0000 -> 0xfc00
+
+module DCPU16
+  class Instruction
+    INSTRUCTIONS = [
+      :reserved,
+      :set, :add, :sub, :mul, :div, :mod,
+      :shl, :shr,
+      :and, :bor, :xor,
+      :ife, :ifn, :ifg, :ifb
+    ]
+
+    NON_BASIC_INSTRUCTIONS = [
+      :reserved,
+      :jsr
+    ]
+
+    attr_reader :opcode, :a, :b, :word
+
+    def initialize(word = nil)
+      @word   = word.value
+      @opcode = @word & 0x000F
+
+      if @opcode == 0x0
+        @non_basic = true
+        @opcode = (@word >> 4) & 0x3f
+        @a      = @word >> 10
+      else
+        @a = (@word >> 4) & 0x3f
+        @b = @word >> 10
+      end
+    end
+
+    def op
+      @non_basic ? NON_BASIC_INSTRUCTIONS[@opcode] : INSTRUCTIONS[@opcode]
+    end
+  end
+end
+

data/lib/dcpu16/literal.rb

@@ -0,0 +1,19 @@
+# Ruby, Y U NO INHERIT FROM INTEGER?
+module DCPU16
+  class Literal
+    def initialize(value)
+      @value = value
+    end
+
+    def value
+      @value
+    end
+    alias_method :read, :value
+
+    # If any instruction tries to assign a literal value, the assignment fails silently
+    def write(value)
+      # pass
+    end
+  end
+end
+

data/lib/dcpu16/memory.rb

@@ -0,0 +1,40 @@
+require 'dcpu16/word'
+
+module DCPU16
+  class Memory < Array
+    SIZE = 0x10000
+    DEFAULT_VALUE = 0x0
+
+    def initialize(default = [])
+      super(SIZE, DEFAULT_VALUE)
+      default.each_with_index { |word, offset| write(offset, word) }
+    end
+
+    def read(offset)
+      # HACK: so we can just pass a Fixnum or a Register
+      offset = offset.value if offset.respond_to? :value
+
+      DCPU16::Word.new(self[offset], self, offset)
+    end
+
+    def write(offset, value)
+      # HACK: so we can just pass a Fixnum or a Register
+      offset = offset.value if offset.respond_to? :value
+
+      self[offset] = value
+    end
+
+    def reset
+    end
+
+    private
+    def [](key)
+      super(key)
+    end
+
+    def []=(key, value)
+      super(key, value)
+    end
+  end
+end
+

data/lib/dcpu16/operand.rb

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+# TODO: Test && Refacoring
+module DCPU16
+  class Operand
+    class NotFound < StandardError; end
+
+    def self.new(cpu, value)
+      if (0x00..0x07).include?(value)
+        # register (A, B, C, X, Y, Z, I or J, in that order)
+        return cpu.registers[value]
+      elsif (0x08..0x0f).include?(value)
+        # [register]
+        register = cpu.registers[value - DCPU16::CPU::REGISTERS_COUNT]
+        return cpu.memory.read(register)
+      elsif (0x10..0x17).include?(value)
+        cpu.cycle += 1
+        offset = cpu.memory.read(cpu.PC).value
+        cpu.PC += 1
+        return cpu.memory.read(offset + cpu.registers[value - 0x10].read)
+      elsif value == 0x18
+        # POP / [SP++]
+        r = cpu.memory.read(cpu.SP)
+        cpu.SP += 1
+        return r
+      elsif value == 0x19
+        # PEEK / [SP]
+        return cpu.memory.read(cpu.SP)
+      elsif value == 0x1a
+        # PUSH / [--SP]
+        cpu.SP -= 1
+        cpu.memory.read(cpu.SP)
+      elsif value == 0x1b
+        # SP
+        return cpu.SP
+      elsif value == 0x1c
+        # PC
+        return cpu.PC
+      elsif value == 0x1d
+        # O
+        return cpu.O
+      elsif value == 0x1e
+        # [next word]
+        cpu.cycle += 1
+        offset = cpu.memory.read(cpu.PC)
+        cpu.PC += 1
+        return cpu.memory.read(offset)
+      elsif value == 0x1f
+        # next word (literal)
+        cpu.cycle += 1
+        r = cpu.memory.read(cpu.PC)
+        cpu.PC += 1
+        return r
+      elsif (0x20..0x3f).include?(value)
+        # literal value 0x00-0x1f (literal)
+        DCPU16::Literal.new(value - 0x20)
+      else
+        raise NotFound
+      end
+    end
+  end
+end
+

data/lib/dcpu16/register.rb

@@ -0,0 +1,35 @@
+module DCPU16
+  class Register
+    attr_reader :value
+
+    def initialize(value = 0x0)
+      @default_value = value
+      reset
+    end
+
+    def value
+      warn "[Register #{self}] No Value defined" unless @value
+      @value
+    end
+    alias_method :read, :value
+
+    def +(value)
+      @value += value
+      self
+    end
+
+    def -(value)
+      @value -= value
+      self
+    end
+
+    def write(value)
+      @value = value
+    end
+
+    def reset
+      @value = @default_value
+    end
+  end
+end
+

data/lib/dcpu16/support/debug.rb

@@ -0,0 +1,47 @@
+# Just a simple Debugger class
+module DCPU16
+  module Debug
+    # Debug-mode turned on?
+    def debug?
+      @debug ||= false
+    end
+
+    private
+    # Debug-Wrapper
+    def debug(msg = nil, &block)
+      return unless debug?
+
+      puts "\n[DEBUG] - #{caller.first}"
+      msg.each { |m| puts(m) } if msg.is_a?(Array)
+
+      if msg.is_a?(Hash)
+        msg.each do |k, v|
+          puts "[#{k.to_s}]"
+
+          if v.is_a?(Array)
+            v.each {|m| puts(m) }
+          else
+            puts v
+          end
+        end
+      elsif (msg.is_a?(String) || msg.is_a?(Symbol))
+        puts msg.to_s
+      end
+
+      yield if block_given?
+      puts "\n"
+    end
+
+    # DCPU16::CPU
+    def debug_state
+      debug do
+        puts "Cycle:\t#{@cycle}"
+        puts "PC:\t#{@PC}"
+        puts "SP:\t#{@SP}"
+        puts "O:\t#{@O}"
+        puts "R:\t#{@registers}"
+      end
+    end
+  end
+end
+

data/lib/dcpu16/version.rb

@@ -0,0 +1,4 @@
+module DCPU16
+  VERSION = "0.0.1"
+end
+

data/lib/dcpu16/word.rb

@@ -0,0 +1,20 @@
+module DCPU16
+  class Word
+    def initialize(value, memory = nil, offset = nil)
+      @value  = value
+      @memory = memory
+      @offset = offset
+    end
+
+    def value
+      @value
+    end
+    alias_method :read, :value
+
+    def write(value)
+      @value = value
+      @memory.write(@offset, value)
+    end
+  end
+end
+

data/lib/dcpu16.rb

@@ -0,0 +1,6 @@
+require 'dcpu16/cpu'
+require 'dcpu16/version'
+
+module DCPU16
+end
+

data/spec/integration/example1_spec.rb

@@ -0,0 +1,28 @@
+require 'spec_helper.rb'
+
+describe DCPU16::CPU do
+  describe "quick example by notch" do
+    let(:dump) do
+      [ 0x7c01, 0x0030, 0x7de1, 0x1000, 0x0020, 0x7803, 0x1000, 0xc00d,
+        0x7dc1, 0x001a, 0xa861, 0x7c01, 0x2000, 0x2161, 0x2000, 0x8463,
+        0x806d, 0x7dc1, 0x000d, 0x9031, 0x7c10, 0x0018, 0x7dc1, 0x001a,
+        #0x9037, 0x61c1, 0x7dc1, 0x001a, 0x0000, 0x0000, 0x0000, 0x0000 ]
+        0x9037, 0x61c1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 ]
+    end
+
+    subject { DCPU16::CPU.new(dump) }
+
+    # Just double-check that memory is loaded
+    specify { subject.memory.read(0x0).value.should == 0x7c01 }
+#    specify { subject.memory.read(0x1b).value.should == 0x001a }
+
+    specify do
+      expect { subject.run }.to raise_error
+
+      subject.cycle.should == 104
+      subject.A.value.should == 0x2000
+      subject.X.value.should == 0x40
+    end
+  end
+end
+

data/spec/spec_helper.rb

@@ -0,0 +1,2 @@
+require 'dcpu16'
+

data/spec/unit/dcpu16_cpu_spec.rb

@@ -0,0 +1,45 @@
+require 'spec_helper.rb'
+require 'unit/support/sample_observer'
+
+describe DCPU16::CPU do
+  # Initialize with non failing memory dump
+  subject { DCPU16::CPU.new( Array.new(10000, 0x01) ) }
+
+  describe "Register" do
+    its(:registers) { subject.length == 8 }
+    its(:registers) { subject[0] == be_kind_of(DCPU16::Register) }
+
+    its(:PC) { should be_kind_of(DCPU16::Register) }
+    its(:SP) { should be_kind_of(DCPU16::Register) }
+    its(:O)  { should be_kind_of(DCPU16::Register) }
+  end
+
+  its(:cycle) { should == 0 }
+  its(:memory) { should be_kind_of(DCPU16::Memory) }
+
+
+  describe "#reset" do
+    it "resets its #cycle" do
+      subject.cycle = 2
+      subject.reset
+      subject.cycle.should == 0
+    end
+    it "resets its #memory" do
+      subject.memory.should_receive(:reset)
+      subject.reset
+    end
+    it "resets its #registers" do
+      subject.registers.each { |register| register.should_receive(:reset) }
+      subject.reset
+    end
+  end
+
+  describe "Observable" do
+    let(:observer) { DCPU16::SampleObserver.new }
+    specify do
+      subject.add_observer(observer)
+      expect { subject.step }.to change{observer.cycle}.by(1)
+    end
+  end
+end
+

data/spec/unit/dcpu16_instruction_spec.rb

@@ -0,0 +1,28 @@
+require 'spec_helper.rb'
+
+describe DCPU16::Instruction do
+  context "when initialized with 0x00" do
+    let(:word) { DCPU16::Word.new(0x00) }
+    subject { DCPU16::Instruction.new(word) }
+    its(:opcode) { should == 0 }
+    its(:a) { should == 0 }
+    its(:b) { should be_nil }
+  end
+
+  context "when initialized with 0x0001" do
+    let(:word) { DCPU16::Word.new(0x0001) }
+    subject { DCPU16::Instruction.new(word) }
+    its(:opcode) { should == 1 }
+    its(:a) { should == 0 }
+    its(:b) { should == 0 }
+  end
+
+  context "when initialized with 0xa861" do
+    let(:word) { DCPU16::Word.new(0xa861) }
+    subject { DCPU16::Instruction.new(word) }
+    its(:opcode) { should == 1 }
+    its(:a) { should == 0x6 }
+    its(:b) { should == 0xa + 0x20 } # Literal value (offset += 0x20)
+  end
+end
+

data/spec/unit/dcpu16_instructions_spec.rb

@@ -0,0 +1,255 @@
+require 'spec_helper.rb'
+
+describe DCPU16::Instructions do
+  subject { DCPU16::CPU.new }
+  let(:a) { 0x01 }
+  let(:b) { 0x02 }
+
+
+  describe "#set" do
+    it "sets a to b" do
+      subject.set(a, b).should == b
+    end
+    it "take 1 cycle, plus the cost of a and b" do
+      expect { subject.set(a, b) }.to change{subject.cycle}.by(1)
+    end
+  end
+
+
+  describe "#add" do
+    it "sets a to a+b" do
+      subject.add(2, 3).should == 5
+    end
+    context "with overflow" do
+      it "sets O to 0x0001" do
+        subject.add(0xFFFE, 2)
+        subject.O.value.should == 0x0001
+      end
+    end
+    context "without overflow" do
+      it "sets O to 0x0" do
+        subject.add(0xFFFE, 1)
+        subject.O.value.should == 0x0
+      end
+    end
+    it "take 2 cycles, plus the cost of a and b" do
+      expect { subject.add(a, b) }.to change{subject.cycle}.by(2)
+    end
+  end
+
+
+  describe "#sub" do
+    it "sets a to a-b" do
+      subject.sub(3, 2).should == 1
+    end
+    context "with underflow" do
+      it "set O to 0xffff" do
+        subject.sub(2, 3)
+        subject.O.value.should == 0xffff
+      end
+    end
+    context "without underflow" do
+      it "set O to 0x0" do
+        subject.sub(2, 2)
+        subject.O.value.should == 0x0
+      end
+    end
+    it "take 2 cycles, plus the cost of a and b" do
+      expect { subject.sub(a, b) }.to change{subject.cycle}.by(2)
+    end
+  end
+
+
+  describe "#mul" do
+    it "sets a to a*b" do
+      subject.mul(2, 3).should == 6
+    end
+    it "sets O to ((a*b)>>16)&0xffff" do
+      subject.mul(256, 256)
+      subject.O.value.should == ((256*256)>>16) & 0xFFFF
+    end
+    it "take 2 cycles, plus the cost of a and b" do
+      expect { subject.mul(a, b) }.to change{subject.cycle}.by(2)
+    end
+  end
+
+
+  describe "#div" do
+    it "sets a to a/b" do
+      subject.div(9, 3).should == 3
+      subject.div(8, 3).should == 2
+    end
+    context "when b != 0" do
+      it "sets O to ((a<<16)/b)&0xffff" do
+        subject.div(1, 2)
+        subject.O.value.should == ((1 << 16)/2) & 0xFFFF
+      end
+    end
+    context "when b == 0" do
+      it "sets a and O to 0" do
+        subject.div(3, 0).should == 0
+        subject.O.value.should == 0
+      end
+    end
+    it "take 3 cycles, plus the cost of a and b" do
+      expect { subject.div(a, b) }.to change{subject.cycle}.by(3)
+    end
+  end
+
+
+  describe "#mod" do
+    context "when b != 0" do
+      it "sets a to a % b" do
+        subject.mod(3, 2).should == 1
+      end
+    end
+    context "when b == 0" do
+      it "sets a to 0" do
+        subject.mod(3, 0).should == 0
+      end
+    end
+    it "take 3 cycles, plus the cost of a and b" do
+      expect { subject.mod(a, b) }.to change{subject.cycle}.by(3)
+    end
+  end
+
+
+  describe "#shl" do
+    it "sets a to a<<b" do
+      subject.shl(4, 2).should == 16
+    end
+    it "sets O to ((a<<b)>>16)&0xffff" do
+      subject.shl(1, 17)
+      subject.O.value.should == ((1 << 17) >> 16)&0xffff
+    end
+    it "take 2 cycles, plus the cost of a and b" do
+      expect { subject.shl(a, b) }.to change{subject.cycle}.by(2)
+    end
+  end
+
+
+  describe "#shr" do
+    it "sets a to a>>b" do
+      subject.shr(4, 2).should == 1
+    end
+    it "sets O to ((a<<16)>>b)&0xffff" do
+      subject.shr(2, 2)
+      subject.O.value.should == ((2 << 16) >> 2) & 0xffff
+    end
+    it "take 2 cycles, plus the cost of a and b" do
+      expect { subject.shr(a, b) }.to change{subject.cycle}.by(2)
+    end
+  end
+
+
+  describe "#and" do
+    it "sets a to a&b" do
+      subject.and(1, 2).should == 0
+      subject.and(1, 3).should == 1
+    end
+    it "take 1 cycles, plus the cost of a and b" do
+      expect { subject.and(a, b) }.to change{subject.cycle}.by(1)
+    end
+  end
+
+
+  describe "#bor" do
+    it "sets a to a|b" do
+      subject.bor(1, 2).should == 3
+    end
+    it "take 1 cycles, plus the cost of a and b" do
+      expect { subject.bor(a, b) }.to change{subject.cycle}.by(1)
+    end
+  end
+
+
+  describe "#xor" do
+    it "sets a to a^b" do
+      subject.xor(1, 3).should == 2
+    end
+    it "take 1 cycles, plus the cost of a and b" do
+      expect { subject.xor(a, b) }.to change{subject.cycle}.by(1)
+    end
+  end
+
+
+  describe "#ife" do
+    it "performs next instruction only if a==b" do
+      subject.ife(1, 1)
+      subject.skip.should be_false
+      subject.ife(1, 2)
+      subject.skip.should be_true
+    end
+    context "if test passes" do
+      it "take 2 cycles, plus the cost of a and b" do
+        expect { subject.ife(2, 2) }.to change{subject.cycle}.by(2)
+      end
+    end
+    context "if test fails" do
+      it "take 3 cycles, plus the cost of a and b" do
+        expect { subject.ife(2, 3) }.to change{subject.cycle}.by(3)
+      end
+    end
+  end
+
+
+  describe "#ifn" do
+    it "performs next instruction only if a!=b" do
+      subject.ifn(1, 1)
+      subject.skip.should be_true
+      subject.ifn(1, 2)
+      subject.skip.should be_false
+    end
+    context "if test passes" do
+      it "take 2 cycles, plus the cost of a and b" do
+        expect { subject.ifn(1, 2) }.to change{subject.cycle}.by(2)
+      end
+    end
+    context "if test fails" do
+      it "take 3 cycles, plus the cost of a and b" do
+        expect { subject.ifn(2, 2) }.to change{subject.cycle}.by(3)
+      end
+    end
+  end
+
+
+  describe "#ifg" do
+    it "performs next instruction only if a > b" do
+      subject.ifg(1, 2)
+      subject.skip.should be_true
+      subject.ifg(2, 1)
+      subject.skip.should be_false
+    end
+    context "if test passes" do
+      it "take 2 cycles, plus the cost of a and b" do
+        expect { subject.ifg(3, 2) }.to change{subject.cycle}.by(2)
+      end
+    end
+    context "if test fails" do
+      it "take 3 cycles, plus the cost of a and b" do
+        expect { subject.ifg(2, 3) }.to change{subject.cycle}.by(3)
+      end
+    end
+  end
+
+
+  describe "#ifb" do
+    it "performs next instruction only if (a&b)!=0" do
+      subject.ifb(1, 3)
+      subject.skip.should be_false
+      subject.ifb(1, 2)
+      subject.skip.should be_true
+    end
+    context "if test passes" do
+      it "take 2 cycles, plus the cost of a and b" do
+        expect { subject.ifb(1, 3) }.to change{subject.cycle}.by(2)
+      end
+    end
+    context "if test fails" do
+      it "take 3 cycles, plus the cost of a and b" do
+        expect { subject.ifb(1, 2) }.to change{subject.cycle}.by(3)
+      end
+    end
+  end
+end
+

data/spec/unit/dcpu16_memory_spec.rb

@@ -0,0 +1,16 @@
+require 'spec_helper.rb'
+
+describe DCPU16::Memory do
+  its(:length) { should == 0x10000 }
+
+  describe "#read" do
+    specify { subject.read(0).should be_a_kind_of(DCPU16::Word) }
+  end
+
+
+  specify "#write" do
+    subject.write(0x1000, 42)
+    subject.read(0x1000).value.should == 42
+  end
+end
+

data/spec/unit/dcpu16_operand_spec.rb

@@ -0,0 +1,78 @@
+require 'spec_helper.rb'
+
+describe DCPU16::Instructions do
+  let(:cpu) { DCPU16::CPU.new }
+
+  context "when value is between 0x00 and 0x07" do
+    specify { DCPU16::Operand.new(cpu, 0x0).should == cpu.A }
+    specify { DCPU16::Operand.new(cpu, 0x1).should == cpu.B }
+    specify { DCPU16::Operand.new(cpu, 0x2).should == cpu.C }
+    specify { DCPU16::Operand.new(cpu, 0x3).should == cpu.X }
+    specify { DCPU16::Operand.new(cpu, 0x4).should == cpu.Y }
+    specify { DCPU16::Operand.new(cpu, 0x5).should == cpu.Z }
+    specify { DCPU16::Operand.new(cpu, 0x6).should == cpu.I }
+    specify { DCPU16::Operand.new(cpu, 0x7).should == cpu.J }
+  end
+
+  context "when value is between 0x08 and 0x17" do
+    before(:all) do
+      cpu.memory.write(0x1000, 0x2a)
+      cpu.registers.each { |r| r.write(0x1000) }
+    end
+
+    specify { DCPU16::Operand.new(cpu, 0x8).value.should == 0x2a }
+    specify { DCPU16::Operand.new(cpu, 0xF).value.should == 0x2a }
+  end
+
+
+  context "when value is between 0x10 and 0x17" do
+    pending
+  end
+
+  context "when value is 0x18" do
+    pending
+  end
+
+  context "when value is 0x19" do
+    pending
+  end
+
+  context "when value is 0x1A" do
+    pending
+  end
+
+  context "when value is 0x1B" do
+    pending
+  end
+
+  context "when value is 0x1C" do
+    pending
+  end
+
+  context "when value is 0x1D" do
+    pending
+  end
+
+  context "when value is 0x1E" do
+    pending
+  end
+
+  context "when value is 0x1F" do
+    pending
+  end
+
+  context "when value is between 0x20 and 0x3f" do
+    specify { DCPU16::Operand.new(cpu, 0x20).should be_a_kind_of(DCPU16::Literal) }
+    specify { DCPU16::Operand.new(cpu, 0x20).value.should == 0x0 }
+    specify { DCPU16::Operand.new(cpu, 0x3f).value.should == 0x1f }
+  end
+
+  context "when value is > 0x3f" do
+    specify do
+      expect {
+        DCPU16::Operand.new(cpu, 0x40)
+      }.to raise_error(DCPU16::Operand::NotFound)
+    end
+  end
+end
+

data/spec/unit/dcpu16_register_spec.rb

@@ -0,0 +1,6 @@
+require 'spec_helper.rb'
+
+describe DCPU16::Register do
+  subject { DCPU16::Register.new(0x00) }
+end
+

data/spec/unit/dcpu16_word_spec.rb

@@ -0,0 +1,17 @@
+require 'spec_helper.rb'
+
+describe DCPU16::Word do
+  let(:memory) { DCPU16::Memory.new }
+  subject { DCPU16::Word.new(2, memory, 0) }
+
+  specify { subject.should be_a_kind_of(DCPU16::Word) }
+  its(:value) { should == 2 }
+  its(:read)  { should == 2 }
+
+  describe "#write" do
+    before { subject.write(42) }
+    its(:value) { should == 42 }
+    specify { memory.read(0).value.should == 42 }
+  end
+end
+

data/spec/unit/support/sample_observer.rb

@@ -0,0 +1,14 @@
+module DCPU16
+  class SampleObserver
+    attr_reader :cycle
+
+    def initialize
+      @cycle = 0
+    end
+
+    def update(cpu)
+      @cycle = cpu.cycle
+    end
+  end
+end
+

metadata

@@ -0,0 +1,90 @@
+--- !ruby/object:Gem::Specification
+name: Rdcpu16
+version: !ruby/object:Gem::Version
+  version: 0.0.1
+  prerelease: 
+platform: ruby
+authors:
+- Patrick Helm
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2012-04-09 00:00:00.000000000 Z
+dependencies:
+- !ruby/object:Gem::Dependency
+  name: rspec
+  requirement: &74148950 !ruby/object:Gem::Requirement
+    none: false
+    requirements:
+    - - ~>
+      - !ruby/object:Gem::Version
+        version: '2.6'
+  type: :development
+  prerelease: false
+  version_requirements: *74148950
+description: This is a simple Ruby port of the fictive 16-bit-cpu DCPU16.
+email:
+- deradon87@gmail.com
+executables: []
+extensions: []
+extra_rdoc_files: []
+files:
+- lib/dcpu16/cpu.rb
+- lib/dcpu16/operand.rb
+- lib/dcpu16/memory.rb
+- lib/dcpu16/word.rb
+- lib/dcpu16/version.rb
+- lib/dcpu16/cpu/instructions.rb
+- lib/dcpu16/support/debug.rb
+- lib/dcpu16/literal.rb
+- lib/dcpu16/instruction.rb
+- lib/dcpu16/register.rb
+- lib/dcpu16.rb
+- MIT-LICENSE
+- Rakefile
+- README.rdoc
+- spec/integration/example1_spec.rb
+- spec/unit/dcpu16_word_spec.rb
+- spec/unit/support/sample_observer.rb
+- spec/unit/dcpu16_register_spec.rb
+- spec/unit/dcpu16_cpu_spec.rb
+- spec/unit/dcpu16_memory_spec.rb
+- spec/unit/dcpu16_instructions_spec.rb
+- spec/unit/dcpu16_operand_spec.rb
+- spec/unit/dcpu16_instruction_spec.rb
+- spec/spec_helper.rb
+homepage: https://github.com/Deradon/Rdcpu16
+licenses: []
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  none: false
+  requirements:
+  - - ! '>='
+    - !ruby/object:Gem::Version
+      version: '0'
+required_rubygems_version: !ruby/object:Gem::Requirement
+  none: false
+  requirements:
+  - - ! '>='
+    - !ruby/object:Gem::Version
+      version: '0'
+requirements: []
+rubyforge_project: 
+rubygems_version: 1.8.10
+signing_key: 
+specification_version: 3
+summary: Ruby port of DCPU16
+test_files:
+- spec/integration/example1_spec.rb
+- spec/unit/dcpu16_word_spec.rb
+- spec/unit/support/sample_observer.rb
+- spec/unit/dcpu16_register_spec.rb
+- spec/unit/dcpu16_cpu_spec.rb
+- spec/unit/dcpu16_memory_spec.rb
+- spec/unit/dcpu16_instructions_spec.rb
+- spec/unit/dcpu16_operand_spec.rb
+- spec/unit/dcpu16_instruction_spec.rb
+- spec/spec_helper.rb