Opcodes 1.3.0

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data/LICENSE.README ADDED
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+ The Opcodes Ruby extension is released under the GNU Public License version 3.0,
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+ distributed in this package as LICENSE.
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+
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+ The intent of this license choice is not to restrict distribution, but for
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+ compatibility with the distribution terms of opdis and GNU binutils.
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+
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+ Contact community@thoughtgang.org for alternative licensing arrangements if
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+ the GPLv3 is too restrictive.
data/README ADDED
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+ Opcodes
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+
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+ A Ruby C extension (and gem) for the GNU Binutils libopcodes library.
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+
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+ BUILD
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+ -----
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+
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+ The standard C extension build process is used:
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+
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+ bash# ruby extconf.rb
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+ bash# make
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+
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+ Note that the Ruby headers must be installed. On Ubuntu, these are in the
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+ ruby-dev or ruby1.9-dev package.
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+
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+
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+ The gem is built using the standard gem build command:
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+
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+ bash# gem build Opcodes.gemspec
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+
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+
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+ The top-level Makefile supports each of these builds with the commands
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+ 'make' and 'make gem'.
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+
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+ bash# make
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+ # builds C extension
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+ bash# make gem
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+ # builds the gem
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+
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+
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+ BINUTILS AND SUPPORTED ARCHITECTURES
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+ ------------------------------------
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+
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+ The implementation of binutils (and libopcodes) does not provide a way to
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+ determine the supported platforms at compile time, unless the config.h file
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+ used to build the binutils package is present.
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+
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+ The extconf.rb file has been modified in order to detect the architectures
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+ supported by the local copy of binutils, and to allow the user to specify
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+ which architectures they want supported.
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+
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+ It does this using the following steps:
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+
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+ 1. run objdump -i to get the supported architectures
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+ 2. each line that matches one of binutils' known architectures is
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+ added as a #define to CPPFLAGS
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+ 3. if no architectures have been found, or if objdump failed to run,
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+ default to the i386 architecture.
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+
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+ The binary used in step 1 can be specified by the user via the --with-objdump
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+ flag. For example:
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+
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+ bash# cat /tmp/objdump.sh
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+ #/bin/sh
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+ echo 'arm'
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+ echo 'sparc'
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+ echo 'm68k'
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+ bash# ruby1.9 extconf.rb --with-objdump=/tmp/objdump.sh
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+ checking for init_disassemble_info() in -lopcodes... yes
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+ Adding architecture 'arm'
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+ Adding architecture 'sparc'
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+ Adding architecture 'm68k'
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+ creating Makefile
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+
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+ This makes it possible to force compilation of support for specific
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+ architectures when there is no working objdump present. Note that libopcodes
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+ must have been compiled with support for the architectures, or you will get
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+ runtime errors.
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+
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+
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+ EXAMPLES
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+
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+ Extended examples are provided in the 'examples' directory. The following
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+ code snippets give a brief overview of using the BFD and Opcodes extensions
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+ together.
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+
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+ require 'BFD'
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+ t = Bfd::Target.new('/tmp/a.out')
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+
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+ require 'Opcodes'
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+ o = Opcodes::Disassembler.new( :bfd => t, :arch => 'x86' )
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+ o.disasm_insn( t.sections['.text'].contents, :vma => 0 )
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+
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+
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+ o = Opcodes::Disassembler.new( :bfd => t )
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+ o.disasm_insn( t.sections['.text'].contents, :vma => 0 )
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+
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+
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+ #!/usr/bin/env ruby
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+ # Disassemble BFD Section
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+ # Copyright 2010 Thoughtgang <http://www.thoughtgang.org>
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+
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+ require 'BFD'
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+ require 'Opcodes'
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+
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+ def print_insn( insn )
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+ puts "%08X\t%s" % [ insn[:vma], insn[:insn].join(' ') ]
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+ end
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+
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+ def disasm_sections(filename, sections)
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+ # BFD for target file
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+ tgt = Bfd::Target.new(filename)
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+ puts "#{tgt.id}: #{tgt.filename}"
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+
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+ # Disassembler for BFD
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+ disasm = Opcodes::Disassembler.new( :bfd => tgt )
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+
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+ # Disassemble until end of buffer is reached
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+ sections.each do |name|
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+ sec = tgt.sections[name]
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+ raise "Section #{name} not in #{tgt.filename}" if not sec
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+
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+ disasm.disasm(sec).each { |i| print_insn i }
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+ end
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+ end
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+
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+ if __FILE__ == $0
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+ raise "Usage: #{$0} FILE SECTION [SECTION...]" if ARGV.length < 2
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+ filename = ARGV.shift
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+
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+ disasm_sections(filename, ARGV)
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+ end
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+ #!/usr/bin/env ruby
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+ # Disassemble BFD Symbol
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+ # Copyright 2010 Thoughtgang <http://www.thoughtgang.org>
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+
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+ require 'BFD'
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+ require 'Opcodes'
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+
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+ def print_insn( insn )
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+ puts "%08X\t%s" % [ insn[:vma], insn[:insn].join(' ') ]
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+ end
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+
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+ def disasm_symbols(filename, symbols)
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+ # BFD for target file
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+ tgt = Bfd::Target.new(filename)
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+ puts "#{tgt.id}: #{tgt.filename}"
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+
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+ # Disassembler for BFD
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+ disasm = Opcodes::Disassembler.new( :bfd => tgt )
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+
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+ # Disassemble until end of buffer is reached
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+ symbols.each do |name|
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+ sym = tgt.symbols[name]
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+ raise "Symbol #{name} not in #{tgt.filename}" if not sym
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+
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+ disasm.disasm(sym).each { |i| print_insn i }
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+ end
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+ end
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+
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+ if __FILE__ == $0
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+ raise "Usage: #{$0} FILE SYMBOL [SYMBOL...]" if ARGV.length < 2
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+ filename = ARGV.shift
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+
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+ disasm_symbols(filename, ARGV)
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+ end
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+ #!/usr/bin/env ruby
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+ # List available architectures
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+ # Copyright 2010 Thoughtgang <http://www.thoughtgang.org>
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+
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+ require 'Opcodes'
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+
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+ if __FILE__ == $0
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+ puts "Supported architectures:"
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+ Opcodes::Disassembler.architectures.each { |a| puts "\t#{a}" }
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+ end
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+ #!/usr/bin/env ruby
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+ # Disassemble x86 Bytes
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+ # Copyright 2010 Thoughtgang <http://www.thoughtgang.org>
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+
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+ require 'Opcodes'
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+
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+ # print a disassembled instruction in standard disasm listing format
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+ def print_insn( insn, buf )
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+ # Unpack instruction bytes from binary string in buf
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+ bytes = buf.unpack('C' * buf.length)[insn[:vma]...(insn[:vma]+insn[:size])]
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+
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+ # Convert bytes to hex strings
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+ hex_str = bytes.collect { |b| "%02X" % b }.join(' ')
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+
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+ # Format as hexump, showing up to 8 bytes (8*2 hex + 8-1 spaces)
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+ puts "%08X %-23.23s %s" % [insn[:vma], hex_str, insn[:insn].join(' ')]
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+ end
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+
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+ # disassemble binary string using x86 architecture
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+ def disasm_bytes( bytes )
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+ # Disassembler for x86
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+ disasm = Opcodes::Disassembler.new( :arch => 'x86' )
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+
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+ # disassemble until end of buffer is reached
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+ pos = 0
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+ while ( pos < bytes.length )
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+ insn = disasm.disasm_insn( bytes, :vma => pos )
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+ print_insn insn, bytes
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+ pos += 1
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+ end
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+
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+ end
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+
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+ # Convert array of hex byte strings to a binary string
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+ def hex_to_bytes( bytes )
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+ bytes.collect { |b| b.hex }.pack( 'C' * bytes.length )
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+ end
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+
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+ if __FILE__ == $0
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+ raise "Usage: #{$0} BYTE [BYTE...]" if ARGV.length == 0
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+
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+ disasm_bytes( hex_to_bytes(ARGV) )
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+ end
data/lib/Opcodes.rb ADDED
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+ #!/usr/bin/env/ruby1.0
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+ # Copyright 2010 Thoughtgang <http://www.thoughtgang.org>
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+ # Ruby additions to the Opcodes module
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+
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+ require 'OpcodesExt'
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+
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+ module Opcodes
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+
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+ class Disassembler
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+
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+ =begin rdoc
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+ Create a new disassembler.
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+ Note: if the option :arch is not specified here or in Disassembler#disasm,
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+ the generic_print_address method will be used -- which only generates the
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+ VMA for an instruction.
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+ =end
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+ def self.new(args={})
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+ dis = ext_new(args)
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+ yield dis if block_given?
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+ dis
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+ end
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+
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+ =begin rdoc
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+ Disassemble all bytes in a buffer. This is simply a wrapper for ext_disasm
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+ that provides a default value for <i>args</i>.
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+ See ext_disasm.
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+ Note: the achhitecture of the target must be specified by the user if the
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+ target is not a BFD::Target. Failure to specify an architecture will
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+ result in instruction token arrays containing only the VMA of the
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+ instruction. See Disassemnbler#new for more info.
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+ =end
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+ def disasm( target, args={} )
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+ # Wrapper provides a default option
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+ raise "Invalid target" if not target
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+
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+ ext_disasm(target, args)
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+ end
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+
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+ =begin rdoc
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+ Disassemble a single instruction in a target buffer. This is simply a wrapper
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+ for ext_disasm_insn that provides a default value for <i>args</i>.
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+ See ext_disasm_insn.
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+ =end
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+ def disasm_insn( target, args={} )
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+ # Wrapper provides a default option
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+ raise "Invalid target" if not target
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+
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+ ext_disasm_insn(target, args)
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+ end
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+
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+ end
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+
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+ end
data/module/Arch.c ADDED
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+ /* Arch.c
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+ * Disassembler definitions for architectures supported by libopcodes
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+ * Copyright 2010 Thoughtgang <http://www.thoughtgang.org>
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+ * Written by TG Community Developers <community@thoughtgang.org>
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+ * Released under the GNU Public License, version 3.
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+ * See http://www.gnu.org/licenses/gpl.txt for details.
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+ */
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+ #include <string.h>
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+
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+ #include "Arch.h"
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+
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+ static int generic_print_address_wrapper(bfd_vma vma, disassemble_info *info ) {
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+ generic_print_address(vma, info);
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+ return 1;
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+ }
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+
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+ static const Opcodes_disasm_def disasm_definitions[] = {
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+ /* Goddamn GNU. They make it near-impossible to get a list of supported
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+ * architectures at build OR run time. */
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+ #ifdef ARCH_ALPHA
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+ {"alpha", bfd_arch_alpha, bfd_mach_alpha_ev4, print_insn_alpha},
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+ {"alphaev4", bfd_arch_alpha, bfd_mach_alpha_ev4,
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+ print_insn_alpha},
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+ {"alphaev5", bfd_arch_alpha, bfd_mach_alpha_ev5,
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+ print_insn_alpha},
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+ {"alphaev6", bfd_arch_alpha, bfd_mach_alpha_ev6,
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+ print_insn_alpha},
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+ #endif
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+ #ifdef ARCH_ARM
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+ {"big_arm", bfd_arch_arm, bfd_mach_arm_umknown,
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+ print_insn_big_arm},
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+ {"little_arm", bfd_arch_arm, bfd_mach_arm_unknown,
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+ print_insn_little_arm},
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+ // TODO: the other ARMs have to be big & little?
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+ #endif
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+ #ifdef ARCH_AVR
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+ {"avr", bfd_arch_avr, bfd_mach_avr1, print_insn_avr},
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+ {"avr1", bfd_arch_avr, bfd_mach_avr1, print_insn_avr},
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+ {"avr2", bfd_arch_avr, bfd_mach_avr2, print_insn_avr},
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+ {"avr25", bfd_arch_avr, bfd_mach_avr25, print_insn_avr},
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+ {"avr3", bfd_arch_avr, bfd_mach_avr3, print_insn_avr},
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+ {"avr31", bfd_arch_avr, bfd_mach_avr31, print_insn_avr},
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+ {"avr35", bfd_arch_avr, bfd_mach_avr35, print_insn_avr},
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+ {"avr4", bfd_arch_avr, bfd_mach_avr4, print_insn_avr},
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+ {"avr5", bfd_arch_avr, bfd_mach_avr5, print_insn_avr},
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+ {"avr51", bfd_arch_avr, bfd_mach_avr51, print_insn_avr},
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+ {"avr6", bfd_arch_avr, bfd_mach_avr6, print_insn_avr},
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+ #endif
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+ #ifdef ARCH_BFIN
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+ {"bfin", bfd_arch_bfin, bfd_mach_bfin, print_insn_bfin},
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+ #endif
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+
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+ #ifdef ARCH_CR16
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+ {"cr16", bfd_arch_cr16, bfd_mach_cr16, print_insn_cr16},
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+ {"cr16c", bfd_arch_cr16c, bfd_mach_cr16c, print_insn_cr16},
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+ #endif
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+ #ifdef ARCH_CRX
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+ {"crx", bfd_arch_crx, bfd_mach_crx, print_insn_crx},
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+ #endif
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+ #ifdef ARCH_D10V
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+ {"d10v", bfd_arch_d10v, bfd_mach_d10v, print_insn_d10v},
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+ {"d10v2", bfd_arch_d10v, bfd_mach_d10v_ts2, print_insn_d10v},
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+ {"d10v3", bfd_arch_d10v, bfd_mach_d10v_ts3, print_insn_d10v},
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+ #endif
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+ #ifdef ARCH_D30V
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+ {"d30v", bfd_arch_d30v, 0, print_insn_d30v},
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+ #endif
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+ #ifdef ARCH_DLX
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+ {"dlx", bfd_arch_dlx, 0, print_insn_dlx},
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+ #endif
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+ #ifdef ARCH_FR30
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+ {"fr30", bfd_arch_fr30, bfd_mach_fr30, print_insn_fr30},
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+ #endif
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+ #ifdef ARCH_FRV
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+ {"frv", bfd_arch_frv, bfd_mach_frv, print_insn_frv},
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+ {"frvsimple", bfd_arch_frv, bfd_mach_frvsimple, print_insn_frv},
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+ {"fr300", bfd_arch_frv, bfd_mach_fr300, print_insn_frv},
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+ {"fr400", bfd_arch_frv, bfd_mach_fr400, print_insn_frv},
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+ {"fr450", bfd_arch_frv, bfd_mach_fr450, print_insn_frv},
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+ {"frvtomcat", bfd_arch_frv, bfd_mach_frvtomcat, print_insn_frv},
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+ {"fr500", bfd_arch_frv, bfd_mach_fr500, print_insn_frv},
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+ {"fr550", bfd_arch_frv, bfd_mach_fr550, print_insn_frv},
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+ #endif
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+ #ifdef ARCH_H8300
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+ {"h8300", bfd_arch_8300, bfd_mach_h8300, print_insn_h8300},
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+ {"h8300h", bfd_arch_8300, bfd_mach_h8300h, print_insn_h8300h},
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+ {"h8300hn", bfd_arch_8300, bfd_mach_h8300hn, print_insn_h8300h},
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+ {"h8300s", bfd_arch_8300, bfd_mach_h8300s, print_insn_h8300s},
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+ {"h8300sn", bfd_arch_8300, bfd_mach_h8300sn, print_insn_h8300s},
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+ {"h8300sx", bfd_arch_8300, bfd_mach_h8300sx, print_insn_h8300s},
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+ {"h8300sxn", bfd_arch_8300, bfd_mach_h8300sxn,
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+ print_insn_h8300s},
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+ #endif
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+ #ifdef ARCH_H8500
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+ {"h8500", bfd_arch_h8500, 0, print_insn_h8500},
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+ #endif
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+ #ifdef ARCH_HPPA
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+ {"hppa", bfd_arch_hppa, bfd_mach_hppa10, print_insn_hppa},
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+ {"hppa11", bfd_arch_hppa, bfd_mach_hppa11, print_insn_hppa},
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+ {"hppa20", bfd_arch_hppa, bfd_mach_hppa20, print_insn_hppa},
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+ {"hppa20w", bfd_arch_hppa, bfd_mach_hppa20w, print_insn_hppa},
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+ #endif
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+ #ifdef ARCH_I370
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+ {"i370", bfd_arch_i370, 0, print_insn_i370},
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+ #endif
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+ #ifdef ARCH_I386
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+ {"8086", bfd_arch_i386, bfd_mach_i386_i8086, print_insn_i386},
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+ {"x86", bfd_arch_i386, bfd_mach_i386_i386, print_insn_i386},
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+ {"x86_att", bfd_arch_i386, bfd_mach_i386_i386,
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+ print_insn_i386_att},
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+ {"x86_intel", bfd_arch_i386, bfd_mach_i386_i386_intel_syntax,
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+ print_insn_i386_intel},
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+ {"x86_64", bfd_arch_i386, bfd_mach_x86_64, print_insn_i386},
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+ {"x86_64_att", bfd_arch_i386, bfd_mach_x86_64, print_insn_i386},
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+ {"x86_64_intel", bfd_arch_i386, bfd_mach_x86_64_intel_syntax,
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+ print_insn_i386},
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+ #endif
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+ #ifdef ARCH_i860
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+ {"i860", bfd_arch_i860, 0, print_insn_i860},
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+ #endif
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+ #ifdef ARCH_i960
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+ {"i960", bfd_arch_i960, bfd_mach_i960_core, print_insn_i960},
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+ {"i960_hx", bfd_arch_i960, bfd_mach_i960_hx, print_insn_i960},
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+ #endif
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+ #ifdef ARCH_ia64
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+ {"ia64", bfd_arch_ia64, bfd_mach_ia64_elf64, print_insn_ia64},
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+ {"ia64_32", bfd_arch_ia64, bfd_mach_ia64_elf32,
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+ print_insn_ia64},
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+ #endif
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+ #ifdef ARCH_IP2K
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+ {"ip2k", bfd_arch_ip2k, bfd_mach_ip2022, print_insn_ip2k},
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+ {"ip2kext", bfd_arch_ip2k, bfd_mach_ip2022ext, print_insn_ip2k},
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+ #endif
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+ #ifdef ARCH_IQ2000
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+ {"iq2000", bfd_arch_iq2000, bfd_mach_iq2000, print_insn_iq2000},
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+ {"iq10", bfd_arch_iq2000, bfd_mach_iq10, print_insn_iq2000},
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+ #endif
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+ #ifdef ARCH_LM32
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+ {"lm32", bfd_arch_lm32, bfd_mach_lm32, print_insn_lm32},
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+ #endif
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+ #ifdef ARCH_M32C
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+ {"m32c", bfd_arch_m32c, bfd_mach_m32c, print_insn_m32c},
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+ {"m16c", bfd_arch_m32c, bfd_mach_m16c, print_insn_m32c},
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+ #endif
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+ #ifdef ARCH_M32R
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+ {"m32r", bfd_arch_m32r, bfd_mach_m32r, print_insn_m32r},
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+ {"m32rx", bfd_arch_m32r, bfd_mach_m32rx, print_insn_m32r},
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+ {"m32r2", bfd_arch_m32r, bfd_mach_m32r2, print_insn_m32r},
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+ #endif
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+ #ifdef ARCH_M68HC11
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+ {"m68hc11", bfd_arch_m68hc11, 0, print_insn_m68hc11},
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+ #endif
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+ #ifdef ARCH_M68HC12
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+ {"m68hc12", bfd_arch_m68hc12, bfd_mach_m6812_default,
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+ print_insn_m68hc12},
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+ {"m68hc12s", bfd_arch_m68hc12, bfd_mach_m6812s,
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+ print_insn_m68hc12},
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+ #endif
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+ #ifdef ARCH_M68K
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+ {"m68k", bfd_arch_m68k, bfd_mach_m68000, print_insn_m68k},
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+ {"m68008", bfd_arch_m68k, bfd_mach_m68008, print_insn_m68k},
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+ {"m68010", bfd_arch_m68k, bfd_mach_m68010, print_insn_m68k},
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+ {"m68020", bfd_arch_m68k, bfd_mach_m68020, print_insn_m68k},
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+ {"m68030", bfd_arch_m68k, bfd_mach_m68030, print_insn_m68k},
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+ {"m68040", bfd_arch_m68k, bfd_mach_m68040, print_insn_m68k},
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+ {"m68060", bfd_arch_m68k, bfd_mach_m68060, print_insn_m68k},
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+ {"m68060", bfd_arch_m68k, bfd_mach_m68060, print_insn_m68k},
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+ {"m68k_cpu32", bfd_arch_m68k, bfd_mach_cpu32, print_insn_m68k},
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+ {"m68k_fido", bfd_arch_m68k, bfd_mach_fido, print_insn_m68k},
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+ #endif
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+ #ifdef ARCH_M88K
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+ {"m88k", bfd_arch_m88k, 0, print_insn_m88k},
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+ #endif
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+ #ifdef ARCH_MAXQ
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+ {"maxq_big", bfd_arch_maxq, 0, print_insn_maxq_big},
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+ {"maxq_little", bfd_arch_maxq, 0, print_insn_maxq_little},
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+ {"maxq10_big", bfd_arch_maxq, bfd_mach_maxq10,
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+ print_insn_maxq_big},
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+ {"maxq10_little", bfd_arch_maxq, bfd_mach_maxq10,
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+ print_insn_maxq_little},
181
+ {"maxq20_big", bfd_arch_maxq, bfd_mach_maxq20,
182
+ print_insn_maxq_big},
183
+ {"maxq20_little", bfd_arch_maxq, bfd_mach_maxq20,
184
+ print_insn_maxq_little},
185
+ #endif
186
+ #ifdef ARCH_MCORE
187
+ {"mcore", bfd_arch_mcore, 0, print_insn_mcore},
188
+ #endif
189
+ #ifdef ARCH_MEP
190
+ {"mep", bfd_arch_mep, 0, print_insn_mep},
191
+ #endif
192
+ #ifdef ARCH_MICROBLAZE
193
+ {"microblaze", bfd_arch_microblaze, print_insn_microblaze},
194
+ #endif
195
+ #ifdef ARCH_MIPS
196
+ {"big_mips", bfd_arch_mips, 0, print_insn_big_mips},
197
+ {"little_mips", bfd_arch_mips, 0, print_insn_little_mips},
198
+ #endif
199
+ #ifdef ARCH_MMIX
200
+ {"mmix", bfd_arch_mmix, 0, print_insn_mmix},
201
+ #endif
202
+ #ifdef ARCH_MN10200
203
+ {"mn10200", bfd_arch_mn10200, 0, print_insn_mn10200},
204
+ #endif
205
+ #ifdef ARCH_MN10300
206
+ {"mn10300", bfd_arch_mn10300, bfd_mach_mn10300,
207
+ print_insn_mn10300},
208
+ #endif
209
+ #ifdef ARCH_MOXIE
210
+ {"moxie", bfd_arch_moxie, bfd_mach_moxie, print_insn_moxie},
211
+ #endif
212
+ #ifdef ARCH_MSP430
213
+ {"msp430", bfd_arch_msp430, 0, print_insn_msp430},
214
+ #endif
215
+ #ifdef ARCH_MT
216
+ {"mt", bfd_arch_mt, 0, print_insn_mt},
217
+ #endif
218
+ #ifdef ARCH_NS32K
219
+ {"ns32k", bfd_arch_ns32k, 0, print_insn_ns32k},
220
+ #endif
221
+ #ifdef ARCH_OPENRISC
222
+ {"openrisc", bfd_arch_openrisc, 0, print_insn_openrisc},
223
+ #endif
224
+ #ifdef ARCH_OR32
225
+ {"big_or32", bfd_arch_or32, 0, print_insn_big_or32},
226
+ {"little_or32", bfd_arch_or32, 0, print_insn_little_or32},
227
+ #endif
228
+ #ifdef ARCH_PDP11
229
+ {"pdp11", bfd_arch_pdp11, 0, print_insn_pdp11},
230
+ #endif
231
+ #ifdef ARCH_PJ
232
+ {"pj", bfd_arch_pj, 0, print_insn_pj},
233
+ #endif
234
+ #ifdef ARCH_POWERPC
235
+ {"big_powerpc", bfd_arch_powerpc, 0, print_insn_big_powerpc},
236
+ {"little_powerpc", bfd_arch_powerpc, 0,
237
+ print_insn_little_powerpc},
238
+ {"big_powerpc32", bfd_arch_powerpc, bfd_mach_ppc,
239
+ print_insn_big_powerpc},
240
+ {"little_powerpc32", bfd_arch_powerpc, bfd_mach_ppc,
241
+ print_insn_little_powerpc},
242
+ {"big_powerpc64", bfd_arch_powerpc, bfd_mach_ppc64,
243
+ print_insn_big_powerpc},
244
+ {"little_powerpc64", bfd_arch_powerpc, bfd_mach_ppc64,
245
+ print_insn_little_powerpc},
246
+ #endif
247
+ #ifdef ARCH_RS6000
248
+ {"rs6000", bfd_arch_rs6000, bfd_mach_rs6k, print_insn_rs6000},
249
+ #endif
250
+ #ifdef ARCH_S390
251
+ {"s390", bfd_arch_s390, 0, print_insn_s390},
252
+ #endif
253
+ #ifdef ARCH_SCORE
254
+ {"big_score", bfd_arch_score, 0, print_insn_big_score},
255
+ {"little_score", bfd_arch_score, 0, print_insn_little_score},
256
+ #endif
257
+ #ifdef ARCH_SH
258
+ {"sh", bfd_arch_sh, bfd_mach_sh, print_insn_sh},
259
+ {"sh2", bfd_arch_sh, bfd_mach_sh2, print_insn_sh},
260
+ {"sh3", bfd_arch_sh, bfd_mach_sh3, print_insn_sh},
261
+ {"sh4", bfd_arch_sh, bfd_mach_sh4, print_insn_sh},
262
+ {"sh5", bfd_arch_sh, bfd_mach_sh5, print_insn_sh},
263
+ {"sh_dsp", bfd_arch_sh, bfd_mach_sh_dsp, print_insn_sh},
264
+ {"sh64", bfd_arch_sh, bfd_mach_sh, print_insn_sh64},
265
+ {"sh64x_media", bfd_mach_sh, bfd_mach_sh,
266
+ print_insn_sh64x_media},
267
+ #endif
268
+ #ifdef ARCH_SPARC
269
+ {"sparc", bfd_arch_sparc, bfd_mach_sparc, print_insn_sparc},
270
+ {"sparclite", bfd_arch_sparc, bfd_mach_sparc_sparclite,
271
+ print_insn_sparc},
272
+ {"sparclitev9", bfd_arch_sparc, bfd_mach_sparc_v9,
273
+ print_insn_sparc},
274
+ #endif
275
+ #ifdef ARCH_SPU
276
+ {"spu", bfd_arch_spu, bfd_mach_spu, print_insn_spu},
277
+ #endif
278
+ #ifdef ARCH_TIC30
279
+ {"tic30", bfd_arch_tic30, 0, print_insn_tic30},
280
+ #endif
281
+ #ifdef ARCH_TIC4X
282
+ {"tic3x", bfd_arch_tic4x, bfd_mach_tic3x, print_insn_tic4x},
283
+ {"tic4x", bfd_arch_tic4x, bfd_mach_tic4x, print_insn_tic4x},
284
+ #endif
285
+ #ifdef ARCH_TIC54X
286
+ {"tic54x", bfd_arch_tic54x, 0, print_insn_tic54x},
287
+ #endif
288
+ #ifdef ARCH_TIC80
289
+ {"tic80", bfd_arch_tic80, 0, print_insn_tic80},
290
+ #endif
291
+ #ifdef ARCH_V850
292
+ {"v850", bfd_arch_v850, bfd_mach_v850, print_insn_v850},
293
+ #endif
294
+ #ifdef ARCH_VAX
295
+ {"vax", bfd_arch_vax, 0, print_insn_vax},
296
+ #endif
297
+ #ifdef ARCH_W65
298
+ {"w65", bfd_arch_w65, 0, print_insn_w65},
299
+ #endif
300
+ #ifdef ARCH_XC16X
301
+ {"xc16x", bfd_arch_xc16x, bfd_mach_xc16x, print_insn_xc16x},
302
+ #endif
303
+ #ifdef ARCH_XSTORMY16
304
+ {"xstormy16", bfd_arch_xstormy16, bfd_mach_xstormy16,
305
+ print_insn_xstormy16},
306
+ #endif
307
+ #ifdef ARCH_XTENSA
308
+ {"xtensa", bfd_arch_xtensa, bfd_mach_xtensa, print_insn_xtensa},
309
+ #endif
310
+ #ifdef ARCH_Z80
311
+ {"z80", bfd_arch_z80, bfd_mach_z80full, print_insn_z80},
312
+ {"z80strict", bfd_arch_z80, bfd_mach_z80strict, print_insn_z80},
313
+ {"r800", bfd_arch_z80, bfd_mach_r800, print_insn_z80},
314
+ #endif
315
+ #ifdef ARCH_Z8K
316
+ {"z8001", bfd_arch_z8k, bfd_mach_z8001, print_insn_z8001},
317
+ {"z8002", bfd_arch_z8k, bfd_mach_z8002, print_insn_z8002},
318
+ #endif
319
+ /* NULL entry to ensure table ends up ok */
320
+ {"INVALID", bfd_arch_unknown, 0, generic_print_address_wrapper}
321
+ };
322
+
323
+ void Opcodes_disasm_iter( OPCODES_DISASM_ITER_FN fn, void * arg ) {
324
+ int i;
325
+ int num_defs = sizeof(disasm_definitions) / sizeof(Opcodes_disasm_def);
326
+
327
+ if (! fn ) {
328
+ return;
329
+ }
330
+
331
+ for ( i = 0; i < num_defs; i++ ) {
332
+ const Opcodes_disasm_def *def = &disasm_definitions[i];
333
+ if (! fn( def, arg ) ) {
334
+ break;
335
+ }
336
+ }
337
+ }
338
+
339
+ struct disasm_find_name_arg {
340
+ const char * name;
341
+ const Opcodes_disasm_def * def;
342
+ };
343
+
344
+ static int is_named_def( const Opcodes_disasm_def * def, void * arg ) {
345
+ struct disasm_find_name_arg * out = (struct disasm_find_name_arg *) arg;
346
+ if (! strcmp( out->name, def->name ) ) {
347
+ out->def = def;
348
+ return 0;
349
+ }
350
+
351
+ return 1;
352
+ }
353
+
354
+ const Opcodes_disasm_def * Opcodes_disasm_for_name( const char * name ) {
355
+ struct disasm_find_name_arg arg = { name, Opcodes_disasm_invalid() };
356
+ Opcodes_disasm_iter( is_named_def, &arg );
357
+ return arg.def;
358
+ }
359
+
360
+ const Opcodes_disasm_def * Opcodes_disasm_invalid( void ) {
361
+ int num_defs = sizeof(disasm_definitions) / sizeof(Opcodes_disasm_def);
362
+ return &disasm_definitions[num_defs-1];
363
+ }
364
+