HDLRuby 2.1.5 → 2.1.6
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- checksums.yaml +4 -4
- data/lib/HDLRuby/hdrcc.rb +3 -1
- data/lib/HDLRuby/hruby_low.rb +14 -1
- data/lib/HDLRuby/hruby_verilog.rb +108 -29
- data/lib/HDLRuby/version.rb +1 -1
- metadata +2 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 9a13c2fd9d9add1fb436eeca3bd6ce2e58975ab2de842573fe6a260a74e6a901
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data.tar.gz: 04f16871ee7993c16b2419a691308a7ad235b487406ca9243085bcdcff1db8aa
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: ff99ac90a5f6bcc09896189f9e77f01e5394446efa8a6687f07d710528973ddf4d5397d5163889c9dc18425805f4a61adc30b56d686a9e6187c7b15a423990b4
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7
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data.tar.gz: 5cfaa77758b3b15154ebf139fb7bd9f424e41d72c7bd642895dfb6b3929b04f889dba320f4141b55ef554996e28cbd8d5072d7ac7242a395a993cff77d3c2835
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data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -8,6 +8,7 @@ require 'HDLRuby/hruby_low2high'
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8
8
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require 'HDLRuby/hruby_low2c'
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9
9
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require 'HDLRuby/hruby_low2vhd'
|
10
10
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require 'HDLRuby/hruby_low_fix_types'
|
11
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+
# require 'HDLRuby/hruby_low_expand_types' # For now dormant
|
11
12
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require 'HDLRuby/hruby_low_without_outread'
|
12
13
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require 'HDLRuby/hruby_low_with_bool'
|
13
14
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require 'HDLRuby/hruby_low_bool2select'
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@@ -573,7 +574,8 @@ elsif $options[:verilog] then
|
|
573
574
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$top_system.each_systemT_deep do |systemT|
|
574
575
|
systemT.to_upper_space!
|
575
576
|
systemT.to_global_systemTs!
|
576
|
-
systemT.break_types!
|
577
|
+
# systemT.break_types!
|
578
|
+
# systemT.expand_types!
|
577
579
|
systemT.with_port!
|
578
580
|
end
|
579
581
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# # Verilog generation
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data/lib/HDLRuby/hruby_low.rb
CHANGED
@@ -1553,6 +1553,16 @@ module HDLRuby::Low
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|
1553
1553
|
@base.equivalent?(type.base) )
|
1554
1554
|
end
|
1555
1555
|
|
1556
|
+
# Should not exists since it identifies types with multiple sub types.
|
1557
|
+
#
|
1558
|
+
# # Iterates over the sub types.
|
1559
|
+
# def each_type(&ruby_block)
|
1560
|
+
# # No ruby block? Return an enumerator.
|
1561
|
+
# return to_enum(:each_type) unless ruby_block
|
1562
|
+
# # A ruby block? Apply it on the base.
|
1563
|
+
# ruby_block.call(@base)
|
1564
|
+
# end
|
1565
|
+
|
1556
1566
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# Iterates over the types deeply if any.
|
1557
1567
|
def each_type_deep(&ruby_block)
|
1558
1568
|
# No ruby block? Return an enumerator.
|
@@ -3153,7 +3163,10 @@ module HDLRuby::Low
|
|
3153
3163
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|
3154
3164
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# Clones the Case (deeply)
|
3155
3165
|
def clone
|
3156
|
-
|
3166
|
+
# Clone the default if any.
|
3167
|
+
defaut = @default ? @default.clone : nil
|
3168
|
+
# Clone the case.
|
3169
|
+
return Case.new(@value.clone,default,(@whens.map do |w|
|
3157
3170
|
w.clone
|
3158
3171
|
end) )
|
3159
3172
|
end
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@@ -1301,6 +1301,21 @@ class RefRange
|
|
1301
1301
|
end
|
1302
1302
|
end
|
1303
1303
|
|
1304
|
+
# Use it when collecting references.
|
1305
|
+
class RefConcat
|
1306
|
+
def to_verilog
|
1307
|
+
ref = self.each_ref.to_a
|
1308
|
+
|
1309
|
+
result = "{"
|
1310
|
+
ref[0..-2].each do |ref|
|
1311
|
+
result << "#{ref.to_verilog},"
|
1312
|
+
end
|
1313
|
+
result << "#{ref.last.to_verilog}}"
|
1314
|
+
|
1315
|
+
return result
|
1316
|
+
end
|
1317
|
+
end
|
1318
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+
|
1304
1319
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# Used to output bitstring.
|
1305
1320
|
# Enhance HDLRuby with generation of verilog code.
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1306
1321
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class HDLRuby::BitString
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@@ -1420,18 +1435,20 @@ class Case
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|
1420
1435
|
end
|
1421
1436
|
end
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1422
1437
|
# The default part is stored in default instead of when. Reads and processes in the same way as when.
|
1423
|
-
if self.default
|
1424
|
-
|
1425
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-
|
1426
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-
|
1427
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-
|
1428
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-
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1429
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-
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1430
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-
|
1431
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-
|
1432
|
-
|
1433
|
-
|
1434
|
-
|
1438
|
+
if self.default then
|
1439
|
+
if self.default.each_statement.count > 1 then
|
1440
|
+
result << " " + " " *$space_count + "default: begin\n"
|
1441
|
+
self.default.each_statement do |statement|
|
1442
|
+
result << " " + " " *$space_count + "#{statement.to_verilog}"
|
1443
|
+
end
|
1444
|
+
result << " end\n"
|
1445
|
+
elsif self.default.each_statement.count == 1 then
|
1446
|
+
result << " " + " " *$space_count + "default: "
|
1447
|
+
self.default.each_statement do |statement|
|
1448
|
+
result << "#{statement.to_verilog}"
|
1449
|
+
end
|
1450
|
+
end
|
1451
|
+
end
|
1435
1452
|
result << " " + " " *$space_count + "endcase\n" # Conclusion.
|
1436
1453
|
|
1437
1454
|
$space_count -= 1 # Since the output ends, reduce the count.
|
@@ -1513,6 +1530,14 @@ class Unary
|
|
1513
1530
|
end
|
1514
1531
|
end
|
1515
1532
|
|
1533
|
+
# Used when casting expressions.
|
1534
|
+
class Cast
|
1535
|
+
# Converts the system to Verilog code.
|
1536
|
+
def to_verilog
|
1537
|
+
return "#{self.type.to_verilog}'(#{self.child.to_verilog})"
|
1538
|
+
end
|
1539
|
+
end
|
1540
|
+
|
1516
1541
|
# For declaring variables.
|
1517
1542
|
# Enhance SignalI with generation of verilog code.
|
1518
1543
|
class SignalI
|
@@ -1616,11 +1641,24 @@ class SystemT
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|
1616
1641
|
# Preprocessing
|
1617
1642
|
# Detect the registers
|
1618
1643
|
regs = []
|
1644
|
+
# The left values.
|
1619
1645
|
self.each_behavior do |behavior|
|
1620
|
-
behavior.block.each_statement do |statement|
|
1621
|
-
|
1646
|
+
# behavior.block.each_statement do |statement|
|
1647
|
+
# regs << statement.left.to_verilog if statement.is_a?(Transmit)
|
1648
|
+
# end
|
1649
|
+
behavior.each_block_deep do |block|
|
1650
|
+
block.each_statement do |statement|
|
1651
|
+
regs << statement.left.to_verilog if statement.is_a?(Transmit)
|
1652
|
+
end
|
1622
1653
|
end
|
1623
1654
|
end
|
1655
|
+
# And the initialized signals.
|
1656
|
+
self.each_output do |output|
|
1657
|
+
regs << output.to_verilog if output.value
|
1658
|
+
end
|
1659
|
+
self.each_inner do |inner|
|
1660
|
+
regs << inner.to_verilog if inner.value
|
1661
|
+
end
|
1624
1662
|
|
1625
1663
|
# Code generation
|
1626
1664
|
inputs = 0
|
@@ -1690,16 +1728,29 @@ class SystemT
|
|
1690
1728
|
else
|
1691
1729
|
code << " output"
|
1692
1730
|
end
|
1693
|
-
code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt};\n"
|
1731
|
+
# code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt};\n"
|
1732
|
+
code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt}"
|
1733
|
+
if output.value then
|
1734
|
+
# There is an initial value.
|
1735
|
+
code << " = #{output.value.to_verilog}"
|
1736
|
+
end
|
1737
|
+
code << ";\n"
|
1694
1738
|
$vector_cnt += 1
|
1695
1739
|
end
|
1696
1740
|
else
|
1697
|
-
if regs.include?(output.name) then
|
1741
|
+
# if regs.include?(output.name) then
|
1742
|
+
if regs.include?(output.to_verilog) then
|
1698
1743
|
code << " output reg"
|
1699
1744
|
else
|
1700
1745
|
code << " output"
|
1701
1746
|
end
|
1702
|
-
code << "#{output.type.to_verilog} #{output.to_verilog};\n"
|
1747
|
+
# code << "#{output.type.to_verilog} #{output.to_verilog};\n"
|
1748
|
+
code << "#{output.type.to_verilog} #{output.to_verilog}"
|
1749
|
+
if output.value then
|
1750
|
+
# There is an initial value.
|
1751
|
+
code << " = #{output.value.to_verilog}"
|
1752
|
+
end
|
1753
|
+
code << ";\n"
|
1703
1754
|
end
|
1704
1755
|
end
|
1705
1756
|
|
@@ -1719,7 +1770,9 @@ class SystemT
|
|
1719
1770
|
|
1720
1771
|
# Declare "inner".
|
1721
1772
|
self.each_inner do |inner|
|
1722
|
-
|
1773
|
+
# puts "for inner: #{inner.to_verilog}"
|
1774
|
+
# if regs.include?(inner.name) then
|
1775
|
+
if regs.include?(inner.to_verilog) then
|
1723
1776
|
code << " reg"
|
1724
1777
|
else
|
1725
1778
|
code << " wire"
|
@@ -1727,19 +1780,28 @@ class SystemT
|
|
1727
1780
|
|
1728
1781
|
if inner.type.base?
|
1729
1782
|
if inner.type.base.base?
|
1730
|
-
code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
|
1783
|
+
# code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
|
1784
|
+
code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
|
1731
1785
|
else
|
1732
|
-
code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
|
1786
|
+
# code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
|
1787
|
+
code << "#{inner.type.to_verilog} #{inner.to_verilog}"
|
1733
1788
|
end
|
1734
1789
|
else
|
1735
|
-
code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
|
1790
|
+
# code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
|
1791
|
+
code << " #{inner.type.to_verilog}#{inner.to_verilog}"
|
1736
1792
|
end
|
1793
|
+
if inner.value then
|
1794
|
+
# There is an initial value.
|
1795
|
+
code << " = #{inner.value.to_verilog}"
|
1796
|
+
end
|
1797
|
+
code << ";\n"
|
1737
1798
|
end
|
1738
1799
|
|
1739
1800
|
# If there is scope in scope, translate it.
|
1740
1801
|
self.each_scope do |scope|
|
1741
1802
|
scope.each_inner do |inner|
|
1742
|
-
if regs.include?(inner.name) then
|
1803
|
+
# if regs.include?(inner.name) then
|
1804
|
+
if regs.include?(inner.to_verilog) then
|
1743
1805
|
code << " reg "
|
1744
1806
|
else
|
1745
1807
|
code << " wire "
|
@@ -1747,13 +1809,21 @@ class SystemT
|
|
1747
1809
|
|
1748
1810
|
if inner.type.respond_to? (:base)
|
1749
1811
|
if inner.type.base.base?
|
1750
|
-
code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
|
1812
|
+
# code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
|
1813
|
+
code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
|
1751
1814
|
else
|
1752
|
-
code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
|
1815
|
+
# code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
|
1816
|
+
code << "#{inner.type.to_verilog} #{inner.to_verilog}"
|
1753
1817
|
end
|
1754
1818
|
else
|
1755
|
-
code << "inner #{inner.type.to_verilog} #{inner.to_verilog};\n"
|
1819
|
+
# code << "inner #{inner.type.to_verilog} #{inner.to_verilog};\n"
|
1820
|
+
code << "inner #{inner.type.to_verilog} #{inner.to_verilog}"
|
1821
|
+
end
|
1822
|
+
if inner.value then
|
1823
|
+
# There is an initial value.
|
1824
|
+
code << " = #{inner.value.to_verilog}"
|
1756
1825
|
end
|
1826
|
+
code << ";\n"
|
1757
1827
|
end
|
1758
1828
|
|
1759
1829
|
scope.each_connection do |connection|
|
@@ -1843,7 +1913,8 @@ class SystemT
|
|
1843
1913
|
|
1844
1914
|
# Declaration of "inner" part within "always".
|
1845
1915
|
block.each_inner do |inner|
|
1846
|
-
if regs.include?(inner.name) then
|
1916
|
+
# if regs.include?(inner.name) then
|
1917
|
+
if regs.include?(inner.to_verilog) then
|
1847
1918
|
code << " reg"
|
1848
1919
|
else
|
1849
1920
|
code << " wire"
|
@@ -1853,13 +1924,21 @@ class SystemT
|
|
1853
1924
|
# It is determined by an if.
|
1854
1925
|
if inner.type.base?
|
1855
1926
|
if inner.type.base.base?
|
1856
|
-
code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
|
1927
|
+
# code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
|
1928
|
+
code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
|
1857
1929
|
else
|
1858
|
-
code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
|
1930
|
+
# code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
|
1931
|
+
code << "#{inner.type.to_verilog} #{inner.to_verilog}"
|
1859
1932
|
end
|
1860
1933
|
else
|
1861
|
-
code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
|
1934
|
+
# code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
|
1935
|
+
code << " #{inner.type.to_verilog}#{inner.to_verilog}"
|
1936
|
+
end
|
1937
|
+
if inner.value then
|
1938
|
+
# There is an initial value.
|
1939
|
+
code << " = #{inner.value.to_verilog}"
|
1862
1940
|
end
|
1941
|
+
code << ";\n"
|
1863
1942
|
end
|
1864
1943
|
|
1865
1944
|
# Translate the block that finished scheduling.
|
data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: HDLRuby
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 2.1.
|
4
|
+
version: 2.1.6
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Lovic Gauthier
|
8
8
|
autorequire:
|
9
9
|
bindir: exe
|
10
10
|
cert_chain: []
|
11
|
-
date: 2020-03-
|
11
|
+
date: 2020-03-08 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|