HDLRuby 2.1.5 → 2.1.6
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/HDLRuby/hdrcc.rb +3 -1
- data/lib/HDLRuby/hruby_low.rb +14 -1
- data/lib/HDLRuby/hruby_verilog.rb +108 -29
- data/lib/HDLRuby/version.rb +1 -1
- metadata +2 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 9a13c2fd9d9add1fb436eeca3bd6ce2e58975ab2de842573fe6a260a74e6a901
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data.tar.gz: 04f16871ee7993c16b2419a691308a7ad235b487406ca9243085bcdcff1db8aa
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: ff99ac90a5f6bcc09896189f9e77f01e5394446efa8a6687f07d710528973ddf4d5397d5163889c9dc18425805f4a61adc30b56d686a9e6187c7b15a423990b4
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data.tar.gz: 5cfaa77758b3b15154ebf139fb7bd9f424e41d72c7bd642895dfb6b3929b04f889dba320f4141b55ef554996e28cbd8d5072d7ac7242a395a993cff77d3c2835
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data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -8,6 +8,7 @@ require 'HDLRuby/hruby_low2high'
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require 'HDLRuby/hruby_low2c'
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require 'HDLRuby/hruby_low2vhd'
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require 'HDLRuby/hruby_low_fix_types'
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# require 'HDLRuby/hruby_low_expand_types' # For now dormant
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require 'HDLRuby/hruby_low_without_outread'
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require 'HDLRuby/hruby_low_with_bool'
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require 'HDLRuby/hruby_low_bool2select'
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@@ -573,7 +574,8 @@ elsif $options[:verilog] then
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$top_system.each_systemT_deep do |systemT|
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systemT.to_upper_space!
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systemT.to_global_systemTs!
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-
systemT.break_types!
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# systemT.break_types!
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# systemT.expand_types!
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systemT.with_port!
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end
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# # Verilog generation
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data/lib/HDLRuby/hruby_low.rb
CHANGED
@@ -1553,6 +1553,16 @@ module HDLRuby::Low
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@base.equivalent?(type.base) )
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end
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# Should not exists since it identifies types with multiple sub types.
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#
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# # Iterates over the sub types.
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# def each_type(&ruby_block)
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# # No ruby block? Return an enumerator.
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# return to_enum(:each_type) unless ruby_block
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# # A ruby block? Apply it on the base.
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# ruby_block.call(@base)
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# end
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# Iterates over the types deeply if any.
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def each_type_deep(&ruby_block)
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# No ruby block? Return an enumerator.
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@@ -3153,7 +3163,10 @@ module HDLRuby::Low
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# Clones the Case (deeply)
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def clone
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-
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# Clone the default if any.
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defaut = @default ? @default.clone : nil
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# Clone the case.
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return Case.new(@value.clone,default,(@whens.map do |w|
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w.clone
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end) )
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end
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@@ -1301,6 +1301,21 @@ class RefRange
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end
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end
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# Use it when collecting references.
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class RefConcat
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def to_verilog
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ref = self.each_ref.to_a
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result = "{"
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ref[0..-2].each do |ref|
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result << "#{ref.to_verilog},"
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end
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result << "#{ref.last.to_verilog}}"
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return result
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end
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end
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# Used to output bitstring.
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# Enhance HDLRuby with generation of verilog code.
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class HDLRuby::BitString
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@@ -1420,18 +1435,20 @@ class Case
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end
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end
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# The default part is stored in default instead of when. Reads and processes in the same way as when.
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if self.default
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-
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-
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if self.default then
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if self.default.each_statement.count > 1 then
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result << " " + " " *$space_count + "default: begin\n"
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self.default.each_statement do |statement|
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result << " " + " " *$space_count + "#{statement.to_verilog}"
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end
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result << " end\n"
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elsif self.default.each_statement.count == 1 then
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result << " " + " " *$space_count + "default: "
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self.default.each_statement do |statement|
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result << "#{statement.to_verilog}"
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end
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end
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end
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result << " " + " " *$space_count + "endcase\n" # Conclusion.
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$space_count -= 1 # Since the output ends, reduce the count.
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@@ -1513,6 +1530,14 @@ class Unary
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end
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end
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# Used when casting expressions.
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class Cast
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# Converts the system to Verilog code.
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def to_verilog
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return "#{self.type.to_verilog}'(#{self.child.to_verilog})"
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end
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end
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# For declaring variables.
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# Enhance SignalI with generation of verilog code.
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class SignalI
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@@ -1616,11 +1641,24 @@ class SystemT
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# Preprocessing
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# Detect the registers
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regs = []
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# The left values.
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self.each_behavior do |behavior|
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behavior.block.each_statement do |statement|
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-
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# behavior.block.each_statement do |statement|
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# regs << statement.left.to_verilog if statement.is_a?(Transmit)
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# end
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behavior.each_block_deep do |block|
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block.each_statement do |statement|
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regs << statement.left.to_verilog if statement.is_a?(Transmit)
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end
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end
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end
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# And the initialized signals.
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self.each_output do |output|
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regs << output.to_verilog if output.value
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end
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self.each_inner do |inner|
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regs << inner.to_verilog if inner.value
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end
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# Code generation
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inputs = 0
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@@ -1690,16 +1728,29 @@ class SystemT
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else
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code << " output"
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end
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code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt};\n"
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# code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt};\n"
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code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt}"
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if output.value then
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# There is an initial value.
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code << " = #{output.value.to_verilog}"
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end
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code << ";\n"
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$vector_cnt += 1
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end
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else
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-
if regs.include?(output.name) then
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# if regs.include?(output.name) then
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if regs.include?(output.to_verilog) then
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code << " output reg"
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else
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code << " output"
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end
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code << "#{output.type.to_verilog} #{output.to_verilog};\n"
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# code << "#{output.type.to_verilog} #{output.to_verilog};\n"
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code << "#{output.type.to_verilog} #{output.to_verilog}"
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if output.value then
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# There is an initial value.
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code << " = #{output.value.to_verilog}"
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end
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code << ";\n"
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end
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end
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@@ -1719,7 +1770,9 @@ class SystemT
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# Declare "inner".
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self.each_inner do |inner|
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-
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# puts "for inner: #{inner.to_verilog}"
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# if regs.include?(inner.name) then
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if regs.include?(inner.to_verilog) then
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code << " reg"
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else
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code << " wire"
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@@ -1727,19 +1780,28 @@ class SystemT
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if inner.type.base?
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if inner.type.base.base?
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code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
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# code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
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code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
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else
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code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
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# code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
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code << "#{inner.type.to_verilog} #{inner.to_verilog}"
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end
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else
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code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
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# code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
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code << " #{inner.type.to_verilog}#{inner.to_verilog}"
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end
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if inner.value then
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# There is an initial value.
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code << " = #{inner.value.to_verilog}"
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end
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code << ";\n"
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end
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# If there is scope in scope, translate it.
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self.each_scope do |scope|
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scope.each_inner do |inner|
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if regs.include?(inner.name) then
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# if regs.include?(inner.name) then
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if regs.include?(inner.to_verilog) then
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code << " reg "
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else
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code << " wire "
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@@ -1747,13 +1809,21 @@ class SystemT
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if inner.type.respond_to? (:base)
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if inner.type.base.base?
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code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
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# code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
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code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
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else
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code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
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# code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
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code << "#{inner.type.to_verilog} #{inner.to_verilog}"
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end
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else
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code << "inner #{inner.type.to_verilog} #{inner.to_verilog};\n"
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# code << "inner #{inner.type.to_verilog} #{inner.to_verilog};\n"
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code << "inner #{inner.type.to_verilog} #{inner.to_verilog}"
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end
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if inner.value then
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# There is an initial value.
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code << " = #{inner.value.to_verilog}"
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end
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code << ";\n"
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end
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scope.each_connection do |connection|
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@@ -1843,7 +1913,8 @@ class SystemT
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# Declaration of "inner" part within "always".
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block.each_inner do |inner|
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-
if regs.include?(inner.name) then
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# if regs.include?(inner.name) then
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if regs.include?(inner.to_verilog) then
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code << " reg"
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else
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code << " wire"
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@@ -1853,13 +1924,21 @@ class SystemT
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# It is determined by an if.
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if inner.type.base?
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if inner.type.base.base?
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code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
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# code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
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code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
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else
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code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
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# code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
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code << "#{inner.type.to_verilog} #{inner.to_verilog}"
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end
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else
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code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
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# code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
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code << " #{inner.type.to_verilog}#{inner.to_verilog}"
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end
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if inner.value then
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# There is an initial value.
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code << " = #{inner.value.to_verilog}"
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end
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code << ";\n"
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end
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# Translate the block that finished scheduling.
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data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
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name: HDLRuby
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version: !ruby/object:Gem::Version
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-
version: 2.1.
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+
version: 2.1.6
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platform: ruby
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authors:
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- Lovic Gauthier
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autorequire:
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bindir: exe
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cert_chain: []
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-
date: 2020-03-
|
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+
date: 2020-03-08 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: bundler
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