HDLRuby 2.1.5 → 2.1.6

checksums.yaml

@@ -1,7 +1,7 @@
 ---
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data/lib/HDLRuby/hdrcc.rb

@@ -8,6 +8,7 @@ require 'HDLRuby/hruby_low2high'
 require 'HDLRuby/hruby_low2c'
 require 'HDLRuby/hruby_low2vhd'
 require 'HDLRuby/hruby_low_fix_types'
+# require 'HDLRuby/hruby_low_expand_types' # For now dormant
 require 'HDLRuby/hruby_low_without_outread'
 require 'HDLRuby/hruby_low_with_bool'
 require 'HDLRuby/hruby_low_bool2select'
@@ -573,7 +574,8 @@ elsif $options[:verilog] then
     $top_system.each_systemT_deep do |systemT|
         systemT.to_upper_space!
         systemT.to_global_systemTs!
-        systemT.break_types!
+        # systemT.break_types!
+        # systemT.expand_types!
         systemT.with_port!
     end
     # # Verilog generation

data/lib/HDLRuby/hruby_low.rb

@@ -1553,6 +1553,16 @@ module HDLRuby::Low
                     @base.equivalent?(type.base) )
         end
 
+        # Should not exists since it identifies types with multiple sub types.
+        #
+        # # Iterates over the sub types.
+        # def each_type(&ruby_block)
+        #     # No ruby block? Return an enumerator.
+        #     return to_enum(:each_type) unless ruby_block
+        #     # A ruby block? Apply it on the base.
+        #     ruby_block.call(@base)
+        # end
+
         # Iterates over the types deeply if any.
         def each_type_deep(&ruby_block)
             # No ruby block? Return an enumerator.
@@ -3153,7 +3163,10 @@ module HDLRuby::Low
 
         # Clones the Case (deeply)
         def clone
-            return Case.new(@value.clone,@default.clone,(@whens.map do |w|
+            # Clone the default if any.
+            defaut = @default ? @default.clone : nil
+            # Clone the case.
+            return Case.new(@value.clone,default,(@whens.map do |w|
                 w.clone
             end) )
         end

data/lib/HDLRuby/hruby_verilog.rb

@@ -1301,6 +1301,21 @@ class RefRange
     end
 end
 
+# Use it when collecting references.
+class RefConcat
+    def to_verilog    
+        ref = self.each_ref.to_a
+
+        result = "{"
+        ref[0..-2].each do |ref|
+            result << "#{ref.to_verilog},"
+        end
+        result << "#{ref.last.to_verilog}}"
+
+        return result
+    end
+end
+
 # Used to output bitstring.
 # Enhance HDLRuby with generation of verilog code.
 class HDLRuby::BitString
@@ -1420,18 +1435,20 @@ class Case
             end
         end
         # The default part is stored in default instead of when. Reads and processes in the same way as when.
-        if self.default.each_statement.count > 1 then
-            result << "      " + "   " *$space_count + "default: begin\n"
-            self.default.each_statement do |statement|
-                result << "                  " + "   " *$space_count + "#{statement.to_verilog}"
-            end
-            result << "                  end\n"
-        elsif self.default.each_statement.count == 1 then
-            result << "      " + "   " *$space_count + "default: "
-            self.default.each_statement do |statement|
-                result << "#{statement.to_verilog}"
-            end
-        end  
+        if self.default then
+            if self.default.each_statement.count > 1 then
+                result << "      " + "   " *$space_count + "default: begin\n"
+                self.default.each_statement do |statement|
+                    result << "                  " + "   " *$space_count + "#{statement.to_verilog}"
+                end
+                result << "                  end\n"
+            elsif self.default.each_statement.count == 1 then
+                result << "      " + "   " *$space_count + "default: "
+                self.default.each_statement do |statement|
+                    result << "#{statement.to_verilog}"
+                end
+            end  
+        end
         result << "   " + "   " *$space_count + "endcase\n" # Conclusion.
 
         $space_count -= 1           # Since the output ends, reduce the count.
@@ -1513,6 +1530,14 @@ class Unary
     end
 end
 
+# Used when casting expressions.
+class Cast
+    # Converts the system to Verilog code.
+    def to_verilog
+        return "#{self.type.to_verilog}'(#{self.child.to_verilog})"
+    end
+end
+
 # For declaring variables.
 # Enhance SignalI with generation of verilog code.
 class SignalI
@@ -1616,11 +1641,24 @@ class SystemT
         # Preprocessing
         # Detect the registers
         regs = []
+        # The left values.
         self.each_behavior do |behavior|
-            behavior.block.each_statement do |statement|
-                regs << statement.left.to_verilog if statement.is_a?(Transmit)
+            # behavior.block.each_statement do |statement|
+            #     regs << statement.left.to_verilog if statement.is_a?(Transmit)
+            # end
+            behavior.each_block_deep do |block|
+                block.each_statement do |statement|
+                    regs << statement.left.to_verilog if statement.is_a?(Transmit)
+                end
             end
         end
+        # And the initialized signals.
+        self.each_output do |output|
+            regs << output.to_verilog if output.value
+        end
+        self.each_inner do |inner|
+            regs << inner.to_verilog if inner.value
+        end
 
         # Code generation
         inputs = 0
@@ -1690,16 +1728,29 @@ class SystemT
                     else
                         code << "   output"
                     end
-                    code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt};\n"
+                    # code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt};\n"
+                    code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt}"
+                    if output.value then
+                        # There is an initial value.
+                        code << " = #{output.value.to_verilog}"
+                    end
+                    code << ";\n"
                     $vector_cnt += 1
                 end        
             else
-                if regs.include?(output.name) then
+                # if regs.include?(output.name) then
+                if regs.include?(output.to_verilog) then
                     code << "   output reg"
                 else
                     code << "   output"
                 end
-                code << "#{output.type.to_verilog} #{output.to_verilog};\n"
+                # code << "#{output.type.to_verilog} #{output.to_verilog};\n"
+                code << "#{output.type.to_verilog} #{output.to_verilog}"
+                if output.value then
+                    # There is an initial value.
+                    code << " = #{output.value.to_verilog}"
+                end
+                code << ";\n"
             end
         end
 
@@ -1719,7 +1770,9 @@ class SystemT
 
         # Declare "inner".
         self.each_inner do |inner|
-            if regs.include?(inner.name) then
+            # puts "for inner: #{inner.to_verilog}"
+            # if regs.include?(inner.name) then
+            if regs.include?(inner.to_verilog) then
                 code << "   reg"
             else
                 code << "   wire"
@@ -1727,19 +1780,28 @@ class SystemT
 
             if inner.type.base? 
                 if inner.type.base.base? 
-                    code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
+                    # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
+                    code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
                 else
-                    code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
+                    # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
+                    code << "#{inner.type.to_verilog} #{inner.to_verilog}"
                 end
             else
-                code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
+                # code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
+                code << " #{inner.type.to_verilog}#{inner.to_verilog}"
             end
+            if inner.value then
+                # There is an initial value.
+                code << " = #{inner.value.to_verilog}"
+            end
+            code << ";\n"
         end
 
         # If there is scope in scope, translate it.
         self.each_scope do |scope|
             scope.each_inner do |inner|
-                if regs.include?(inner.name) then
+                # if regs.include?(inner.name) then
+                if regs.include?(inner.to_verilog) then
                     code << "   reg "
                 else
                     code << "   wire "
@@ -1747,13 +1809,21 @@ class SystemT
 
                 if inner.type.respond_to? (:base) 
                     if inner.type.base.base?
-                        code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
+                        # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
+                        code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
                     else
-                        code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
+                        # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
+                        code << "#{inner.type.to_verilog} #{inner.to_verilog}"
                     end
                 else
-                    code << "inner #{inner.type.to_verilog} #{inner.to_verilog};\n"
+                    # code << "inner #{inner.type.to_verilog} #{inner.to_verilog};\n"
+                    code << "inner #{inner.type.to_verilog} #{inner.to_verilog}"
+                end
+                if inner.value then
+                    # There is an initial value.
+                    code << " = #{inner.value.to_verilog}"
                 end
+                code << ";\n"
             end    
 
             scope.each_connection do |connection|
@@ -1843,7 +1913,8 @@ class SystemT
 
             # Declaration of "inner" part within "always".
             block.each_inner do |inner|
-                if regs.include?(inner.name) then
+                # if regs.include?(inner.name) then
+                if regs.include?(inner.to_verilog) then
                     code << "      reg"
                 else
                     code << "      wire"
@@ -1853,13 +1924,21 @@ class SystemT
                 # It is determined by an if.
                 if inner.type.base? 
                     if inner.type.base.base? 
-                        code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
+                        # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
+                        code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
                     else
-                        code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
+                        # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
+                        code << "#{inner.type.to_verilog} #{inner.to_verilog}"
                     end
                 else
-                    code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
+                    # code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
+                    code << " #{inner.type.to_verilog}#{inner.to_verilog}"
+                end
+                if inner.value then
+                    # There is an initial value.
+                    code << " = #{inner.value.to_verilog}"
                 end
+                code << ";\n"
             end
 
             # Translate the block that finished scheduling.

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.1.5"
+  VERSION = "2.1.6"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.1.5
+  version: 2.1.6
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-03-04 00:00:00.000000000 Z
+date: 2020-03-08 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler