HDLRuby 2.1.5 → 2.1.6

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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data/lib/HDLRuby/hdrcc.rb CHANGED
@@ -8,6 +8,7 @@ require 'HDLRuby/hruby_low2high'
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  require 'HDLRuby/hruby_low2c'
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  require 'HDLRuby/hruby_low2vhd'
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  require 'HDLRuby/hruby_low_fix_types'
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+ # require 'HDLRuby/hruby_low_expand_types' # For now dormant
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  require 'HDLRuby/hruby_low_without_outread'
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  require 'HDLRuby/hruby_low_with_bool'
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  require 'HDLRuby/hruby_low_bool2select'
@@ -573,7 +574,8 @@ elsif $options[:verilog] then
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  $top_system.each_systemT_deep do |systemT|
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  systemT.to_upper_space!
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  systemT.to_global_systemTs!
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- systemT.break_types!
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+ # systemT.break_types!
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+ # systemT.expand_types!
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  systemT.with_port!
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  end
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  # # Verilog generation
@@ -1553,6 +1553,16 @@ module HDLRuby::Low
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  @base.equivalent?(type.base) )
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  end
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+ # Should not exists since it identifies types with multiple sub types.
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+ #
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+ # # Iterates over the sub types.
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+ # def each_type(&ruby_block)
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+ # # No ruby block? Return an enumerator.
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+ # return to_enum(:each_type) unless ruby_block
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+ # # A ruby block? Apply it on the base.
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+ # ruby_block.call(@base)
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+ # end
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+
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  # Iterates over the types deeply if any.
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  def each_type_deep(&ruby_block)
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  # No ruby block? Return an enumerator.
@@ -3153,7 +3163,10 @@ module HDLRuby::Low
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3154
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  # Clones the Case (deeply)
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  def clone
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- return Case.new(@value.clone,@default.clone,(@whens.map do |w|
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+ # Clone the default if any.
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+ defaut = @default ? @default.clone : nil
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+ # Clone the case.
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+ return Case.new(@value.clone,default,(@whens.map do |w|
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  w.clone
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  end) )
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  end
@@ -1301,6 +1301,21 @@ class RefRange
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  end
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  end
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1303
 
1304
+ # Use it when collecting references.
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+ class RefConcat
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+ def to_verilog
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+ ref = self.each_ref.to_a
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+
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+ result = "{"
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+ ref[0..-2].each do |ref|
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+ result << "#{ref.to_verilog},"
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+ end
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+ result << "#{ref.last.to_verilog}}"
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+
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+ return result
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+ end
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+ end
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+
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  # Used to output bitstring.
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  # Enhance HDLRuby with generation of verilog code.
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  class HDLRuby::BitString
@@ -1420,18 +1435,20 @@ class Case
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  end
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  end
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  # The default part is stored in default instead of when. Reads and processes in the same way as when.
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- if self.default.each_statement.count > 1 then
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- result << " " + " " *$space_count + "default: begin\n"
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- self.default.each_statement do |statement|
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- result << " " + " " *$space_count + "#{statement.to_verilog}"
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- end
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- result << " end\n"
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- elsif self.default.each_statement.count == 1 then
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- result << " " + " " *$space_count + "default: "
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- self.default.each_statement do |statement|
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- result << "#{statement.to_verilog}"
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- end
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- end
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+ if self.default then
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+ if self.default.each_statement.count > 1 then
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+ result << " " + " " *$space_count + "default: begin\n"
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+ self.default.each_statement do |statement|
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+ result << " " + " " *$space_count + "#{statement.to_verilog}"
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+ end
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+ result << " end\n"
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+ elsif self.default.each_statement.count == 1 then
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+ result << " " + " " *$space_count + "default: "
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+ self.default.each_statement do |statement|
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+ result << "#{statement.to_verilog}"
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+ end
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+ end
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+ end
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  result << " " + " " *$space_count + "endcase\n" # Conclusion.
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1453
 
1437
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  $space_count -= 1 # Since the output ends, reduce the count.
@@ -1513,6 +1530,14 @@ class Unary
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1530
  end
1514
1531
  end
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+ # Used when casting expressions.
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+ class Cast
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+ # Converts the system to Verilog code.
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+ def to_verilog
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+ return "#{self.type.to_verilog}'(#{self.child.to_verilog})"
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+ end
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+ end
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+
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  # For declaring variables.
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  # Enhance SignalI with generation of verilog code.
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  class SignalI
@@ -1616,11 +1641,24 @@ class SystemT
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  # Preprocessing
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  # Detect the registers
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  regs = []
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+ # The left values.
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  self.each_behavior do |behavior|
1620
- behavior.block.each_statement do |statement|
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- regs << statement.left.to_verilog if statement.is_a?(Transmit)
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+ # behavior.block.each_statement do |statement|
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+ # regs << statement.left.to_verilog if statement.is_a?(Transmit)
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+ # end
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+ behavior.each_block_deep do |block|
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+ block.each_statement do |statement|
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+ regs << statement.left.to_verilog if statement.is_a?(Transmit)
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+ end
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  end
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  end
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+ # And the initialized signals.
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+ self.each_output do |output|
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+ regs << output.to_verilog if output.value
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+ end
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+ self.each_inner do |inner|
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+ regs << inner.to_verilog if inner.value
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+ end
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1625
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  # Code generation
1626
1664
  inputs = 0
@@ -1690,16 +1728,29 @@ class SystemT
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  else
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1729
  code << " output"
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  end
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- code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt};\n"
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+ # code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt};\n"
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+ code << "#{type.to_verilog} #{$vector_reg}:#{$vector_cnt}"
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+ if output.value then
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+ # There is an initial value.
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+ code << " = #{output.value.to_verilog}"
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+ end
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+ code << ";\n"
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  $vector_cnt += 1
1695
1739
  end
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  else
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- if regs.include?(output.name) then
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+ # if regs.include?(output.name) then
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+ if regs.include?(output.to_verilog) then
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  code << " output reg"
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  else
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1745
  code << " output"
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  end
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- code << "#{output.type.to_verilog} #{output.to_verilog};\n"
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+ # code << "#{output.type.to_verilog} #{output.to_verilog};\n"
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+ code << "#{output.type.to_verilog} #{output.to_verilog}"
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+ if output.value then
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+ # There is an initial value.
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+ code << " = #{output.value.to_verilog}"
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+ end
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+ code << ";\n"
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1754
  end
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  end
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@@ -1719,7 +1770,9 @@ class SystemT
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1770
 
1720
1771
  # Declare "inner".
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  self.each_inner do |inner|
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- if regs.include?(inner.name) then
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+ # puts "for inner: #{inner.to_verilog}"
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+ # if regs.include?(inner.name) then
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+ if regs.include?(inner.to_verilog) then
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1776
  code << " reg"
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1777
  else
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1778
  code << " wire"
@@ -1727,19 +1780,28 @@ class SystemT
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1780
 
1728
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  if inner.type.base?
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1782
  if inner.type.base.base?
1730
- code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
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+ # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
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+ code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
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1785
  else
1732
- code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
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+ # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
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+ code << "#{inner.type.to_verilog} #{inner.to_verilog}"
1733
1788
  end
1734
1789
  else
1735
- code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
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+ # code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
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+ code << " #{inner.type.to_verilog}#{inner.to_verilog}"
1736
1792
  end
1793
+ if inner.value then
1794
+ # There is an initial value.
1795
+ code << " = #{inner.value.to_verilog}"
1796
+ end
1797
+ code << ";\n"
1737
1798
  end
1738
1799
 
1739
1800
  # If there is scope in scope, translate it.
1740
1801
  self.each_scope do |scope|
1741
1802
  scope.each_inner do |inner|
1742
- if regs.include?(inner.name) then
1803
+ # if regs.include?(inner.name) then
1804
+ if regs.include?(inner.to_verilog) then
1743
1805
  code << " reg "
1744
1806
  else
1745
1807
  code << " wire "
@@ -1747,13 +1809,21 @@ class SystemT
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1809
 
1748
1810
  if inner.type.respond_to? (:base)
1749
1811
  if inner.type.base.base?
1750
- code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
1812
+ # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
1813
+ code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
1751
1814
  else
1752
- code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
1815
+ # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
1816
+ code << "#{inner.type.to_verilog} #{inner.to_verilog}"
1753
1817
  end
1754
1818
  else
1755
- code << "inner #{inner.type.to_verilog} #{inner.to_verilog};\n"
1819
+ # code << "inner #{inner.type.to_verilog} #{inner.to_verilog};\n"
1820
+ code << "inner #{inner.type.to_verilog} #{inner.to_verilog}"
1821
+ end
1822
+ if inner.value then
1823
+ # There is an initial value.
1824
+ code << " = #{inner.value.to_verilog}"
1756
1825
  end
1826
+ code << ";\n"
1757
1827
  end
1758
1828
 
1759
1829
  scope.each_connection do |connection|
@@ -1843,7 +1913,8 @@ class SystemT
1843
1913
 
1844
1914
  # Declaration of "inner" part within "always".
1845
1915
  block.each_inner do |inner|
1846
- if regs.include?(inner.name) then
1916
+ # if regs.include?(inner.name) then
1917
+ if regs.include?(inner.to_verilog) then
1847
1918
  code << " reg"
1848
1919
  else
1849
1920
  code << " wire"
@@ -1853,13 +1924,21 @@ class SystemT
1853
1924
  # It is determined by an if.
1854
1925
  if inner.type.base?
1855
1926
  if inner.type.base.base?
1856
- code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
1927
+ # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
1928
+ code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
1857
1929
  else
1858
- code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
1930
+ # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
1931
+ code << "#{inner.type.to_verilog} #{inner.to_verilog}"
1859
1932
  end
1860
1933
  else
1861
- code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
1934
+ # code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
1935
+ code << " #{inner.type.to_verilog}#{inner.to_verilog}"
1936
+ end
1937
+ if inner.value then
1938
+ # There is an initial value.
1939
+ code << " = #{inner.value.to_verilog}"
1862
1940
  end
1941
+ code << ";\n"
1863
1942
  end
1864
1943
 
1865
1944
  # Translate the block that finished scheduling.
@@ -1,3 +1,3 @@
1
1
  module HDLRuby
2
- VERSION = "2.1.5"
2
+ VERSION = "2.1.6"
3
3
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: HDLRuby
3
3
  version: !ruby/object:Gem::Version
4
- version: 2.1.5
4
+ version: 2.1.6
5
5
  platform: ruby
6
6
  authors:
7
7
  - Lovic Gauthier
8
8
  autorequire:
9
9
  bindir: exe
10
10
  cert_chain: []
11
- date: 2020-03-04 00:00:00.000000000 Z
11
+ date: 2020-03-08 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: bundler