HDLRuby 3.9.3 → 3.9.6

data/lib/HDLRuby/std/decoder.rb

@@ -131,10 +131,10 @@ module HDLRuby::High::Std
             format = format.to_s
             width = format.size
             # For that purpose create the regular expression used to process it.
-            prs = "([0-1]+)|(a+)|(b+)|(c+)|(d+)|(e+)|(g+)|(h+)|(i+)|(j+)|(k+)|(l+)|(m+)|(n+)|(o+)|(p+)|(q+)|(r+)|(s+)|(t+)|(u+)|(v+)|(w+)|(x+)|(y+)|(z+)"
+            prs = "([0-1]+)|(a+)|(b+)|(c+)|(d+)|(e+)|(f+)|(g+)|(h+)|(i+)|(j+)|(k+)|(l+)|(m+)|(n+)|(o+)|(p+)|(q+)|(r+)|(s+)|(t+)|(u+)|(v+)|(w+)|(x+)|(y+)|(z+)"
             # Check if the format is compatible with it.
             unless format =~ Regexp.new("^(#{prs})+$") then
-                raise AnyError("Invalid format for a field: #{format}")
+                raise AnyError, "Invalid format for a field: #{format}"
             end
             # Split the format in fields.
             format = format.split(Regexp.new(prs)).select {|str| !str.empty?}

data/lib/HDLRuby/std/sequencer.rb

@@ -2266,13 +2266,12 @@ module HDLRuby::High::Std
             end
             # Create the hardware iterator.
             this = self
-            size = this.size ? this.size : this.last - this.first + 1
-            # size = size.to_expr
-            # if size.respond_to?(:cast) then
-            #     size = size.cast(typ)
-            # else
-            #     size = size.as(typ)
-            # end
+            # size = this.size ? this.size : this.last - this.first + 1
+            if this.last.is_a?(SignalI) or this.first.is_a?(SignalI) then
+              size = this.last.to_expr - this.first.to_expr + 1
+            else
+              size = this.last.to_i - this.first.to_i + 1
+            end
             size = size.to_expr.as(typ)
             # hw_enum = SEnumeratorBase.new(signed[32],size) do |idx|
             hw_enum = SEnumeratorBase.new(typ,size) do |idx|

data/lib/HDLRuby/verilog_hruby.rb

@@ -889,6 +889,34 @@ module VerilogTools
         state.indent = indent
         state.level  = level
         return case_txt
+      when :casez
+        # Saves the state.
+        indent = state.indent
+        level = state.level
+        # Generate the hcase.
+        state.indent += "  "
+        case_txt = indent + "hcasez(" + ast[1].to_HDLRuby(state) + ")\n"
+        # Generate the case items.
+        case_txt += ast[2].map do |item|
+          res_txt = ""
+          if item[0] != "default" then
+            # hwhen case.
+            res_txt += indent + "hwhen(" 
+            res_txt += item[0].map {|e| e.to_HDLRuby(state) }.join(",")
+            res_txt += ") do\n"
+            res_txt += item[1].to_HDLRuby(state)
+            res_txt += indent + "end\n"
+          else
+            # helse case.
+            res_txt += indent + "helse do\n"
+            res_txt += item[1].to_HDLRuby(state) + indent + "end\n"
+          end
+          res_txt
+        end.join
+        # Restore the state and return the result.
+        state.indent = indent
+        state.level  = level
+        return case_txt
       when :blocking_assignment, :non_blocking_assignment
         return ast[0].to_HDLRuby(state)
       when :statement
@@ -1094,6 +1122,8 @@ module VerilogTools
       base = ast[1] ? ast[1].to_HDLRuby(state) : ""
       # Get the second number if any.
       number1 = ast[2] ? ast[2].to_HDLRuby(state) : ""
+      # In HDLRuby, for now, wildcards work like z.
+      number1 = number1.gsub("?","z")
       # Depending on the base.
       case base
       when "'b"

data/lib/HDLRuby/verilog_parser.rb

@@ -1220,7 +1220,7 @@ module VerilogTools
     CLOSE_BRA_COLON_TOKS = [ "\\" + CLOSE_BRA_TOK, COLON_TOK ]
     CLOSE_BRA_COLON_REX  = /\G#{S}(#{CLOSE_BRA_COLON_TOKS.join("|")})/
 
-    STATEMENT_TOKS = [ IF_TOK, CASE_TOK, CASEZ_TOK, CASEX_TOK, 
+    STATEMENT_TOKS = [ IF_TOK, CASEZ_TOK, CASEX_TOK, CASE_TOK,  
                        FOREVER_TOK, REPEAT_TOK, WHILE_TOK, FOR_TOK,
                        WAIT_TOK, RIGHT_ARROW_TOK, DISABLE_TOK,
                        ASSIGN_TOK, FORCE_TOK, DEASSIGN_TOK, RELEASE_TOK ]

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "3.9.3"
+  VERSION = "3.9.6"
 end

metadata

@@ -1,7 +1,7 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 3.9.3
+  version: 3.9.6
 platform: ruby
 authors:
 - Lovic Gauthier
@@ -193,11 +193,13 @@ files:
 - lib/HDLRuby/hdr_samples/tuple.rb
 - lib/HDLRuby/hdr_samples/type_minmax_bench.rb
 - lib/HDLRuby/hdr_samples/verilog_parser_bench.rb
+- lib/HDLRuby/hdr_samples/with_assign_to_slice.rb
 - lib/HDLRuby/hdr_samples/with_board.rb
 - lib/HDLRuby/hdr_samples/with_board_sequencer.rb
 - lib/HDLRuby/hdr_samples/with_bram.rb
 - lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb
 - lib/HDLRuby/hdr_samples/with_bram_stack.rb
+- lib/HDLRuby/hdr_samples/with_casez.rb
 - lib/HDLRuby/hdr_samples/with_casts.rb
 - lib/HDLRuby/hdr_samples/with_channel.rb
 - lib/HDLRuby/hdr_samples/with_channel_other.rb
@@ -502,7 +504,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.7.2
+rubygems_version: 4.0.18
 specification_version: 4
 summary: HDLRuby is a library for describing and simulating digital electronic systems.
 test_files: []