HDLRuby 3.9.1 → 3.9.3
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.html +4121 -4648
- data/README.md +9 -1
- data/ext/hruby_sim/hruby_rcsim_build.c +2 -0
- data/ext/hruby_sim/hruby_sim.h +6 -0
- data/ext/hruby_sim/hruby_sim_calc.c +67 -0
- data/lib/HDLRuby/hdr_samples/with_henumerable.rb +281 -258
- data/lib/HDLRuby/hdr_samples/with_to_svg.rb +37 -0
- data/lib/HDLRuby/hdr_samples/with_unary_reduction.rb +23 -0
- data/lib/HDLRuby/hdr_samples/with_values.rb +4 -0
- data/lib/HDLRuby/hdrcc.rb +3 -0
- data/lib/HDLRuby/hruby_bstr.rb +2 -1
- data/lib/HDLRuby/hruby_high.rb +35 -7
- data/lib/HDLRuby/hruby_low.rb +52 -87
- data/lib/HDLRuby/hruby_low_split_signals.rb +213 -0
- data/lib/HDLRuby/hruby_types.rb +6 -2
- data/lib/HDLRuby/hruby_viz.rb +359 -166
- data/lib/HDLRuby/std/hruby_enum.rb +104 -28
- data/lib/HDLRuby/std/sequencer.rb +17 -3
- data/lib/HDLRuby/verilog_hruby.rb +70 -28
- data/lib/HDLRuby/verilog_parser.rb +38 -18
- data/lib/HDLRuby/version.rb +1 -1
- metadata +5 -2
data/README.md
CHANGED
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@@ -71,7 +71,11 @@ hdrcc --get-tuto
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71
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__What's New__
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-
For
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For HDKRuby version 3.9.2:
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* Added the `hbreak` command for exiting parallel enumerator loops.
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For HDLRuby version 3.9.0/3.9.1:
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* Added the parallel enumerators to the software sequencers.
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@@ -3981,6 +3985,10 @@ Parallel enumerators provide several control methods:
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* `+`: Concatenates two enumerators.
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Additionaly, it is possible to exit an enumeration loop using the following command:
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* `hbreak`: Exits the current enumeration loop.
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__Hardware Implementations of Enumerable Methods__
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Using parallel enumerators, HDLRuby provides hardware implementations of many Ruby Enumerable methods. These are available for any enumerable object and can be used inside or outside processes.
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@@ -760,6 +760,8 @@ VALUE rcsim_make_unary(VALUE mod, VALUE type, VALUE operator, VALUE child) {
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switch(sym_to_char(operator)) {
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case (unsigned char)'~': unary->oper = not_value; break;
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case (unsigned char)('-'+'@'*2): unary->oper = neg_value; break;
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case (unsigned char)'|': unary->oper = reduce_or_value; break;
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case (unsigned char)'&': unary->oper = reduce_and_value; break;
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default: perror("Invalid operator for unary.");
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}
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value_to_rcsim(ExpressionS,child,unary->child);
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data/ext/hruby_sim/hruby_sim.h
CHANGED
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@@ -252,6 +252,12 @@ extern Value not_value(Value src, Value dst);
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* @return dst */
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extern Value reduce_or_value(Value src, Value dst);
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/** Compute the and of the bits a a value.
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* @param src the source value
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* @param dst the destination value
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* @return dst */
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extern Value reduce_and_value(Value src, Value dst);
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/** Computes the AND of two values.
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* @param src0 the first source value of the and
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* @param src1 the second source value of the and
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@@ -1348,6 +1348,44 @@ Value reduce_or_value_bitstring(Value src, Value dst) {
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return dst;
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}
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/** Compute the and of the bits a bitstring value.
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* @param src the source value
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* @param dst the destination value
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* @return dst */
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Value reduce_and_value_bitstring(Value src, Value dst) {
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/* Compute the width of the result in bits. */
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unsigned long long width = type_width(src->type);
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/* Update the destination capacity if required. */
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resize_value(dst,width);
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/* Set the type and size of the destination from the type of the source.*/
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dst->type = src->type;
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dst->numeric = 0;
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/* Get access to the source and destination data. */
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char* src_data = src->data_str;
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char* dst_data = dst->data_str;
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/* Performs the reduce or. */
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unsigned long long count;
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char res = 0;
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for(count = 0; count < width; ++count) {
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/* Performs the reduce and. */
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char d = src_data[count] - '0'; /* Get and convert to bit. */
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if ((d == (d&1)) && (res != 'x'-'0')) { /* d is defined. */
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res &= d;
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} else {
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/* res is undefined. */
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res = 'x' - '0';
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}
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/* Apart for the first bit, there are only 0, still we are in
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* the loop, set it. */
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dst_data[count] = '0';
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}
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dst_data[0] = res + '0';
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/* Return the destination. */
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return dst;
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}
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/** Computes the and of two bitstring values.
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* @param src0 the first source value of the and
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@@ -2280,6 +2318,21 @@ Value reduce_or_value_numeric(Value src, Value dst) {
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return dst;
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}
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/** Compute the and of the bits a numeric value.
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* @param src the source value
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* @param dst the destination value
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* @return dst */
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Value reduce_and_value_numeric(Value src, Value dst) {
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/* Sets state of the destination using the first source. */
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dst->type = src->type;
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dst->numeric = 1;
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/* Perform the reduce and. */
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unsigned long long mask = ~(-1LL << type_width(src->type));
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dst->data_int = fix_numeric_type(dst->type, (~src->data_int & mask) == 0);
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return dst;
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}
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/** Computes the AND of two numeric values.
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* @param src0 the first source value of the addition
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@@ -3061,6 +3114,20 @@ Value reduce_or_value(Value src, Value dst) {
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}
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}
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/** Compute the and of the bits a value.
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* @param src the source value
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* @param dst the destination value
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* @return dst */
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Value reduce_and_value(Value src, Value dst) {
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if (src->numeric) {
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/* The source is numeric. */
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return reduce_and_value_numeric(src,dst);
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} else {
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/* The source cannot be numeric, compute bitsitrings. */
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return reduce_and_value_bitstring(src,dst);
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}
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}
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/** Computes the AND of two general values.
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* @param src0 the first source value of the addition
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