HDLRuby 3.7.2 → 3.7.3
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.md +26 -0
- data/ext/hruby_sim/hruby_rcsim_build.c +47 -2
- data/ext/hruby_sim/hruby_sim.h +8 -0
- data/ext/hruby_sim/hruby_sim_calc.c +3 -2
- data/ext/hruby_sim/hruby_sim_core.c +24 -7
- data/lib/HDLRuby/hdr_samples/ruby_program/with_sw_hruby_function.rb +31 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_array.rb +48 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_sequencer.rb +49 -0
- data/lib/HDLRuby/hruby_high.rb +23 -0
- data/lib/HDLRuby/hruby_low.rb +25 -0
- data/lib/HDLRuby/hruby_rcsim.rb +8 -0
- data/lib/HDLRuby/std/sequencer.rb +5 -0
- data/lib/HDLRuby/std/sequencer_sw.rb +390 -103
- data/lib/HDLRuby/version.rb +1 -1
- data/lib/rubyHDL.rb +26 -0
- metadata +5 -2
data/lib/HDLRuby/version.rb
CHANGED
data/lib/rubyHDL.rb
CHANGED
|
@@ -6,6 +6,32 @@ require 'hruby_sim/hruby_sim'
|
|
|
6
6
|
########################################################################
|
|
7
7
|
module RubyHDL
|
|
8
8
|
|
|
9
|
+
# Wrapper for array signal accesses.
|
|
10
|
+
class ArrayWrapper
|
|
11
|
+
# Create a new memory wrapper for signal +sig+
|
|
12
|
+
def initialize(sig)
|
|
13
|
+
@signal = sig
|
|
14
|
+
end
|
|
15
|
+
|
|
16
|
+
# Read the array.
|
|
17
|
+
def [](idx)
|
|
18
|
+
return RCSim.rcsim_read_index_fixnum(@signal,idx)
|
|
19
|
+
end
|
|
20
|
+
|
|
21
|
+
# Write to the array.
|
|
22
|
+
def []=(idx,val)
|
|
23
|
+
return RCSim.rcsim_write_index_fixnum_seq(@signal,idx,val)
|
|
24
|
+
end
|
|
25
|
+
end
|
|
26
|
+
|
|
27
|
+
# Creates a new array port 'name' assigned to signal 'sig'.
|
|
28
|
+
def self.arrayport(name,sig)
|
|
29
|
+
# Creating the accessing method.
|
|
30
|
+
define_singleton_method(name.to_sym) do
|
|
31
|
+
ArrayWrapper.new(sig)
|
|
32
|
+
end
|
|
33
|
+
end
|
|
34
|
+
|
|
9
35
|
# Creates a new port 'name' assigned to signal 'sig' for reading.
|
|
10
36
|
def self.inport(name,sig)
|
|
11
37
|
# Create the accessing methods.
|
metadata
CHANGED
|
@@ -1,13 +1,13 @@
|
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
|
2
2
|
name: HDLRuby
|
|
3
3
|
version: !ruby/object:Gem::Version
|
|
4
|
-
version: 3.7.
|
|
4
|
+
version: 3.7.3
|
|
5
5
|
platform: ruby
|
|
6
6
|
authors:
|
|
7
7
|
- Lovic Gauthier
|
|
8
8
|
bindir: exe
|
|
9
9
|
cert_chain: []
|
|
10
|
-
date: 2025-
|
|
10
|
+
date: 2025-04-14 00:00:00.000000000 Z
|
|
11
11
|
dependencies:
|
|
12
12
|
- !ruby/object:Gem::Dependency
|
|
13
13
|
name: bundler
|
|
@@ -180,6 +180,7 @@ files:
|
|
|
180
180
|
- lib/HDLRuby/hdr_samples/ruby_program/sw_inc_mem.rb
|
|
181
181
|
- lib/HDLRuby/hdr_samples/ruby_program/sw_log.rb
|
|
182
182
|
- lib/HDLRuby/hdr_samples/ruby_program/with_sw_hruby.rb
|
|
183
|
+
- lib/HDLRuby/hdr_samples/ruby_program/with_sw_hruby_function.rb
|
|
183
184
|
- lib/HDLRuby/hdr_samples/ruby_program/with_sw_hruby_hruby_test.rb
|
|
184
185
|
- lib/HDLRuby/hdr_samples/seqpar_bench.rb
|
|
185
186
|
- lib/HDLRuby/hdr_samples/simple_counter_bench.rb
|
|
@@ -226,9 +227,11 @@ files:
|
|
|
226
227
|
- lib/HDLRuby/hdr_samples/with_of.rb
|
|
227
228
|
- lib/HDLRuby/hdr_samples/with_program_c.rb
|
|
228
229
|
- lib/HDLRuby/hdr_samples/with_program_ruby.rb
|
|
230
|
+
- lib/HDLRuby/hdr_samples/with_program_ruby_array.rb
|
|
229
231
|
- lib/HDLRuby/hdr_samples/with_program_ruby_cpu.rb
|
|
230
232
|
- lib/HDLRuby/hdr_samples/with_program_ruby_io.rb
|
|
231
233
|
- lib/HDLRuby/hdr_samples/with_program_ruby_mem.rb
|
|
234
|
+
- lib/HDLRuby/hdr_samples/with_program_ruby_sequencer.rb
|
|
232
235
|
- lib/HDLRuby/hdr_samples/with_program_ruby_threads.rb
|
|
233
236
|
- lib/HDLRuby/hdr_samples/with_reconf.rb
|
|
234
237
|
- lib/HDLRuby/hdr_samples/with_reduce.rb
|