HDLRuby 3.4.0 → 3.5.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/HDLRuby.gemspec

@@ -8,6 +8,7 @@ Gem::Specification.new do |spec|
   spec.version       = HDLRuby::VERSION
   spec.authors       = ["Lovic Gauthier"]
   spec.email         = ["lovic@ariake-nct.ac.jp"]
+  spec.platform      = "ruby"
 
   spec.summary       = %q{HDLRuby is a library for describing and simulating digital electronic systems.}
   spec.description   = %q{HDLRuby is a library for describing and simulating digital electronic systems. With this library it will possible to describe synthesizable hardware using all the features of the Ruby language, e.g., object orientation, duck typing, closure. This library is also usable through irb for interactive design and simulation.}

data/README.md

@@ -17,6 +17,13 @@ hdrcc --get-tuto
 
 __What's new__
 
+For HDLRuby version 3.5.0:
+
+ * Added direct support for Verilog HDL files as input to 'hdrcc'.
+
+ * Added the ability to generate a graphical representation of the RTL code in SVG format using the '--svg' option for 'hdrcc'.
+
+
 For HDLRuby version 3.4.0:
 
  * Improved synchronization of the browser-base graphical interface with the HDLRuby simulator.
@@ -106,14 +113,14 @@ __Warning__:
 __Usage__:
 
 ```
-hdrcc [options] <input file> <output directory>
+hdrcc [options] <input file> <output/working directory>
 ```
 
 Where:
 
  * `options` is a list of options
  * `<input file>` is the initial file to compile (mandatory)
- *  `<output directory>` is the directory where the generated files will be put
+ *  `<output/working directory>` is the directory where the output and temporary files will be put
 
 |  Options         |          |
 |:------------------|:-----------------------------------------------------|
@@ -128,6 +135,7 @@ Where:
 | `--rsim`          | Perform the simulation with the Ruby engine          |
 | `--rcsim`         | Perform the simulation with the Hybrid engine        |
 | `--vcd`           | Make the simulator generate a VCD file               |
+| `--svg`           | Output a graphical representation of the RTL (SVG format) |
 | `-d, --directory` | Specify the base directory for loading the HDLRuby files |
 | `-D, --debug`     | Set the HDLRuby debug mode |
 | `-t, --top system`| Specify the top system describing the circuit to compile |
@@ -151,16 +159,16 @@ __Notes__:
 
 __Examples__:
 
-* Compile system named `adder` from `adder.rb` input file and generate a low-level YAML description into directory `adder`:
+* Compile `adder.rb` input file and generate a low-level Verilog HDL description into the directory `adder`:
 
 ```bash
-hdrcc --yaml --top adder adder.rb adder
+hdrcc -v adder.rb adder
 ```
 
-* Compile `adder.rb` input file and generate a low-level Verilog HDL description into the directory `adder`:
+* Compile `adder8.v` input Verilog HDL file with `adder8` as top module, and generate a graphical representation of its RTL in the `view` directory:
 
 ```bash
-hdrcc -v adder.rb adder
+hdrcc adder8.v -t adder8 --svg view
 ```
   
 * Compile system `adder` whose bit width is generic from `adder_gen.rb` input file to a 16-bit circuit low-level VHDL description into directory `adder`:

data/lib/HDLRuby/hdr_samples/hard_to_route.rb

@@ -0,0 +1,30 @@
+# A benchmark for testing the router of SVG generation with hard to
+# handle patterns.
+# Note that the circuit is not synthesizable here, it is just for
+# testing difficult routing patterns, even if they are illegal in practice.
+
+system :adder do |typ|
+    typ.input :x, :y
+    typ.output :z
+
+    z <= x + y
+end
+
+
+system :hard_to_route do
+
+    [8].inner :x, :y, :z, :c
+
+    adder(bit[8]).(:adderI0).(x,y,z)
+    adder(bit[8]).(:adderI1).(x: x, y: y, z: z)
+
+    timed do
+        !10.ns
+        x <= 0
+        y <= 0
+        !10.ns
+        x <= 1
+        y <= 1
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_generic_in_generic.rb

@@ -0,0 +1,31 @@
+# Samples for testing instantiation of generic system within generic system.
+
+
+system :inner_generic do |typeI, typeO|
+  typeI.input :din
+  typeO.output :dout
+
+  dout <= din * 2
+end
+
+
+system :outer_generic do |typeI, typeO|
+  typeI.input :din_
+  typeO.output :dout_
+
+  inner_generic(typeI,typeO).(:my_inner_generic).(din_,dout_)
+end
+
+
+system :test_generic_in_generic do
+  [8].inner :x, :y
+
+  outer_generic(bit[8],bit[16]).(:my_outer_generic).(x,y)
+
+  timed do
+    x <= 0
+    !10.ns
+    x <= 1
+    !10.ns
+  end
+end

data/lib/HDLRuby/hdr_samples/with_seq_case.rb

@@ -0,0 +1,28 @@
+
+
+# A benchmark for testing case in seq blocks.
+system :with_seq_case_bench do
+    [2].inner :s
+    [8].inner :z
+
+    seq do
+       z <= 4
+       hcase(s)
+       hwhen(0) { z <= 0 }
+       hwhen(1) { z <= 1 }
+       hwhen(2) {        } # Intentionally left blank
+       helse    { z <= 3 }
+       z <= z+1
+    end
+
+    timed do
+        s <= 0
+        !10.ns
+        s <= 1
+        !10.ns
+        s <= 2
+        !10.ns
+        s <= 3
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_seq_if.rb

@@ -0,0 +1,25 @@
+
+
+# A benchmark for testing if in seq blocks.
+system :with_seq_if_bench do
+    [2].inner :s
+    [8].inner :z
+
+    seq do
+       hif(s==0)    { z <= 0 }
+       helsif(s==1) { z <= 1 }
+       helsif(s==2) { z <= 2 }
+       helse        { z <= 3 }
+    end
+
+    timed do
+        s <= 0
+        !10.ns
+        s <= 1
+        !10.ns
+        s <= 2
+        !10.ns
+        s <= 3
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_seq_if_succ.rb

@@ -0,0 +1,27 @@
+
+
+# A benchmark for testing if in seq blocks.
+system :with_seq_if_bench do
+    [2].inner :s
+    [8].inner :u, :v
+
+    seq do
+       hif(s==0)    { u <= 0; v <= 3 }
+       helsif(s==1) { u <= 1; v <= 2 }
+       helsif(s==2) { u <= 2; v <= 1 }
+       helse        { u <= 3; v <= 0 }
+       u <= u + 1
+       v <= v + 2
+    end
+
+    timed do
+        s <= 0
+        !10.ns
+        s <= 1
+        !10.ns
+        s <= 2
+        !10.ns
+        s <= 3
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_verilog.rb

@@ -1,4 +1,4 @@
-# Sample HDLRuby instantiating a Verilog HDL-described adder (adder.v)
+# Sample HDLRuby instantiating a Verilog HDL-described adder (adder8.v)
 
 require_verilog "adder8.v"
 

data/lib/HDLRuby/hdrcc.rb

@@ -254,15 +254,15 @@ module HDLRuby
                 # No, look for it.
                 @top_system = get_top
                 # show? "@top_system=#{@top_system}"
-                unless @top_system then
-                    # Not found? Error.
-                    # Maybe it is a parse error, look for it.
-                    bind = TOPLEVEL_BINDING.clone
-                    eval("require 'HDLRuby'\n\nconfigure_high\n\n",bind)
-                    eval(@texts[0],bind,@top_file_name,1)
-                    # No parse error found.
-                    raise "Cannot find a top system." unless @top_system
-                end
+                # unless @top_system then
+                #     # Not found? Error.
+                #     # Maybe it is a parse error, look for it.
+                #     bind = TOPLEVEL_BINDING.clone
+                #     eval("require 'HDLRuby'\n\nconfigure_high\n\n",bind)
+                #     eval(@texts[0],bind,@top_file_name,1)
+                #     # No parse error found.
+                #     raise "Cannot find a top system." unless @top_system
+                # end
             end
             # Initialize the environment for processing the hdr file.
             bind = TOPLEVEL_BINDING.clone
@@ -272,16 +272,20 @@ module HDLRuby
             end
             # Process it.
             eval(@texts[0],bind,@top_file_name,1)
-            # Get the resulting instance
-            if @params.empty? then
+            # Get the resulting instance if any.
+            if @top_system then
+              if @params.empty? then
                 # There is no generic parameter
                 @top_instance = 
-                    eval("#{@top_system} :#{@top_name}\n#{@top_name}",bind)
-            else
+                  eval("#{@top_system} :#{@top_name}\n#{@top_name}",bind)
+              else
                 # There are generic parameters
                 @top_instance = 
-                    # eval("#{@top_system} :#{@top_name},#{@params.join(",")}\n#{@top_name}",bind)
-                    eval("#{@top_system}(#{@params.join(",")}).(:#{@top_name})\n#{@top_name}",bind)
+                  eval("#{@top_system}(#{@params.join(",")}).(:#{@top_name})\n#{@top_name}",bind)
+              end
+            else
+              # No top instance.
+              @top_instance = nil
             end
         end
     end
@@ -348,13 +352,15 @@ $options = {}
 $options[:std] = true
 # Parse the options
 $optparse = OptionParser.new do |opts|
-    opts.banner = "Usage: hdrcc.rb [options] <input file> [<output directory or file>]"
+    opts.banner = "Usage: hdrcc.rb [options] [<input file>] [<output/working directory>]"
 
     opts.separator ""
     opts.separator "Where:"
     opts.separator "* `options` is a list of options"
-    opts.separator "* `<input file>` is the initial file to compile (mandatory)"
-    opts.separator "* `<output file>` is the output file"
+    opts.separator "* `<input file>` is the initial file to compile."
+    opts.separator "  This input can either be HDLRuby (.rb) or Verilog HDL (.v),"
+    opts.separator "  however, for the latter the top module must be specified using --top"
+    opts.separator "* `<output/working directory>` is the directory where to put temporary and output files"
     opts.separator ""
     opts.separator "Options:"
 
@@ -456,6 +462,11 @@ $optparse = OptionParser.new do |opts|
         $options[:vhdl08] = true
         $gen = true
     end
+    opts.on("--svg","Output a graphical representation of the RTL (SVG format)") do |v|
+      $options[:svg] = v
+      $options[:multiple] = v
+      $gen = true
+    end
     opts.on("-s", "--syntax","Output the Ruby syntax tree") do |s|
         $options[:syntax] = s
     end
@@ -541,15 +552,15 @@ $optparse.parse!
 # show? "options=#{$options}"
 
 # Check the compatibility of the options
-if $options.count {|op| [:yaml,:hdr,:verilog,:vhdl].include?(op) } > 1 then
-    warn("Please choose either YAML, HDLRuby, Verilog HDL, or VHDL output.")
+if $options.count {|op| [:yaml,:hdr,:verilog,:vhdl,:svg].include?(op) } > 1 then
+    warn("Please choose either YAML, HDLRuby, Verilog HDL, VHDL, SVG (visualize) output.")
     puts $optparse.help()
 end
 
 # Get the the input and the output files.
 $input,$output = $*
-    # Get the top system name if name.
-    $top = $options[:top].to_s
+# Get the top system name if name.
+$top = $options[:top].to_s
 unless $top == "" || (/^[_[[:alpha:]]][_\w]*$/ =~ $top) then
     warn("Please provide a valid top system name.")
     exit
@@ -593,17 +604,42 @@ if $output then
             FileUtils.mkdir_p($output)
         end
     else
-        # Open the file.
-        $output = File.open($output,"w")
+        # Now, nothing to do: specified output files are not to be
+        # handled by hdrcc directly with handles output directories only.
+        # 
+        # # Open the file if it is one, otherwise use a string.
+        # if File.file?($output) then
+        #     $output = File.open($output,"w")
+        # else
+        #     $output = StringIO.new
+        # end
     end
 else
     if $options[:multiple] then
-        raise "Need a target directory in multiple files generation mode."
+        # raise "Need a target directory in multiple files generation mode."
+        warn("Need a output/working directory.")
+        warn($optparse.banner)
+        exit
     end
     $output = $stdout
 end
 
-# Load and process the hdr files.
+# Process non-HDLRuby files.
+if $input.end_with?(".v") then
+  if $top.empty? then
+    warn("The top module must be specified using \"--top <top module>\".")
+    exit
+  end
+  # Processing a Verilog HDL file, embed it into regular HDLRuby
+  # Generate a temporary HDLRuby file to process it.
+  rinput = $output+"/"+$input.chomp(".v")+".rb"
+  File.open(rinput,"w") do |f|
+    f << "require_verilog '#{$input}'\n"
+  end
+  $input = rinput
+end
+
+# Load and process the HDLRuby files.
 $options[:directory] ||= "./"
 $loader = HDRLoad.new($top,$input,$options[:directory].to_s,*$params)
 $loader.read_all
@@ -637,7 +673,13 @@ end
 # Get the top systemT.
 HDLRuby.show "#{Time.now}#{show_mem}"
 # Ruby simulation uses the HDLRuby::High tree, other the HDLRuby::Lowais used 
-$top_system = ($options[:rsim] || $options[:rcsim]) ? $top_instance.systemT : $top_instance.to_low.systemT
+if $top_instance then
+  $top_system = ($options[:rsim] || $options[:rcsim]) ? $top_instance.systemT : $top_instance.to_low.systemT
+else
+  # No top system, end here.
+  HDLRuby.show "##### End here since not top system #####"
+  exit
+end
 $top_intance = nil # Free as much memory as possible.
 HDLRuby.show "##### Top system built #####"
 HDLRuby.show "#{Time.now}#{show_mem}"
@@ -1025,6 +1067,21 @@ elsif $options[:vhdl] then
             $output << systemT.to_vhdl
         end
     end
+elsif $options[:svg] then
+    # Requires the viz library.
+    require "HDLRuby/hruby_viz.rb"
+    # Generate the viz structure.
+    viz = $top_system.to_viz
+    # Do the place and route.
+    viz.place_and_route_deep
+    viz.scale = 30.0
+    # Get the base name of the input file, it will be used for
+    # generating the main name of the multiple result files.
+    $basename = File.basename($input,File.extname($input))
+    $basename = $output + "/" + $basename
+    $name = $basename + ".svg"
+    # Generate the svg file.
+    File.open($name,"w") { |file| file.write(viz.to_svg) }
 end
 
 HDLRuby.show "##### Code generated #####"

data/lib/HDLRuby/hruby_bstr.rb

@@ -70,7 +70,7 @@ module HDLRuby
                 # Content is not a numeric nor a BitString.
                 @content = []
                 # Ensure it is a string.
-                val = val.to_s.downcase
+                val = val.to_s.chomp.downcase
                 val.each_byte.reverse_each do |c|
                     case c
                     when 48  # "0"
@@ -82,7 +82,7 @@ module HDLRuby
                     when 122 # "z"
                         @content << 2
                     else
-                        raise "Invalid bit: #{b.chr}"
+                      raise "Invalid bit '#{c.chr}' in #{val}"
                     end
                 end
             end

data/lib/HDLRuby/hruby_high.rb

@@ -420,6 +420,7 @@ module HDLRuby::High
         #
         # NOTE: a name can also be a signal, is which case it is duplicated. 
         def make_inputs(type, *names)
+            # puts "for inputs=#{names} top_user=#{High.top_user}(#{High.top_user.name}) @scope=#{@scope}(#{@scope.name})"
             # Check if called within the top scope of the block.
             if High.top_user != @scope then
                 # No, cannot make an input from here.
@@ -874,6 +875,7 @@ module HDLRuby::High
 
         # Converts the system to HDLRuby::Low and set its +name+.
         def to_low(name = self.name)
+            # puts "to_low for system=#{name}"
             name = name.to_s
             if name.empty? then
                 raise AnyError, 
@@ -2307,6 +2309,11 @@ module HDLRuby::High
 
         # Creates a new system instance of system type +systemT+ named +name+.
         def initialize(name, systemT)
+            # Check the validity of the name.
+            unless name.is_a?(String) or name.is_a?(Symbol)
+                raise AnyError, 
+                  "Missing instance name for system instantiation."
+            end
             # Initialize the system instance structure.
             super(name,systemT)
 
@@ -2361,7 +2368,16 @@ module HDLRuby::High
                 end
             else
                 # No, perform a connection is order of declaration
+                # But first check if there are not too many of them.
+              if connects.size > 
+                self.systemT.each_signal_with_included.to_a.size then
+                    raise AnyError, "Too many connections to instance " +
+                      "#{self.name}: got #{connects.size} " +
+                      "but expecting at most " +
+                      "#{self.systemT.each_signal_with_included.to_a.size}"
+                end
                 connects.each.with_index do |csig,i|
+                # Now do the connection.
                     # puts "systemT inputs=#{systemT.each_input.to_a.size}"
                     # Gets i-est signal to connect
                     ssig = self.systemT.get_interface_with_included(i)
@@ -3563,12 +3579,21 @@ module HDLRuby::High
 
         # Converts the name reference to a HDLRuby::Low::RefName.
         def to_low
-            # puts "to_low with base=#{@base} @object=#{@object}"
-            # puts "@object.name=#{@object.name} @object.parent=#{@object.parent.name}"
+            # puts "to_low with base=#{@base} @object=#{@object} @object.parent=#{@object.parent} High.cur_system=#{High.cur_system}"
+            # puts "@object.name=#{@object.name}"
+            # puts "@object.parent.name=#{@object.parent.name}" if @object.parent
+            # Check if a direct access is possible or not.
+            # It is possible if the object parent is the top level,
+            # or if it is a system or the first scope of a system.
+            # (NOTE: previously we ensured that it was only for the
+            # current system, however, this did not support the case
+            # of object within included systems).
             if @base.is_a?(RefThis) && 
                     (@object.parent != High.top_user) &&
-                    (@object.parent != High.cur_system) &&
-                    (@object.parent != High.cur_system.scope) then # &&
+                    # (@object.parent != High.cur_system) &&
+                    (!@object.parent.is_a?(SystemT)) &&
+                    # (@object.parent != High.cur_system.scope) then # &&
+                    (!(@object.parent.is_a?(Scope) && @object.parent.parent.is_a?(SystemT))) then
                     # (!@object.parent.name.empty?) then
                 # Need to have a hierachical access.
                 if @object.respond_to?(:low_object) && @object.low_object then
@@ -4497,17 +4522,16 @@ module HDLRuby::High
             self.add_statement(TimeWait.new(delay))
         end
 
-        # # Adds a loop until +delay+ statement in the block in +mode+ whose
-        # # loop content is built using +ruby_block+.
-        # def repeat(delay, mode = nil, &ruby_block)
-        # Adds a +number+ times loop statement in the block in +mode+ whose
+        # # Adds a +number+ times loop statement in the block in +mode+ whose
+        # def repeat(number = -1, mode = nil, &ruby_block)
+        # Adds a +number+ times loop statement in the block whose
         # loop content is built using +ruby_block+.
         # NOTE: if +number+ is negative, the number of iteration is infinite.
-        def repeat(number = -1, mode = nil, &ruby_block)
+        def repeat(number = -1, &ruby_block)
             # Ensure there is a block.
             ruby_block = proc {} unless block_given?
-            # Build the content block.
-            content = High.make_block(mode,&ruby_block)
+            # Build the content block: necessarily seq since timed.
+            content = High.make_block(:seq,&ruby_block)
             # Create and add the statement.
             # self.add_statement(TimeRepeat.new(content,delay))
             self.add_statement(TimeRepeat.new(number,content))
@@ -4835,6 +4859,11 @@ module HDLRuby::High
     # Registers hardware referencing method +name+ to the current namespace.
     def self.space_reg(name,&ruby_block)
         # print "registering #{name} in #{Namespaces[-1]}\n"
+        # Check the name class. 
+        unless name.is_a?(String) or name.is_a?(Symbol) then
+          raise AnyError, 
+            "Invalid class for a name, string or symbol expected but got: #{name.class}"
+        end
         Namespaces[-1].add_method(name,&ruby_block)
     end
 

data/lib/HDLRuby/hruby_low.rb

@@ -6194,6 +6194,10 @@ module HDLRuby::Low
         # Create a new named reference with +type+ accessing +ref+ with +name+.
         # def initialize(ref,name)
         def initialize(type,ref,name)
+            # puts "new RefName with name=#{name}"
+            if !name or name.empty? then
+              raise "Internal error: Creating a RefName without a name."
+            end
             super(type)
             # Check and set the accessed reference.
             unless ref.is_a?(Ref) then