HDLRuby 3.2.0 → 3.3.1

data/lib/HDLRuby/hruby_error.rb

@@ -5,6 +5,10 @@ module HDLRuby
     class AnyError < ::StandardError
     end
 
+    ## The HDLRuby UI error class.
+    class UIError < ::StandardError
+    end
+
     module High
         ## The HDLRuby::High error class.
         class AnyError < HDLRuby::AnyError
@@ -13,12 +17,21 @@ module HDLRuby
         ## The HDLRuby error class replacing the standard Ruby NoMethodError
         class NotDefinedError < AnyError
         end
+
+        ## The HDLRuby::High UI error class.
+        class UIError < HDLRuby::UIError
+        end
     end
 
+
     module Low
         ## The HDLRuby::Low error class.
         class AnyError < HDLRuby::AnyError
         end
+
+        ## The HDLRuby::Low UI error class.
+        class UIError < HDLRuby::UIError
+        end
     end
 
     ## Execution context for processing error messages in +code+.

data/lib/HDLRuby/hruby_high.rb

@@ -1171,10 +1171,10 @@ module HDLRuby::High
         end
 
         # Declares a program in language +lang+ with start function named +func+
-        # and accessed expressions an code given in +args+.
-        def program(lang, func, *args)
+        # and built through +ruby_block+.
+        def program(lang, func, &ruby_block)
             # Create the program.
-            prog = Program.new(lang, func, *args)
+            prog = Program.new(lang, func, &ruby_block)
             # Adds the resulting program to the current scope.
             HDLRuby::High.top_user.add_program(prog)
             # Return the resulting program
@@ -2502,16 +2502,59 @@ module HDLRuby::High
     ##
     # Describes a program.
     class Program < HDLRuby::Low::Program
+
+        include Hmissing
+
+        attr_reader :namespace
+
+        # Create a program in language +lang+ with start function named +func+
+        # and built through +ruby_block+.
+        def initialize(lang, func, &ruby_block)
+            # Create the program.
+            super(lang,func)
+            # Create the namespace for the program.
+            @namespace = Namespace.new(self)
+            # Build the program object.
+            High.space_push(@namespace)
+            High.top_user.instance_eval(&ruby_block)
+            High.space_pop
+        end
+
         # Converts the if to HDLRuby::Low.
         def to_low
             # Create the resulting program.
-            progL = HDLRuby::Low::Program.new(self.lang,self.function,
-                                            *self.each_expression.map(&:to_low),
-                                            *self.each_event.map(&:to_low),
-                                            *self.each_code)
+            progL = HDLRuby::Low::Program.new(self.lang,self.function)
+            # Add the wakening events.
+            self.each_event  { |ev| progL.add_event(ev.to_low) }
+            # Add the code files.
+            self.each_code   { |ev| progL.add_code(code) }
+            # Add the input signals references.
+            self.each_input  { |ref| progL.add_input(ref.to_low) }
+            # Add the output signals references.
+            self.each_output { |ref| progL.add_output(ref.to_low) }
             # Return the resulting program.
             return progL
         end
+
+        # Adds new activation ports.
+        def actport(*evs)
+            evs.each(&method(:add_actport))
+        end
+
+        # Adds new code files.
+        def code(*codes)
+            codes.each(&method(:add_code))
+        end
+
+        # Adds new input ports.
+        def inport(ports = {})
+          ports.each { |k,v| self.add_inport(k,v) }
+        end
+
+        # Adds new output ports.
+        def outport(ports = {})
+          ports.each { |k,v| self.add_outport(k,v) }
+        end
     end
 
 

data/lib/HDLRuby/hruby_low.rb

@@ -844,10 +844,10 @@ module HDLRuby::Low
                       "Invalid class for a program: #{prog.class}"
             end
             # Set the parent of the program.
-            program.parent = self
+            prog.parent = self
             # Add the program.
-            @programs << program
-            program
+            @programs << prog
+            prog
         end
 
         # Iterates over the programs.
@@ -3006,57 +3006,101 @@ module HDLRuby::Low
         attr_reader :language, :function
 
         # Creates a new program in language +lang+ with start function
-        # named +func+ accessed expressions, events and code files given in
-        # +args+.
-        def initialize(lang,func,*args)
+        # named +func+.
+        def initialize(lang,func)
             # Sets the language.
             @language = lang.to_sym
             # Sets the start function.
             @function = func.to_s
-            # Process the expressions and code files arguments.
-            @exprs = []
-            @events = []
-            @codes = []
-            args.each do |arg|
-                if arg.is_a?(String) then
-                    @codes << arg
-                elsif arg.is_a?(Event) then
-                    @events << arg
-                else
-                    @exprs << arg.to_expr
-                end
+            # Initializes the contents.
+            @actports = [] # The activation ports.
+            @codes    = [] # The code files.
+            @inports  = {} # The input ports.
+            @outports = {} # The output ports.
+        end
+
+        # Add a new activation port.
+        def add_actport(ev)
+            unless ev.is_a?(Event) then
+                raise AnyError, "Invalid class for an event: #{ev.class}"
+            end
+            @actports << ev
+        end
+
+        # Add a new code file.
+        def add_code(code)
+            @codes << code.to_s
+        end
+
+        # Add a new input port.
+        def add_inport(name, sig)
+            # Ensure name is a symbol.
+            unless name.is_a?(Symbol) then
+                name = name.to_s.to_sym
             end
+            # Ensure sig is a signal.
+            unless sig.is_a?(SignalI) then
+                raise AnyError, "Invalid class for a signal: #{sig.class}"
+            end
+            # Add the new port.
+            @inports[name] = sig
+        end
+
+        # Add a new output port.
+        def add_outport(name, sig)
+            # Ensure name is a symbol.
+            unless name.is_a?(Symbol) then
+                name = name.to_s.to_sym
+            end
+            # Ensure sig is a signal.
+            unless sig.is_a?(SignalI) then
+                raise AnyError, "Invalid class for a signal: #{sig.class}"
+            end
+            # Add the new port.
+            @outports[name] = sig
+        end
+
+
+        # Iterates over each activation event.
+        #
+        # Returns an enumerator if no ruby block is given.
+        def each_actport(&ruby_block)
+            # No block? Return an enumerator.
+            return to_enum(:each_actport) unless ruby_block
+            # A block is given, apply it.
+            @actports.each(&ruby_block)
         end
 
-        # Iterates over each accessed expression.
+        # Iterates over each code file.
         #
         # Returns an enumerator if no ruby block is given.
-        def each_expression(&ruby_block)
+        def each_code(&ruby_block)
             # No block? Return an enumerator.
-            return to_enum(:each_expression) unless ruby_block
+            return to_enum(:each_code) unless ruby_block
             # A block is given, apply it.
-            @exprs.each(&ruby_block)
+            @codes.each(&ruby_block)
         end
 
-        # Iterates over each accessed event.
+        # Iterate over each input port.
         #
         # Returns an enumerator if no ruby block is given.
-        def each_event(&ruby_block)
+        def each_inport(&ruby_block)
             # No block? Return an enumerator.
-            return to_enum(:each_event) unless ruby_block
+            return to_enum(:each_inport) unless ruby_block
             # A block is given, apply it.
-            @events.each(&ruby_block)
+            @inports.each(&ruby_block)
         end
 
-        # Iterates over each code files.
+        # Iterate over each output port.
         #
         # Returns an enumerator if no ruby block is given.
-        def each_code(&ruby_block)
+        def each_outport(&ruby_block)
             # No block? Return an enumerator.
-            return to_enum(:each_code) unless ruby_block
+            return to_enum(:each_outport) unless ruby_block
             # A block is given, apply it.
-            @codes.each(&ruby_block)
+            @outports.each(&ruby_block)
         end
+
     end
 
 

data/lib/HDLRuby/hruby_rcsim.rb

@@ -3,6 +3,8 @@ require 'HDLRuby'
 require 'hruby_high_fullname'
 require 'hruby_sim/hruby_sim'
 
+require 'rubyHDL'
+
 
 module HDLRuby::High
 
@@ -189,7 +191,6 @@ module HDLRuby::High
             rcbehs = self.each_behavior.map {|beh| beh.to_rcsim(subowner)} # +
                 # self.each_connection.map {|cxt| cxt.to_rcsim(subowner) }
             self.each_connection do |cnx|
-                # ICIICI
                 if !cnx.right.is_a?(RefObject) then
                     rcbehs << cnx.to_rcsim(subowner)
                 else
@@ -209,8 +210,11 @@ module HDLRuby::High
                 RCSim.rcsim_add_scope_behaviors(@rcscope,rcbehs)
             end
 
-            # Create and add the codes.
-            # TODO!!
+            # Create and add the programs.
+            rcprogs = self.each_program.map {|prog| prog.to_rcsim(subowner)} 
+            if rcprogs.any? then
+                RCSim.rcsim_add_scope_codes(@rcscope,rcprogs);
+            end
 
             return @rcscope
         end
@@ -512,12 +516,92 @@ module HDLRuby::High
 
     class Chunk
         ## Extends the Chunk class for hybrid Ruby-C simulation.
-        # TODO!!
+        # Deprecated!!
     end
 
     class Code
         ## Extends the Code class for hybrid Ruby-C simulation.
-        # TODO!!
+        # Deprecated!!
+    end
+
+    class Program
+        ## Extends the Program class for hybrid Ruby-C simulation.
+        #  NOTE: produce a low-level Code, and not program. For now,
+        #  Program is a high-level interface for software description and
+        #  is not ment to be simulated as is. It may hcange in the future 
+        #  though.
+
+        attr_reader :rccode # The access to the C version of the code.
+
+        # Generate the C description of the code comming from object
+        # whose C description is +rcowner+.
+        # NOTE: also update the table of signals accessed from software
+        # code.
+        def to_rcsim(rcowner)
+            # puts "to_rcsim for program=#{self}"
+
+            # Create the code C object.
+            # puts "make code with self.class=#{self.class}"
+            @rccode = RCSim.rcsim_make_code(self.language.to_s, self.function.to_s)
+
+            # Set the owner.
+            RCSim.rcsim_set_owner(@rccode,rcowner)
+
+            # Create and add the events.
+            if self.each_actport.any? then
+                RCSim.rcsim_add_code_events(@rccode, self.each_actport.map do|ev|
+                    ev.to_rcsim(@rccode)
+                end)
+            end
+
+            # Create the software interface.
+            if self.language == :ruby then
+                # Loads the code files.
+                self.each_code do |code|
+                    Kernel.require("./"+code.to_s)
+                end
+                # Add the input ports.
+                self.each_inport do |sym, sig|
+                    RubyHDL.inport(sym,sig.rcsignalI)
+                end
+                # Add the output ports.
+                self.each_outport do |sym, sig|
+                    RubyHDL.outport(sym,sig.rcsignalI)
+                end
+            elsif self.language == :c then
+                # Loads the code file: only the last one remains.
+                self.each_code do |code|
+                    code = code.to_s
+                    # Check if the file exists.
+                    unless File.file?(code) then
+                        # The code name may be not complete, 
+                        # try ".so", ".bundle" or ".dll" extensions.
+                        if File.file?(code+".so") then
+                            code += ".so"
+                        elsif File.file?(code + ".bundle") then
+                            code += ".bundle"
+                        elsif File.file?(code + ".dll") then
+                            code += ".dll"
+                        else
+                            # Code not found.
+                            raise "C code library not found: " + code
+                        end
+                    end
+                    RCSim.rcsim_load_c(@rccode,code,self.function.to_s)
+                end
+                # Add the input ports.
+                self.each_inport do |sym, sig|
+                    RCSim::CPorts[sym] = sig.rcsignalI
+                end
+                # Add the output ports.
+                self.each_outport do |sym, sig|
+                    RCSim::CPorts[sym] = sig.rcsignalI
+                end
+            end
+
+
+            return @rccode
+        end
     end
 
 

data/lib/HDLRuby/std/clocks.rb

@@ -4,10 +4,10 @@ module HDLRuby::High::Std
 # Standard HDLRuby::High library: clocks
 # 
 ########################################################################
-
+    @@__clocks_rst = nil
 
     # Initialize the clock generator with +rst+ as reset signal.
-    def configure_clocks(rst = $rst)
+    def configure_clocks(rst = nil)
         @@__clocks_rst = rst
     end
 
@@ -19,13 +19,22 @@ module HDLRuby::High::Std
         HDLRuby::High.cur_system.open do
 
             # Ensures times is a value.
-            times = times.to_value
+            times = times.to_value - 1
+            if (times == 0) then
+              AnyError.new("Clock multiplier must be >= 2.") 
+            end
 
             # Create the counter.
             # Create the name of the counter.
             name = HDLRuby.uniq_name
             # Declare the counter.
-            [times.width].inner(name)
+            if @@__clocks_rst then
+                # There is a reset, so no need to initialize.
+                [times.width].inner(name)
+            else
+                # There is no reset, so need to initialize.
+              [times.width].inner(name => times)
+            end
             # Get the signal of the counter.
             counter = get_inner(name)
 
@@ -33,51 +42,77 @@ module HDLRuby::High::Std
             # Create the name of the clock.
             name = HDLRuby.uniq_name
             # Declares the clock.
-            bit.inner(name)
+            if @@__clocks_rst then
+                # There is a reset, so no need to initialize.
+                bit.inner(name)
+            else
+                # There is no reset, so need to initialize.
+                bit.inner(name => times)
+            end
             # Get the signal of the clock.
             clock = get_inner(name)
             
             # Control it.
             par(event) do
-                hif(@@__clocks_rst) do
-                    counter.to_ref <= times.to_expr
-                    clock.to_ref <= 0
-                end
-                helsif(counter.to_expr == 0) do
-                    counter.to_ref <= times.to_expr 
-                    clock.to_ref <= ~ clock.to_expr
-                end
-                helse do
-                    counter.to_ref <= counter.to_expr + 1
+                if @@__clocks_rst then
+                    # There is a reset, handle it.
+                    hif(@@__clocks_rst) do
+                      counter <= times
+                        clock <= 0
+                    end
+                    helsif(counter.to_expr == 0) do
+                        counter <= times 
+                        clock   <= ~ clock
+                    end
+                    helse do
+                        counter <= counter - 1
+                    end
+                else
+                    # There is no reset.
+                    hif(counter == 0) do
+                        counter <= times 
+                        clock   <= ~ clock
+                    end
+                    helse do
+                        counter <= counter - 1
+                    end
                 end
             end
         end
         return clock
     end
 
-    # module clk_div3(clk,reset, clk_out);
-
-    #     input clk;
-    #     input reset;
-    #     output clk_out;
-
-    #     reg [1:0] pos_count, neg_count;
-    #     wire [1:0] r_nxt;
-
-    #     always @(posedge clk)
-    #     if (reset)
-    #         pos_count <=0;
-    #     else if (pos_count ==2) pos_count <= 0;
-    #     else pos_count<= pos_count +1;
 
-    #     always @(negedge clk)
-    #     if (reset)
-    #         neg_count <=0;
-    #     else  if (neg_count ==2) neg_count <= 0;
-    #     else neg_count<= neg_count +1;
+# https://referencedesigner.com/tutorials/verilogexamples/verilog_ex_07.php
+# 
+# module clk_divn #(
+# parameter WIDTH = 3,
+# parameter N = 5)
+#  
+# (clk,reset, clk_out);
+#  
+# input clk;
+# input reset;
+# output clk_out;
+#  
+# reg [WIDTH-1:0] pos_count, neg_count;
+# wire [WIDTH-1:0] r_nxt;
+#  
+#  always @(posedge clk)
+#  if (reset)
+#  pos_count <=0;
+#  else if (pos_count ==N-1) pos_count <= 0;
+#  else pos_count<= pos_count +1;
+#  
+#  always @(negedge clk)
+#  if (reset)
+#  neg_count <=0;
+#  else  if (neg_count ==N-1) neg_count <= 0;
+#  else neg_count<= neg_count +1; 
+#  
+# assign clk_out = ((pos_count > (N>>1)) | (neg_count > (N>>1))); 
+# endmodule
 
-    #     assign clk_out = ((pos_count == 2) | (neg_count == 2));
-    # endmodule
 
     # Creates a clock inverted every +times+ occurence of an +event+ and its
     # everted.
@@ -87,13 +122,22 @@ module HDLRuby::High::Std
         # Enters the current system
         HDLRuby::High.cur_system.open do
             # Ensure times is a value.
-            times = times.to_value
+            times = times.to_value 
+            if (times == 1) then
+              AnyError.new("Clock multiplier must be >= 2.") 
+            end
 
             # Create the event counter.
             # Create the name of the counter.
             name = HDLRuby.uniq_name
             # Declare the counter.
-            [times.width].inner(name)
+            if @@__clocks_rst then
+                # There is a reset, so no need to initialize.
+                [times.width].inner(name)
+            else
+                # There is no reset, so need to initialize.
+                [times.width].inner(name => 0)
+            end
             # Get the signal of the counter.
             counter = get_inner(name)
 
@@ -101,7 +145,13 @@ module HDLRuby::High::Std
             # Create the name of the counter.
             name = HDLRuby.uniq_name
             # Declare the counter.
-            [times.width].inner(name)
+            if @@__clocks_rst then
+                # There is a reset, so no need to initialize.
+                [times.width].inner(name)
+            else
+                # There is no reset, so need to initialize.
+              [times.width].inner(name => 0)
+            end
             # Get the signal of the counter.
             counter_inv = get_inner(name)
 
@@ -109,32 +159,50 @@ module HDLRuby::High::Std
             # Create the name of the clock.
             name = HDLRuby.uniq_name
             # Declare the clock.
-            bit.inner(name)
+            if @@__clocks_rst then
+                # There is a reset, so no need to initialize.
+                bit.inner(name)
+            else
+                # There is no reset, so need to initialize.
+                bit.inner(name => 0)
+            end
             # Get the signal of the clock.
             clock = get_inner(name)
 
-            # Control the event counter
+            # Control the even counter.
             par(event) do
-                hif(@@__clocks_rst | counter.to_expr == 0) do
-                    counter.to_ref <= times.to_expr/2 + 1
+                if @@__clocks_rst then
+                    hif(@@__clocks_rst)        { counter <= 0 }
+                    helsif(counter == times-1) { counter <= 0 }
+                    helse                      { counter <= counter + 1 }
+                else
+                    hif(counter == times-1)     { counter <= 0 }
+                    helse                      { counter <= counter + 1 }
                 end
             end
-            # Control the inverteed event counter
+
+            # Control the odd counter.
             par(event.invert) do
-                hif(@@__clocks_rst | counter_inv.to_expr == 0) do
-                    counter_inv.to_ref <= times.to_expr/2 + 1
+                if @@__clocks_rst then
+                    hif(@@__clocks_rst)        { counter_inv <= 0 }
+                    helsif(counter == times-1) { counter_inv <= 0 }
+                    helse                      { counter_inv <= counter_inv + 1 }
+                else
+                    hif(counter == times-1)     { counter_inv <= 0 }
+                    helse                      { counter_inv <= counter_inv + 1 }
                 end
             end
-            # Compute the clock.
-            clock.to_ref <= (counter.to_expr == times.to_expr/2 + 1) |
-                (counter_inv.to_expr == times.to_expr/2 + 1)
+
+            clock <= ((counter > (times/2)) | (counter_inv > (times/2)))
         end
-        # Return it.
+        # Return the clock.
         return clock
     end
+
 end
 
 
+
 class HDLRuby::High::Event
     # Enhance the events with multiply operator.
 

data/lib/HDLRuby/std/std.rb

@@ -4,6 +4,8 @@
 # 
 ########################################################################
 
+# Hardware libraries.
+
 require 'std/clocks.rb'
 require 'std/fixpoint.rb'
 require 'std/decoder.rb'
@@ -12,3 +14,6 @@ require 'std/sequencer.rb'
 require 'std/sequencer_channel.rb'
 require 'std/sequencer_sync.rb'
 require 'std/sequencer_func.rb'
+
+# User interface libraries.
+require 'ui/hruby_board.rb'